tomahawk3_mmu_flexport.h (9727B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $File: tomahawk3_mmu_flexport.h 8 */ 9 10 11 12 #ifndef _SOC_TOMAHAWK3_MMU_FLEXPORT_H_ 13 #define _SOC_TOMAHAWK3_MMU_FLEXPORT_H_ 14 15 16 #include <soc/flexport/flexport_common.h> 17 18 19 /*** START SDK API COMMON CODE ***/ 20 21 /*! @file tomahawk3_mmu_flexport.h 22 * @brief Macros used in APIs of MMU for Tomahawk3. 23 * Details are shown below. 24 */ 25 26 #define TH3_MMU_NUM_L0_NODES_PER_HSP_PORT 12 27 #define TH3_MMU_NUM_L0_NODES_FOR_CPU_PORT 12 28 #define TH3_MMU_NUM_L1_NODES_PER_HSP_PORT 2 29 #define TH3_MMU_NUM_L1_NODES_FOR_CPU_PORT 48 30 #define TH3_MMU_NUM_Q_PER_HSP_PORT 12 31 #define TH3_MMU_NUM_Q_FOR_CPU_PORT 48 32 33 #define TH3_MMU_NUM_PORTS_PER_PIPE 32 34 #define TH3_MMU_NUM_PORTS_PER_PIPE_L 20 35 #define TH3_MMU_MAX_PORTS_PER_PIPE 32 36 #define TH3_MMU_NUM_HSP_PORTS_PER_PIPE 32 37 #define TH3_THDO_INVALID_DEV_PORT 255 38 #define TH3_INVALID_MMU_PORT 255 39 #define TH3_INVALID_DEV_PORT 160 40 #define TH3_MMU_PORT_PIPE_OFFSET 32 41 #define TH3_PHY_PORT_PIPE_OFFSET 32 42 43 #define TH3_MMU_CPU_PORT_NUM 19 44 #define TH3_MMU_MGMT0_PORT_NUM 51 45 #define TH3_MMU_MGMT1_PORT_NUM 179 46 #define TH3_MMU_LB0_PORT_NUM ((0*TH3_MMU_NUM_PORTS_PER_PIPE) + \ 47 (TH3_MMU_NUM_PORTS_PER_PIPE_L-2)) 48 #define TH3_MMU_LB1_PORT_NUM ((1*TH3_MMU_NUM_PORTS_PER_PIPE) + \ 49 (TH3_MMU_NUM_PORTS_PER_PIPE_L-2)) 50 #define TH3_MMU_LB2_PORT_NUM ((2*TH3_MMU_NUM_PORTS_PER_PIPE) + \ 51 (TH3_MMU_NUM_PORTS_PER_PIPE_L-2)) 52 #define TH3_MMU_LB3_PORT_NUM ((3*TH3_MMU_NUM_PORTS_PER_PIPE) + \ 53 (TH3_MMU_NUM_PORTS_PER_PIPE_L-2)) 54 #define TH3_MMU_LB4_PORT_NUM ((4*TH3_MMU_NUM_PORTS_PER_PIPE) + \ 55 (TH3_MMU_NUM_PORTS_PER_PIPE_L-2)) 56 #define TH3_MMU_LB5_PORT_NUM ((5*TH3_MMU_NUM_PORTS_PER_PIPE) + \ 57 (TH3_MMU_NUM_PORTS_PER_PIPE_L-2)) 58 #define TH3_MMU_LB6_PORT_NUM ((6*TH3_MMU_NUM_PORTS_PER_PIPE) + \ 59 (TH3_MMU_NUM_PORTS_PER_PIPE_L-2)) 60 #define TH3_MMU_LB7_PORT_NUM ((7*TH3_MMU_NUM_PORTS_PER_PIPE) + \ 61 (TH3_MMU_NUM_PORTS_PER_PIPE_L-2)) 62 63 #define TH3_MMU_BST_TRACK_MODE 0 64 #define TH3_MMU_BST_WMARK_MODE 1 65 #define TH3_MMU_NUM_PGS 8 66 #define TH3_MMU_NUM_SPS 4 67 #define TH3_MMU_NUM_COS 12 68 #define TH3_MMU_THDI_PG_MIN_LIMIT_LOSSLESS 7 69 #define TH3_MMU_THDI_PG_MIN_LIMIT_LOSSY 0 70 #define TH3_MMU_THDI_PG_HDRM_LIMIT_LOSSY 0 71 #define TH3_MMU_NUM_SPEEDS 7 72 #define TH3_MMU_TCT_ON_TO_CT_OFFSET 5 73 74 #define TH3_MMU_PAUSE_PG 7 /*PG7-Used for Initial PG_Min/hdrm + for Pause */ 75 76 typedef enum pipe_s 77 { 78 TH3_IPIPE, 79 TH3_EPIPE 80 } pipe_t; 81 82 #define TH3_MMU_FLUSH_OFF 0 83 #define TH3_MMU_FLUSH_ON 1 84 #define TH3_MMU_THD_RX_ENABLED 1 85 #define TH3_MMU_THD_RX_DISABLED 0 86 87 #define TH3_MMU_IS_CPU_PORT(pipe, port) ((pipe == 0) && \ 88 (port == TH3_MMU_CPU_PORT_NUM)) 89 #define TH3_MMU_IS_MGMT_PORT(pipe, port) \ 90 ( ((pipe == 1) && (port == TH3_MMU_MGMT0_PORT_NUM)) || \ 91 ((pipe == 5) && (port == TH3_MMU_MGMT1_PORT_NUM))) 92 #define TH3_MMU_IS_LPBK_PORT(port) (port == TH3_MMU_LB0_PORT_NUM \ 93 || port == TH3_MMU_LB1_PORT_NUM \ 94 || port == TH3_MMU_LB2_PORT_NUM \ 95 || port == TH3_MMU_LB3_PORT_NUM \ 96 || port == TH3_MMU_LB4_PORT_NUM \ 97 || port == TH3_MMU_LB5_PORT_NUM \ 98 || port == TH3_MMU_LB6_PORT_NUM \ 99 || port == TH3_MMU_LB7_PORT_NUM \ 100 ) 101 #define TH3_MMU_GET_PIPE_NUM(port, pipe) \ 102 pipe = port/TH3_MMU_PORT_PIPE_OFFSET 103 #define TH3_MMU_PIPE_NUM(port) port/TH3_MMU_PORT_PIPE_OFFSET 104 105 106 107 /* Some functions from MMU_CONFIG */ 108 extern int soc_tomahawk3_mmu_get_num_queues_for_port(int unit, int pipe, 109 int lcl_port, 110 int *number_of_queues); 111 112 extern int soc_tomahawk3_mmu_get_valid_pipes_for_itm(int unit, int itm, 113 int *pipes); 114 115 extern int soc_tomahawk3_mmu_get_itm_from_pipe_num(int unit, int pipe, 116 int *itm_num); 117 118 extern void soc_tomahawk3_mmu_get_q_base_num_for_pipe(int unit, int pipe, 119 int *pipe_q_base_num); 120 121 extern int soc_tomahawk3_mmu_get_chip_q_num_base_for_port(int unit, int pipe, 122 int local_mmu_port, 123 int *chip_q_base_num_for_port); 124 125 126 extern int soc_tomahawk3_mmu_get_thdi_bst_mode(int unit, 127 int *thdi_bst_mode); 128 129 extern int soc_tomahawk3_mmu_get_thdo_bst_mode(int unit, 130 int *thdo_bst_mode); 131 132 133 extern void soc_tomahawk3_mmu_get_pipe_flexed_status( 134 int unit, soc_port_schedule_state_t *port_schedule_state_t, 135 int pipe, 136 int *pipe_flexed); 137 138 extern int soc_tomahawk3_mmu_get_itm_flexed_status( 139 int unit, soc_port_schedule_state_t *port_schedule_state_t, 140 int itm, 141 int *itm_flexed); 142 143 144 extern int soc_tomahawk3_mmu_thdi_get_pg_hdrm_setting(int unit, int speed, 145 int line_rate, 146 uint32 *setting); 147 148 149 /*PORT FLUSH Functions*/ 150 151 extern int soc_tomahawk3_mmu_mtro_port_metering_config(int unit, 152 soc_port_schedule_state_t *port_schedule_state_t, 153 int pipe, uint32 set_val_mtro); 154 155 extern int soc_tomahawk3_mmu_qsch_port_flush(int unit, 156 soc_port_schedule_state_t *port_schedule_state_t, 157 int pipe, uint32 set_val); 158 159 extern int soc_tomahawk3_mmu_ebqs_port_flush(int unit, 160 soc_port_schedule_state_t *port_schedule_state_t, 161 int pipe, uint32 set_val); 162 163 extern int soc_tomahawk3_mmu_rqe_port_flush(int unit, 164 int itm, 165 int call_iter); 166 167 extern int soc_tomahawk3_mmu_wait_ebctm_empty(int unit, 168 soc_port_schedule_state_t *port_schedule_state_t, 169 int pipe); 170 171 /* THDI/WRED Clear Functions */ 172 extern int soc_tomahawk3_mmu_thdi_bst_clr(int unit, 173 soc_port_resource_t *port_resource_t); 174 175 176 extern int soc_tomahawk3_mmu_wred_clr(int unit, 177 soc_port_resource_t *port_resource_t); 178 179 180 /* THDI Setup function */ 181 extern int soc_tomahawk3_mmu_thdi_setup(int unit, 182 soc_port_resource_t *port_resource_t, 183 int lossy); 184 185 186 /*PORT MAPPING */ 187 extern int soc_tomahawk3_mmu_set_mmu_port_mappings(int unit, 188 soc_port_schedule_state_t *port_schedule_state_t, 189 soc_port_resource_t *port_resource_t); 190 191 /*QSCH Credit Clear Functions */ 192 extern int soc_tomahawk3_mmu_clear_qsch_credit_memories(int unit, 193 soc_port_resource_t *port_resource_t); 194 195 196 /* MTRO Credit Clear Functions */ 197 extern int soc_tomahawk3_mmu_clear_mtro_bucket_mems(int unit, 198 soc_port_resource_t *port_resource_t); 199 200 201 /* Port Flush Sequence */ 202 extern int soc_tomahawk3_flex_mmu_port_flush(int unit, 203 soc_port_schedule_state_t *port_schedule_state_t); 204 205 /* FlexPort Port Down Sequence */ 206 extern int soc_tomahawk3_flex_mmu_port_down(int unit, 207 soc_port_schedule_state_t *port_schedule_state_t); 208 209 /* Port Down Sequence */ 210 extern int soc_tomahawk3_mmu_port_down(int unit, 211 soc_port_schedule_state_t *port_schedule_state_t); 212 213 /* Port Up Sequence */ 214 extern int soc_tomahawk3_mmu_port_up(int unit, 215 soc_port_schedule_state_t *port_schedule_state_t); 216 217 /* Reconfigure Sequence Phase 1 Phase 2 */ 218 extern int soc_tomahawk3_flex_mmu_reconfigure_phase1(int unit, 219 soc_port_schedule_state_t *port_schedule_state_t); 220 221 222 extern int soc_tomahawk3_flex_mmu_reconfigure_phase2(int unit, 223 soc_port_schedule_state_t *port_schedule_state_t); 224 225 226 /* Per-block reconfigure functions */ 227 228 extern int soc_tomahawk3_mmu_crb_reconfig(int unit, 229 soc_port_resource_t *port_resource_t); 230 231 extern int soc_tomahawk3_mmu_scb_reconfig(int unit, 232 soc_port_resource_t *port_resource_t); 233 234 extern int soc_tomahawk3_mmu_oqs_reconfig(int unit, 235 soc_port_resource_t *port_resource_t); 236 237 extern int soc_tomahawk3_mmu_ebctm_reconfig(int unit, 238 soc_port_resource_t *port_resource_t, 239 soc_asf_mode_e ct_mode, 240 int mmu_port); 241 242 extern int soc_tomahawk3_mmu_ebpcc_reconfig(int unit, 243 soc_port_resource_t *port_resource_t); 244 245 extern int soc_tomahawk3_mmu_eb_sch_reconfig(int unit, 246 soc_port_resource_t *port_resource_t); 247 248 extern int soc_tomahawk3_mmu_intfo_clr_port_en(int unit, 249 soc_port_schedule_state_t *port_schedule_state_t, 250 int pipe); 251 252 253 extern int soc_tomahawk3_mmu_set_crb_port_mapping(int unit, 254 soc_port_resource_t *port_resource_t); 255 256 extern int soc_tomahawk3_mmu_set_rqe_port_mapping(int unit, 257 soc_port_resource_t *port_resource_t); 258 259 extern int soc_tomahawk3_mmu_set_ebcfp_port_mapping(int unit, 260 soc_port_schedule_state_t *port_schedule_state_t, 261 soc_port_resource_t *port_resource_t); 262 263 extern int soc_tomahawk3_mmu_set_intfi_port_mapping(int unit, 264 soc_port_schedule_state_t *port_schedule_state_t, 265 soc_port_resource_t *port_resource_t); 266 267 extern int soc_tomahawk3_mmu_set_intfo_port_mapping(int unit, 268 soc_port_schedule_state_t *port_schedule_state_t, 269 soc_port_resource_t *port_resource_t); 270 271 extern int soc_tomahawk3_mmu_set_thdo_port_mapping(int unit, 272 soc_port_schedule_state_t *port_schedule_state_t, 273 soc_port_resource_t *port_resource_t); 274 275 276 /* THDO functions */ 277 extern int soc_tomahawk3_mmu_thdo_bst_clr( 278 int unit, 279 soc_port_resource_t *port_resource_t); 280 281 extern int soc_tomahawk3_mmu_thdo_pktstat_clr( 282 int unit, 283 soc_port_resource_t *port_resource_t); 284 285 extern int soc_tomahawk3_mmu_thdo_config( 286 int unit, 287 soc_port_resource_t *port_resource_t); 288 289 extern int soc_tomahawk3_get_max_src_ct_speed(int unit, int dst_speed, 290 int ct_mode, 291 uint32 *max_speed); 292 293 extern void soc_tomahawk3_mmu_get_speed_decode(int unit, int speed, 294 uint32 *speed_decode); 295 296 297 /*** END SDK API COMMON CODE ***/ 298 299 #endif /* _SOC_TOMAHAWK3_MMU_FLEXPORT_H_ */