tomahawk2_mmu_defines.h (6457B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $File: tomahawk2_mmu_defines.h 8 */ 9 10 11 #ifndef TOMAHAWK2_MMU_DEFINES_H 12 #define TOMAHAWK2_MMU_DEFINES_H 13 14 /*! @file tomahawk2_mmu_defines.h 15 * @brief Macros used in APIs of MMU for Tomahawk2. 16 * Details are shown below. 17 */ 18 19 #define TH2_MMU_NUM_L0_NODES_PER_HSP_PORT 10 20 #define TH2_MMU_NUM_L0_NODES_FOR_CPU_PORT 48 21 #define TH2_MMU_NUM_UCQ_PER_HSP_PORT 10 22 #define TH2_MMU_NUM_MCQ_PER_HSP_PORT 10 23 #define TH2_MMU_NUM_MCQ_FOR_CPU_PORT 48 24 #define TH2_MMU_CPU_PORT_NUM 32 25 #define TH2_MMU_MGMT_PORT_NUM 32 26 #define TH2_MMU_MAX_PORTS_PER_PIPE 34 27 #define TH2_MMU_NUM_HSP_PORTS_PER_PIPE 32 28 #define TH2_MMU_LPBK_PORT_NUM 33 29 #define TH2_INVALID_MMU_PORT 255 30 #define TH2_INVALID_PHY_PORT_NUMBER 511 31 #define TH2_INVALID_DEV_PORT_NUMBER 255 32 #define TH2_MMU_PORT_PIPE_OFFSET 64 33 #define TH2_MMU_MCQ_NUMBER_START 330 34 #define TH2_MMU_NUM_UCQ 330 35 #define TH2_MMU_NUM_MC_QUEUES 378 36 #define TH2_MMU_NUM_MCQ_FP_PORTS 320 37 #define TH2_MMU_LPBK_PORT_L1_START TH2_MMU_MCQ_NUMBER_START+ \ 38 TH2_MMU_NUM_MCQ_FP_PORTS 39 #define TH2_MMU_MGMT_CPU_PORT_L1_START TH2_MMU_LPBK_PORT_L1_START+ \ 40 TH2_MMU_NUM_MCQ_PER_HSP_PORT 41 #define TH2_MMU_PIPE1_QUEUE_START TH2_MMU_NUM_UC_QUEUES+TH2_MMU_NUM_MC_QUEUES 42 43 44 #define TH2_MMU_BST_TRACK_MODE 0 45 #define TH2_MMU_BST_WMARK_MODE 1 46 #define TH2_MMU_MEM_ADDR__MEMIDX_WIDTH 16 47 #define TH2_MMU_NUM_XPES 4 48 #define TH2_MMU_NUM_XPES_PER_PIPE 2 49 #define TH2_MMU_NUM_PGS 8 50 #define TH2_MMU_NUM_SPS 4 51 #define TH2_MMU_NUM_COS 10 52 #define TH2_MMU_NUM_UC_QUEUES 330 53 #define TH2_MMU_NUM_QUEUES 330 54 #define TH2_MMU_NUM_PORTS_PER_PIPE 34 55 #define TH2_MMU_ACC_TYPE__ADDR_SPLIT_DIST 10 56 #define TH2_MMU_ACC_TYPE__ADDR_SPLIT_SPLIT 12 57 #define TH2_MMU_ACC_TYPE__DATA_SPLIT 14 58 #define TH2_MMU_ACC_TYPE__DUPLICATE 9 59 #define TH2_MMU_ACC_TYPE__SINGLE 20 60 #define TH2_MMU_ACC_TYPE__UNIQUE 31 61 #define TH2_MMU_ACC_TYPE__UNIQUE_PIPE0 0 62 #define TH2_MMU_ACC_TYPE__UNIQUE_PIPE1 1 63 #define TH2_MMU_ACC_TYPE__UNIQUE_PIPE2 2 64 #define TH2_MMU_ACC_TYPE__UNIQUE_PIPE3 3 65 #define TH2_MMU_BASE_TYPE__XPE 5 66 #define TH2_MMU_BASE_TYPE__CHIP 4 67 #define TH2_MMU_BASE_TYPE__SLICE 6 68 #define TH2_MMU_BASE_TYPE__EPORT 1 69 #define TH2_MMU_BASE_TYPE__IPIPE 2 70 #define TH2_MMU_BASE_TYPE__EPIPE 3 71 #define TH2_MMU_BASE_TYPE__IPORT 0 72 #define TH2_MMU_BASE_TYPE__LAYER 7 73 #define TH2_MMU_THDU_UCQ_PER_PORT 10 74 #define TH2_MMU_THDI_PG_MIN_LIMIT_LOSSLESS 8 75 #define TH2_MMU_THDI_PG_MIN_LIMIT_LOSSY 0 76 #define TH2_MMU_THDI_PG_HDRM_LIMIT_LOSSY 0 77 #define TH2_MMU_THDI_SP_MAX_LIMIT 53248 78 #define TH2_MMU_THDI_SP_RESUME_LIMIT 53232 79 #define TH2_MMU_NUM_SPEEDS 6 80 #define TH2_MMU_NUM_PORT_COLOR_DROP_ENTRIES 5 81 #define TH2_OTP_OFF_NUM_PIPES 2 82 83 #define TH2_MMU_THDI_PORT_XON_ENABLE_VAL 65535 84 #define TH2_MMU_THDU_QGRP_MIN_LIMIT_LOSELESS 16 85 #define TH2_MMU_THDU_QGRP_MIN_LIMIT_LOSSY TH2_MMU_THDU_QGRP_MIN_LIMIT_LOSELESS 86 #define TH2_MMU_THDU_QUEUE_SHARED_ALPHA_LOSSY 8 87 #define TH2_MMU_THDU_QUEUE_SHARED_ALPHA_LOSSLESS 52296 88 #define TH2_MMU_THDU_QUEUE_SHARED_LIMIT_LOSSY 8 89 #define TH2_MMU_THDU_QUEUE_SHARED_LIMIT_LOSSLESS 52296 90 #define TH2_MMU_THDU_QUEUE_LIMIT_DYNAMIC_LOSSY 1 91 #define TH2_MMU_THDU_QUEUE_LIMIT_DYNAMIC_LOSSLESS 0 92 #define TH2_MMU_THDU_QUEUE_COLOR_LIMIT_DYNAMIC_LOSSY 1 93 #define TH2_MMU_THDU_QUEUE_COLOR_LIMIT_DYNAMIC_LOSSLESS 0 94 #define TH2_MMU_THDU_QUEUE_LIMIT_ENABLE_LOSSY 1 95 #define TH2_MMU_THDU_QUEUE_LIMIT_ENABLE_LOSSLESS 0 96 #define TH2_MMU_NUM_CT_SPEED_GROUPS 12 97 #define TH2_MAX_NUM_CELLS 46 /* (9416-144)/208 + 1 SOP Cell */ 98 #define TH2_CT_FIFO_WAIT 15 /*Refer to port_down seq. in TH2 flexport arch */ 99 #define TH2_MMU_PAUSE_PG 7 /*PG7-Used for Initial PG_Min/hdrm + for Pause */ 100 101 typedef enum pipe_s 102 { 103 TH2_IPIPE, 104 TH2_EPIPE 105 } pipe_t; 106 107 #define TH2_MMU_MEM_ADDR__MEMIDX_WIDTH 16 108 #define TH2_MMU_FLUSH_OFF 0 109 #define TH2_MMU_FLUSH_ON 1 110 #define TH2_PKTSTATS_ON 1 111 #define TH2_MMU_THD_RX_ENABLED 1 112 #define TH2_MMU_THD_RX_DISABLED 0 113 114 #define TH2_MMU_IS_CPU_PORT(pipe, port) ((pipe == 0) && \ 115 (port == TH2_MMU_CPU_PORT_NUM)) 116 #define TH2_MMU_IS_MGMT_PORT(pipe, \ 117 port) ((pipe == 1 || \ 118 pipe == 2) && \ 119 (port == TH2_MMU_MGMT_PORT_NUM)) 120 #define TH2_MMU_IS_LPBK_PORT(port) (port == TH2_MMU_LPBK_PORT_NUM) 121 #define TH2_MMU_GET_PIPE_NUM(port, pipe) \ 122 pipe = port/TH2_MMU_PORT_PIPE_OFFSET 123 #define TH2_MMU_PIPE_NUM(port) port/TH2_MMU_PORT_PIPE_OFFSET 124 125 #define TH2_MMU_HANDLE_ENUMS_EPIPE_DUPLICATE(mem_name) \ 126 soc_mem_t mem_name ## _enums[4][2] = \ 127 {{mem_name ## _PIPE0m, \ 128 -1}, \ 129 {mem_name ## _PIPE1m, \ 130 -1}, {mem_name ## _PIPE2m, -1}, {mem_name ## _PIPE3m, -1}} 131 132 #define TH2_MMU_HANDLE_ENUMS_IPIPE_DUPLICATE(mem_name) \ 133 soc_mem_t mem_name ## _enums[4][2] = \ 134 {{mem_name ## _PIPE0m, \ 135 -1}, \ 136 {mem_name ## _PIPE1m, \ 137 -1}, {mem_name ## _PIPE2m, -1}, {mem_name ## _PIPE3m, -1}} 138 139 #define TH2_MMU_HANDLE_ENUMS_EPIPE_UNIQUE(mem_name) \ 140 soc_mem_t mem_name ## _enums[4][2] = \ 141 {{mem_name ## _XPE0_PIPE0m, \ 142 mem_name ## _XPE2_PIPE0m}, \ 143 {mem_name ## _XPE0_PIPE1m, \ 144 mem_name ## _XPE2_PIPE1m}, \ 145 {mem_name ## _XPE1_PIPE2m, \ 146 mem_name ## _XPE3_PIPE2m}, \ 147 {mem_name ## _XPE1_PIPE3m, mem_name ## _XPE3_PIPE3m}}; \ 148 149 #define TH2_MMU_HANDLE_ENUMS_IPIPE_UNIQUE(mem_name) \ 150 soc_mem_t mem_name ## _enums[4][2] = \ 151 {{mem_name ## _XPE0_PIPE0m, \ 152 mem_name ## _XPE1_PIPE0m}, \ 153 {mem_name ## _XPE2_PIPE1m, \ 154 mem_name ## _XPE3_PIPE1m}, \ 155 {mem_name ## _XPE2_PIPE2m, \ 156 mem_name ## _XPE3_PIPE2m}, \ 157 {mem_name ## _XPE0_PIPE3m, mem_name ## _XPE1_PIPE3m}}; \ 158 159 #define TH2_MMU_GET_HANDLE(mem_name, base_index, acc_index, handle) \ 160 handle = mem_name ## _enums[base_index][acc_index] 161 162 /* START - FlexPort types as defined in SDK. */ 163 typedef enum { 164 TH2_SPEED_10G_ETH_DECODE = 1, 165 TH2_SPEED_10G_HG_DECODE = 2, 166 TH2_SPEED_20G_ETH_DECODE = 3, 167 TH2_SPEED_20G_HG_DECODE = 4, 168 TH2_SPEED_25G_ETH_DECODE = 5, 169 TH2_SPEED_25G_HG_DECODE = 6, 170 TH2_SPEED_40G_ETH_DECODE = 7, 171 TH2_SPEED_40G_HG_DECODE = 8, 172 TH2_SPEED_50G_ETH_DECODE = 9, 173 TH2_SPEED_50G_HG_DECODE = 10, 174 TH2_SPEED_100G_ETH_DECODE = 11, 175 TH2_SPEED_100G_HG_DECODE = 12 176 } _soc_th2_ct_speed_decode_e; 177 178 #endif /* TOMAHAWK2_MMU_DEFINES_H */