maverick2_mmu_defines.h (6283B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $File: maverick2_mmu_defines.h 8 */ 9 10 11 #ifndef MAVERICK2_MMU_DEFINES_H 12 #define MAVERICK2_MMU_DEFINES_H 13 14 /*! @file maverick2_mmu_defines.h 15 * @brief Macros used in APIs of MMU for Tomahawk2. 16 * Details are shown below. 17 */ 18 19 #define MV2_MMU_NUM_L0_NODES_PER_HSP_PORT 10 20 #define MV2_MMU_NUM_L0_NODES_FOR_CPU_PORT 48 21 #define MV2_MMU_NUM_UCQ_PER_HSP_PORT 10 22 #define MV2_MMU_NUM_MCQ_PER_HSP_PORT 10 23 #define MV2_MMU_NUM_MCQ_FOR_CPU_PORT 48 24 #define MV2_MMU_CPU_PORT_NUM 64 25 #define MV2_MMU_MGMT_PORT_NUM 63 26 #define MV2_MMU_MAX_PORTS_PER_PIPE 66 27 #define MV2_MMU_NUM_HSP_PORTS_PER_PIPE 66 28 #define MV2_MMU_LPBK_PORT_NUM 65 29 #define MV2_INVALID_MMU_PORT 255 30 #define MV2_INVALID_PHY_PORT_NUMBER 255 31 #define MV2_INVALID_DEV_PORT_NUMBER 255 32 #define MV2_MMU_PORT_PIPE_OFFSET 128 33 #define MV2_MMU_MCQ_NUMBER_START 660 34 #define MV2_MMU_NUM_UCQ 640 35 #define MV2_MMU_NUM_MC_QUEUES 698 36 #define MV2_MMU_NUM_MCQ_FP_PORTS 640 37 #define MV2_MMU_LPBK_PORT_L1_START MV2_MMU_MCQ_NUMBER_START+ \ 38 MV2_MMU_NUM_MCQ_FP_PORTS 39 #define MV2_MMU_MGMT_CPU_PORT_L1_START MV2_MMU_LPBK_PORT_L1_START+ \ 40 MV2_MMU_NUM_MCQ_PER_HSP_PORT 41 #define MV2_MMU_PIPE1_QUEUE_START MV2_MMU_NUM_UC_QUEUES+MV2_MMU_NUM_MC_QUEUES 42 43 44 #define MV2_MMU_BST_TRACK_MODE 0 45 #define MV2_MMU_BST_WMARK_MODE 1 46 #define MV2_MMU_MEM_ADDR__MEMIDX_WIDTH 16 47 #define MV2_MMU_NUM_PGS 8 48 #define MV2_MMU_NUM_SPS 4 49 #define MV2_MMU_NUM_COS 10 50 #define MV2_MMU_NUM_UC_QUEUES 640 51 #define MV2_MMU_NUM_PORTS_PER_PIPE 66 52 #define MV2_MMU_ACC_TYPE__ADDR_SPLIT_DIST 10 53 #define MV2_MMU_ACC_TYPE__ADDR_SPLIT_SPLIT 12 54 #define MV2_MMU_ACC_TYPE__DATA_SPLIT 14 55 #define MV2_MMU_ACC_TYPE__DUPLICATE 9 56 #define MV2_MMU_ACC_TYPE__SINGLE 20 57 #define MV2_MMU_ACC_TYPE__UNIQUE 31 58 #define MV2_MMU_ACC_TYPE__UNIQUE_PIPE0 0 59 #define MV2_MMU_ACC_TYPE__UNIQUE_PIPE1 1 60 #define MV2_MMU_ACC_TYPE__UNIQUE_PIPE2 2 61 #define MV2_MMU_ACC_TYPE__UNIQUE_PIPE3 3 62 #define MV2_MMU_BASE_TYPE__XPE 5 63 #define MV2_MMU_BASE_TYPE__CHIP 4 64 #define MV2_MMU_BASE_TYPE__SLICE 6 65 #define MV2_MMU_BASE_TYPE__EPORT 1 66 #define MV2_MMU_BASE_TYPE__IPIPE 2 67 #define MV2_MMU_BASE_TYPE__EPIPE 3 68 #define MV2_MMU_BASE_TYPE__IPORT 0 69 #define MV2_MMU_BASE_TYPE__LAYER 7 70 #define MV2_MMU_THDU_UCQ_PER_PORT 10 71 #define MV2_MMU_THDI_PG_MIN_LIMIT_LOSSLESS 7 72 #define MV2_MMU_THDI_PG_MIN_LIMIT_LOSSY 0 73 #define MV2_MMU_THDI_PG_HDRM_LIMIT_LOSSY 0 74 #define MV2_MMU_THDI_SP_MAX_LIMIT 129024 75 #define MV2_MMU_THDI_SP_RESUME_LIMIT 129024 76 #define MV2_MMU_NUM_SPEEDS 7 77 #define MV2_MMU_NUM_PORT_COLOR_DROP_ENTRIES 5 78 79 #define MV2_MMU_THDI_PORT_XON_ENABLE_VAL 65535 80 #define MV2_MMU_THDU_QGRP_MIN_LIMIT_LOSELESS 14 81 #define MV2_MMU_THDU_QGRP_MIN_LIMIT_LOSSY MV2_MMU_THDU_QGRP_MIN_LIMIT_LOSELESS 82 #define MV2_MMU_THDU_QUEUE_SHARED_ALPHA_LOSSY 8 83 #define MV2_MMU_THDU_QUEUE_SHARED_ALPHA_LOSSLESS 127645 84 #define MV2_MMU_THDU_QUEUE_SHARED_LIMIT_LOSSY 8 85 #define MV2_MMU_THDU_QUEUE_SHARED_LIMIT_LOSSLESS 127645 86 #define MV2_MMU_THDU_QUEUE_LIMIT_DYNAMIC_LOSSY 1 87 #define MV2_MMU_THDU_QUEUE_LIMIT_DYNAMIC_LOSSLESS 0 88 #define MV2_MMU_THDU_QUEUE_COLOR_LIMIT_DYNAMIC_LOSSY 1 89 #define MV2_MMU_THDU_QUEUE_COLOR_LIMIT_DYNAMIC_LOSSLESS 0 90 #define MV2_MMU_THDU_QUEUE_LIMIT_ENABLE_LOSSY 1 91 #define MV2_MMU_THDU_QUEUE_LIMIT_ENABLE_LOSSLESS 0 92 #define MV2_MMU_NUM_CT_SPEED_GROUPS 12 93 #define MV2_MAX_NUM_CELLS 37 /* (9416-192)/256 + 1 SOP Cell */ 94 #define MV2_CT_FIFO_WAIT 15 /*Refer to port_down seq. in TH2 flexport arch */ 95 #define MV2_MMU_PAUSE_PG 7 /*PG7-Used for Initial PG_Min/hdrm + for Pause */ 96 typedef enum pipe_s 97 { 98 MV2_IPIPE, 99 MV2_EPIPE 100 } pipe_t; 101 102 #define MV2_MMU_MEM_ADDR__MEMIDX_WIDTH 16 103 #define MV2_MMU_FLUSH_OFF 0 104 #define MV2_MMU_FLUSH_ON 1 105 #define MV2_PKTSTATS_ON 1 106 #define MV2_MMU_THD_RX_ENABLED 1 107 #define MV2_MMU_THD_RX_DISABLED 0 108 109 #define MV2_MMU_IS_CPU_PORT(pipe, port) ((pipe == 0) && \ 110 (port == MV2_MMU_CPU_PORT_NUM)) 111 #define MV2_MMU_IS_MGMT_PORT(pipe, \ 112 port) ((pipe == 1) && \ 113 (port == MV2_MMU_MGMT_PORT_NUM)) 114 #define MV2_MMU_IS_LPBK_PORT(port) (port == MV2_MMU_LPBK_PORT_NUM) 115 #define MV2_MMU_GET_PIPE_NUM(port, pipe) \ 116 pipe = port/MV2_MMU_PORT_PIPE_OFFSET 117 #define MV2_MMU_PIPE_NUM(port) port/MV2_MMU_PORT_PIPE_OFFSET 118 119 #define MV2_MMU_HANDLE_ENUMS_EPIPE_DUPLICATE(mem_name) \ 120 soc_mem_t mem_name ## _enums[4][2] = \ 121 {{mem_name ## _PIPE0m, \ 122 -1}, \ 123 {mem_name ## _PIPE1m, \ 124 -1}, {mem_name ## _PIPE2m, -1}, {mem_name ## _PIPE3m, -1}} 125 126 #define MV2_MMU_HANDLE_ENUMS_IPIPE_DUPLICATE(mem_name) \ 127 soc_mem_t mem_name ## _enums[4][2] = \ 128 {{mem_name ## _PIPE0m, \ 129 -1}, \ 130 {mem_name ## _PIPE1m, \ 131 -1}, {mem_name ## _PIPE2m, -1}, {mem_name ## _PIPE3m, -1}} 132 133 #define MV2_MMU_HANDLE_ENUMS_EPIPE_UNIQUE(mem_name) \ 134 soc_mem_t mem_name ## _enums[4][2] = \ 135 {{mem_name ## _XPE0_PIPE0m, \ 136 mem_name ## _XPE2_PIPE0m}, \ 137 {mem_name ## _XPE0_PIPE1m, \ 138 mem_name ## _XPE2_PIPE1m}, \ 139 {mem_name ## _XPE1_PIPE2m, \ 140 mem_name ## _XPE3_PIPE2m}, \ 141 {mem_name ## _XPE1_PIPE3m, mem_name ## _XPE3_PIPE3m}}; \ 142 143 #define MV2_MMU_HANDLE_ENUMS_IPIPE_UNIQUE(mem_name) \ 144 soc_mem_t mem_name ## _enums[4][2] = \ 145 {{mem_name ## _XPE0_PIPE0m, \ 146 mem_name ## _XPE1_PIPE0m}, \ 147 {mem_name ## _XPE2_PIPE1m, \ 148 mem_name ## _XPE3_PIPE1m}, \ 149 {mem_name ## _XPE2_PIPE2m, \ 150 mem_name ## _XPE3_PIPE2m}, \ 151 {mem_name ## _XPE0_PIPE3m, mem_name ## _XPE1_PIPE3m}}; \ 152 153 #define MV2_MMU_GET_HANDLE(mem_name, base_index, acc_index, handle) \ 154 handle = mem_name ## _enums[base_index][acc_index] 155 156 /* START - FlexPort types as defined in SDK. */ 157 typedef enum { 158 MV2_SPEED_10G_ETH_DECODE = 1, 159 MV2_SPEED_10G_HG_DECODE = 2, 160 MV2_SPEED_20G_ETH_DECODE = 3, 161 MV2_SPEED_20G_HG_DECODE = 4, 162 MV2_SPEED_25G_ETH_DECODE = 5, 163 MV2_SPEED_25G_HG_DECODE = 6, 164 MV2_SPEED_40G_ETH_DECODE = 7, 165 MV2_SPEED_40G_HG_DECODE = 8, 166 MV2_SPEED_50G_ETH_DECODE = 9, 167 MV2_SPEED_50G_HG_DECODE = 10, 168 MV2_SPEED_100G_ETH_DECODE = 11, 169 MV2_SPEED_100G_HG_DECODE = 12 170 } _soc_mv2_ct_speed_decode_e; 171 172 #endif /* MAVERICK2_MMU_DEFINES_H */