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maverick2_flexport.h (6446B)

      1 /*
      2 * 
      3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      4 * 
      5 * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      6 *
      7 * $File:  maverick2_flexport.h
      8 */
      9 
     10 
     11 #ifndef SOC_MAVERICK2_FLEXPORT_H
     12 #define SOC_MAVERICK2_FLEXPORT_H
     13 
     14 #include <soc/flexport/flexport_common.h>
     15 
     16 /*** START SDK API COMMON CODE ***/
     17 
     18 /*! @file maverick2_flexport.h
     19     @brief FlexPort functions and structures for Trident3.
     20     Details are shown below.
     21 */
     22 
     23 #include <soc/flexport/maverick2/maverick2_flexport_defines.h>
     24 
     25 #include <soc/flexport/maverick2/maverick2_tdm_flexport.h>
     26 #include <soc/flexport/maverick2/maverick2_idb_flexport.h>
     27 #include <soc/flexport/maverick2/maverick2_ep_flexport.h>
     28 #include <soc/flexport/maverick2/maverick2_mac_flexport.h>
     29 #include <soc/flexport/maverick2/maverick2_mmu_flex_init.h>
     30 
     31 
     32 /*! @struct soc_maverick2_flex_scratch_t
     33     @brief Scratch pad locals. Caller must not allocate. Callee allocates 
     34            at entry and deallocates before return. This area is pointed 
     35            to by the cookie in soc_port_schedule_state_t struct type.
     36 */
     37 typedef struct soc_maverick2_flex_scratch_s {
     38     /*!< Previous OVS tables needed by the OVS consolidation sequence */
     39     soc_tdm_schedule_pipe_t   prev_tdm_ingress_schedule_pipe[SOC_MAX_NUM_PIPES];
     40     soc_tdm_schedule_pipe_t   prev_tdm_egress_schedule_pipe[SOC_MAX_NUM_PIPES];
     41     /*!< Current state of OVS tables; is changing during flexport sequence
     42          initial state is prev OVS tables and after OVS flexport sequence 
     43          converges to new_ OVS tables*/
     44     soc_tdm_schedule_pipe_t   curr_tdm_ingress_schedule_pipe[SOC_MAX_NUM_PIPES];
     45     soc_tdm_schedule_pipe_t   curr_tdm_egress_schedule_pipe[SOC_MAX_NUM_PIPES];
     46     /*!< Previous and new Oversub ratios; per PIPE and per HALF PIPE
     47      * These are coded as follows:
     48      *  10  - this is LR;
     49      *  15  - this is OVS with 3:2;         ovs_ratio <= 1.5;
     50      *  20  - this is OVS with 2:1;  1.5 <  ovs_ratio <= 2.0;
     51      */
     52     int prev_pipe_ovs_ratio[SOC_MAX_NUM_PIPES]; /* per PIPE ovs_ratio
     53                                                  * per Half PIPE ovs_ratio */
     54     int prev_hpipe_ovs_ratio[SOC_MAX_NUM_PIPES][MAVERICK2_OVS_HPIPE_COUNT_PER_PIPE];
     55     int new_pipe_ovs_ratio[SOC_MAX_NUM_PIPES]; /* per PIPE ovs_ratio
     56                                                 * per Half PIPE ovs_ratio */
     57     int new_hpipe_ovs_ratio[SOC_MAX_NUM_PIPES][MAVERICK2_OVS_HPIPE_COUNT_PER_PIPE];
     58 
     59     /* This keeps the exact bitrate of the out_port_map.log_port_speed[] */
     60     enum port_speed_e exact_out_log_port_speed[SOC_MAX_NUM_PORTS];
     61 } soc_maverick2_flex_scratch_t;
     62 
     63 
     64 /*! @fn void *soc_maverick2_port_lane_info_alloc(void)
     65     @brief Allocates memory pointed to by soc_port_lane_info_t. Need this 
     66            special function because SystemVerilog-C DPI limitations in 
     67            synchronizing memory space that is a pointer to a struct type.
     68            Since s/w owns the the pointer to soc_port_lane_info_t struct
     69            in soc_port_resource_t, we cannot change it.
     70 */
     71 extern void *soc_maverick2_port_lane_info_alloc (
     72   void
     73   );
     74 
     75 
     76 /*! @fn int soc_maverick2_set_port_lane_info(int unit, const void *lane_info_ptr, int port_idx, int pgw, int xlp)
     77     @param unit Chip unit number.
     78     @param lane_info_ptr Pointer to a soc_port_lane_info_t struct variable. 
     79     @param port_idx Index within XLP.
     80     @param pgw PGW instance where lane resides.
     81     @param xlp XLP number within PGW.
     82     @brief Sets all members in a soc_port_lane_info_t struct variable.  
     83 */
     84 extern int soc_maverick2_set_port_lane_info (
     85   int unit,
     86   const void *lane_info_ptr,
     87   int port_idx, 
     88   int pgw,
     89   int xlp
     90   );
     91 
     92 
     93 /*! @fn int soc_maverick2_get_port_lane_info(int unit, const void *lane_info_ptr, int *port_idx, int *pgw, int *xlp)
     94     @param unit Chip unit number.
     95     @param lane_info_ptr Pointer to a soc_port_lane_info_t struct variable. 
     96     @param port_idx Index within XLP.
     97     @param pgw PGW instance where lane resides.
     98     @param xlp XLP number within PGW.
     99     @brief Gets all members in a soc_port_lane_info_t struct variable.  
    100 */
    101 extern int soc_maverick2_get_port_lane_info (
    102   int unit,
    103   const void *lane_info_ptr,
    104   int *port_idx, 
    105   int *pgw,
    106   int *xlp
    107   );
    108 
    109 
    110 /*! @fn int soc_maverick2_reconfigure_ports(int unit, soc_port_schedule_state_t *port_schedule_state)
    111     @param unit Chip unit number.
    112     @param port_schedule_state Pointer to data holding all required information for FlexPort opeations. 
    113     @brief Top-level call carrying out all FlexPort functionalities.
    114 */
    115 extern int soc_maverick2_reconfigure_ports (
    116   int unit,
    117   soc_port_schedule_state_t *port_schedule_state
    118   );
    119 
    120 
    121 /*! @fn int soc_maverick2_flex_start(int unit, soc_port_schedule_state_t *port_schedule_state)
    122     @param unit Chip unit number.
    123     @param port_schedule_state Pointer to data holding all required information for FlexPort opeations. 
    124     @brief The start of FlexPort series of operations along with allocations of required program memory.
    125 */
    126 extern int soc_maverick2_flex_start (
    127   int unit,
    128   soc_port_schedule_state_t *port_schedule_state
    129   );
    130 
    131 
    132 /*! @fn int soc_maverick2_flex_end(int unit, soc_port_schedule_state_t *port_schedule_state)
    133     @param unit Chip unit number.
    134     @param port_schedule_state Pointer to data holding all required information for FlexPort opeations. 
    135     @brief The end of FlexPort series of operations along with deallocations of program memory.
    136 */
    137 extern int soc_maverick2_flex_end (
    138   int unit,
    139   soc_port_schedule_state_t *port_schedule_state
    140   );
    141 
    142 
    143 extern int soc_maverick2_flex_top_port_down (
    144     int                        unit,
    145     soc_port_schedule_state_t *port_schedule_state
    146     );
    147 
    148 
    149 extern int soc_maverick2_flex_top_port_up (
    150     int                        unit,
    151     soc_port_schedule_state_t *port_schedule_state
    152     );
    153 
    154 extern int soc_maverick2_get_ct_class(int speed);
    155 
    156 /*! @fn int (*mv2_flexport_phases[MAX_FLEX_PHASES]) (int unit, soc_port_schedule_state_t *port_schedule_state)
    157     @param unit Chip unit number.
    158     @param port_schedule_state Pointer to data holding all required information for FlexPort opeations. 
    159     @brief Phase control array containing the right sequence of FlexPort phases implemented as functions.
    160 */
    161 extern int (*mv2_flexport_phases[MAX_FLEX_PHASES]) (int unit, soc_port_schedule_state_t *port_schedule_state);
    162 
    163 
    164 /*** END SDK API COMMON CODE ***/
    165 
    166 #endif /* SOC_MAVERICK2_FLEXPORT_H */
    167