helix5_mmu_defines.h (9158B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 * File: helix5_mmu_defines.h 7 * Purpose: 8 * Requires: 9 */ 10 11 #ifndef HELIX5_MMU_DEFINES_H 12 #define HELIX5_MMU_DEFINES_H 13 14 /*! @file helix5_mmu_defines.h 15 * @brief Macros used in APIs of MMU for Tomahawk2. 16 * Details are shown below. 17 */ 18 #define HX5_MMU_NUM_DL_PORTS 54 19 #define HX5_MMU_NUM_UP_PORTS 16 20 #define HX5_MMU_NUM_NORMAL_PORTS 70 21 #define HX5_MMU_NUM_L0_NODES_PER_HSP_DL_PORT 1 22 #define HX5_MMU_NUM_L0_NODES_PER_HSP_UP_PORT 3 23 #define HX5_MMU_NUM_L0_NODES_CPU_PORT 1 24 #define HX5_MMU_NUM_L0_NODES_LPBK_PORT 1 25 #define HX5_MMU_NUM_L1_NODES_PER_HSP_DL_PORT 2 26 #define HX5_MMU_NUM_L1_NODES_PER_HSP_UP_PORT 4 27 #define HX5_MMU_NUM_L1_NODES_CPU_PORT 1 28 #define HX5_MMU_NUM_L1_NODES_LPBK_PORT 1 29 #define HX5_MMU_NUM_L2_NODES_PER_HSP_DL_PORT 16 30 #define HX5_MMU_NUM_L2_NODES_PER_HSP_UP_PORT 26 31 #define HX5_MMU_NUM_L2_NODES_CPU_PORT 10 32 #define HX5_MMU_NUM_L2_NODES_LPBK_PORT 10 33 #define HX5_MMU_NUM_L3_NODES_CPU_PORT 48 34 #define HX5_MMU_NUM_L3_NODES_LPBK_PORT 10 35 /* #define HX5_MMU_NUM_L3_NODES_PER_HSP_DL_PORT 32 */ 36 /* #define HX5_MMU_NUM_L3_NODES_PER_HSP_UP_PORT 52 */ 37 #define HX5_MMU_NUM_UCQ_PER_HSP_DL_PORT 16 38 #define HX5_MMU_NUM_MCQ_PER_HSP_DL_PORT 16 39 #define HX5_MMU_NUM_UCQ_PER_HSP_UP_PORT 26 40 #define HX5_MMU_NUM_MCQ_PER_HSP_UP_PORT 26 41 /* #define HX5_MMU_NUM_L0_NODES_PER_HSP_PORT 10 */ 42 /* #define HX5_MMU_NUM_L0_NODES_FOR_CPU_PORT 48 */ 43 /* #define HX5_MMU_NUM_UCQ_PER_HSP_PORT 10 */ 44 /* #define HX5_MMU_NUM_MCQ_PER_HSP_PORT 10 */ 45 #define HX5_MMU_NUM_MCQ_FOR_CPU_PORT 48 46 #define HX5_MMU_CPU_PORT_NUM 70 47 /* #define HX5_MMU_MGMT_PORT_NUM 64 */ 48 #define HX5_MMU_MAX_PORTS_PER_PIPE 72 49 #define HX5_MMU_NUM_HSP_PORTS_PER_PIPE 72 50 #define HX5_MMU_LPBK_PORT_NUM 71 51 #define HX5_INVALID_MMU_PORT 255 52 #define HX5_INVALID_PHY_PORT_NUMBER 255 53 #define HX5_INVALID_DEV_PORT_NUMBER 255 54 #define HX5_MMU_PORT_PIPE_OFFSET 72 55 #define HX5_MMU_MCQ_NUMBER_START 1280 56 #define HX5_MMU_NUM_UCQ 1280 57 #define HX5_MMU_NUM_MC_QUEUES 1338 58 #define HX5_MMU_NUM_MCQ_FP_PORTS 1280 59 #define HX5_MMU_LPBK_PORT_L0_START HX5_MMU_NUM_DL_PORTS*HX5_MMU_NUM_L0_NODES_PER_HSP_DL_PORT + \ 60 HX5_MMU_NUM_UP_PORTS*HX5_MMU_NUM_L0_NODES_PER_HSP_UP_PORT 61 #define HX5_MMU_LPBK_PORT_L1_START HX5_MMU_NUM_DL_PORTS*HX5_MMU_NUM_L1_NODES_PER_HSP_DL_PORT + \ 62 HX5_MMU_NUM_UP_PORTS*HX5_MMU_NUM_L1_NODES_PER_HSP_UP_PORT 63 #define HX5_MMU_LPBK_PORT_L2_START HX5_MMU_NUM_DL_PORTS*HX5_MMU_NUM_L2_NODES_PER_HSP_DL_PORT + \ 64 HX5_MMU_NUM_UP_PORTS*HX5_MMU_NUM_L2_NODES_PER_HSP_UP_PORT 65 #define HX5_MMU_LPBK_PORT_L3_START HX5_MMU_MCQ_NUMBER_START+ \ 66 HX5_MMU_NUM_MCQ_FP_PORTS 67 #define HX5_MMU_CPU_PORT_L0_START HX5_MMU_LPBK_PORT_L0_START+ \ 68 HX5_MMU_NUM_L0_NODES_LPBK_PORT 69 #define HX5_MMU_CPU_PORT_L1_START HX5_MMU_LPBK_PORT_L1_START+ \ 70 HX5_MMU_NUM_L1_NODES_LPBK_PORT 71 #define HX5_MMU_CPU_PORT_L2_START HX5_MMU_LPBK_PORT_L2_START+ \ 72 HX5_MMU_NUM_L2_NODES_LPBK_PORT 73 #define HX5_MMU_CPU_PORT_L3_START HX5_MMU_LPBK_PORT_L3_START+ \ 74 HX5_MMU_NUM_L3_NODES_LPBK_PORT 75 /*#define HX5_MMU_MGMT_CPU_PORT_L3_START HX5_MMU_LPBK_PORT_L3_START+ \ 76 * HX5_MMU_NUM_MCQ_PER_HSP_PORT 77 * #define HX5_MMU_LPBK_PORT_L1_START HX5_MMU_MCQ_NUMBER_START+ \ 78 * HX5_MMU_NUM_MCQ_FP_PORTS 79 * #define HX5_MMU_MGMT_CPU_PORT_L1_START HX5_MMU_LPBK_PORT_L1_START+ \ 80 * HX5_MMU_NUM_MCQ_PER_HSP_PORT 81 * #define HX5_MMU_PIPE1_QUEUE_START HX5_MMU_NUM_UC_QUEUES+HX5_MMU_NUM_MC_QUEUES 82 */ 83 84 #define HX5_MMU_BST_TRACK_MODE 0 85 #define HX5_MMU_BST_WMARK_MODE 1 86 #define HX5_MMU_MEM_ADDR__MEMIDX_WIDTH 16 87 #define HX5_MMU_NUM_PGS 8 88 #define HX5_MMU_NUM_SPS 4 89 /* #define HX5_MMU_NUM_COS 10 */ 90 /* #define HX5_MMU_NUM_COS 10 */ 91 #define HX5_MMU_NUM_UC_QUEUES 1280 92 /* define HX5_MMU_ACC_TYPE__ADDR_SPLIT_DIST 10 93 * #define HX5_MMU_ACC_TYPE__ADDR_SPLIT_SPLIT 12 94 */ 95 #define HX5_MMU_ACC_TYPE__DATA_SPLIT 14 96 #define HX5_MMU_ACC_TYPE__DUPLICATE 9 97 #define HX5_MMU_ACC_TYPE__SINGLE 20 98 #define HX5_MMU_ACC_TYPE__UNIQUE 31 99 #define HX5_MMU_ACC_TYPE__UNIQUE_PIPE0 0 100 #define HX5_MMU_ACC_TYPE__UNIQUE_PIPE1 1 101 #define HX5_MMU_ACC_TYPE__UNIQUE_PIPE2 2 102 #define HX5_MMU_ACC_TYPE__UNIQUE_PIPE3 3 103 #define HX5_MMU_BASE_TYPE__XPE 5 104 #define HX5_MMU_BASE_TYPE__CHIP 4 105 #define HX5_MMU_BASE_TYPE__SLICE 6 106 #define HX5_MMU_BASE_TYPE__EPORT 1 107 #define HX5_MMU_BASE_TYPE__IPIPE 2 108 #define HX5_MMU_BASE_TYPE__EPIPE 3 109 #define HX5_MMU_BASE_TYPE__IPORT 0 110 #define HX5_MMU_BASE_TYPE__LAYER 7 111 /* #define HX5_MMU_THDU_UCQ_PER_PORT 10 */ 112 #define HX5_MMU_THDU_UCQ_PER_UP_PORT 26 113 #define HX5_MMU_THDU_UCQ_PER_DL_PORT 16 114 #define HX5_MMU_THDI_PG_MIN_LIMIT_LOSSLESS 8 115 #define HX5_MMU_THDI_PG_MIN_LIMIT_LOSSY 0 116 #define HX5_MMU_THDI_PG_HDRM_LIMIT_LOSSY 0 117 #define HX5_MMU_THDI_SP_MAX_LIMIT 32768 118 #define HX5_MMU_THDI_SP_RESUME_LIMIT 32754 119 #define HX5_MMU_NUM_SPEEDS 9 120 #define HX5_MMU_NUM_PORT_COLOR_DROP_ENTRIES 5 121 122 #define HX5_MMU_THDI_PORT_XON_ENABLE_VAL 65535 123 #define HX5_MMU_THDU_QGRP_MIN_LIMIT_LOSELESS 14 124 #define HX5_MMU_THDU_QGRP_MIN_LIMIT_LOSSY HX5_MMU_THDU_QGRP_MIN_LIMIT_LOSELESS 125 #define HX5_MMU_THDU_QUEUE_SHARED_ALPHA_LOSSY 8 126 #define HX5_MMU_THDU_QUEUE_SHARED_ALPHA_LOSSLESS 32691 127 #define HX5_MMU_THDU_QUEUE_SHARED_LIMIT_LOSSY 8 128 #define HX5_MMU_THDU_QUEUE_SHARED_LIMIT_LOSSLESS 32691 129 #define HX5_MMU_THDU_QUEUE_LIMIT_DYNAMIC_LOSSY 1 130 #define HX5_MMU_THDU_QUEUE_LIMIT_DYNAMIC_LOSSLESS 0 131 #define HX5_MMU_THDU_QUEUE_COLOR_LIMIT_DYNAMIC_LOSSY 1 132 #define HX5_MMU_THDU_QUEUE_COLOR_LIMIT_DYNAMIC_LOSSLESS 0 133 #define HX5_MMU_THDU_QUEUE_LIMIT_ENABLE_LOSSY 1 134 #define HX5_MMU_THDU_QUEUE_LIMIT_ENABLE_LOSSLESS 0 135 #define HX5_MMU_NUM_CT_SPEED_GROUPS 12 136 #define HX5_MAX_NUM_CELLS 37 /* (9416-192)/256 + 1 SOP Cell */ 137 #define HX5_CT_FIFO_WAIT 15 /*Refer to port_down seq. in TH2 flexport arch */ 138 139 typedef enum pipe_s 140 { 141 HX5_IPIPE, 142 HX5_EPIPE 143 } pipe_t; 144 145 #define HX5_MMU_MEM_ADDR__MEMIDX_WIDTH 16 146 #define HX5_MMU_FLUSH_OFF 0 147 #define HX5_MMU_FLUSH_ON 1 148 #define HX5_PKTSTATS_ON 1 149 #define HX5_MMU_THD_RX_ENABLED 1 150 #define HX5_MMU_THD_RX_DISABLED 0 151 152 #define HX5_MMU_IS_CPU_PORT(pipe, port) ((pipe == 0) && \ 153 (port == HX5_MMU_CPU_PORT_NUM)) 154 /*#define HX5_MMU_IS_MGMT_PORT(pipe, \ 155 * port) ((pipe == 1) && \ 156 * (port == HX5_MMU_MGMT_PORT_NUM)) 157 */ 158 #define HX5_MMU_IS_LPBK_PORT(port) (port == HX5_MMU_LPBK_PORT_NUM) 159 #define HX5_MMU_GET_PIPE_NUM(port, pipe) \ 160 pipe = port/HX5_MMU_PORT_PIPE_OFFSET 161 #define HX5_MMU_PIPE_NUM(port) port/HX5_MMU_PORT_PIPE_OFFSET 162 163 #define HX5_MMU_HANDLE_ENUMS_EPIPE_DUPLICATE(mem_name) \ 164 soc_mem_t mem_name ## _enums[4][2] = \ 165 {{mem_name ## _PIPE0m, \ 166 -1}, \ 167 {mem_name ## _PIPE1m, \ 168 -1}, {mem_name ## _PIPE2m, -1}, {mem_name ## _PIPE3m, -1}} 169 170 #define HX5_MMU_HANDLE_ENUMS_IPIPE_DUPLICATE(mem_name) \ 171 soc_mem_t mem_name ## _enums[4][2] = \ 172 {{mem_name ## _PIPE0m, \ 173 -1}, \ 174 {mem_name ## _PIPE1m, \ 175 -1}, {mem_name ## _PIPE2m, -1}, {mem_name ## _PIPE3m, -1}} 176 177 #define HX5_MMU_HANDLE_ENUMS_EPIPE_UNIQUE(mem_name) \ 178 soc_mem_t mem_name ## _enums[4][2] = \ 179 {{mem_name ## _XPE0_PIPE0m, \ 180 mem_name ## _XPE2_PIPE0m}, \ 181 {mem_name ## _XPE0_PIPE1m, \ 182 mem_name ## _XPE2_PIPE1m}, \ 183 {mem_name ## _XPE1_PIPE2m, \ 184 mem_name ## _XPE3_PIPE2m}, \ 185 {mem_name ## _XPE1_PIPE3m, mem_name ## _XPE3_PIPE3m}}; \ 186 187 #define HX5_MMU_HANDLE_ENUMS_IPIPE_UNIQUE(mem_name) \ 188 soc_mem_t mem_name ## _enums[4][2] = \ 189 {{mem_name ## _XPE0_PIPE0m, \ 190 mem_name ## _XPE1_PIPE0m}, \ 191 {mem_name ## _XPE2_PIPE1m, \ 192 mem_name ## _XPE3_PIPE1m}, \ 193 {mem_name ## _XPE2_PIPE2m, \ 194 mem_name ## _XPE3_PIPE2m}, \ 195 {mem_name ## _XPE0_PIPE3m, mem_name ## _XPE1_PIPE3m}}; \ 196 197 #define HX5_MMU_GET_HANDLE(mem_name, base_index, acc_index, handle) \ 198 handle = mem_name ## _enums[base_index][acc_index] 199 200 /* START - FlexPort types as defined in SDK. */ 201 typedef enum { 202 HX5_SPEED_10G_ETH_DECODE = 1, 203 HX5_SPEED_10G_HG_DECODE = 2, 204 HX5_SPEED_20G_ETH_DECODE = 3, 205 HX5_SPEED_20G_HG_DECODE = 4, 206 HX5_SPEED_25G_ETH_DECODE = 5, 207 HX5_SPEED_25G_HG_DECODE = 6, 208 HX5_SPEED_40G_ETH_DECODE = 7, 209 HX5_SPEED_40G_HG_DECODE = 8, 210 HX5_SPEED_50G_ETH_DECODE = 9, 211 HX5_SPEED_50G_HG_DECODE = 10, 212 HX5_SPEED_100G_ETH_DECODE = 11, 213 HX5_SPEED_100G_HG_DECODE = 12 214 } _soc_td3_ct_speed_decode_e; 215 216 #endif /* HELIX5_MMU_DEFINES_H */