helix5_flexport.h (6541B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 * File: helix5_flexport.h 7 * Purpose: 8 * Requires: 9 */ 10 11 #ifndef SOC_HELIX5_FLEXPORT_H 12 #define SOC_HELIX5_FLEXPORT_H 13 14 #include <soc/flexport/flexport_common.h> 15 16 /*** START SDK API COMMON CODE ***/ 17 18 /*! @file helix5_flexport.h 19 @brief FlexPort functions and structures for Trident3. 20 Details are shown below. 21 */ 22 23 #include <soc/flexport/helix5/helix5_flexport_defines.h> 24 25 #include <soc/flexport/helix5/helix5_tdm_flexport.h> 26 #include <soc/flexport/helix5/helix5_idb_flexport.h> 27 #include <soc/flexport/helix5/helix5_ep_flexport.h> 28 #include <soc/flexport/helix5/helix5_mac_flexport.h> 29 #include <soc/flexport/helix5/helix5_mmu_flex_init.h> 30 31 32 #define MAX_FLEX_PHASES 25 33 34 35 /*! @struct soc_helix5_flex_scratch_t 36 @brief Scratch pad locals. Caller must not allocate. Callee allocates 37 at entry and deallocates before return. This area is pointed 38 to by the cookie in soc_port_schedule_state_t struct type. 39 */ 40 typedef struct soc_helix5_flex_scratch_s { 41 /*!< Previous OVS tables needed by the OVS consolidation sequence */ 42 soc_tdm_schedule_pipe_t prev_tdm_ingress_schedule_pipe[SOC_MAX_NUM_PIPES]; 43 soc_tdm_schedule_pipe_t prev_tdm_egress_schedule_pipe[SOC_MAX_NUM_PIPES]; 44 /*!< Current state of OVS tables; is changing during flexport sequence 45 initial state is prev OVS tables and after OVS flexport sequence 46 converges to new_ OVS tables*/ 47 soc_tdm_schedule_pipe_t curr_tdm_ingress_schedule_pipe[SOC_MAX_NUM_PIPES]; 48 soc_tdm_schedule_pipe_t curr_tdm_egress_schedule_pipe[SOC_MAX_NUM_PIPES]; 49 /*!< Previous and new Oversub ratios; per PIPE and per HALF PIPE 50 * These are coded as follows: 51 * 10 - this is LR; 52 * 15 - this is OVS with 3:2; ovs_ratio <= 1.5; 53 * 20 - this is OVS with 2:1; 1.5 < ovs_ratio <= 2.0; 54 */ 55 int prev_pipe_ovs_ratio[SOC_MAX_NUM_PIPES]; /* per PIPE ovs_ratio 56 * per Half PIPE ovs_ratio */ 57 int prev_hpipe_ovs_ratio[SOC_MAX_NUM_PIPES][HELIX5_OVS_HPIPE_COUNT_PER_PIPE]; 58 int new_pipe_ovs_ratio[SOC_MAX_NUM_PIPES]; /* per PIPE ovs_ratio 59 * per Half PIPE ovs_ratio */ 60 int new_hpipe_ovs_ratio[SOC_MAX_NUM_PIPES][HELIX5_OVS_HPIPE_COUNT_PER_PIPE]; 61 62 /* This keeps the exact bitrate of the out_port_map.log_port_speed[] */ 63 enum port_speed_e exact_out_log_port_speed[SOC_MAX_NUM_PORTS]; 64 } soc_helix5_flex_scratch_t; 65 66 67 /*! @fn void *soc_helix5_port_lane_info_alloc(void) 68 @brief Allocates memory pointed to by soc_port_lane_info_t. Need this 69 special function because SystemVerilog-C DPI limitations in 70 synchronizing memory space that is a pointer to a struct type. 71 Since s/w owns the the pointer to soc_port_lane_info_t struct 72 in soc_port_resource_t, we cannot change it. 73 */ 74 extern void *soc_helix5_port_lane_info_alloc ( 75 void 76 ); 77 78 79 /*! @fn int soc_helix5_set_port_lane_info(int unit, const void *lane_info_ptr, int port_idx, int pgw, int xlp) 80 @param unit Chip unit number. 81 @param lane_info_ptr Pointer to a soc_port_lane_info_t struct variable. 82 @param port_idx Index within XLP. 83 @param pgw PGW instance where lane resides. 84 @param xlp XLP number within PGW. 85 @brief Sets all members in a soc_port_lane_info_t struct variable. 86 */ 87 extern int soc_helix5_set_port_lane_info ( 88 int unit, 89 const void *lane_info_ptr, 90 int port_idx, 91 int pgw, 92 int xlp 93 ); 94 95 96 /*! @fn int soc_helix5_get_port_lane_info(int unit, const void *lane_info_ptr, int *port_idx, int *pgw, int *xlp) 97 @param unit Chip unit number. 98 @param lane_info_ptr Pointer to a soc_port_lane_info_t struct variable. 99 @param port_idx Index within XLP. 100 @param pgw PGW instance where lane resides. 101 @param xlp XLP number within PGW. 102 @brief Gets all members in a soc_port_lane_info_t struct variable. 103 */ 104 extern int soc_helix5_get_port_lane_info ( 105 int unit, 106 const void *lane_info_ptr, 107 int *port_idx, 108 int *pgw, 109 int *xlp 110 ); 111 112 113 /*! @fn int soc_helix5_reconfigure_ports(int unit, soc_port_schedule_state_t *port_schedule_state) 114 @param unit Chip unit number. 115 @param port_schedule_state Pointer to data holding all required information for FlexPort opeations. 116 @brief Top-level call carrying out all FlexPort functionalities. 117 */ 118 extern int soc_helix5_reconfigure_ports ( 119 int unit, 120 soc_port_schedule_state_t *port_schedule_state 121 ); 122 123 124 /*! @fn int soc_helix5_flex_start(int unit, soc_port_schedule_state_t *port_schedule_state) 125 @param unit Chip unit number. 126 @param port_schedule_state Pointer to data holding all required information for FlexPort opeations. 127 @brief The start of FlexPort series of operations along with allocations of required program memory. 128 */ 129 extern int soc_helix5_flex_start ( 130 int unit, 131 soc_port_schedule_state_t *port_schedule_state 132 ); 133 134 135 /*! @fn int soc_helix5_flex_end(int unit, soc_port_schedule_state_t *port_schedule_state) 136 @param unit Chip unit number. 137 @param port_schedule_state Pointer to data holding all required information for FlexPort opeations. 138 @brief The end of FlexPort series of operations along with deallocations of program memory. 139 */ 140 extern int soc_helix5_flex_end ( 141 int unit, 142 soc_port_schedule_state_t *port_schedule_state 143 ); 144 145 146 extern int soc_helix5_flex_top_port_down ( 147 int unit, 148 soc_port_schedule_state_t *port_schedule_state 149 ); 150 151 152 extern int soc_helix5_flex_top_port_up ( 153 int unit, 154 soc_port_schedule_state_t *port_schedule_state 155 ); 156 157 extern int soc_helix5_flex_mmu_port_up_top ( 158 int unit, 159 soc_port_schedule_state_t *port_schedule_state 160 ); 161 162 extern int soc_helix5_get_ct_class(int speed); 163 164 /*! @fn int (*flexport_phases[MAX_FLEX_PHASES]) (int unit, soc_port_schedule_state_t *port_schedule_state) 165 @param unit Chip unit number. 166 @param port_schedule_state Pointer to data holding all required information for FlexPort opeations. 167 @brief Phase control array containing the right sequence of FlexPort phases implemented as functions. 168 */ 169 extern int (*hx5_flexport_phases[MAX_FLEX_PHASES]) (int unit, soc_port_schedule_state_t *port_schedule_state); 170 171 172 /*** END SDK API COMMON CODE ***/ 173 174 #endif /* SOC_HELIX5_FLEXPORT_H */ 175