feature.h (99483B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * SOC_FEATURE definitions 8 * 9 * File: feature.h 10 * Purpose: Define features by chip 11 */ 12 13 #ifndef _SOC_FEATURE_H 14 #define _SOC_FEATURE_H 15 16 #include <shared/enumgen.h> 17 18 /* 19 * Defines enums of the form soc_feature_xxx, and a corresponding list 20 * of initializer strings "xxx". New additions should be made in the 21 * following section between the zero and count entries. 22 */ 23 24 #define SHR_G_ENTRIES(DONT_CARE) \ 25 SHR_G_ENTRY(zero), /* ALWAYS FIRST PLEASE (DO NOT CHANGE) */ \ 26 SHR_G_ENTRY(arl_hashed), \ 27 SHR_G_ENTRY(arl_lookup_cmd), \ 28 SHR_G_ENTRY(arl_lookup_retry), /* All-0's response requires retry */ \ 29 SHR_G_ENTRY(arl_insert_ovr), /* ARL ins overwrites if key exists */ \ 30 SHR_G_ENTRY(cfap_pool), /* Software CFAP initialization. */ \ 31 SHR_G_ENTRY(cos_rx_dma), /* COS based RX DMA */ \ 32 SHR_G_ENTRY(dcb_type3), /* 5690 */ \ 33 SHR_G_ENTRY(dcb_type4), /* 5670 */ \ 34 SHR_G_ENTRY(dcb_type5), /* 5673 */ \ 35 SHR_G_ENTRY(dcb_type6), /* 5665 */ \ 36 SHR_G_ENTRY(dcb_type7), /* 5695 when enabled */ \ 37 SHR_G_ENTRY(dcb_type8), /* not used (5345) */ \ 38 SHR_G_ENTRY(dcb_type9), /* 56504 */ \ 39 SHR_G_ENTRY(dcb_type10), /* 56601 */ \ 40 SHR_G_ENTRY(dcb_type11), /* 56580, 56700, 56800 */ \ 41 SHR_G_ENTRY(dcb_type12), /* 56218 */ \ 42 SHR_G_ENTRY(dcb_type13), /* 56514 */ \ 43 SHR_G_ENTRY(dcb_type14), /* 56624, 56680 */ \ 44 SHR_G_ENTRY(dcb_type15), /* 56224 A0 */ \ 45 SHR_G_ENTRY(dcb_type16), /* 56820 */ \ 46 SHR_G_ENTRY(dcb_type17), /* 53314 */ \ 47 SHR_G_ENTRY(dcb_type18), /* 56224 B0 */ \ 48 SHR_G_ENTRY(dcb_type19), /* 56634, 56524, 56685 */ \ 49 SHR_G_ENTRY(dcb_type20), /* 5623x */ \ 50 SHR_G_ENTRY(dcb_type21), /* 56840 */ \ 51 SHR_G_ENTRY(dcb_type22), /* 88732 */ \ 52 SHR_G_ENTRY(dcb_type23), /* 56640 */ \ 53 SHR_G_ENTRY(dcb_type24), /* 56440 */ \ 54 SHR_G_ENTRY(dcb_type26), /* 56850 */ \ 55 SHR_G_ENTRY(dcb_type28), /* 88650 */ \ 56 SHR_G_ENTRY(dcb_type29), /* 56450 */ \ 57 SHR_G_ENTRY(dcb_type30), /* 56150 */ \ 58 SHR_G_ENTRY(dcb_type31), /* 53400 */ \ 59 SHR_G_ENTRY(dcb_type32), /* 56960 */ \ 60 SHR_G_ENTRY(dcb_type33), /* 56860 */ \ 61 SHR_G_ENTRY(dcb_type34), /* 56160, 53570 */ \ 62 SHR_G_ENTRY(dcb_type35), /* 56560 */ \ 63 SHR_G_ENTRY(dcb_type36), /* 56870 */ \ 64 SHR_G_ENTRY(dcb_type37), /* 53570 */ \ 65 SHR_G_ENTRY(dcb_type38), /* 56980 */ \ 66 SHR_G_ENTRY(dcb_type39), /* 88690, 88800 */ \ 67 SHR_G_ENTRY(fe_gig_macs), \ 68 SHR_G_ENTRY(trimac), \ 69 SHR_G_ENTRY(filter), \ 70 SHR_G_ENTRY(filter_extended), \ 71 SHR_G_ENTRY(filter_xgs), \ 72 SHR_G_ENTRY(filter_pktfmtext), /* Enhanced pkt format spec for XGS */ \ 73 SHR_G_ENTRY(filter_metering), \ 74 SHR_G_ENTRY(ingress_metering), \ 75 SHR_G_ENTRY(egress_metering), \ 76 SHR_G_ENTRY(filter_tucana), \ 77 SHR_G_ENTRY(filter_draco15), \ 78 SHR_G_ENTRY(has_gbp), \ 79 SHR_G_ENTRY(l3), /* Capable of Layer 3 switching. */ \ 80 SHR_G_ENTRY(l3_ip6), /* IPv6 capable device. */ \ 81 SHR_G_ENTRY(l3_lookup_cmd), \ 82 SHR_G_ENTRY(ip_mcast), \ 83 SHR_G_ENTRY(ip_mcast_repl), /* IPMC replication */ \ 84 SHR_G_ENTRY(led_proc), /* LED microprocessor */ \ 85 SHR_G_ENTRY(led_data_offset_a0),/* LED RAM data offset for Link Status */ \ 86 SHR_G_ENTRY(schmsg_alias), \ 87 SHR_G_ENTRY(stack_my_modid), \ 88 SHR_G_ENTRY(stat_dma), \ 89 SHR_G_ENTRY(cpuport_stat_dma), \ 90 SHR_G_ENTRY(table_dma), \ 91 SHR_G_ENTRY(tslam_dma), \ 92 SHR_G_ENTRY(stg), /* Generic STG */ \ 93 SHR_G_ENTRY(stg_xgs), /* XGS implementation specific STG */ \ 94 SHR_G_ENTRY(remap_ut_prio), /* Remap prio of untagged pkts by port */ \ 95 SHR_G_ENTRY(link_down_fd), /* Bug in BCM5645 MAC; see mac.c */ \ 96 SHR_G_ENTRY(phy_5690_link_war), \ 97 SHR_G_ENTRY(l3x_delete_bf_bug), /* L3 delete fails if bucket full */ \ 98 SHR_G_ENTRY(xgxs_v1), /* FusionCore version 1 (BCM5670/90 A0) */\ 99 SHR_G_ENTRY(xgxs_v2), /* FusionCore version 2 (BCM5670/90 A1) */\ 100 SHR_G_ENTRY(xgxs_v3), /* FusionCore version 3 (BCM5673) */ \ 101 SHR_G_ENTRY(xgxs_v4), /* FusionCore version 4 (BCM5674) */ \ 102 SHR_G_ENTRY(xgxs_v5), /* FusionCore version 5 (BCM56504/56601)*/\ 103 SHR_G_ENTRY(xgxs_v6), /* FusionCore version 6 (BCM56700/56800)*/\ 104 SHR_G_ENTRY(xgxs_v7), /* FusionCore version 7 (BCM56624/56680)*/\ 105 SHR_G_ENTRY(lmd), /* Lane Mux/DMux 2.5 Gbps speed support */\ 106 SHR_G_ENTRY(bigmac_fault_stat), /* BigMac supports link fault status*/ \ 107 SHR_G_ENTRY(phy_cl45), /* Clause 45 phy support */ \ 108 SHR_G_ENTRY(aging_extended), /* extended l2 age control */ \ 109 SHR_G_ENTRY(dmux), /* DMUX capability */ \ 110 SHR_G_ENTRY(ext_gth_hd_ipg), /* Longer half dup. IPG (BCM5690A0/A1) */ \ 111 SHR_G_ENTRY(l2x_ins_sets_hit), /* L2X insert hardcodes HIT bit to 1 */ \ 112 SHR_G_ENTRY(l3x_ins_igns_hit), /* L3X insert does not affect HIT bit */ \ 113 SHR_G_ENTRY(fabric_debug), /* Debug support works on 5670 types */ \ 114 SHR_G_ENTRY(filter_krules), /* All FFP rules usable on 5673 */ \ 115 SHR_G_ENTRY(srcmod_filter), /* Chip can filter on src modid */ \ 116 SHR_G_ENTRY(dcb_st0_bug), /* Unreliable DCB status 0 (BCM5665 A0) */\ 117 SHR_G_ENTRY(filter_128_rules), /* 128 FFP rules usable on 5673 */ \ 118 SHR_G_ENTRY(modmap), /* Module ID remap */ \ 119 SHR_G_ENTRY(recheck_cntrs), /* Counter collection bug */ \ 120 SHR_G_ENTRY(bigmac_rxcnt_bug), /* BigMAC Rx counter bug */ \ 121 SHR_G_ENTRY(block_ctrl_ingress),/* Must block ctrl frames in xPIC */ \ 122 SHR_G_ENTRY(mstp_mask), /* VLAN mask for MSTP drops */ \ 123 SHR_G_ENTRY(mstp_lookup), /* VLAN lookup for MSTP drops */ \ 124 SHR_G_ENTRY(mstp_uipmc), /* MSTP for UIPMC */ \ 125 SHR_G_ENTRY(ipmc_lookup), /* IPMC echo suppression */ \ 126 SHR_G_ENTRY(lynx_l3_expanded), /* Lynx 1.5 with expanded L3 tables */ \ 127 SHR_G_ENTRY(fast_rate_limit), /* Short pulse rate limits (Lynx !A0) */ \ 128 SHR_G_ENTRY(l3_sgv), /* (S,G,V) hash key in L3 table */ \ 129 SHR_G_ENTRY(l3_sgv_aisb_hash), /* (S,G,V) variant hash */ \ 130 SHR_G_ENTRY(l3_dynamic_ecmp_group),/* Ecmp group use base and count */ \ 131 SHR_G_ENTRY(l3_host_ecmp_group), /* Ecmp group for Host Entries */ \ 132 SHR_G_ENTRY(l2_hashed), \ 133 SHR_G_ENTRY(l2_lookup_cmd), \ 134 SHR_G_ENTRY(l2_lookup_retry), /* All-0's response requires retry */ \ 135 SHR_G_ENTRY(l2_user_table), /* Implements L2 User table */ \ 136 SHR_G_ENTRY(rsv_mask), /* RSV_MASK needs 10/100 mode adjust */ \ 137 SHR_G_ENTRY(schan_hw_timeout), /* H/W can indicate SCHAN timeout */ \ 138 SHR_G_ENTRY(lpm_tcam), /* LPM table is a TCAM */ \ 139 SHR_G_ENTRY(mdio_enhanced), /* MDIO address remapping + C45/C22 */ \ 140 SHR_G_ENTRY(mem_cmd), /* Memory commands supported */ \ 141 SHR_G_ENTRY(two_ingress_pipes), /* Has two ingress pipelines */ \ 142 SHR_G_ENTRY(multi_pipe_mapped_ports), /* Has multiple pipes and ports mapped per pipe */ \ 143 SHR_G_ENTRY(mpls), /* MPLS for XGS3 */ \ 144 SHR_G_ENTRY(xgxs_lcpll), /* LCPLL Clock for XGXS */ \ 145 SHR_G_ENTRY(dodeca_serdes), /* Dodeca Serdes */ \ 146 SHR_G_ENTRY(txdma_purge), /* TX Purge packet after DMA abort */ \ 147 SHR_G_ENTRY(rxdma_cleanup), /* Check RX Packet SOP after DMA abort */ \ 148 SHR_G_ENTRY(pkt_tx_align), /* Fix Tx alignment for 128 byte burst */ \ 149 SHR_G_ENTRY(status_link_fail), /* H/W linkcsan gives Link fail status */ \ 150 SHR_G_ENTRY(fe_maxframe), /* FE MAC MAXFR is max frame len + 1 */ \ 151 SHR_G_ENTRY(l2x_parity), /* Parity support on L2X table */ \ 152 SHR_G_ENTRY(l3x_parity), /* Parity support on L3 tables */ \ 153 SHR_G_ENTRY(l3defip_parity), /* Parity support on L3 DEFIP tables */ \ 154 SHR_G_ENTRY(l3_defip_map), /* Map out unused L3_DEFIP blocks */ \ 155 SHR_G_ENTRY(l2_modfifo), /* L2 Modfifo for L2 table sync */ \ 156 SHR_G_ENTRY(l2_modfifo_def), /* Default to L2 Modfifo for L2 table sync */ \ 157 SHR_G_ENTRY(l2_multiple), /* Multiple L2 tables implemented */ \ 158 SHR_G_ENTRY(l2_overflow), /* L2 overflow mechanism implemented */ \ 159 SHR_G_ENTRY(l2_overflow_bucket), /* L2 overflow table implemented */ \ 160 SHR_G_ENTRY(vlan_mc_flood_ctrl),/* VLAN multicast flood control (PFM) */ \ 161 SHR_G_ENTRY(vfi_mc_flood_ctrl), /* VFI multicast flood control (PFM) */ \ 162 SHR_G_ENTRY(vlan_translation), /* VLAN translation feature */ \ 163 SHR_G_ENTRY(egr_vlan_pfm), /* MH PFM control per VLAN FB A0 */ \ 164 SHR_G_ENTRY(parity_err_tocpu), /* Packet to CPU on lookup parity error*/ \ 165 SHR_G_ENTRY(nip_l3_err_tocpu), /* Packet to CPU on non-IP L3 error */ \ 166 SHR_G_ENTRY(l3mtu_fail_tocpu), /* Packet to CPU on L3 MTU check fail */ \ 167 SHR_G_ENTRY(meter_adjust), /* Packet length adjustment for meter */ \ 168 SHR_G_ENTRY(prime_ctr_writes), /* Prepare counter writes with read */ \ 169 SHR_G_ENTRY(xgxs_power), /* Power up XGSS */ \ 170 SHR_G_ENTRY(src_modid_blk), /* SRC_MODID_BLOCK table support */ \ 171 SHR_G_ENTRY(src_modid_blk_ucast_override),/* MODID_BLOCK ucast overide */ \ 172 SHR_G_ENTRY(src_modid_blk_opcode_override),/* MODID_BLOCK opcode overide */ \ 173 SHR_G_ENTRY(src_modid_blk_profile), /* SRC_MODID_* block profile table */ \ 174 SHR_G_ENTRY(egress_blk_ucast_override), /* egr mask opcode overide */ \ 175 SHR_G_ENTRY(stat_jumbo_adj), /* Adjustable stats *OVR threshold */ \ 176 SHR_G_ENTRY(stat_xgs3), /* XGS3 dbg counters and IPv6 supports */ \ 177 SHR_G_ENTRY(dbgc_higig_lkup), /* FB B0 dbg counters w/ HiGig lookup */ \ 178 SHR_G_ENTRY(port_trunk_index), /* FB B0 trunk programmable hash */ \ 179 SHR_G_ENTRY(port_flow_hash), /* HB/GW enhanced hashing */ \ 180 SHR_G_ENTRY(seer_bcam_tune), /* Retune SEER BCAM table */ \ 181 SHR_G_ENTRY(mcu_fifo_suppress), /* MCU fifo error suppression */ \ 182 SHR_G_ENTRY(cpuport_switched), /* CPU port can act as switch port */ \ 183 SHR_G_ENTRY(cpuport_mirror), /* CPU port can be mirrored */ \ 184 SHR_G_ENTRY(higig2), /* Higig2 support */ \ 185 SHR_G_ENTRY(cpu_tx_proc), /* CPU TX Proc support */ \ 186 SHR_G_ENTRY(color), /* Select color from priority/CFI */ \ 187 SHR_G_ENTRY(color_inner_cfi), /* Select color from inner tag CFI */ \ 188 SHR_G_ENTRY(color_prio_map), /* Map color/int_prio from/to prio/CFI */ \ 189 SHR_G_ENTRY(untagged_vt_miss), /* Drop untagged VLAN xlate miss */ \ 190 SHR_G_ENTRY(module_loopback), /* Allow local module ingress */ \ 191 SHR_G_ENTRY(dscp_map_per_port), /* Per Port DSCP mapping table support */ \ 192 SHR_G_ENTRY(egr_dscp_map_per_port), /* Per Egress Port DSCP mapping table support */ \ 193 SHR_G_ENTRY(dscp_map_mode_all), /* DSCP map mode ALL or NONE support */ \ 194 SHR_G_ENTRY(vp_dscp_map), /* VP DSCP map set and get support */ \ 195 SHR_G_ENTRY(multi_tunnel_label_count), /* Multi tunnel label counting */ \ 196 SHR_G_ENTRY(oam_split_counter_pools), /* Split counter pools for oam*/ \ 197 SHR_G_ENTRY(l3defip_bound_adj), /* L3 defip boundary adjustment */ \ 198 SHR_G_ENTRY(tunnel_dscp_trust), /* Trust incomming tunnel DSCP */ \ 199 SHR_G_ENTRY(tunnel_protocol_match),/* Tunnel term key includes protocol. */ \ 200 SHR_G_ENTRY(higig_lookup), /* FB B0 Proxy (HG lookup) */ \ 201 SHR_G_ENTRY(egr_l3_mtu), /* L3 MTU check */ \ 202 SHR_G_ENTRY(egr_mirror_path), /* Alternate path for egress mirror */ \ 203 SHR_G_ENTRY(xgs1_mirror), /* XGS1 mirroring compatibility support*/ \ 204 SHR_G_ENTRY(register_hi), /* _HI designation for > 32 ports */ \ 205 SHR_G_ENTRY(table_hi), /* _HI designation for > 32 ports */ \ 206 SHR_G_ENTRY(trunk_extended), /* extended designation for > 32 trunks*/ \ 207 SHR_G_ENTRY(trunk_extended_only), /* only support extended trunk mode */ \ 208 SHR_G_ENTRY(hg_trunking), /* higig trunking support */ \ 209 SHR_G_ENTRY(hg_trunk_override), /* higig trunk override support */ \ 210 SHR_G_ENTRY(trunk_group_size), /* trunk group size support */ \ 211 SHR_G_ENTRY(shared_trunk_member_table), /* shared trunk member table */ \ 212 SHR_G_ENTRY(egr_vlan_check), /* Support for Egress VLAN check PBM */ \ 213 SHR_G_ENTRY(mod1), /* Ports spread over two module Ids */ \ 214 SHR_G_ENTRY(egr_ts_ctrl), /* Egress Time Slot Control */ \ 215 SHR_G_ENTRY(ipmc_grp_parity), /* Parity support on IPMC GROUP table */ \ 216 SHR_G_ENTRY(mpls_pop_search), /* MPLS pop search support */ \ 217 SHR_G_ENTRY(cpu_proto_prio), /* CPU protocol priority support */ \ 218 SHR_G_ENTRY(ignore_pkt_tag), /* Ignore packet vlan tag support */ \ 219 SHR_G_ENTRY(port_lag_failover), /* Port LAG failover support */ \ 220 SHR_G_ENTRY(hg_trunk_failover), /* Higig trunk failover support */ \ 221 SHR_G_ENTRY(trunk_egress), /* Trunk egress support */ \ 222 SHR_G_ENTRY(force_forward), /* Egress port override support */ \ 223 SHR_G_ENTRY(port_egr_block_ctl),/* L2/L3 port egress block control */ \ 224 SHR_G_ENTRY(ipmc_repl_freeze), /* IPMC repl config pauses traffic */ \ 225 SHR_G_ENTRY(bucket_support), /* MAX/MIN BUCKET support */ \ 226 SHR_G_ENTRY(remote_learn_trust),/* DO_NOT_LEARN bit in HiGig Header */ \ 227 SHR_G_ENTRY(ipmc_group_mtu), /* IPMC MTU Setting for all Groups */ \ 228 SHR_G_ENTRY(tx_fast_path), /* TX Descriptor mapped send */ \ 229 SHR_G_ENTRY(deskew_dll), /* Deskew DLL present */ \ 230 SHR_G_ENTRY(src_mac_group), /* Src MAC Group (MAC Block Index) */ \ 231 SHR_G_ENTRY(storm_control), /* Strom Control */ \ 232 SHR_G_ENTRY(hw_stats_calc), /* Calculation of stats in HW */ \ 233 SHR_G_ENTRY(ext_tcam_sharing), /* External TCAM sharing support */ \ 234 SHR_G_ENTRY(mac_learn_limit), /* MAC Learn limit support */ \ 235 SHR_G_ENTRY(mac_learn_limit_rollover), /* MAC Learn limit counter roll over */ \ 236 SHR_G_ENTRY(linear_drr_weight), /* Linear DRR weight calculation */ \ 237 SHR_G_ENTRY(igmp_mld_support), /* IGMP MLD snooping support */ \ 238 SHR_G_ENTRY(basic_dos_ctrl), /* TCP flags, L4 port, TCP frag, ICMP */ \ 239 SHR_G_ENTRY(enhanced_dos_ctrl), /* Enhanced DOS control features */ \ 240 SHR_G_ENTRY(ctr_xaui_activity), /* XAUI counter activity support */ \ 241 SHR_G_ENTRY(proto_pkt_ctrl), /* Protocol packet control */ \ 242 SHR_G_ENTRY(vlan_ctrl), /* Per VLAN property control */ \ 243 SHR_G_ENTRY(tunnel_6to4_secure),/* Secure IPv6 to IPv4 tunnel support. */ \ 244 SHR_G_ENTRY(tunnel_any_in_6), /* Any in IPv6 tunnel support. */ \ 245 SHR_G_ENTRY(tunnel_gre), /* GRE tunneling support. */ \ 246 SHR_G_ENTRY(unknown_ipmc_tocpu),/* Send unknown IPMC packet to CPU. */ \ 247 SHR_G_ENTRY(src_trunk_port_bridge), /* Source trunk port bridge */ \ 248 SHR_G_ENTRY(stat_dma_error_ack),/* Stat DMA error acknowledge bit offset */ \ 249 SHR_G_ENTRY(big_icmpv6_ping_check),/* ICMP V6 oversize packet disacrd */ \ 250 SHR_G_ENTRY(asf), /* Alternate Store and Forward */ \ 251 SHR_G_ENTRY(asf_no_10_100), /* No ASF support for 10/100Mb speeds */ \ 252 SHR_G_ENTRY(trunk_group_overlay),/* Direct TGID overlay of modid/port */ \ 253 SHR_G_ENTRY(xport_convertible), /* XPORT <-> Higig support */ \ 254 SHR_G_ENTRY(dual_hash), /* Dual hash tables support */ \ 255 SHR_G_ENTRY(dscp), /* DiffServ QoS */ \ 256 SHR_G_ENTRY(auth), /* AUTH 802.1x support */ \ 257 SHR_G_ENTRY(mstp), \ 258 SHR_G_ENTRY(arl_mode_control), /* ARL CONTROL (DS/DD/CPU) */ \ 259 SHR_G_ENTRY(no_stat_mib), \ 260 SHR_G_ENTRY(rcpu_1), /* Remote CPU feature (Raptor) */ \ 261 SHR_G_ENTRY(unimac), /* UniMAC 10/100/1000 */ \ 262 SHR_G_ENTRY(xmac), /* XMAC */ \ 263 SHR_G_ENTRY(xlmac), /* XLMAC */ \ 264 SHR_G_ENTRY(cmac), /* CMAC */ \ 265 SHR_G_ENTRY(clmac), /* CLMAC */ \ 266 SHR_G_ENTRY(generic_table_ops), /* Generic SCHAN table operations */ \ 267 SHR_G_ENTRY(lpm_prefix_length_max_128),/* Maximum lpm prefix len 128 */ \ 268 SHR_G_ENTRY(tag_enforcement), /* BRCM tag with tag_enforcement */ \ 269 SHR_G_ENTRY(vlan_translation_range), /* VLAN translation range */ \ 270 SHR_G_ENTRY(vlan_xlate_dtag_range), /*VLAN translation double tag range*/ \ 271 SHR_G_ENTRY(vlan_xlate_has_class_id), /*Ing and Egr VLAN XLATE tables have class_id*/ \ 272 SHR_G_ENTRY(mpls_per_vlan), /* MPLS enable per-vlan */ \ 273 SHR_G_ENTRY(mpls_bos_lookup), /* Second lookup bottom of stack == 0 */ \ 274 SHR_G_ENTRY(mpls_frr_lookup), /* MPLS Fast Re-Route label lookup */ \ 275 SHR_G_ENTRY(l3_tunnel_mode_fld_is_keytype), /* L3_TUNNEL MODE field */ \ 276 SHR_G_ENTRY(class_based_learning), /* L2 class based learning */ \ 277 SHR_G_ENTRY(static_pfm), /* Static MH PFM control */ \ 278 SHR_G_ENTRY(ipmc_repl_penultimate), /* Flag last IPMC replication */ \ 279 SHR_G_ENTRY(sgmii_autoneg), /* Support SGMII autonegotiation */ \ 280 SHR_G_ENTRY(gmii_clkout), /* Support GMII clock output */ \ 281 SHR_G_ENTRY(ip_ep_mem_parity), /* Parity support on IP, EP memories */ \ 282 SHR_G_ENTRY(post), /* Post after reset init */ \ 283 SHR_G_ENTRY(rcpu_priority), /* Remote CPU packet QoS handling */ \ 284 SHR_G_ENTRY(rcpu_tc_mapping), /* Remote CPU traffic class to queue */ \ 285 SHR_G_ENTRY(mem_push_pop), /* SCHAN push/pop operations */ \ 286 SHR_G_ENTRY(dcb_reason_hi), /* Number of RX reasons exceeds 32 */ \ 287 SHR_G_ENTRY(multi_sbus_cmds), /* SCHAN multiple sbus commands */ \ 288 SHR_G_ENTRY(flexible_dma_steps),/* Flexible sbus address increment step */ \ 289 SHR_G_ENTRY(new_sbus_format), /* New sbus command format */ \ 290 SHR_G_ENTRY(new_sbus_old_resp), /* New sbus command format, Old Response */ \ 291 SHR_G_ENTRY(sbus_format_v4), /* Sbus command format version 4 */ \ 292 SHR_G_ENTRY(blkid_extended_format), /* Block ID bigger than 127 */ \ 293 SHR_G_ENTRY(esm_support), /* External TCAM support */ \ 294 SHR_G_ENTRY(esm_rxfifo_resync), /* ESM with DDR RX_FIFO resync logic */ \ 295 SHR_G_ENTRY(fifo_dma), /* fifo DMA support */ \ 296 SHR_G_ENTRY(fifo_dma_active), /* fifo DMA active bit set if its not empty */ \ 297 SHR_G_ENTRY(ipfix), /* IPFIX support */ \ 298 SHR_G_ENTRY(ipfix_rate), /* IPFIX rate and rate mirror support */ \ 299 SHR_G_ENTRY(ipfix_flow_mirror), /* IPFIX flow mirror support */ \ 300 SHR_G_ENTRY(l3_entry_key_type), /* Data stored in first entry only. */ \ 301 SHR_G_ENTRY(fp_routing_mirage), /* Mirage fp based routing. */ \ 302 SHR_G_ENTRY(fp_routing_hk), /* Hawkeye fp based routing. */ \ 303 SHR_G_ENTRY(subport), /* Subport support */ \ 304 SHR_G_ENTRY(reset_delay), /* Delay after CMIC soft reset */ \ 305 SHR_G_ENTRY(fast_egr_cell_count), /* HW accelerated cell count retrieval */ \ 306 SHR_G_ENTRY(802_3as), /* 802.3as */ \ 307 SHR_G_ENTRY(l2_pending), /* L2 table pending support */ \ 308 SHR_G_ENTRY(discard_ability), /* discard/WRED support */ \ 309 SHR_G_ENTRY(discard_ability_color_black), /* discard/WRED color black */ \ 310 SHR_G_ENTRY(distribution_ability), /* distribution/ESET support */ \ 311 SHR_G_ENTRY(mc_group_ability), /* McGroup support */ \ 312 SHR_G_ENTRY(cosq_gport_stat_ability), /* COS queue stats support */ \ 313 SHR_G_ENTRY(standalone), /* standalone switch mode */ \ 314 SHR_G_ENTRY(internal_loopback), /* internal loopback port */ \ 315 SHR_G_ENTRY(packet_adj_len), /* packet adjust length */ \ 316 SHR_G_ENTRY(vlan_action), /* VLAN action support */ \ 317 SHR_G_ENTRY(vlan_pri_cfi_action), /* VLAN pri/CFI action support */ \ 318 SHR_G_ENTRY(vlan_copy_action), /* VLAN copy action support */ \ 319 SHR_G_ENTRY(packet_rate_limit), /* Packet-based rate limitting to CPU */ \ 320 SHR_G_ENTRY(system_mac_learn_limit), /* System MAC Learn limit support */ \ 321 SHR_G_ENTRY(fp_based_routing), /* L3 based on field processor. */ \ 322 SHR_G_ENTRY(field), /* Field Processor (FP) for XGS3 */ \ 323 SHR_G_ENTRY(field_slices2), /* FP TCAM has 2 slices, instead of 16 */ \ 324 SHR_G_ENTRY(field_slices4), /* FP TCAM has 4 slices, instead of 16 */ \ 325 SHR_G_ENTRY(field_slices8), /* FP TCAM has 8 slices, instead of 16 */ \ 326 SHR_G_ENTRY(field_slices10), /* FP TCAM has 10 slices,instead of 16 */ \ 327 SHR_G_ENTRY(field_slices12), /* FP TCAM has 12 slices,instead of 16 */ \ 328 SHR_G_ENTRY(field_slices18), /* IFP TCAM has 18 slices */ \ 329 SHR_G_ENTRY(field_meter_pools4),/* FP TCAM has 4 global meter pools. */ \ 330 SHR_G_ENTRY(field_meter_pools8),/* FP TCAM has 8 global meter pools. */ \ 331 SHR_G_ENTRY(field_meter_pools12),/* FP TCAM has 12 global meter pools. */ \ 332 SHR_G_ENTRY(field_mirror_ovr), /* FP has MirrorOverride action */ \ 333 SHR_G_ENTRY(field_udf_higig), /* FP UDF window contains HiGig header */ \ 334 SHR_G_ENTRY(field_udf_higig2), /* FP UDF window contains HiGig2 header */ \ 335 SHR_G_ENTRY(field_udf_hg), /* FP UDF2.0->2.2 HiGig header */ \ 336 SHR_G_ENTRY(field_udf_ethertype), /* FP UDF can ues extra ethertypes */ \ 337 SHR_G_ENTRY(field_comb_read), /* FP can read TCAM & Policy as one */ \ 338 SHR_G_ENTRY(field_wide), /* FP has wide-mode combining of slices*/ \ 339 SHR_G_ENTRY(field_slice_enable),/* FP enable/disable on per slice basis*/ \ 340 SHR_G_ENTRY(field_cos), /* FP has CoS Queue actions */ \ 341 SHR_G_ENTRY(field_ingress_late),/* FP has late ingress pipeline stage */ \ 342 SHR_G_ENTRY(field_color_indep), /* FP can set color in/dependence */ \ 343 SHR_G_ENTRY(field_qual_drop), /* FP can qualify on drop state */ \ 344 SHR_G_ENTRY(field_qual_IpType), /* FP can qualify on IpType alone */ \ 345 SHR_G_ENTRY(field_qual_Ip6High), /* FP can qualify on Src/Dst Ip 6 High */ \ 346 SHR_G_ENTRY(field_mirror_pkts_ctl), /* Enable FP for mirror packtes */ \ 347 SHR_G_ENTRY(field_intraslice_basic_key), /* Only IP4 or IP6 key. */ \ 348 SHR_G_ENTRY(field_ingress_two_slice_types),/* Ingress FP has 2 slice types*/\ 349 SHR_G_ENTRY(field_ingress_global_meter_pools), /* Global Meter Pools */ \ 350 SHR_G_ENTRY(field_ingress_ipbm), /* FP IPBM qualifier is always present*/ \ 351 SHR_G_ENTRY(field_egress_flexible_v6_key), /* Egress FP KEY2 SIP6/DIP6.*/ \ 352 SHR_G_ENTRY(field_egress_global_counters), /* Global Counters */ \ 353 SHR_G_ENTRY(field_egress_metering), /* FP allows metering in egress mode */ \ 354 SHR_G_ENTRY(field_ing_egr_separate_packet_byte_counters), /* */ \ 355 SHR_G_ENTRY(field_multi_stage), /* Multi staged field processor. */ \ 356 SHR_G_ENTRY(field_intraslice_double_wide), /* FP double wide in 1 slice*/ \ 357 SHR_G_ENTRY(field_int_fsel_adj),/* FP internal field select adjust */ \ 358 SHR_G_ENTRY(field_pkt_res_adj), /* FP field packet resolution adjust */ \ 359 SHR_G_ENTRY(field_virtual_slice_group), /* Virtual slice/groups in FP */ \ 360 SHR_G_ENTRY(field_qualify_gport), /* EgrObj/Mcast Grp/Gport qualifiers */ \ 361 SHR_G_ENTRY(field_action_redirect_ipmc), /* Redirect to ipmc index. */ \ 362 SHR_G_ENTRY(field_action_timestamp), /* Copy to cpu with timestamp. */ \ 363 SHR_G_ENTRY(field_action_l2_change), /* Modify l2 packets sa/da/vlan. */ \ 364 SHR_G_ENTRY(field_action_fabric_queue), /* Add HiGig2 extension header. */ \ 365 SHR_G_ENTRY(field_virtual_queue), /* Virtual queue support. */ \ 366 SHR_G_ENTRY(field_vfp_flex_counter), /* Flex cntrs support in vfp. */ \ 367 SHR_G_ENTRY(field_tcam_hw_move), /* TCAM move support via HW. */ \ 368 SHR_G_ENTRY(field_tcam_parity_check), /* TCAM parity check. */ \ 369 SHR_G_ENTRY(field_qual_my_station_hit), /* FP can qualify on My Station Hit*/ \ 370 SHR_G_ENTRY(field_action_redirect_nexthop), /* Redirect packet to Next Hop index */ \ 371 SHR_G_ENTRY(field_action_redirect_ecmp), /* Redirect packet to ECMP group */ \ 372 SHR_G_ENTRY(field_slice_dest_entity_select), /* FP can qualify on destination type */ \ 373 SHR_G_ENTRY(field_packet_based_metering), /* FP supports packet based metering */ \ 374 SHR_G_ENTRY(field_stage_half_slice), /* Only half the number of total entries in FP_TCAM and FP_POLICY tables are used */ \ 375 SHR_G_ENTRY(field_stage_quarter_slice), /* Only quarter the number of total entries in FP_TCAM and FP_POLICY tables are used */ \ 376 SHR_G_ENTRY(field_slice_size128),/* Only 128 entries in FP_TCAM and FP_POLICY tables are used */ \ 377 SHR_G_ENTRY(field_stage_ingress_256_half_slice),/* Only half entries/slice are used when FP_TCAM and FP_POLICY have 256 entries/slice */\ 378 SHR_G_ENTRY(field_stage_ingress_512_half_slice),/* Only half entries/slice are used when FP_TCAM and FP_POLICY have 512 entries/slice */\ 379 SHR_G_ENTRY(field_stage_egress_256_half_slice),/* Only half entries/slice are used when EFP_TCAM has 256 entries/slice */\ 380 SHR_G_ENTRY(field_stage_egress_512_half_slice),/* Only half entries/slice are used when EFP_TCAM has 512 entries/slice */\ 381 SHR_G_ENTRY(field_stage_lookup_256_half_slice),/* Only half entries/slice are used when VFP_TCAM has 256 entries/slice */\ 382 SHR_G_ENTRY(field_stage_lookup_512_half_slice),/* Only half entries/slice are used when VFP_TCAM has 512 entries/slice */\ 383 SHR_G_ENTRY(field_oam_actions), /* FP supports OAM actions. */ \ 384 SHR_G_ENTRY(field_ingress_cosq_override), /* Ingress FP overrides assigned CoSQ */ \ 385 SHR_G_ENTRY(field_egress_tocpu), /* Egress copy-to-cpu */\ 386 SHR_G_ENTRY(field_multi_pipe_support), /* FP per-pipe configuration model supported. */\ 387 SHR_G_ENTRY(field_single_pipe_support), /* FP Single pipe mode supported. */\ 388 SHR_G_ENTRY(range_check_group_support), /* Range check group is supported. */\ 389 SHR_G_ENTRY(field_ingress_triple_wide), /* Ingress FP supports pairing of three slices. */\ 390 SHR_G_ENTRY(field_preselector_support), /* IFP preselector Module Support. */\ 391 SHR_G_ENTRY(virtual_switching), /* Virtual lan services support */ \ 392 SHR_G_ENTRY(lport_tab_profile), /* Lport table is profiled per svp */ \ 393 SHR_G_ENTRY(xgport_one_xe_six_ge), /* XGPORT mode with 1x10G + 6x1GE */ \ 394 SHR_G_ENTRY(sample_offset8), /* Sample threshold is shifted << 8 bits */ \ 395 SHR_G_ENTRY(sample_thresh16), /* Sample threshold 16 bit wide */ \ 396 SHR_G_ENTRY(sample_thresh24), /* Sample threshold 24 bit wide */ \ 397 SHR_G_ENTRY(mim), /* MIM for XGS3 */ \ 398 SHR_G_ENTRY(oam), /* OAM for XGS3 */ \ 399 SHR_G_ENTRY(bfd), /* BFD for XGS3 */ \ 400 SHR_G_ENTRY(bhh), /* BHH for XGS3 */ \ 401 SHR_G_ENTRY(eth_lm_dm), /* ETH_LM_DM for XGS3 */ \ 402 SHR_G_ENTRY(ptp), /* PTP for XGS3 */ \ 403 SHR_G_ENTRY(ifa), /* IFA for XGS */ \ 404 SHR_G_ENTRY(sat), /* SAT for XGS4 */ \ 405 SHR_G_ENTRY(hybrid), /* global hybrid configuration feature */ \ 406 SHR_G_ENTRY(node_hybrid), /* node hybrid configuration feature */ \ 407 SHR_G_ENTRY(arbiter), /* arbiter feature */ \ 408 SHR_G_ENTRY(arbiter_capable), /* arbiter capable feature */ \ 409 SHR_G_ENTRY(node), /* node hybrid configuration mode */ \ 410 SHR_G_ENTRY(lcm), /* lcm feature */ \ 411 SHR_G_ENTRY(xbar), /* xbar feature */ \ 412 SHR_G_ENTRY(egr_independent_fc), /* egr fifo independent flow control */ \ 413 SHR_G_ENTRY(egr_multicast_independent_fc), /* egr multicast fifo independent flow control */ \ 414 SHR_G_ENTRY(always_drive_dbus), /* drive esm dbus */ \ 415 SHR_G_ENTRY(ignore_cmic_xgxs_pll_status), /* ignore CMIC XGXS PLL lock status */ \ 416 SHR_G_ENTRY(mmu_virtual_ports), /* internal MMU virtual ports */ \ 417 SHR_G_ENTRY(phy_lb_needed_in_mac_lb), /* PHY loopback has to be set when in MAC loopback mode */ \ 418 SHR_G_ENTRY(gport_service_counters), /* Counters for ports and services */ \ 419 SHR_G_ENTRY(use_double_freq_for_ddr_pll), /* use double freq for DDR PLL */\ 420 SHR_G_ENTRY(eav_support), /* EAV supporting */ \ 421 SHR_G_ENTRY(wlan), /* WLAN for XGS3 */ \ 422 SHR_G_ENTRY(counter_parity), /* Counter registers have parity fields */ \ 423 SHR_G_ENTRY(time_support), /* Time module support */ \ 424 SHR_G_ENTRY(rsvd1_intf), /* RSVD1 Interface support */ \ 425 SHR_G_ENTRY(gdpll_support), /* GDPLL module support */ \ 426 SHR_G_ENTRY(time_v3), /* 3rd gen time arch: 48b TS, dual BS/TS */ \ 427 SHR_G_ENTRY(time_v3_no_bs), /* No BroadSync for certian SKUs */ \ 428 SHR_G_ENTRY(timesync_support), /* Time module support */ \ 429 SHR_G_ENTRY(timesync_v3), /* 3rd gen timesync/1588 arch: 48bit TS */ \ 430 SHR_G_ENTRY(tdpll_outputclk_synce3),/* TDPLL output clock XGPLL2/PMHPLL support */ \ 431 SHR_G_ENTRY(tdpll_outputclk_xgpll3),/* TDPLL output clock XGPLL3 support */ \ 432 SHR_G_ENTRY(ip_source_bind), /* IP to MAC address binding feature */ \ 433 SHR_G_ENTRY(auto_multicast), /* Automatic Multicast Tunneling Support */ \ 434 SHR_G_ENTRY(embedded_higig), /* Embedded Higig Tunneling Support */ \ 435 SHR_G_ENTRY(higig_over_ethernet), /* Higig over Ethernet */ \ 436 SHR_G_ENTRY(hawkeye_a0_war), /* QSGMII Workaroud */ \ 437 SHR_G_ENTRY(vlan_queue_map), /* VLAN queue mapping support */ \ 438 SHR_G_ENTRY(vlan_multicast_queue_map), /* VLAN multicast queue mapping support */ \ 439 SHR_G_ENTRY(mpls_software_failover), /* MPLS FRR support within Software */ \ 440 SHR_G_ENTRY(mpls_failover), /* MPLS FRR support */ \ 441 SHR_G_ENTRY(extended_pci_error), /* More DMA info for PCI errors */ \ 442 SHR_G_ENTRY(subport_enhanced), /* Enhanced Subport Support */ \ 443 SHR_G_ENTRY(priority_flow_control), /* Per-priority flow control */ \ 444 SHR_G_ENTRY(source_port_priority_flow_control), /* Per-(source port, priority) flow control */ \ 445 SHR_G_ENTRY(flex_port), /* Flex-port aka hot-swap Support */ \ 446 SHR_G_ENTRY(qos_profile), /* QoS profiles for ingress and egress */ \ 447 SHR_G_ENTRY(fe_ports), /* Raven/Raptor with FE ports */ \ 448 SHR_G_ENTRY(mirror_flexible), /* Flexible ingress/egress mirroring */ \ 449 SHR_G_ENTRY(egr_mirror_true), /* True egress mirroring */ \ 450 SHR_G_ENTRY(failover), /* Generalized VP failover */ \ 451 SHR_G_ENTRY(delay_core_pll_lock), /* Tune core clock before PLL lock */ \ 452 SHR_G_ENTRY(extended_cmic_error), /* Block specific errors in CMIC_IRQ_STAT_1/2 */ \ 453 SHR_G_ENTRY(short_cmic_error), /* Override Block specific errors in CMIC_IRQ_STAT_1/2 */ \ 454 SHR_G_ENTRY(urpf), /* Unicast reverse path check. */ \ 455 SHR_G_ENTRY(no_bridging), /* No L2 and L3. */ \ 456 SHR_G_ENTRY(no_higig), /* No higig support */ \ 457 SHR_G_ENTRY(no_higig_plus), /* No higig plus support */ \ 458 SHR_G_ENTRY(no_epc_link), /* No EPC_LINK_BMAP */ \ 459 SHR_G_ENTRY(no_mirror), /* No mirror support */ \ 460 SHR_G_ENTRY(no_learning), /* No CML support */ \ 461 SHR_G_ENTRY(rx_timestamp), /* RX packet timestamp filed should be updated */ \ 462 SHR_G_ENTRY(rx_timestamp_upper),/* RX packet timestamp uper 32bit filed should be updated */ \ 463 SHR_G_ENTRY(sysport_remap), /* Support for remapping system port to physical port */ \ 464 SHR_G_ENTRY(flexible_xgport), /* Allow 10G/1G speed change on XGPORT */ \ 465 SHR_G_ENTRY(logical_port_num),/* Physical/logical port number mapping */ \ 466 SHR_G_ENTRY(mmu_config_property),/* MMU config property */ \ 467 SHR_G_ENTRY(l2_bulk_control), /* L2 bulk control */ \ 468 SHR_G_ENTRY(l2_bulk_unified_table), /*L2 bulk control with single table*/ \ 469 SHR_G_ENTRY(l2_bulk_bypass_replace), /* L2 bulk control bypass replace */ \ 470 SHR_G_ENTRY(timestamp_counter), /* Timestamp FIFO in counter range */ \ 471 SHR_G_ENTRY(l3_ingress_interface), /* Layer-3 Ingress Interface Object */ \ 472 SHR_G_ENTRY(ingress_size_templates), /* Ingress Size Tempaltes */ \ 473 SHR_G_ENTRY(l3_defip_ecmp_count), /* L3 DEFIP ECMP Count */ \ 474 SHR_G_ENTRY(ppa_bypass), /* PPA ignoring key type field in L2X */ \ 475 SHR_G_ENTRY(ppa_match_vp), /* PPA allows to match on virtual port */ \ 476 SHR_G_ENTRY(generic_counters), /* Common counters shared by both XE/GE */ \ 477 SHR_G_ENTRY(mpls_enhanced), /* MPLS Enhancements */ \ 478 SHR_G_ENTRY(trill), /* Trill support */ \ 479 SHR_G_ENTRY(niv), /* Network interface virtualization */ \ 480 SHR_G_ENTRY(unimac_tx_crs), /* Unimac TX CRS */ \ 481 SHR_G_ENTRY(hg_trunk_override_profile), /* Higig trunk override is profiled */ \ 482 SHR_G_ENTRY(modport_map_profile), /* Modport map table is profiled */ \ 483 SHR_G_ENTRY(hg_dlb), /* Higig DLB */ \ 484 SHR_G_ENTRY(l3_defip_hole), /* L3 DEFIP Hole */ \ 485 SHR_G_ENTRY(eee), /* Energy Efficient Ethernet */ \ 486 SHR_G_ENTRY(mdio_setup), /* MDIO setup for FE devices */ \ 487 SHR_G_ENTRY(ser_parity), /* SER parity protection available */ \ 488 SHR_G_ENTRY(ser_engine), /* Standalone SER engine available */ \ 489 SHR_G_ENTRY(ser_system_scrub), /* Enabling system scrub during shut down */ \ 490 SHR_G_ENTRY(ser_fifo), /* Hardware reports events via SER fifos */ \ 491 SHR_G_ENTRY(ser_hw_bg_read), /* Standalone SER engine has background read available */ \ 492 SHR_G_ENTRY(ser_log_info), /* ser log info recording and get */ \ 493 SHR_G_ENTRY(ser_error_stat), /* Get ser error statistics */ \ 494 SHR_G_ENTRY(mem_cache), /* Memory cache for SER correction */ \ 495 SHR_G_ENTRY(mem_wb_cache_reload), /* Enabling WB mem cache reload */ \ 496 SHR_G_ENTRY(regs_as_mem), /* Registers implemented as memory */ \ 497 SHR_G_ENTRY(fp_meter_ser_verify), /* Reverify FP METER TABLE SER */ \ 498 SHR_G_ENTRY(int_cpu_arbiter), /* Internal CPU arbiter */ \ 499 SHR_G_ENTRY(ets), /* Enhanced transmission selection */ \ 500 SHR_G_ENTRY(qcn), /* Quantized congestion notification */ \ 501 SHR_G_ENTRY(xy_tcam), /* Non data/mask type TCAM */ \ 502 SHR_G_ENTRY(xy_tcam_direct), /* Non data/mask type TCAM with h/w translation bypass */ \ 503 SHR_G_ENTRY(xy_tcam_28nm), /* Non data/mask type TCAM */ \ 504 SHR_G_ENTRY(xy_tcam_lpt), /* Non data/mask type TCAM with LPT encoding */ \ 505 SHR_G_ENTRY(bucket_update_freeze), /* Disable refresh when updating bucket */ \ 506 SHR_G_ENTRY(hg_trunk_16_members), /* Higig trunk has fixed size of 16 */ \ 507 SHR_G_ENTRY(vlan_vp), /* VLAN virtual port switching */ \ 508 SHR_G_ENTRY(vp_group_ingress_vlan_membership), /* Ingress VLAN virtual port group membership */ \ 509 SHR_G_ENTRY(vp_group_egress_vlan_membership), /* Egress VLAN virtual port group membership */ \ 510 SHR_G_ENTRY(ing_vp_vlan_membership), /* Ingress VLAN virtual port membership */ \ 511 SHR_G_ENTRY(egr_vp_vlan_membership), /* Egress VLAN virtual port membership */ \ 512 /* Supports olicer in flow mode with committed rate */ \ 513 SHR_G_ENTRY(policer_mode_flow_rate_committed), \ 514 SHR_G_ENTRY(vlan_egr_it_inner_replace), \ 515 SHR_G_ENTRY(src_modid_base_index), /* Per source module ID base index */ \ 516 SHR_G_ENTRY(wesp), /* Wrapped Encapsulating Security Payload */ \ 517 SHR_G_ENTRY(cmicm), /* CMICm */ \ 518 SHR_G_ENTRY(cmicm_b0), /* CMICm B0 */ \ 519 SHR_G_ENTRY(cmicd), /* CMICd */ \ 520 SHR_G_ENTRY(cmicx), /* CMICx */ \ 521 SHR_G_ENTRY(continuous_dma), /* Support for Continuous DMA */ \ 522 SHR_G_ENTRY(mcs), /* Micro Controller Subsystem */ \ 523 SHR_G_ENTRY(iproc), /* iProc Internal Processor Subsystem */ \ 524 SHR_G_ENTRY(iproc_7), /* iProc 7 profile */ \ 525 SHR_G_ENTRY(cmicm_extended_interrupts), /* CMICm IRQ1, IRQ2 */ \ 526 SHR_G_ENTRY(cmicm_multi_dma_cmc), /* CMICm dma on multiple cmc */ \ 527 SHR_G_ENTRY(ism_memory), /* Support for ISM memory */ \ 528 SHR_G_ENTRY(shared_hash_mem), /* Support for shared hash memory */ \ 529 SHR_G_ENTRY(shared_hash_ins), /* Support for sw based shared hash ins */ \ 530 SHR_G_ENTRY(unified_port), /* Support new unified port design */ \ 531 SHR_G_ENTRY(sbusdma), /* CMICM SBUSDMA support */ \ 532 SHR_G_ENTRY(regex), /* Regex signature match */ \ 533 SHR_G_ENTRY(l3_ecmp_1k_groups), /* L3 ECMP 1K Groups */ \ 534 SHR_G_ENTRY(advanced_flex_counter), /* Advance flexible counter feature */ \ 535 SHR_G_ENTRY(ces), /* Circuit Emulation Services */ \ 536 SHR_G_ENTRY(ddr3), /* External DDR3 Buffer */ \ 537 SHR_G_ENTRY(iproc_ddr), /* iProc DDR initialization */ \ 538 SHR_G_ENTRY(mpls_entropy), /* MPLS Entropy-label feature */ \ 539 SHR_G_ENTRY(global_meter), /* Service meter */ \ 540 SHR_G_ENTRY(global_meter_v2), /* Service meter filter packet attribute with TCAM */ \ 541 SHR_G_ENTRY(global_meter_source_l2), /* Service meter support Policer ID associated with L2 table */ \ 542 SHR_G_ENTRY(global_meter_mef_10dot3), /* MEF 10.3 compliant Service meter */ \ 543 SHR_G_ENTRY(global_meter_macro_micro_same_pool), /* Both must be in same pool */ \ 544 SHR_G_ENTRY(global_meter_pool_priority_descending), /* Global meter pool priority Order 0[high]-7[low] */ \ 545 SHR_G_ENTRY(modport_map_dest_is_port_or_trunk), /* Modport map destination is specified as a Higig port or a Higig trunk, instead of as a Higig port bitmap */ \ 546 SHR_G_ENTRY(mirror_encap_profile), /* Egress mirror encap data profile */ \ 547 SHR_G_ENTRY(directed_mirror_only), /* Only directed mirroring mode */ \ 548 SHR_G_ENTRY(axp), /* Auxiliary ports */ \ 549 SHR_G_ENTRY(etu_support), /* External TCAM support */ \ 550 SHR_G_ENTRY(controlled_counters), /* L3 ECMP 1K Groups */ \ 551 SHR_G_ENTRY(higig_misc_speed_support), /* Misc speed support - 21G, 42G */ \ 552 SHR_G_ENTRY(e2ecc), /* End-to-end congestion control */ \ 553 SHR_G_ENTRY(vpd_profile), /* VLAN protocol data profile */ \ 554 SHR_G_ENTRY(color_prio_map_profile), /* Map color priority via profile */ \ 555 SHR_G_ENTRY(hg_dlb_member_id), /* Higig DLB member ports are converted to member IDs */ \ 556 SHR_G_ENTRY(lag_dlb), /* LAG dynamic load balancing */ \ 557 SHR_G_ENTRY(ecmp_dlb), /* ECMP dynamic load balancing */ \ 558 SHR_G_ENTRY(ecmp_dlb_optimized), /* TH2 version ECMP Dynamic load balancing. */ \ 559 SHR_G_ENTRY(hgt_lag_dlb_optimized), /* TH2 version HGT/LAG Dynamic load balancing. */ \ 560 SHR_G_ENTRY(ecmp_dlb_property_force_set), /* force set without notifying when ecmp member's dlb property conflicts. */ \ 561 SHR_G_ENTRY(td3_dlb), /* dlb TD3 changes */ \ 562 SHR_G_ENTRY(td3_lpm_ipmc_war), /* LPM IPMC WAR for TD3X */ \ 563 SHR_G_ENTRY(dgm), /* Dynamic Group Multipath */ \ 564 SHR_G_ENTRY(l2gre), /* L2-VPN over GRE Tunnels */ \ 565 SHR_G_ENTRY(l2gre_default_tunnel), /* Default tunnel based forwarding during L2-GRE VPN lookup failure */ \ 566 SHR_G_ENTRY(static_repl_head_alloc), /* Allocation of REPL_HEAD table entries is static */ \ 567 SHR_G_ENTRY(vlan_double_tag_range_compress), /* VLAN range compression for double tagged packets */\ 568 SHR_G_ENTRY(vlan_protocol_pkt_ctrl), /* per VLAN protocol packet control */ \ 569 SHR_G_ENTRY(l3_extended_host_entry), /* Extended L3 host entry with embedded NHs */ \ 570 SHR_G_ENTRY(repl_head_ptr_replace), /* MMU supports replacement of REPL_HEAD pointers in multicast queues */ \ 571 SHR_G_ENTRY(remote_encap), /* Higig2 remote replication encap */ \ 572 SHR_G_ENTRY(rx_reason_overlay), /* RX reasons are in overlays */ \ 573 SHR_G_ENTRY(extended_queueing), /* Extened queueing suport */ \ 574 SHR_G_ENTRY(dynamic_sched_update), /* Enable dynamic update of scheduler mode */ \ 575 SHR_G_ENTRY(schan_err_check), /* Enable dynamic update of scheduler mode */\ 576 SHR_G_ENTRY(l3_reduced_defip_table), /* Reduced L3 route table */ \ 577 SHR_G_ENTRY(l3_expanded_defip_table), /* Expanded L3 route table - e.g. 32 physical tcams */ \ 578 SHR_G_ENTRY(rtag1_6_max_portcnt_less_than_rtag7), /* Max port count for RTAG 1-6 is less than RTAG 7 */ \ 579 SHR_G_ENTRY(vlan_xlate), /* Vlan translation on MPLS packets */ \ 580 SHR_G_ENTRY(split_repl_group_table), /* MMU replication group table is split into 2 halves */ \ 581 SHR_G_ENTRY(pim_bidir), /* Bidirectional PIM */ \ 582 SHR_G_ENTRY(l3_iif_zero_invalid), /* L3 ingress interface ID 0 is invalid */ \ 583 SHR_G_ENTRY(vector_based_spri), /* MMU vector based strict priority scheduling */ \ 584 SHR_G_ENTRY(vxlan), /* L2-VPN over UDP Tunnels */ \ 585 SHR_G_ENTRY(ep_redirect), /* Egress pipeline redirection */ \ 586 SHR_G_ENTRY(repl_l3_intf_use_next_hop), /* For each L3 interface, MMU replication outputs a next hop index */ \ 587 SHR_G_ENTRY(dynamic_shaper_update), /* Enable dynamic update of shaper rates */ \ 588 SHR_G_ENTRY(nat), /* NAT */ \ 589 SHR_G_ENTRY(l3_iif_profile), /* Profile for L3_IIF */ \ 590 SHR_G_ENTRY(l3_ip4_options_profile), /* Supports special handling for IP4 options */\ 591 SHR_G_ENTRY(linkphy_coe), /* Supports LinkPHY subports (IEEE G.999.1) */ \ 592 SHR_G_ENTRY(subtag_coe), /* Supports SubTag (Third VLAN tag) subports */ \ 593 SHR_G_ENTRY(tr3_sp_vector_mask), /* SP <-> WRR configuration sequence */ \ 594 SHR_G_ENTRY(cmic_reserved_queues), /* CMIC has reserved queues */ \ 595 SHR_G_ENTRY(pgw_mac_rsv_mask_remap), /* PGW_MAC_RSV_MASK address remap */ \ 596 SHR_G_ENTRY(endpoint_queuing), /* Endpoint queuing */ \ 597 SHR_G_ENTRY(service_queuing), /* Service queuing */ \ 598 SHR_G_ENTRY(mirror_control_mem), /* Mirror control is not register */ \ 599 SHR_G_ENTRY(mirror_table_trunk), /* Mirror MTPs duplicate trunk info */ \ 600 SHR_G_ENTRY(port_extension), /* Port Extension (IEEE 802.1Qbh) */ \ 601 SHR_G_ENTRY(port_extension_kt2_key_type), /* Port Extension key type change for certain devices */\ 602 SHR_G_ENTRY(linkscan_pause_timeout), /* wating for Linkscan stopped signal with timeout*/\ 603 SHR_G_ENTRY(port_extender_vp_sharing), /* Port Extender vp sharing for certain devices */\ 604 SHR_G_ENTRY(linkscan_lock_per_unit), /* linkscsan lock per unit instead of spl*/\ 605 SHR_G_ENTRY(easy_reload_wb_compat), /* Support Easy Reload and Warm boot within the same compilation*/\ 606 SHR_G_ENTRY(mac_virtual_port), /* MAC-based virtual port */ \ 607 SHR_G_ENTRY(virtual_port_routing), /* VP based routing for VP LAG */ \ 608 SHR_G_ENTRY(counter_toggled_read), /* Toggled read of counter tables */ \ 609 SHR_G_ENTRY(vp_lag), /* Virtual port LAG */ \ 610 SHR_G_ENTRY(min_resume_limit_1), /* min resume limit for port-sp */ \ 611 SHR_G_ENTRY(hg_dlb_id_equal_hg_tid), /* Higig DLB ID is the same as Higig trunk ID */ \ 612 SHR_G_ENTRY(hg_resilient_hash), /* Higig resilient hashing */ \ 613 SHR_G_ENTRY(lag_resilient_hash), /* LAG resilient hashing */ \ 614 SHR_G_ENTRY(ecmp_resilient_hash), /* ECMP resilient hashing */ \ 615 SHR_G_ENTRY(min_cell_per_queue), /* reserve a min number of cells for queue */ \ 616 SHR_G_ENTRY(gphy), /* Built-in GPhy Support */ \ 617 SHR_G_ENTRY(cpu_bp_toggle), /* CMICm backpressure toggle */ \ 618 SHR_G_ENTRY(ipmc_reduced_table_size), /* IPMC with reduced table size */ \ 619 SHR_G_ENTRY(mmu_reduced_internal_buffer), /* Recuded MMU internal packet buffer */\ 620 SHR_G_ENTRY(ipmc_unicast), /* Support for IPMC with unicast MAC-DA */\ 621 SHR_G_ENTRY(l3_256_defip_table), /* Route table sizing for certain device SKUs */\ 622 SHR_G_ENTRY(l3_32k_defip_table), /* Route table sizing for 32k indexed defip device */\ 623 SHR_G_ENTRY(no_vrf_stats), /* VRF Stats not available on device. E.g. Ranger/Ranger+ */\ 624 SHR_G_ENTRY(mmu_packing), /* MMU buffer packing */\ 625 SHR_G_ENTRY(mmu_hw_flush), /* MMU Hardware Flush */\ 626 SHR_G_ENTRY(l3_shared_defip_table), /* lpm table sharing between 128b and V4, 64b entries */\ 627 SHR_G_ENTRY(l3_nh_attr_table), /* A separate attribute table to hold DLB adjustments and L3 MTU */\ 628 SHR_G_ENTRY(fcoe), /* fiber channel over ethernet */ \ 629 SHR_G_ENTRY(system_reserved_vlan), /* Supports System Reserved VLAN */ \ 630 SHR_G_ENTRY(ipmc_remap), /* Supports IPMC remapping */ \ 631 SHR_G_ENTRY(proxy_port_property), /* Allow configuration of per-source port LPORT properties. */ \ 632 SHR_G_ENTRY(multiple_split_horizon_group), /* multiple split horizon group support */ \ 633 SHR_G_ENTRY(reserve_shg_network_port), /* Reserve split horizon group (1) for network port by default */ \ 634 SHR_G_ENTRY(shg_support_remote_port), /* Allow remote ports to be part of same SHG split horizon group */ \ 635 SHR_G_ENTRY(uc), /* Embedded core(s) for applications */ \ 636 SHR_G_ENTRY(uc_mhost), /* Embedded core(s) - iProc mHost */ \ 637 SHR_G_ENTRY(overlaid_address_class), /* Overlaid address class support (With over lay PRI bits)*/ \ 638 SHR_G_ENTRY(special_egr_ip_tunnel_ser), /* EGR_IP_TUNNEL overlay memory ser support for older devices */ \ 639 SHR_G_ENTRY(common_egr_ip_tunnel_ser), /* EGR_IP_TUNNEL genernal memory ser support */ \ 640 SHR_G_ENTRY(efp_meter_table_write_ignore_nack), /* Ignore unexpected nack when writing to EFP_METER_TABLE */ \ 641 SHR_G_ENTRY(memory_2bit_ecc_ser), /* Memory SER support inject 2 bit error */ \ 642 SHR_G_ENTRY(mirror_cos), /* Mirror UC/MC COS controls */ \ 643 SHR_G_ENTRY(lltag), /* The out most tag as the LLTAG */\ 644 SHR_G_ENTRY(mem_parity_eccmask), /* memory fields of Parity and ECC masking */ \ 645 SHR_G_ENTRY(wred_drop_counter_per_port), /* Per port WRED dropped counter */ \ 646 SHR_G_ENTRY(l2_no_vfi), /* No VFI support */ \ 647 SHR_G_ENTRY(l3mc_use_egress_next_hop), /* L3MC egress logic will use egress next hop for replication */ \ 648 SHR_G_ENTRY(field_action_pfc_class), /* Replace the internal priority of PFC class */ \ 649 SHR_G_ENTRY(fifo_dma_hu2), /* use the hu2 driver fucntion to handle the fifo dma */ \ 650 SHR_G_ENTRY(eee_bb_mode), /* EEE burst and batch mode */ \ 651 SHR_G_ENTRY(cmicd_v2), /* CMICd v2 */ \ 652 SHR_G_ENTRY(int_common_init), /* internal function _bcm_common_init */ \ 653 SHR_G_ENTRY(inner_tpid_enable), /* inner tpid enable to detect itag */\ 654 SHR_G_ENTRY(counter_eviction), /* Counter eviction */\ 655 SHR_G_ENTRY(l3_no_ecmp), /* no ECMP */ \ 656 SHR_G_ENTRY(no_tunnel), /* no tunnel */ \ 657 SHR_G_ENTRY(ecn_wred), /* ECN-WRED architecture */ \ 658 SHR_G_ENTRY(ipmc_use_configured_dest_mac), /* IPMC configure multicast mac address */ \ 659 SHR_G_ENTRY(core_clock_300m), /* system core clock is 300 Mhz */ \ 660 SHR_G_ENTRY(l3_lpm_scaling_enable), /* Allows 64b entries to be added in the paired TCAM*/\ 661 SHR_G_ENTRY(l3_lpm_128b_entries_reserved), /* Paired TCAM space is not reserved */\ 662 SHR_G_ENTRY(hg_no_speed_change), /* HiGig encap setup without speed modification */ \ 663 SHR_G_ENTRY(mac_based_vlan), /* MAC based VLAN support */ \ 664 SHR_G_ENTRY(esm_correction), /* Recovery for esm when esm fatal error detected */ \ 665 SHR_G_ENTRY(l3_defip_advanced_lookup), /* both DIP and SIP lookup using single DEFIP entry */ \ 666 SHR_G_ENTRY(ip_subnet_based_vlan), /* IP subnet based VLAN support */ \ 667 SHR_G_ENTRY(portmod), /* MAC and PHY managed trough Portmod */ \ 668 SHR_G_ENTRY(fabric_cell_pcp), /* packet cell packing */ \ 669 SHR_G_ENTRY(fe_mc_id_range), /* FE multicast id and mode */ \ 670 SHR_G_ENTRY(fe_mc_priority_mode_enable), /* FE multicast cell priority mode */ \ 671 SHR_G_ENTRY(round_robin_load_balance), /* Round Robin Load Balance for HG Trunk and LAG */ \ 672 SHR_G_ENTRY(randomized_load_balance), /* Randomized Load Balance for HG Trunk and LAG */ \ 673 SHR_G_ENTRY(asymmetric_dual_modid), /* Asymmetric dual module ID support */ \ 674 SHR_G_ENTRY(mim_reserve_default_port), /* reserve default svp port for MiM */ \ 675 SHR_G_ENTRY(mim_peer_sharing), /* Support for sharing a peer mim port */ \ 676 SHR_G_ENTRY(tsce), /* TSC Eagle */ \ 677 SHR_G_ENTRY(tscf), /* TSC Falcon */ \ 678 SHR_G_ENTRY(hr2_dual_hash), /* HR2 series including GH style dual hash, \ 679 used to handle the difference with other chips */\ 680 SHR_G_ENTRY(l2_hw_aging_bug), /* L2 HW aging bug (BCM56850_A0/A1/A2) */ \ 681 SHR_G_ENTRY(flex_hashing), /* Flexible hashing support */ \ 682 SHR_G_ENTRY(udf_hashing), /* UDF hashing support */ \ 683 SHR_G_ENTRY(visibility), /* Instrumentation: visibility support */ \ 684 SHR_G_ENTRY(l3_ecmp_2k_groups), /* L3 ECMP 2K Groups */ \ 685 SHR_G_ENTRY(ecmp_resilient_hash_optimized), /* ECMP RH where RH group is in member table */ \ 686 SHR_G_ENTRY(ecmp_random), /* Randomized Load Balancing for ECMP */ \ 687 SHR_G_ENTRY(ecmp_round_robin), /* Round Robin Load Balancing for ECMP */ \ 688 SHR_G_ENTRY(asf_multimode), /* Multimode ASF (Cutthrough) */ \ 689 SHR_G_ENTRY(led_cmicd_v2), /* LED processor support in CMICd v2 */ \ 690 SHR_G_ENTRY(epc_linkflap_recover), /* WAR for EPC_LINK_BMP modport issue - SDK-55975*/ \ 691 SHR_G_ENTRY(timesync_timestampingmode), /* 32bit or 48bit timestamping mode for 1588 packets*/ \ 692 SHR_G_ENTRY(trill_ttl), /* TTL control for TRILL Rbridge*/ \ 693 SHR_G_ENTRY(oam_lookup_bypass_cpu_tx_packets), /*Bypass OAM look up for CPU generated packets */ \ 694 SHR_G_ENTRY(unique_acc_type_access), /* unique acc_type = pipe_num */ \ 695 SHR_G_ENTRY(memscan_ifp_slice_adjust), /* memscan will do idx adjustments for narrow, wide ifp_slice */ \ 696 SHR_G_ENTRY(robust_hash), /* Robust Hash support */ \ 697 SHR_G_ENTRY(extended_hash), /* Extended hash tables support (BCM56850|BCM56960) */ \ 698 SHR_G_ENTRY(cport_clmac), /*Chip uses a CLMAC in a CPORT block*/ \ 699 SHR_G_ENTRY(td2p_multi_modid), /* TD2+ supports multiple modids*/ \ 700 SHR_G_ENTRY(vlan_vfi_membership), /* TD2+ has new vlan vfi membership tables*/ \ 701 SHR_G_ENTRY(vlan_filter), /* TD2+ has EN_IFILTER and EN_EFILTER fields per vlan */ \ 702 SHR_G_ENTRY(l3_egr_intf_zero_invalid), /* On TD2+, l3 egress intf index 0 is invalid */ \ 703 SHR_G_ENTRY(egr_vlan_control_is_memory), /* On TD2+, egr_vlan_control_1/2/3 are memories, not registers */ \ 704 SHR_G_ENTRY(meter_control_is_memory), /* On TD2+, meter related egr_counter_control/egr_shaping_control are memories, not registers */ \ 705 SHR_G_ENTRY(shaper_control_is_memory), /* On TD2+, shaper related egr_shaping_control is memory, not register */ \ 706 SHR_G_ENTRY(td2p_style_egr_outer_tpid), /* On TD2+, egr_port_1 is a memory */ \ 707 SHR_G_ENTRY(td2p_dvp_mirroring), /* On TD2+, EGR_MIRROR_ENABLE moved from ING_DVP_TABLE to ING_DVP_2_TABLE */ \ 708 SHR_G_ENTRY(my_station_2), /* TD2+ has MY_STATION_TCAM_2*/ \ 709 SHR_G_ENTRY(ingress_dest_port_enable), /* Ingress pipeline last stage packet block */ \ 710 SHR_G_ENTRY(llfc_force_xon), /* TD2+ and Tomahawk must set llfc xon */ \ 711 SHR_G_ENTRY(parity_injection_l2), /* TD2+ L2 parity */ \ 712 SHR_G_ENTRY(td2_l2gre), /* Td2+/Td2/TH has use the same tabel for l2gre */ \ 713 SHR_G_ENTRY(egr_modport_to_nhi), /* td2p maps global port to nexthop by EGR_DGPP_TO_NHIm */ \ 714 SHR_G_ENTRY(rtag7_port_profile), /* Td2+ get rtag7 profile index from PORT_TAB */ \ 715 SHR_G_ENTRY(egr_l3_next_hop_next_ptr), /* Td2+ has its own style EGR_L3_NEXT_HOP */ \ 716 SHR_G_ENTRY(ing_l3_next_hop_encoded_dest), /* Td2+ has different encodings for different destinations` */ \ 717 SHR_G_ENTRY(td2p_mpls_linear_protection), /* TD2+ 1:1 and 1+1 protection switching */ \ 718 SHR_G_ENTRY(vfi_zero_invalid), /* VFI value 0 is invalid on Tomahawk and TD2+ */ \ 719 SHR_G_ENTRY(ifp_redirect_to_dvp), /* ING_DVP_2 table to be read when IFP redirects a packet to a DVP */ \ 720 SHR_G_ENTRY(tcam_shift), /*TD2+ only*/ \ 721 SHR_G_ENTRY(hgproxy_subtag_coe), /* Enhanced support SubTag (Third VLAN tag) subports */ \ 722 SHR_G_ENTRY(snap), /* SNAP header */ \ 723 SHR_G_ENTRY(CnTag), /* CnTag */ \ 724 SHR_G_ENTRY(enable_lp), /*TD2+ enabling low power lookups */ \ 725 SHR_G_ENTRY(shared_bank_lp_disabled), /* Low power mode disabled for shared banks. */ \ 726 SHR_G_ENTRY(pgw_mac_control_frame), /*TD2+ use PGW_MAC_RSV_MASK instead of CLMAC_RX_CTRL.RX_PASS_CTRL */ \ 727 SHR_G_ENTRY(pgw_mac_pfc_frame), /*TD2+ use PGW_MAC_RSV_MASK instead of CLMAC_PFC_CTRL.RX_PASS_PFC */ \ 728 SHR_G_ENTRY(mpls_lsr_ecmp), /* MPLS LSR ECMP*/ \ 729 SHR_G_ENTRY(avs), /* AVS closeloop algorithm support */ \ 730 SHR_G_ENTRY(avs_openloop), /* AVS openloop algorithm support */ \ 731 SHR_G_ENTRY(src_port_consistency_check_skip), /* Don't perform SRC port consistency check*/ \ 732 SHR_G_ENTRY(hg_proxy_second_pass), /*TD2+ uses reserved DGLP to trigger loopback processing.*/ \ 733 SHR_G_ENTRY(l2_entry_used_as_my_station), /*TD2+ use L2_ENTRY and L2_USER_ENTRY as my station */ \ 734 SHR_G_ENTRY(egr_ipmc_cfg2_is_memory), /* EGR_IPMC_CFG2 register is a memory on TD2+ */ \ 735 SHR_G_ENTRY(vrf_aware_vxlan_termination), /*TD2+ support VRF aware vxlan termination */ \ 736 SHR_G_ENTRY(mbist), /* MBIST support */ \ 737 SHR_G_ENTRY(ecmp_failover), /* ECMP failover support */ \ 738 SHR_G_ENTRY(ecmp_failover_config_check), /* Check configuration on ECMP failover */ \ 739 SHR_G_ENTRY(ukernel_debug), /* ukernel debugging software support */ \ 740 SHR_G_ENTRY(sflow_ing_mem), /* Ingress Sflow data table support */ \ 741 SHR_G_ENTRY(hierarchical_ecmp), /* Hierarchical ECMP support */ \ 742 SHR_G_ENTRY(udf_support), /* UDF Support */ \ 743 SHR_G_ENTRY(vp_sharing), /* TD2+ supports shared VP across multiple VFIs */ \ 744 SHR_G_ENTRY(nexthop_share_dvp), /* TD2 supports shared network DVP across multiple nexthops */ \ 745 SHR_G_ENTRY(vfi_from_vlan_tables), /*TD2+ supports VFI assignment from VLAN, VFP and VLAN_XLATE table */ \ 746 SHR_G_ENTRY(egr_vlan_xlate_key_on_dvp), /*TD2+ supports egress vlan translation key generation on DVP */ \ 747 SHR_G_ENTRY(ing_vlan_xlate_second_lookup), /*TD2+ supports two ingress vlan translation lookups */ \ 748 SHR_G_ENTRY(egr_vlan_xlate_second_lookup), /* Apache supports two egress vlan translation lookups */ \ 749 SHR_G_ENTRY(egr_vxlate_supports_dgpp), /* Apache supports DGPP based entries in EGR_VLAN_XLATE table*/ \ 750 SHR_G_ENTRY(mpls_entry_second_label_lookup), /* Apache supports two mpls entry lookups */ \ 751 SHR_G_ENTRY(multi_next_hops_on_port), /* TD2+ multiple next hops on local port */ \ 752 SHR_G_ENTRY(use_flex_ctr_oam_lm), /* TD2Plus use Flex counters for OAM LM Measurement */ \ 753 SHR_G_ENTRY(ipmc_to_l2mc_table_size_2_to_3), /* TD2+ supports 8kL2MC groups and 16kIPMC groups, L2MC table size 24K*/ \ 754 SHR_G_ENTRY(reserve_vp_lag_resource_index_zero), /* Reserve entry 0 of VP LAG related resource */ \ 755 SHR_G_ENTRY(turbo_boot), /* Feature that speeds up initialization */ \ 756 SHR_G_ENTRY(oob_fc), /* OOB Flow Control */ \ 757 SHR_G_ENTRY(oob_stats), /* OOB Stats */ \ 758 SHR_G_ENTRY(fp_based_oam), /* OAM support based on FP */ \ 759 SHR_G_ENTRY(fp_based_sat), /* SAT support based on FP */ \ 760 SHR_G_ENTRY(uc_ccm), /* UC based OAM CCM Engine */ \ 761 SHR_G_ENTRY(mim_bvid_insertion_control), /* MIM BVID insertion controlled by EGR_L3_NEXT_HOP.BVID_VALID */ \ 762 SHR_G_ENTRY(td2p_mpls_entropy_label), /* TD2+ supports MPLS entropy label identifier at TOS*/ \ 763 SHR_G_ENTRY(reset_xlport_block_tsc12), /* reset XLPORT block in TSC12 in 100G config. */ \ 764 SHR_G_ENTRY(egress_lport), /* Egress Lport support */ \ 765 SHR_G_ENTRY(same_vlan_pruning_override), /* Same VLAN Pruning override */ \ 766 SHR_G_ENTRY(separate_ing_lport_rtag7_profile), /* The Ingress LPORT and RTAG7 profiling is done separately */ \ 767 SHR_G_ENTRY(egr_lport_tab_profile), /* Egress LPORT profiling support */ \ 768 SHR_G_ENTRY(misc_i2e_hgclass_combo_profile), /* Misc combined profiling for I2E/HG_CLASSID_SELECT */ \ 769 SHR_G_ENTRY(egr_qos_combo_profile), /* Egress QOS DSCP and PRI_CNG_MAP profiling together */ \ 770 SHR_G_ENTRY(riot), /* Routing Into and Out of Tunnels */ \ 771 SHR_G_ENTRY(vfi_profile), /* VFI Profile */ \ 772 SHR_G_ENTRY(exact_width_match_mode), /* Exact width match mode for lookup */ \ 773 SHR_G_ENTRY(oam_service_pri_map), /* QOS Map infrastructure for adding map in ING/EGR_SERVICE_PRI_MAP_0/1/2 tables */ \ 774 SHR_G_ENTRY(td2p_ovstb_toggle), /* TD2+ execute the OVST sequence */ \ 775 SHR_G_ENTRY(extended_view_no_trunk_support), /* Trunks or Lags not supported in extended view */ \ 776 SHR_G_ENTRY(key_type_valid_on_vp_vlan_membership), /* Key type is valid on ing/egr_vp_vlan_membership */ \ 777 SHR_G_ENTRY(prigrp_to_obm_prio_map), /* Use the Priority Group (PG) Mapping as OBM Priority Map*/ \ 778 SHR_G_ENTRY(sflow_flex), /* Flex sFlow support */ \ 779 SHR_G_ENTRY(td2p_fp_sw_war), /* TD2+ A0 FP SW WAR */ \ 780 SHR_G_ENTRY(td2p_a0_sw_war), /* TD2+ A0 SW WAR */ \ 781 SHR_G_ENTRY(monterey_a0_fp_sw_war), /* Monterey A0 FP SW WAR */ \ 782 SHR_G_ENTRY(monterey_b0_fp_sw_war), /* Monterey B0 FP SW WAR */ \ 783 SHR_G_ENTRY(advanced_flex_counter_dual_pipe), /* TD2/TD2+/TT2 use advanced flex dual counter memory */ \ 784 SHR_G_ENTRY(sflow_ing_mirror), /* Support sflow sample packet ingress mirroring */ \ 785 SHR_G_ENTRY(l3_iif_under_4k), /* l3_iif table size under 4096 */ \ 786 SHR_G_ENTRY(ipmc_l2_use_vlan_vpn), /* Devices which provide vlan based lookup for IPMC in L3 MCAST ENTRY */ \ 787 SHR_G_ENTRY(ipmc_defip), /* Lookup defip table when L3_ENTRY table lookup failed for IP MC pkt */ \ 788 SHR_G_ENTRY(fastlag), /* TH supports only Fast LAG in Low Latency Modes */ \ 789 SHR_G_ENTRY(cancun), /* Cancun capable */ \ 790 SHR_G_ENTRY(l3_max_2_defip_tcams), /* Only 2 L3_DEFIP tcams present */ \ 791 SHR_G_ENTRY(oam_pm), /* Performance monitoring support for LM DM apps */\ 792 SHR_G_ENTRY(faults_multi_ep_get), /* OAM faults get for all Endpoints */\ 793 SHR_G_ENTRY(sflow_counters), /* sFlow counters support */ \ 794 SHR_G_ENTRY(nh_for_ifp_actions), /* All the IP and non-IP packets will be redirected to the given next hop index if the FP rule hits. */ \ 795 SHR_G_ENTRY(pause_control_update), /* PAUSE Control value updated, to prevent packet loss */ \ 796 SHR_G_ENTRY(egress_failover), /*egress protection switching for multicast/broadcast/DLF traffic using flood and prune in TD2+*/ \ 797 SHR_G_ENTRY(field_exact_match_support), /* FP per-pipe exact match stage supported. */ \ 798 SHR_G_ENTRY(flexport_based_speed_set), /* Use flexport operation for speed change, where supported, when MAC/PHY 799 ability masks do not support the requested speed change */ \ 800 SHR_G_ENTRY(udf_multi_pipe_support), /* UDF per-pipe configuration model supported. */\ 801 SHR_G_ENTRY(fast_ecmp), /* Fast ECMP */ \ 802 SHR_G_ENTRY(multi_level_ecmp), /* Multi-level ECMP support */ \ 803 SHR_G_ENTRY(miml), /* Mac-in-Mac Lite (MiML) support */ \ 804 SHR_G_ENTRY(flowcnt), /* flow counter */ \ 805 SHR_G_ENTRY(custom_header), /* 32-bits custom header support */ \ 806 SHR_G_ENTRY(ing_capwap_parser), /* Ingress CAPWAP parser support */ \ 807 SHR_G_ENTRY(agm), /* Aggregation Monitor */ \ 808 SHR_G_ENTRY(flex_counter_opaque_stat_id), /* Flex counter opaque Stat ID */ \ 809 SHR_G_ENTRY(field_quarter_slice_single_tcam), /* Support for Quarter Slice in Chips where there is only 810 * one tcam per slice */ \ 811 SHR_G_ENTRY(field_half_slice_single_tcam), /* Support for Half Slice in Chips where there is only 812 * one tcam per slice */ \ 813 SHR_G_ENTRY(th_a0_sw_war), /* Feature used to enable all SW WARs for TH A0 */ \ 814 SHR_G_ENTRY(time_synce_divisor_setting), /* SyncE Divisor Setting */ \ 815 SHR_G_ENTRY(pfc_deadlock), /* PFC Deadclock Detection and Recovery feature */ \ 816 SHR_G_ENTRY(alpm), /* ALPM feature */ \ 817 SHR_G_ENTRY(alpm2), /* ALPM 2nd gen feature */ \ 818 SHR_G_ENTRY(alpm_flex_stat), /* ALPM flex counter feature */ \ 819 SHR_G_ENTRY(alpm_flex_stat_v6_64), /* ALPM v6_64 flex counter WAR */ \ 820 SHR_G_ENTRY(alpm_addr_xlate), /* ALPM address translation */ \ 821 SHR_G_ENTRY(trust_outer_dot1p), /*trust outer dot1p */ \ 822 SHR_G_ENTRY(gh_style_pfc_config), /* GH style PFC configuration */ \ 823 SHR_G_ENTRY(mpls_5_label_parsing), /* MPLS 5 label parsing */ \ 824 SHR_G_ENTRY(egr_ipmc_mem_field_l3_payload_valid), /* egress ipmc mem field l3_payload valid */ \ 825 SHR_G_ENTRY(centralized_counter), /* Support for Centralized counter model */ \ 826 SHR_G_ENTRY(l3_2k_defip_table), /* Route table size for 56832 SKU 827 since it has only 2 TCAMs */ \ 828 SHR_G_ENTRY(l3_1k_defip_table), /* Route table size for Ranger3+ */ \ 829 SHR_G_ENTRY(egr_mmu_cell_credit_is_memory), /* EGR_MMU_CELL_CREDIT is a memory instead of register on TH2 */ \ 830 SHR_G_ENTRY(mmu_sed), /* New block is introduced in TH2 for MMU Slice Control Enqueue Dequeue (SED) */ \ 831 SHR_G_ENTRY(ing_trill_adjacency_is_memory), /* ING_TRILL_ADJACENCY is a memory instead of register on TH2 */ \ 832 SHR_G_ENTRY(clmac_16byte_interface_mode), /* CLMAC supports 16 Byte interface mode */ \ 833 SHR_G_ENTRY(pm_refclk_master), /* port macros act as the refclk master */ \ 834 SHR_G_ENTRY(mpls_ecn), /* mpls ecn feature */ \ 835 SHR_G_ENTRY(xgs5_flexport_legacy_mode), /* xgs5 implementation for legacy flexport APIs */ \ 836 SHR_G_ENTRY(cmicd_v4), /* CMICd V4 */ \ 837 SHR_G_ENTRY(led_cmicd_v4), /* LED processor support in CMICd v4 */ \ 838 SHR_G_ENTRY(mor_dma), /* Support for Multiple Outstanding Request DMA */ \ 839 SHR_G_ENTRY(mpls_segment_routing), /* Segment routing support on Apache */ \ 840 SHR_G_ENTRY(ep_redirect_v2), /* EP Redirect V2 */ \ 841 SHR_G_ENTRY(flex_ctr_mpls_3_label_count), /* 3 Label MPLS counting support on Apache */ \ 842 SHR_G_ENTRY(hierarchical_protection), /* hierarchical protection support on Apache */ \ 843 SHR_G_ENTRY(olp), /* Device supports OLP */ \ 844 SHR_G_ENTRY(cpu_as_olp), /* Device supports configuring cpu port as olp port*/ \ 845 SHR_G_ENTRY(deprecated_api), /* For APIs need to be deprecated */ \ 846 SHR_G_ENTRY(fp_nw_tcam_prio_order_war), /* Feature used to enable SW WAR for adjusting narrow wide TCAM indices in priority order. */ \ 847 SHR_G_ENTRY(field_qual_vlanformat_reverse), /* The position of outer/inner tagged bits are reverse */ \ 848 SHR_G_ENTRY(cpureg_dump), /* Use reg info to dump cpureg */ \ 849 SHR_G_ENTRY(generic_dest), /* Support Generic DESTINATION format-in-format field */ \ 850 SHR_G_ENTRY(base_valid), /* Support base valid resolution */ \ 851 SHR_G_ENTRY(mirror_four_port_trunk), /* Mirror supports upto 4 ports in trunk group */ \ 852 SHR_G_ENTRY(field_compression), /*FP compression supported. */\ 853 SHR_G_ENTRY(fast_egr_vlan_action), /* Egress VLAN action for low latency mode */ \ 854 SHR_G_ENTRY(vlan_vfi), /* Vlan Vfi */ \ 855 SHR_G_ENTRY(egr_vlan_action), /* Egress VLAN action for balanced mode */ \ 856 SHR_G_ENTRY(clmac_partial_support), /* Only few CPORTs support CLMAC. */ \ 857 SHR_G_ENTRY(hr3_switch_encap_index_shift2_war), /* Feature used to enable SW WAR for 858 adjusting EGR_HEADER_ENCAP_DATA indices are shifted << 2 bits. */ \ 859 SHR_G_ENTRY(mpls_exp_to_phb_cng_map), /* MPLS EXP to PHB,CNG Map tables */ \ 860 SHR_G_ENTRY(mmu_hqos_four_level), /*Four level Hqos suppport for Apache */\ 861 SHR_G_ENTRY(management_port_lanes), /* Number of lanes for Management port */ \ 862 SHR_G_ENTRY(fp_oam_drop_control), /* FP based OAM drop control */ \ 863 SHR_G_ENTRY(rx_pkt_hdr_format_higig2), /* CPU packets recevied from CMIC have higig2 header */ \ 864 SHR_G_ENTRY(mpls_swap_label_preserve), /* mpls swap label is kept intact*/ \ 865 SHR_G_ENTRY(fast_init), /* Fast init for low latency modes */ \ 866 SHR_G_ENTRY(cmicd_v3), /* CMICD V3 */ \ 867 SHR_G_ENTRY(no_l2_remote_trunk), /*No L2 remote trunk (BCM56560_A0/BCM56860_A0) */ \ 868 SHR_G_ENTRY(dump_socmem_uses_dma), /* Feature to enable table dma for dump socmem */ \ 869 SHR_G_ENTRY(mmu_3k_uc_queue), /*device has 3k ucq */\ 870 SHR_G_ENTRY(mmu_1k_uc_queue), /*device has 1k ucq */\ 871 SHR_G_ENTRY(untethered_otp), /* Untethred Otp */ \ 872 SHR_G_ENTRY(vlan_vfi_untag_profile), /* Profile table for VLAN_VFI_UNTAG */ \ 873 SHR_G_ENTRY(cxl_mib), /* separate mib counter for different port types */ \ 874 SHR_G_ENTRY(cd_mib), /* separate mib counter for different port types */ \ 875 SHR_G_ENTRY(l2mc_table_no_shared_ipmc), /* L2MC table is not shared with IPMC 876 * on higig ports */ \ 877 SHR_G_ENTRY(uc_ulink), /* Ucore maintains link status */ \ 878 SHR_G_ENTRY(nh_ifp_action_src_dst_mac_swap), /* Swap source/destination MAC for outgoing packets, for IFP application only. */ \ 879 SHR_G_ENTRY(ignore_mem_write_nak), /* war to avoid the unexpected mem_write nak */ \ 880 SHR_G_ENTRY(ingress_failover), /* Support ingress protection switching */ \ 881 SHR_G_ENTRY(l2_use_l3_class_id), /* Enable L3 Lookup to get classids based on DIP & SIP for L2 Switched packets. */ \ 882 SHR_G_ENTRY(field_tcam_hitless_update_on_modify), /* Hitless update of tcams on modify */ \ 883 SHR_G_ENTRY(extended_address_class), /*extended address class id*/ \ 884 SHR_G_ENTRY(unimac_reset_wo_clock), /* Unimac sync reset without clock */ \ 885 SHR_G_ENTRY(internal_phy_link_check), /* checking internal phy link status when 886 external phy link up is detected */ \ 887 SHR_G_ENTRY(ing_l2tunnel_tpid_parser), /*Global Inner TPID of L2 Tunnel payload */ \ 888 SHR_G_ENTRY(l2_tunnel_transit_payload_tpid_parser), /* Matched TPID of Transit MIM/VXLAN/L2GRE Payload for Parser */ \ 889 SHR_G_ENTRY(field_udf_offset_hg_114B), /* HG+ header is located at Byte 114-125 in UDF */ \ 890 SHR_G_ENTRY(field_udf_offset_hg2_110B), /* HG2 header is located at Byte 110-125 in UDF */ \ 891 SHR_G_ENTRY(tcb), /* support tcb */ \ 892 SHR_G_ENTRY(ecmp_hash_bit_count_select), /* support to select lower bits of 16 bits hash value */ \ 893 SHR_G_ENTRY(pipe2_pipe3_disabled), /* Pipe2/Pipe3 are disabled */ \ 894 SHR_G_ENTRY(no_efp), /* EFP disabled */ \ 895 SHR_G_ENTRY(no_ifp), /* IFP disabled */ \ 896 SHR_G_ENTRY(no_vfp), /* VFP disabled */ \ 897 SHR_G_ENTRY(uft_bank_0), /* UFT bank 0 enabled */ \ 898 SHR_G_ENTRY(uft_bank_1), /* UFT bank 1 enabled */ \ 899 SHR_G_ENTRY(uft_bank_2), /* UFT bank 2 enabled */ \ 900 SHR_G_ENTRY(uft_bank_3), /* UFT bank 3 enabled */ \ 901 SHR_G_ENTRY(mpls_frr), /* MPLS fast reroute */ \ 902 SHR_G_ENTRY(timestamp), /* Timestamp enabled */ \ 903 SHR_G_ENTRY(field_multi_pipe_enhanced), /* TH2 enhanced Field features */ \ 904 SHR_G_ENTRY(miml_no_l3), /* Mac-in-Mac Lite (MiML) support without L3 feature */ \ 905 SHR_G_ENTRY(l3_tunnel_mpls_frr), /*To check l3 tunnel mpls frr lookup in apache*/ \ 906 SHR_G_ENTRY(l3_ecmp_4k_groups), /* L3 ECMP 4K Groups */ \ 907 SHR_G_ENTRY(esm_l2_lookup_for_ip6), /*Enable ESM L2 lookup for IPv6 packets*/ \ 908 SHR_G_ENTRY(flex_stat_ing_pools_4), /* Ingress Flexible Counters with 4 pools */ \ 909 SHR_G_ENTRY(hg_trunk_groups_max_2), /* Max Number of HiGig Trunk Groups is 2 */\ 910 SHR_G_ENTRY(hg_trunk_group_members_max_4),/* HiGig Trunk Group with maximum of 4 Members*/\ 911 SHR_G_ENTRY(dvp_2_config_required), /*Required to configure ING_DVP_2_TABLE*/ \ 912 SHR_G_ENTRY(xmac_reset_on_mode_change), /* Reset xmac on mode change */ \ 913 SHR_G_ENTRY(forwarding_db_no_support), /* forwarding database id-no support*/ \ 914 SHR_G_ENTRY(xlportb0), /* XLPORT B0 for PM4x10 in Apache A0 */ \ 915 SHR_G_ENTRY(clport_gen2), /* CLPORT GEN2 for PM4x25 in Apache B00 */ \ 916 SHR_G_ENTRY(l2_drop_mc_mac), /* L2 discard traffic with multicast destination */ \ 917 SHR_G_ENTRY(shared_defip_stat_support), /* Statistics support on shared defip tables */ \ 918 SHR_G_ENTRY(mpls_xgs5_nw_port_match), /* match mpls nw port to see if duplicate entry exists */ \ 919 SHR_G_ENTRY(mirror_ing_egr_single), /* restrict ingress/egress mirror on same port */ \ 920 SHR_G_ENTRY(dvp_group_pruning), /* Dvp group based pruning */ \ 921 SHR_G_ENTRY(hr3_lite_lpm_shadow_hit), /* HR3-Lite's LPM shadow hit(LPM entry in range of 32~63 for LPM hit operation will be occurre on LPM entry in 512~543 */ \ 922 SHR_G_ENTRY(l3_kt2_shared_defip_table), /* kt2 shared defip support */ \ 923 SHR_G_ENTRY(eee_stat_clear_directly), /* Clear EEE statistics by writing EEE counter/register directly */ \ 924 SHR_G_ENTRY(vc_and_swap_table_overlaid), /* vc and swap label tabe overlaid by egr_dvp_attribute_1*/ \ 925 SHR_G_ENTRY(field_action_l3_route_disabled), /* L3 routing base on FP action is disabled */ \ 926 SHR_G_ENTRY(th_tflow), /* Tomahawk Random sampling */ \ 927 SHR_G_ENTRY(th_fp_ctc_manipulate), /* To support CTC Manipulate SW WAR for TH Field Module. */ \ 928 SHR_G_ENTRY(th_pkt_trace_sw_war), /* SW workaround for TH packet trace. */ \ 929 SHR_G_ENTRY(td3_style_proxy), /* To support TD3 relevant proxy functionality */ \ 930 SHR_G_ENTRY(src_tgid_valid), /* To support instances where SRC_TGID is a valid field name */ \ 931 SHR_G_ENTRY(egr_intf_vlan_vfi_deoverlay), /* Egress Interface simultaneously provides both OVID as well as VFI */ \ 932 SHR_G_ENTRY(td3_style_riot), /* TD3 RIOT related programming changes */ \ 933 SHR_G_ENTRY(mem_access_data_type), /* Interpret data in a table by looking at DATA_TYPEf */ \ 934 SHR_G_ENTRY(pktpri_as_dot1p), /* Treat packet priority as dot1p. */ \ 935 SHR_G_ENTRY(split_repl_head_table), /* MMU_REPL_HEAD_TABLE is split */ \ 936 SHR_G_ENTRY(egr_all_profile), /* Enabled if mem_idx_cnt(EGR_VLAN_CONTROL_1m) == mem_idx_cnt(EGR_LPORT_PROFILEm) */ \ 937 SHR_G_ENTRY(mysta_profile), /* TRUE if MY_STATION_PROFILE_1/2 presents */ \ 938 SHR_G_ENTRY(flex_flow), /* Flex Flow implemented by FLexPP arch */ \ 939 SHR_G_ENTRY(no_egr_ipmc_cfg), /* EGR_IPMC_CFG table/reg is removed */ \ 940 SHR_G_ENTRY(td3_style_mpls), /* Trident3 Mpls Support */ \ 941 SHR_G_ENTRY(robust_hash_byte_boundary_alignment), /* Byte Boundary alignment for Robust Hash */ \ 942 SHR_G_ENTRY(mpls_special_label), /* special label controls */ \ 943 SHR_G_ENTRY(failover_mpls_check), /* Check for failover enable on MPLS ports */ \ 944 SHR_G_ENTRY(th_nh_no_overlap_ecmp), /* TH alloc NHI without overlapping ECMP indexes. */ \ 945 SHR_G_ENTRY(trill_egr_dvp_classid), /* Class ID assignment for TRILL flows using EGR_DVP_ATTRIBUTE_1 table */ \ 946 SHR_G_ENTRY(egr_nh_class_id_valid), /* feature check to read class id from egr nh only for valid devices */ \ 947 SHR_G_ENTRY(cosq_hol_drop_packet_count), /* Per COSQ HOL drop packet count. */ \ 948 SHR_G_ENTRY(hg_proxy_module_config), /* Module configurations for HG-Proxy and Two-pass loopback applications */ \ 949 SHR_G_ENTRY(l3_tunnel_expanded_mod_mask), /* 8 bit mod mask for l3 tunnel term */ \ 950 SHR_G_ENTRY(fp_qual_recovery_with_group_create), /* Group Qualifier offset recovery based on dummy group create */ \ 951 SHR_G_ENTRY(linkscan_continuous), /* Perform MDIO write/read operation without stalling active linkscan operation */ \ 952 SHR_G_ENTRY(vlan_egress_membership_l3_only), /* Egress VLAN membership check for L3 flow only */ \ 953 SHR_G_ENTRY(egr_ip_tnl_mpls_double_wide), /* Apache variants support double wide EGR_IP_TUNNEL_MPLS */ \ 954 SHR_G_ENTRY(mpls_lm_dm), /* Device supports MPLS_LM_DM App */ \ 955 SHR_G_ENTRY(lls_port_mema_config_match), /* ES_PIPE0/1_LLS_PORT_MEMA/B_CONFIG table size defined in regsfile match with actual physical memory size */ \ 956 SHR_G_ENTRY(link_status_get_need_phy_read_twice), /* In legacy devices, PHY status register may show wrong status on first read and we need to confirm by reading second time*/ \ 957 SHR_G_ENTRY(pm_fc_merge_mode), /* Merge mode should be enabled in PM FC config */ \ 958 SHR_G_ENTRY(egress_object_mac_da_replace), /* When MPLS egress object is replaced/converted to L3 object using BCM_L3_REPLACE flag, MAC DA in the L3 object will be configred with new value instead of using MAC DA from MPLS egress object */ \ 959 SHR_G_ENTRY(lpm_atomic_write), /* In order to provide atomicity during LPM entry updates (add or delete). */ \ 960 SHR_G_ENTRY(gh2_my_station), /* GH2 style MY_STATION_TCAM support */ \ 961 SHR_G_ENTRY(gh2_rtag7), /* RTAG7 support for GH2 */ \ 962 SHR_G_ENTRY(high_portcount_register), /* pbmp register is splited to two more reg due to 963 high port count(over 64 bits) */ \ 964 SHR_G_ENTRY(preemption), /* TSN preemption */ \ 965 SHR_G_ENTRY(preemption_cnt), /* TSN preemption counter */ \ 966 SHR_G_ENTRY(tas), /* TSN Time Aware Scheduling */ \ 967 SHR_G_ENTRY(preempt_mib_support), /* Preempt MIB counters support */ \ 968 SHR_G_ENTRY(clmib_support), /* CLMIB counters support for CL port */ \ 969 SHR_G_ENTRY(hg2_light_in_portmacro), /* to support HG2-Lite in PortMacro */ \ 970 SHR_G_ENTRY(vxlan_lite), /* L2-VPN over UDP Tunnels Lite support */ \ 971 SHR_G_ENTRY(tsn), /* Time-Sensitive Networking (TSN) */ \ 972 SHR_G_ENTRY(tsn_mtu_stu), /* TSN MTU/STU size check */ \ 973 SHR_G_ENTRY(tsn_sr), /* TSN Seamless Redundancy (SR) support */ \ 974 SHR_G_ENTRY(tsn_sr_hsr), /* TSN SR High-availability Seamless Redundancy (HSR) support */ \ 975 SHR_G_ENTRY(tsn_sr_prp), /* TSN SR Parallel Redundancy Protocol (PRP) support */ \ 976 SHR_G_ENTRY(tsn_sr_802_1cb), /* TSN SR IEEE 802.1CB support */ \ 977 SHR_G_ENTRY(tsn_sr_auto_learn), /* TSN SR automatic flow learning support */ \ 978 SHR_G_ENTRY(tsn_sr_flow_no_asf_select), /* No ASF can be selected for TSN SR flows */ \ 979 SHR_G_ENTRY(tsn_flow_no_asf_select), /* No ASF can be selected for TSN flows */ \ 980 SHR_G_ENTRY(tsn_taf), /* TSN Time Aware Filtering */ \ 981 SHR_G_ENTRY(rroce), /* Routable RDMA over Converged Ethernet (RRoCE) */ \ 982 SHR_G_ENTRY(discontinuous_pp_port), /* discontinuous pp port feature */ \ 983 SHR_G_ENTRY(port_group_for_ivxlt), /* Port-Group key type for ingress vlan translation */ \ 984 SHR_G_ENTRY(apache_round_robin_fp_lag), /* Apache Round Robin LAG support */ \ 985 SHR_G_ENTRY(apache_ovst_toggle), /* Apache A0/B0 parts needing ovst toggle sequence */ \ 986 SHR_G_ENTRY(truncate_cpu_copy), /* truncate_cpu_copy support */ \ 987 SHR_G_ENTRY(no_fabric), /* no Fabric */ \ 988 SHR_G_ENTRY(iddq_new_default), /* default value of iddq field changed */ \ 989 SHR_G_ENTRY(no_tdm), /* no TDM */ \ 990 SHR_G_ENTRY(no_sw_rx_los), /* No SOFTWARE_RX_LOS supported. */ \ 991 SHR_G_ENTRY(cmicm_multi_schan_cmc), /* CMICm schan on multiple cmc */ \ 992 SHR_G_ENTRY(evt_replace_tpid_only), /* EGR_VLAN_XLATE supports the ability to replace SD tag TPID only */ \ 993 SHR_G_ENTRY(redirect_nh_to_ecmp_for_mpls_php), /* Redirect NH to ECMP for MPLS PHP */ \ 994 SHR_G_ENTRY(sb2plus_1k_ecmp_groups), /*Differentiate Max ECMP group of SB2+(1024) from SB2(128) */ \ 995 SHR_G_ENTRY(inner_vlan_range_check), /* Support the ability to check inner vlan range */ \ 996 SHR_G_ENTRY(l2_cache_use_my_station), /* L2 cache entry configured with BCM_L2_CACHE_L3 will use my_station_tcam table */ \ 997 SHR_G_ENTRY(tcam_scan_engine), /* HW TCAM scan engine */ \ 998 SHR_G_ENTRY(port_leverage), /* Leverage DV port up/down for port enable/disable */\ 999 SHR_G_ENTRY(pstats), /* Packetized mmu Statistic */ \ 1000 SHR_G_ENTRY(flexport_no_legacy), /* Don't support legacy flexport API */\ 1001 SHR_G_ENTRY(ecmp_1k_paths_4_subgroups), /* 1K members per ECMP group with 4 subgroups having 256 members */ \ 1002 SHR_G_ENTRY(ifp_timestamptocpu_optimized), /*IFP COPY-with-TIMESTAMP action doesn't need Drop to be set on TD2/TD2+/TH/TH2*/ \ 1003 SHR_G_ENTRY(td3_style_dlb_rh), /* TD3 Resilient hashing programming changes*/ \ 1004 SHR_G_ENTRY(mpls_nh_ttl_control), /*Control TTL decrement per Next Hop for MPLS flows */\ 1005 SHR_G_ENTRY(rescal), /*support rescal*/ \ 1006 SHR_G_ENTRY(sw_autoneg), /* Support for SW AUTONEG */ \ 1007 SHR_G_ENTRY(vfp_no_inner_ip_fields_support), /* Doesn't support VFP matching on Inner IP fields */ \ 1008 SHR_G_ENTRY(td3_style_fp), /* TD3 Field Programming changes */ \ 1009 SHR_G_ENTRY(ifp_action_profiling), /* IFP action profiling feature changes */ \ 1010 SHR_G_ENTRY(ifp_no_inports_support), /* IFP qualifying on Inports is not supported */ \ 1011 SHR_G_ENTRY(xflow_macsec), /* Feature for Xflow Macsec */ \ 1012 SHR_G_ENTRY(xflow_macsec_stat), /* Feature for Xflow Macsec */ \ 1013 SHR_G_ENTRY(no_vlan_vrf), /* VRF is supported but has no VLAN based VRF */ \ 1014 SHR_G_ENTRY(switch_match), /* Switch Match Service */ \ 1015 SHR_G_ENTRY(half_of_l3_defip_ipv4_capacity), /* disable half of l3_defip ipv4 capacity */ \ 1016 SHR_G_ENTRY(e2efc), /* End-to-end flow control */ \ 1017 SHR_G_ENTRY(l2_learn_stats), /* L2 learned statistic support */ \ 1018 SHR_G_ENTRY(stat_multi_pipe_support), /* Stat per-pipe configuration model supported. */\ 1019 SHR_G_ENTRY(intcn_to_exp_nosupport), /* INTCN->EXP is support is deprecated in Trident3*/ \ 1020 SHR_G_ENTRY(flexible_higig_hdr), /* Supports flexible HG header construction */\ 1021 SHR_G_ENTRY(udf_td3x_support), /* TD3 UDF Support feature */ \ 1022 SHR_G_ENTRY(xy_tcam_x0y), /* New tcam encoding in TH2 IFP IPBMf */ \ 1023 SHR_G_ENTRY(packet_tdm_marking), /* fabric module is supported, but no fabric link used, WA for tdm latency */ \ 1024 SHR_G_ENTRY(vlan_pbmp_profile_mgmt), /* VLAN pbmp management using profile mem */ \ 1025 SHR_G_ENTRY(fp_no_dvp_support), /* No support for DVP */ \ 1026 SHR_G_ENTRY(fp_no_inner_vlan_support), /* No support for Inner Vlan Tag */ \ 1027 SHR_G_ENTRY(tunnel_term_hash_table), /* Tunnel term is a Hash table */ \ 1028 SHR_G_ENTRY(defip_2_tcams_with_separate_rpf), /* used 2 tcams for DIP and extra tcams for RPF */ \ 1029 SHR_G_ENTRY(sync_port_lport_tab), /* sync the configure to both port and lport table */ \ 1030 SHR_G_ENTRY(no_qt_gport), /* No gport model in QT */ \ 1031 SHR_G_ENTRY(use_local_1588), /* use local IP 1588 time info */ \ 1032 SHR_G_ENTRY(my_station_tcam_check), /* My_station_tcam delete check for TD2+ and Apache */ \ 1033 SHR_G_ENTRY(stat_egr_multi_pipe_support), /* Stat per-pipe configuration model supported in egress. */\ 1034 SHR_G_ENTRY(agm_support_for_dgm), /* Support agm for dgm ecmp group */ \ 1035 SHR_G_ENTRY(l2_activity_freeze_ser), /* Freezing and restoring L2 activity during SER */ \ 1036 SHR_G_ENTRY(modport_map_dest_is_hg_port_bitmap), /* Modport map destination is specified as a Higig port bitmap, instead of as a Higig port or a Higig trunk */ \ 1037 SHR_G_ENTRY(ecn_dscp_map_mode), /* support RFC3168 ECN mapping mode */ \ 1038 SHR_G_ENTRY(td3_reduced_pm), /* TD3 2T with reduced port count */ \ 1039 SHR_G_ENTRY(no_lls), /* No support for lls */ \ 1040 SHR_G_ENTRY(port_encap_speed_max_config), /* Adjust max speed when port encap changed */ \ 1041 SHR_G_ENTRY(vlan_xlate_iif_with_dummy_vp), /* reserve a dummy vp for vlan_xlate */ \ 1042 SHR_G_ENTRY(iproc_14_tx_arbiter_priority), /* Workaround for iProc-14 TX Arbiter Priority */ \ 1043 SHR_G_ENTRY(ifp_no_narrow_mode_support), /* IFP narrow mode not supported */ \ 1044 SHR_G_ENTRY(hx5_style_ifp_no_narrow_mode_support), /* HX5 style IFP narrow mode not supported */ \ 1045 SHR_G_ENTRY(no_fp_data_qual_api_support), /* Feature to deprecate data qualifiers for newer devices */ \ 1046 SHR_G_ENTRY(udf_selector_support), /* UDF1/2 selection based scheme for FP UDF */ \ 1047 SHR_G_ENTRY(th3_style_simple_mpls), /* Tomahawk3 Mpls Support */ \ 1048 SHR_G_ENTRY(roe), /* Feature for ROE Frame encap/decap support */ \ 1049 SHR_G_ENTRY(roe_custom), /* Feature for custom ROE Frame encap/decap support */ \ 1050 SHR_G_ENTRY(td2_style_l3_defip_cnt), /* Entries occupied in L3_DEFIPm excluding L3_DEFIP_128m */ \ 1051 SHR_G_ENTRY(uc_flowtracker_learn), /* Flow tracker APP will learn the flows */ \ 1052 SHR_G_ENTRY(uc_flowtracker_export), /* Flow tracker APP will export the flow data */ \ 1053 SHR_G_ENTRY(vfi_combo_profile), /* VFI_PROFILE and VFI_PROFILE_2 profiling together */ \ 1054 SHR_G_ENTRY(xlmac_speed_display_above_10g), /* Reflect >10G speed from XLMAC */ \ 1055 SHR_G_ENTRY(field_flowtracker_support), /* Flowtracker stage support in field processor */ \ 1056 SHR_G_ENTRY(ifg_wb_include_unimac), /* Port ifg warmboot support include UNIMAC */ \ 1057 SHR_G_ENTRY(xlmac_timestamp_disable), /* Timestamp can be disabled on XLMAC */ \ 1058 SHR_G_ENTRY(timesync_block_iproc), /* Timesync block is in iProc */ \ 1059 SHR_G_ENTRY(configurable_storm_control_meter_mapping), /* Feature to enable configuration of STORM_CONTROL_METER_MAPPINGr */ \ 1060 SHR_G_ENTRY(decouple_protocol_vlan), /* decouple protocol vlan in bcm_port_untagged_vlan_set */ \ 1061 SHR_G_ENTRY(l3_mtu_size_default), /* From HX5 devices software has to handle the setting of default MTU_SIZE in L3_MTU_VALUES table. */ \ 1062 SHR_G_ENTRY(skip_port_initial_copy_count), /* For HX5 updating the port_initial_copy_count is not needed */ \ 1063 SHR_G_ENTRY(flex_flowtracker_ver_1), /* Flexible Flowtracker version 1 support */ \ 1064 SHR_G_ENTRY(serdes_firmware_pos_by_host_endian), /* Determine serdes firmware pos by host endian */ \ 1065 SHR_G_ENTRY(pvlan_on_vfi), /* pvlan supported on VFI domain */ \ 1066 SHR_G_ENTRY(dport_update_hl), /* dport update on HL(HigigLite) PBMP */ \ 1067 SHR_G_ENTRY(post_ifp_single_stage_ecmp), /* ECMP Supported only in the POST IFP stage*/ \ 1068 SHR_G_ENTRY(l3_ecmp_weighted), /* Weighted ECMP */ \ 1069 SHR_G_ENTRY(vxlan_lite_riot), /* VXLAN-Lite Routing Into and Out of Tunnels support */ \ 1070 SHR_G_ENTRY(wh2), /* Wolfhound2 device */ \ 1071 SHR_G_ENTRY(phy_interface_wb), /* support phy interface wb in bcm port layer */ \ 1072 SHR_G_ENTRY(uc_image_name_with_no_chip_rev), /* ukernel firmware image name do not have chip revision */ \ 1073 SHR_G_ENTRY(port_enable_encap_restore), /* restore the port enable/disable during encap change */ \ 1074 SHR_G_ENTRY(distributed_hit_bits), /* hit bits are distributed */ \ 1075 SHR_G_ENTRY(flex_stat_compression_share), /* share compressed hw tables among flex counter mode ids */ \ 1076 SHR_G_ENTRY(flex_stat_compaction_support), /* To support flexible allocation of pools to accouting objects and compaction */ \ 1077 SHR_G_ENTRY(flex_stat_attributes_class), /* To enable grouping of different attributes together as a class. */ \ 1078 SHR_G_ENTRY(flex_stat_ing_tcp_flags_support), /* To enable counting ingress packets based on their TCP flags mapping. */ \ 1079 SHR_G_ENTRY(flex_stat_int_cn_support), /* To enable counting packets based on the mapped internal congestion value. */ \ 1080 SHR_G_ENTRY(fp_class_map_no_support), /* Feature to not support field class map APIs. */ \ 1081 SHR_G_ENTRY(disable_rx_on_port), /* Disable RX on a port. */ \ 1082 SHR_G_ENTRY(vxlan_decoupled_mode), /* To support vxlan decoupled mode */ \ 1083 SHR_G_ENTRY(global_meter_compression_share), /* share compressed hw tables among policer group mode ids */ \ 1084 SHR_G_ENTRY(global_meter_compaction_support), /* To support flexible allocation of pools to policer groups and compaction */ \ 1085 SHR_G_ENTRY(qmode_mib_counters), /* MIB counters when port block in Q mode */ \ 1086 SHR_G_ENTRY(broadscan_dos_ctrl), /* Dos controls for broadscan feature */ \ 1087 SHR_G_ENTRY(bscan_ft_fifodma_support), /* HX5: flowtracker feature support using HW broadscan engine. */ \ 1088 SHR_G_ENTRY(helix5_ecn), /* In helix5 mpls ecn is not supported,hence seperate soc feature is required to initialize ecn to support ip flows */ \ 1089 SHR_G_ENTRY(vlan_wirelss_traffic_select), /* In helix5 we can treat the traffic as wired or wireless, added soc feature to support this */ \ 1090 SHR_G_ENTRY(l3_ecmp_hier_tbl), /* Separate tbl for Overlay ECMP Groups*/ \ 1091 SHR_G_ENTRY(th3_style_fp), /* TH3 Field Programming changes */ \ 1092 SHR_G_ENTRY(inband_network_telemetry), /* Inband network Telemetry */ \ 1093 SHR_G_ENTRY(latency_monitor), /* Latency Monitor Histogram */ \ 1094 SHR_G_ENTRY(th3_style_dlb), /* TH3 style dlb */ \ 1095 SHR_G_ENTRY(general_cascade), /* To support general purpose subport on a physical port */ \ 1096 SHR_G_ENTRY(obm_tpid_sync), /* Sync legacy TPID configuration to BOM module*/ \ 1097 SHR_G_ENTRY(eeprom_iproc), /* To support iproc eeprom read write */ \ 1098 SHR_G_ENTRY(hw_etrap), /* ETRAP implemented in H/w */ \ 1099 SHR_G_ENTRY(vxlan_evpn), /* To support VXLAN EVPN */ \ 1100 SHR_G_ENTRY(mv2_style_flowtracker), /* maverick2 style flow tracker */ \ 1101 SHR_G_ENTRY(mv2_dummy_flowtracker), /* dummy flow tracker feature, to be removed */ \ 1102 SHR_G_ENTRY(bscan_fae_port_flow_exclude), /* Do not flowtracker ipfix packets coming from FAE port to prevent loop. */ \ 1103 SHR_G_ENTRY(hx5_ft_32bit_param_update), /* 32 bit params cannot be stored in PDD, so it needs to be updated to split in 2 16bits. */\ 1104 SHR_G_ENTRY(mmu_repl_alloc_unfrag), /* Optimize MMU replication table allocation to avoid fragmentation.*/ \ 1105 SHR_G_ENTRY(flex_stat_egr_queue_congestion_marked), /* Support queue and congestion status as packet attribute */ \ 1106 SHR_G_ENTRY(hr3_egphy28_phyrev_override), /* To override EGPHY_28 phy_rev for Hurricane3 */ \ 1107 SHR_G_ENTRY(xflow_macsec_poll_intr), /* Implementation of workaround CRMACSEC-383 */ \ 1108 SHR_G_ENTRY(xflow_macsec_olp), /* Implementation of VLAN reserve for OLP based MACSEC */ \ 1109 SHR_G_ENTRY(collector), /* Common collector module for instrumentation applications */ \ 1110 SHR_G_ENTRY(telemetry), /* Common Telemetry module for instrumentation applications */ \ 1111 SHR_G_ENTRY(failover_fixed_nh_offset), /* TH3 failover with fixed next hop offset */ \ 1112 SHR_G_ENTRY(skip_null_table_lkup), /* Skip logical to physical index map lookup if table depth is 0 */ \ 1113 SHR_G_ENTRY(ser_scrub_delay), /* Monterey delay scrubing if there is pending ser error */ \ 1114 SHR_G_ENTRY(erspan3_support), /* Implementation of ERSPANv3 support */ \ 1115 SHR_G_ENTRY(dlb_flow_monitoring), /* DLB flow monitoring */ \ 1116 SHR_G_ENTRY(uc_int_turnaround), /* INT Turnaround Eapp */ \ 1117 SHR_G_ENTRY(mont_roe_classid_sw_war), /* RoE sw war for classid and roe type */ \ 1118 SHR_G_ENTRY(sw_mmu_flush_rqe_operation), /* SW WAR for MMU RQE Flush operation */ \ 1119 SHR_G_ENTRY(ignore_controlled_counter_priority), /* ignore the controlled counter counter level flag for priority*/ \ 1120 SHR_G_ENTRY(flowtracker_ver_1_8K_ft_table), /* Session table length is 8k */\ 1121 SHR_G_ENTRY(flowtracker_ver_1_16K_ft_table), /* Session table length is 16k */\ 1122 SHR_G_ENTRY(flowtracker_ver_1_32K_ft_table), /* Session table length is 32k */\ 1123 SHR_G_ENTRY(flowtracker_ver_1_collector_copy), /* No support for collector copies. */\ 1124 SHR_G_ENTRY(flowtracker_ver_1_ipfix_remote_collector), /* flowtracker ipfix packer build logic support. */ \ 1125 SHR_G_ENTRY(flowtracker_ver_1_bidirectional), /* TCP bidirectional support */ \ 1126 SHR_G_ENTRY(flowtracker_ver_1_dos_attack_check), /* Dos Attack vector support */ \ 1127 SHR_G_ENTRY(flowtracker_ver_1_metering), /* flowtracker metering support. */ \ 1128 SHR_G_ENTRY(flowtracker_ver_1_alu32_0_1_banks), /* Flowtracker alu32 limited to 2 banks. */ \ 1129 SHR_G_ENTRY(alpm_hit_bits_not_support), /* Trident2 ALPM hit bits is not updated correctly */ \ 1130 SHR_G_ENTRY(fp_ltid_match_all_parts), /* IFP Logical table match on all slice parts to avoid false hit */ \ 1131 SHR_G_ENTRY(use_smbus2_for_i2c), /* Helix5 uses SMBUS2 for I2C access (TD3 uses smbus1) */ \ 1132 SHR_G_ENTRY(ecmp_rh_1k_unique_members), /* maximum 1K unique members for RH-ECMP. */ \ 1133 SHR_G_ENTRY(rsvd4_support), /* Control rsvd4. */ \ 1134 SHR_G_ENTRY(xflow_macsec_crypto_aes_256), /* MACSEC crypto AES-256 support */ \ 1135 SHR_G_ENTRY(sum), /* SUM Eapp for XGS */ \ 1136 SHR_G_ENTRY(l3_egress_idx_scale_200K), /* l3 egress idx scale is 200k. */ \ 1137 SHR_G_ENTRY(preserve_otag_before_itag), /* Preserved OTAG order wrt. ITAG */ \ 1138 SHR_G_ENTRY(chip_config_read_war), /* Set if WAR is needed when reading CHIP_CONFIGr (HX5) */ \ 1139 SHR_G_ENTRY(mirror_rspan_no_mtp0), /* Don't use MTP0 for RSPAN encap */ \ 1140 SHR_G_ENTRY(l3_ecmp_protected_access), /* Preserved OTAG order wrt. ITAG */ \ 1141 SHR_G_ENTRY(l3_ingress_intf_kt2_recover), /* Sync/Recover L3 IIF entries bitmap in KT2 */ \ 1142 SHR_G_ENTRY(linkscan_remove_port_info), /* Not calling bcm_port_info_get in linkscan to improve performance */ \ 1143 SHR_G_ENTRY(no_ep_to_cpu), /* CMICx without EP_TO_CPU header */ \ 1144 SHR_G_ENTRY(mem_direct_acc_last_used_first), /* saving the last memory used in order to optimize addr to mem time*/ \ 1145 SHR_G_ENTRY(hx5_oam_support), /* Helix5 based OAM implementation */ \ 1146 SHR_G_ENTRY(prop_suffix_group_with_revision), /* reading soc properties with group + revision (i.e. BCM8869X_B0) */ \ 1147 SHR_G_ENTRY(timesync_time_capture), /* Time Capture from TimeSync block. */ \ 1148 SHR_G_ENTRY(hash_fcoe_field), /* Rtag7 Hashing Field Selection Bitmap for FCoE packets. */ \ 1149 SHR_G_ENTRY(hash_flex_bin), /* TD3 RTAG7 hash flex bin selection */ \ 1150 SHR_G_ENTRY(twamp_owamp_support), /* TWAMP/OWAMP feature support. */ \ 1151 SHR_G_ENTRY(large_scale_nat), /* Large Scale Egress NAT. */ \ 1152 SHR_G_ENTRY(vfi_switched_l2_change_fields), /* L2 change fields for VFI switched packets. */ \ 1153 SHR_G_ENTRY(wh2_miim_delay), /* WH2 need miim delay for cable diag */ \ 1154 SHR_G_ENTRY(l3defip_rp_l3iif_resolve), /* Route IPMC RP or L3IIF will be resolved by end user. */ \ 1155 SHR_G_ENTRY(enable_flow_based_udf_extraction), /* Enable flow based UDF container extraction */ \ 1156 SHR_G_ENTRY(count) /* ALWAYS LAST PLEASE (DO NOT CHANGE) */ 1157 1158 /* Make the enums */ 1159 #undef SHR_G_MAKE_STR 1160 #undef SHR_G_MAKE_STR1 1161 #undef SHR_G_MAKE_STR_CONCAT 1162 #define SHR_G_MAKE_STR1(a) a 1163 #define SHR_G_MAKE_STR_CONCAT(e,a) SHR_G_MAKE_STR1(e##a) 1164 #define SHR_G_MAKE_STR(a) SHR_G_MAKE_STR_CONCAT(soc_feature_,a) 1165 SHR_G_MAKE_ENUM(soc_feature_); 1166 1167 /* Make the string array */ 1168 #undef SHR_G_MAKE_STR 1169 #define SHR_G_MAKE_STR(a) #a 1170 #define SOC_FEATURE_NAME_INITIALIZER \ 1171 SHR_G_NAME_BEGIN(dont_care) \ 1172 SHR_G_ENTRIES(dont_care) \ 1173 SHR_G_NAME_END(dont_care) 1174 1175 /* Feature-defining functions */ 1176 extern int soc_features_bcm5670_a0(int unit, soc_feature_t feature); 1177 extern int soc_features_bcm5673_a0(int unit, soc_feature_t feature); 1178 extern int soc_features_bcm5690_a0(int unit, soc_feature_t feature); 1179 extern int soc_features_bcm5665_a0(int unit, soc_feature_t feature); 1180 extern int soc_features_bcm5695_a0(int unit, soc_feature_t feature); 1181 extern int soc_features_bcm5675_a0(int unit, soc_feature_t feature); 1182 extern int soc_features_bcm5674_a0(int unit, soc_feature_t feature); 1183 extern int soc_features_bcm5665_b0(int unit, soc_feature_t feature); 1184 extern int soc_features_bcm56601_a0(int unit, soc_feature_t feature); 1185 extern int soc_features_bcm56601_b0(int unit, soc_feature_t feature); 1186 extern int soc_features_bcm56601_c0(int unit, soc_feature_t feature); 1187 extern int soc_features_bcm56602_a0(int unit, soc_feature_t feature); 1188 extern int soc_features_bcm56602_b0(int unit, soc_feature_t feature); 1189 extern int soc_features_bcm56602_c0(int unit, soc_feature_t feature); 1190 extern int soc_features_bcm56504_a0(int unit, soc_feature_t feature); 1191 extern int soc_features_bcm56504_b0(int unit, soc_feature_t feature); 1192 extern int soc_features_bcm56102_a0(int unit, soc_feature_t feature); 1193 extern int soc_features_bcm56304_b0(int unit, soc_feature_t feature); 1194 extern int soc_features_bcm56112_a0(int unit, soc_feature_t feature); 1195 extern int soc_features_bcm56314_a0(int unit, soc_feature_t feature); 1196 extern int soc_features_bcm5650_c0(int unit, soc_feature_t feature); 1197 extern int soc_features_bcm56800_a0(int unit, soc_feature_t feature); 1198 extern int soc_features_bcm56218_a0(int unit, soc_feature_t feature); 1199 extern int soc_features_bcm56514_a0(int unit, soc_feature_t feature); 1200 extern int soc_features_bcm56624_a0(int unit, soc_feature_t feature); 1201 extern int soc_features_bcm56624_b0(int unit, soc_feature_t feature); 1202 extern int soc_features_bcm56680_a0(int unit, soc_feature_t feature); 1203 extern int soc_features_bcm56680_b0(int unit, soc_feature_t feature); 1204 extern int soc_features_bcm56634_a0(int unit, soc_feature_t feature); 1205 extern int soc_features_bcm56634_b0(int unit, soc_feature_t feature); 1206 extern int soc_features_bcm56524_a0(int unit, soc_feature_t feature); 1207 extern int soc_features_bcm56524_b0(int unit, soc_feature_t feature); 1208 extern int soc_features_bcm56685_a0(int unit, soc_feature_t feature); 1209 extern int soc_features_bcm56685_b0(int unit, soc_feature_t feature); 1210 extern int soc_features_bcm56334_a0(int unit, soc_feature_t feature); 1211 extern int soc_features_bcm56334_b0(int unit, soc_feature_t feature); 1212 extern int soc_features_bcm56840_a0(int unit, soc_feature_t feature); 1213 extern int soc_features_bcm56840_b0(int unit, soc_feature_t feature); 1214 extern int soc_features_bcm56640_a0(int unit, soc_feature_t feature); 1215 extern int soc_features_bcm56640_b0(int unit, soc_feature_t feature); 1216 extern int soc_features_bcm56340_a0(int unit, soc_feature_t feature); 1217 extern int soc_features_bcm56540_a0(int unit, soc_feature_t feature); 1218 extern int soc_features_bcm56850_a0(int unit, soc_feature_t feature); 1219 extern int soc_features_bcm56960_a0(int unit, soc_feature_t feature); 1220 extern int soc_features_bcm56965_a0(int unit, soc_feature_t feature); 1221 extern int soc_features_bcm56965_a1(int unit, soc_feature_t feature); 1222 extern int soc_features_bcm56970_a0(int unit, soc_feature_t feature); 1223 extern int soc_features_bcm56224_a0(int unit, soc_feature_t feature); 1224 extern int soc_features_bcm56224_b0(int unit, soc_feature_t feature); 1225 extern int soc_features_bcm56820_a0(int unit, soc_feature_t feature); 1226 extern int soc_features_bcm56725_a0(int unit, soc_feature_t feature); 1227 extern int soc_features_bcm53314_a0(int unit, soc_feature_t feature); 1228 extern int soc_features_bcm53324_a0(int unit, soc_feature_t feature); 1229 extern int soc_features_bcm56142_a0(int unit, soc_feature_t feature); 1230 extern int soc_features_bcm56150_a0(int unit, soc_feature_t feature); 1231 extern int soc_features_bcm88650_a0(int unit, soc_feature_t feature); 1232 extern int soc_features_bcm2801pm_a0(int unit, soc_feature_t feature); 1233 extern int soc_features_bcm88650_b0(int unit, soc_feature_t feature); 1234 extern int soc_features_bcm88660_a0(int unit, soc_feature_t feature); 1235 extern int soc_features_bcm88675_a0(int unit, soc_feature_t feature); 1236 extern int soc_features_bcm88675_b0(int unit, soc_feature_t feature); 1237 extern int soc_features_bcm88375_a0(int unit, soc_feature_t feature); 1238 extern int soc_features_bcm88375_b0(int unit, soc_feature_t feature); 1239 extern int soc_features_bcm88470_a0(int unit, soc_feature_t feature); 1240 extern int soc_features_bcm88470_b0(int unit, soc_feature_t feature); 1241 extern int soc_features_bcm88270_a0(int unit, soc_feature_t feature); 1242 extern int soc_features_bcm8206_a0(int unit, soc_feature_t feature); 1243 extern int soc_features_bcm88680_a0(int unit, soc_feature_t feature); 1244 extern int soc_features_bcm88690_a0(int unit, soc_feature_t feature); 1245 extern int soc_features_bcm88690_b0(int unit, soc_feature_t feature); 1246 extern int soc_features_bcm88800_a0(int unit, soc_feature_t feature); 1247 extern int soc_features_bcm88202_a0(int unit, soc_feature_t feature); 1248 extern int soc_features_bcm88732_a0(int unit, soc_feature_t feature); 1249 extern int soc_features_bcm56440_a0(int unit, soc_feature_t feature); 1250 extern int soc_features_bcm56440_b0(int unit, soc_feature_t feature); 1251 extern int soc_features_bcm56450_a0(int unit, soc_feature_t feature); 1252 extern int soc_features_bcm56450_b0(int unit, soc_feature_t feature); 1253 extern int soc_features_bcm56450_b1(int unit, soc_feature_t feature); 1254 extern int soc_features_bcm56860_a0(int unit, soc_feature_t feature); 1255 extern int soc_features_bcm56560_a0(int unit, soc_feature_t feature); 1256 extern int soc_features_bcm56870_a0(int unit, soc_feature_t feature); 1257 extern int soc_features_bcm56370_a0(int unit, soc_feature_t feature); 1258 extern int soc_features_bcm56770_a0(int unit, soc_feature_t feature); 1259 extern int soc_features_bcm56980_a0(int unit, soc_feature_t feature); 1260 extern int soc_features_bcm56980_b0(int unit, soc_feature_t feature); 1261 extern int soc_features_bcm56560_b0(int unit, soc_feature_t feature); 1262 extern int soc_features_bcm56670_a0(int unit, soc_feature_t feature); 1263 extern int soc_features_bcm56670_b0(int unit, soc_feature_t feature); 1264 extern int soc_features_bcm88750_a0(int unit, soc_feature_t feature); 1265 extern int soc_features_bcm88750_b0(int unit, soc_feature_t feature); 1266 extern int soc_features_bcm88754_a0(int unit, soc_feature_t feature); 1267 extern int soc_features_bcm56260_a0(int unit, soc_feature_t feature); 1268 extern int soc_features_bcm56260_b0(int unit, soc_feature_t feature); 1269 extern int soc_features_bcm56270_a0(int unit, soc_feature_t feature); 1270 extern int soc_features_bcm53460_a0(int unit, soc_feature_t feature); 1271 extern int soc_features_bcm88752_a0(int unit, soc_feature_t feature); 1272 extern int soc_features_bcm88752_b0(int unit, soc_feature_t feature); 1273 extern int soc_features_bcm88950_a0(int unit, soc_feature_t feature); 1274 extern int soc_features_bcm88790_a0(int unit, soc_feature_t feature); 1275 extern int soc_features_bcm88790_b0(int unit, soc_feature_t feature); 1276 extern int soc_features_bcm83207_a0(int unit, soc_feature_t feature); 1277 extern int soc_features_bcm83208_a0(int unit, soc_feature_t feature); 1278 1279 extern int soc_features_bcm53400_a0(int unit, soc_feature_t feature); 1280 extern int soc_features_bcm56160_a0(int unit, soc_feature_t feature); 1281 extern int soc_features_bcm53570_a0(int unit, soc_feature_t feature); 1282 extern int soc_features_bcm53570_b0(int unit, soc_feature_t feature); 1283 extern int soc_features_bcm53540_a0(int unit, soc_feature_t feature); 1284 1285 extern void soc_feature_init(int unit); 1286 extern int soc_flex_counter_feature_init(int unit); 1287 extern char *soc_feature_name[]; 1288 1289 #define soc_feature(unit, feature) ((SOC_CONTROL(unit) != NULL) ? SOC_FEATURE_GET(unit, feature) : 0) 1290 1291 #endif /* !_SOC_FEATURE_H */