portctrl.h (10805B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: portctrl.h 8 * Purpose: SDK SOC Port Control Glue Layer 9 */ 10 11 #ifndef _SOC_ESW_PORTCTRL_H_ 12 #define _SOC_ESW_PORTCTRL_H_ 13 14 #include <soc/feature.h> 15 #include <soc/property.h> 16 #include <soc/phyctrl.h> 17 #include <soc/error.h> 18 #include <soc/drv.h> 19 #include <soc/esw/port.h> 20 21 #ifdef PORTMOD_SUPPORT 22 #include <soc/portmod/portmod_common.h> 23 #include <soc/portmod/portmod.h> 24 #endif 25 26 #define SOC_USE_PORTCTRL(_unit) \ 27 (soc_feature(_unit, soc_feature_portmod)) 28 29 #ifdef PORTMOD_SUPPORT 30 #define SOC_PORTCTRL_NOT_INITIALIZED (0) 31 #define SOC_PORTCTRL_INITIALIZED (1) 32 33 /* PORT MACRO PM */ 34 #define SOC_PM12X10_PM4X10_COUNT (3) 35 #define SOC_PM4X10_NUM_LANES (4) 36 #define SOC_PM4X10_LANE_MASK (0xF) 37 #define SOC_PM12X10_NUM_LANES (10) 38 #define SOC_PM12X10_LANE_MASK (0x3FF) 39 #define SOC_PM4X25_NUM_LANES (4) 40 #define SOC_PM4X25_LANE_MASK (0xF) 41 #define SOC_PM_QTC_NUM_LANES (16) 42 #define SOC_PM_QTC_LANE_MASK (0xFFFF) 43 #define SOC_PM_GPHY_NUM_LANES (8) 44 #define SOC_PM_GPHY_LANE_MASK (0xFF) 45 #define SOC_PM8X50_NUM_LANES (8) 46 #define SOC_PM8X50_LANE_MASK (0xFF) 47 #define SOC_PM4X10_QTC_NUM_LANES (4) 48 #endif 49 50 #define SOC_PM_PHY_NAME_MAX_LEN 32 51 52 #define SOC_PORTCTRL_HG2_TO_IEEE_BW_GET(_speed_) \ 53 (_speed_ == 11000 ? 10000 : \ 54 (_speed_ == 21000 ? 20000 : \ 55 (_speed_ == 27000 ? 25000 : \ 56 (_speed_ == 42000 ? 40000 : \ 57 (_speed_ == 53000 ? 50000 : \ 58 (_speed_ == 106000 ? 100000 : \ 59 (_speed_ == 127000 ? 120000 : (_speed_)))))))) 60 61 #define SOC_PORTCTRL_IS_HG2_SPEED(_speed_) \ 62 (_speed_ == 11000 ? 1 : \ 63 (_speed_ == 21000 ? 1 : \ 64 (_speed_ == 27000 ? 1 : \ 65 (_speed_ == 42000 ? 1 : \ 66 (_speed_ == 53000 ? 1 : \ 67 (_speed_ == 106000 ? 1 : \ 68 (_speed_ == 127000 ? 1 : 0))))))) 69 70 /* device-specific function vectors */ 71 extern soc_portctrl_functions_t soc_td3_portctrl_func; 72 extern soc_portctrl_functions_t soc_hx5_portctrl_func; 73 extern soc_portctrl_functions_t soc_mv2_portctrl_func; 74 extern soc_portctrl_functions_t soc_td2p_portctrl_func; 75 extern soc_portctrl_functions_t soc_th_portctrl_func; 76 extern soc_portctrl_functions_t soc_gh_portctrl_func; 77 78 /* 79 * Define: 80 * PORTMOD_SUCCESS 81 * PORTMOD_FAILURE 82 * PORTMOD_IF_ERROR_RETURN 83 * Purpose: 84 * Checks PortMod and PhyMod library error return code. 85 * PORTMOD_IF_ERROR_RETURN() causes routine to return on error. 86 * Note: 87 * Currently, the PortMod functions return error codes are the same as 88 * the SHARED error codes, which are used by the BCM and SOC layers. 89 * Phymod functions error codes are also the same as the 90 * SHARED error codes. 91 */ 92 #define PORTMOD_SUCCESS(_rv) _SHR_E_SUCCESS(_rv) 93 #define PORTMOD_FAILURE(_rv) _SHR_E_FAILURE(_rv) 94 #define PORTMOD_IF_ERROR_RETURN(_op) _SHR_E_IF_ERROR_RETURN(_op) 95 96 #define SOC_PORT_RESOURCE_CONFIGURE_FLEX (0) 97 #define SOC_PORT_RESOURCE_CONFIGURE_SPEED_ONLY (1) 98 #define SOC_PORT_RESOURCE_CONFIGURE_LANES_ONLY (2) 99 100 /* This structrure is used to pass information to Portmod API during Flexport 101 * reconfiguration of PGW. NOte it is used for TD2+ only 102 */ 103 typedef struct soc_esw_portctrl_pgw_s { 104 int mode; 105 int lanes; 106 int port_index; 107 int flags; 108 } soc_esw_portctrl_pgw_t; 109 110 /* Port type used in PortMod functions */ 111 typedef int portctrl_pport_t; 112 113 extern int 114 soc_esw_portctrl_init(int unit); 115 extern int 116 soc_esw_portctrl_deinit(int unit); 117 118 extern int 119 soc_portctrl_software_deinit(int unit); 120 121 extern int 122 soc_esw_portctrl_add(int unit, soc_port_t port, int init_flag, 123 void *add_info); 124 125 extern int 126 soc_esw_portctrl_delete(int unit, soc_port_t port); 127 128 extern int 129 soc_esw_portctrl_pgw_reconfigure(int unit, soc_port_t port, 130 int phy_port, soc_esw_portctrl_pgw_t *data); 131 132 extern int 133 soc_esw_portctrl_duplex_get(int unit, soc_port_t port, int *duplex); 134 135 extern int 136 soc_esw_portctrl_duplex_set(int unit, soc_port_t port, int duplex); 137 138 extern int 139 soc_esw_portctrl_port_fc_config_init(int unit, soc_port_t port); 140 141 extern int 142 soc_esw_portctrl_frame_max_set(int unit, soc_port_t port, int size); 143 144 extern int 145 soc_esw_portctrl_frame_max_get(int unit, soc_port_t port, int *size); 146 147 extern int 148 soc_esw_portctrl_pause_set(int unit, soc_port_t port, int pause_tx, int pause_rx); 149 150 extern int 151 soc_esw_portctrl_pause_get(int unit, soc_port_t port, int *pause_tx, int *pause_rx); 152 153 extern int 154 soc_esw_portctrl_ifg_set(int unit, soc_port_t port, int speed, 155 soc_port_duplex_t duplex, int ifg); 156 157 extern int 158 soc_esw_portctrl_ifg_get(int unit, soc_port_t port, int speed, 159 soc_port_duplex_t duplex, int *ifg); 160 161 extern int 162 soc_portctrl_led_chain_config(int unit, int port, int value); 163 164 extern int 165 soc_portctrl_phy_name_get(int unit, int port, char *phy_name); 166 167 extern int 168 soc_portctrl_port_mode_set(int unit, int port, int mode); 169 extern int 170 soc_portctrl_port_mode_get(int unit, int port, int *mode, int *lanes); 171 172 extern int 173 soc_portctrl_phy_control_set(int unit, soc_port_t port, int phyn, 174 int phy_lane, int sys_side, 175 soc_phy_control_t phy_ctrl, uint32 value); 176 extern int 177 soc_portctrl_phy_control_get(int unit, soc_port_t port, int phyn, 178 int phy_lane, int sys_side, 179 soc_phy_control_t phy_ctrl, uint32 *value); 180 extern int 181 soc_portctrl_phy_timesync_config_set(int unit, soc_port_t port, 182 soc_port_phy_timesync_config_t *conf); 183 extern int 184 soc_portctrl_phy_timesync_config_get(int unit, soc_port_t port, 185 soc_port_phy_timesync_config_t *conf); 186 extern int 187 soc_portctrl_control_phy_timesync_set(int unit, soc_port_t port, 188 soc_port_control_phy_timesync_t type, 189 uint64 value); 190 extern int 191 soc_portctrl_control_phy_timesync_get(int unit, soc_port_t port, 192 soc_port_control_phy_timesync_t type, 193 uint64 *value); 194 195 extern int 196 soc_esw_portctrl_encap_get(int unit, soc_port_t port, int *mode); 197 198 extern int 199 soc_esw_portctrl_port_to_phyaddr(int unit, soc_port_t port, uint8* phy_addr); 200 201 extern int 202 soc_portctrl_pm_type_get(int unit, soc_port_t phy_port, int* pm_type); 203 204 extern int 205 soc_esw_portctrl_functions_register(int unit, soc_driver_t *drv); 206 207 extern int 208 soc_esw_portctrl_speed_get(int unit, soc_port_t port, int *speed); 209 210 int 211 soc_esw_portctrl_is_same_speed_class(int unit, int pre_speed, int post_speed); 212 213 extern soc_error_t 214 soc_esw_portctrl_port_ability_update(int unit, soc_port_t port, soc_port_ability_t *ability); 215 216 #ifdef PORTMOD_SUPPORT 217 extern int 218 soc_esw_portctrl_init_check(int unit); 219 220 /* utility functions called from device specific portmod code */ 221 extern int 222 soc_esw_portctrl_pm_user_access_alloc(int unit, int num, 223 portmod_default_user_access_t **user_acc); 224 extern void 225 soc_esw_portctrl_dump_txrx_lane_map(int unit, int first_port, int logical_port, 226 int core_num, uint32 txlane_map_b, uint32 rxlane_map_b, 227 uint32 txlane_map, uint32 rxlane_map); 228 229 extern int soc_esw_portctrl_xphy_wb_db_restore(int unit); 230 extern int soc_esw_portctrl_setup_ext_phy_add(int unit, int port, portmod_pbmp_t *phy_ports); 231 extern int soc_esw_portctrl_reset_tsc0_cb(int unit, int port, uint32 in_reset); 232 extern int soc_esw_portctrl_reset_tsc1_cb(int unit, int port, uint32 in_reset); 233 extern int soc_esw_portctrl_reset_tsc2_cb(int unit, int port, uint32 in_reset); 234 extern int soc_esw_portctrl_reset_tsc3_cb(int unit, int port, uint32 in_reset); 235 extern int soc_esw_portctrl_reset_qtsce_cb(int unit, int port, uint32 in_reset); 236 extern int soc_esw_portctrl_reset_gphy_cb(int unit, int port, uint32 in_reset); 237 238 extern int 239 soc_esw_portctrl_config_get(int unit, soc_port_t port, 240 portmod_port_interface_config_t* interface_config, 241 portmod_port_init_config_t* init_config, 242 phymod_operation_mode_t *phy_op_mode); 243 244 extern int 245 soc_esw_portctrl_pm_update_vco_soc_info(int unit, const int *phy_ports, 246 int num_ports, 247 int pm_id, 248 portmod_dispatch_type_t pm_type, 249 uint32 flags); 250 extern int 251 soc_esw_portctrl_update_vco_soc_info(int unit); 252 253 extern int 254 soc_esw_portctrl_pm_vco_store(int unit, int index, const void *pm_vco_info); 255 256 257 extern int 258 soc_esw_portctrl_speed_config_fill(int unit, soc_port_t port, 259 int speed, 260 int num_lane, 261 int fec, 262 int link_training, 263 int lane_config, 264 void *speed_config); 265 266 extern int 267 soc_esw_portmod_port_vcos_get(int unit, soc_port_t phy_port , 268 portmod_dispatch_type_t pm_type, int* lanes, 269 int* speed , int* encap ,int size); 270 #endif /* PORTMOD_SUPPORT */ 271 extern int 272 soc_esw_portctrl_flex_vco_validation(int unit, 273 soc_port_schedule_state_t *port_schedule_state); 274 275 extern int 276 soc_esw_portctrl_pm_vco_fetch(int unit, int index, void *pm_vco_info); 277 278 extern int 279 soc_esw_portctrl_pm_vco_store_clear(int unit); 280 281 extern int 282 soc_esw_portctrl_pm_vco_reconfigure(int unit); 283 284 extern int 285 soc_esw_portctrl_pll_div_get(int unit, soc_port_t logic_port, soc_port_t phy_port, 286 int speed, int num_lane, int encap_mode, 287 uint32 *pll_div); 288 289 extern int 290 soc_esw_portctrl_pm_ports_delete(int unit, 291 int nport, 292 soc_port_resource_t *resource); 293 294 extern int 295 soc_esw_portctrl_pm_ports_add(int unit, 296 int nport, 297 soc_port_resource_t *resource); 298 extern int 299 soc_esw_portctrl_phy_tx_set(int unit, soc_port_t port, 300 int phyn, int phy_lane, 301 int sys_side, soc_port_phy_tx_t *tx); 302 303 extern int 304 soc_esw_portctrl_phy_tx_get(int unit, soc_port_t port, 305 int phyn, int phy_lane, 306 int sys_side, soc_port_phy_tx_t *tx); 307 308 309 #endif /* _SOC_ESW_PORTCTRL_H_ */ 310