port.h (12129B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: port.h 8 * Purpose: SOC Port definitions. 9 */ 10 11 #ifndef _SOC_ESW_PORT_H_ 12 #define _SOC_ESW_PORT_H_ 13 #include <soc/drv.h> 14 #include <soc/tdm/core/tdm_top.h> 15 16 /* 17 * Internal flags 18 * 19 * SOC_PORT_RESOURCE_I_MAP Indicates legacy FlexPort API is used. 20 * In this case, when flexing to a fewer 21 * number of ports (4x10 -> 1x40), the 'old' 22 * ports become inactive rather than 23 * being detached and destroyed (which is 24 * what happens with the new multi_set API). 25 * To be used only by legacy API. 26 * 27 * SOC_PORT_RESOURCE_INACTIVE Indicates if port is inactive or active. 28 * To be used only by legacy API. 29 * 30 * SOC_PORT_RESOURCE_ATTACH The port needs to go through the attach 31 * sequence. 32 * 33 * SOC_PORT_RESOURCE_DETACH The port needs to go through the detach 34 * sequence. 35 * 36 * SOC_PORT_RESOURCE_NEW A new logical port, which previously 37 * didn't exist, is added as a result of 38 * a FlexPort operation. 39 * 40 * SOC_PORT_RESOURCE_DESTROY The logical port is deleted and 41 * no longer exists in the system after 42 * FlexPort. 43 * 44 * SOC_PORT_RESOURCE_REMAP The logical port existed before FlexPort 45 * but is mapped to a different physical port 46 * after FlexPort. 47 * SOC_PORT_RESOURCE_SPEED Only speed is changed. Logical-physical mapping, 48 * lanes, encap remain the same 49 */ 50 #define SOC_PORT_RESOURCE_I_MAP (1 << 31) 51 #define SOC_PORT_RESOURCE_INACTIVE (1 << 30) 52 #define SOC_PORT_RESOURCE_ATTACH (1 << 29) 53 #define SOC_PORT_RESOURCE_DETACH (1 << 28) 54 #define SOC_PORT_RESOURCE_NEW (1 << 27) 55 #define SOC_PORT_RESOURCE_DESTROY (1 << 26) 56 #define SOC_PORT_RESOURCE_REMAP (1 << 25) 57 #define SOC_PORT_RESOURCE_SPEED (1 << 24) 58 59 60 /* Maximum number of lanes that a port can have */ 61 #define SOC_PORT_RESOURCE_LANES_MAX 12 62 63 /* Maximum number of auxiliary ports */ 64 #define SOC_PORT_AUXILIARY_MAX 8 65 66 /* 67 * Lane Information 68 * 69 * Contains information on a given lane for a port. 70 * 71 * A port that uses 'x' number of lanes will have 'x' soc_port_lane_info_t 72 * elements, one for each of the lanes that the port will use. 73 */ 74 typedef struct soc_port_lane_info_s { 75 int pgw; /* PGW instance where lane resides */ 76 int xlp; /* XLP number within PGW */ 77 int tsc; /* TSC number (Same as XLP) */ 78 int port_index; /* Index within XLP */ 79 } soc_port_lane_info_t; 80 81 82 /* FEC types supported. This MUST match the _SHR_PORT_PHY_FEC_* values */ 83 typedef enum _soc_port_phy_fec_e { 84 socPortPhyFecInvalid = _SHR_PORT_PHY_FEC_INVALID, 85 socPortPhyFecNone = _SHR_PORT_PHY_FEC_NONE, 86 socPortPhyFecBaseR = _SHR_PORT_PHY_FEC_BASE_R, 87 socPortPhyFecRsFec = _SHR_PORT_PHY_FEC_RS_FEC, 88 socPortPhyFecRs544 = _SHR_PORT_PHY_FEC_RS_544, 89 socPortPhyFecRs272 = _SHR_PORT_PHY_FEC_RS_272, 90 socPortPhyFecRs206 = _SHR_PORT_PHY_FEC_RS_206, 91 socPortPhyFecRs108 = _SHR_PORT_PHY_FEC_RS_108, 92 socPortPhyFecRs545 = _SHR_PORT_PHY_FEC_RS_545, 93 socPortPhyFecRs304 = _SHR_PORT_PHY_FEC_RS_304, 94 socPortPhyFecRs544_2xN = _SHR_PORT_PHY_FEC_RS_544_2XN, 95 socPortPhyFecRs272_2xN = _SHR_PORT_PHY_FEC_RS_272_2XN, 96 socPortPhyFecCount = _SHR_PORT_PHY_FEC_COUNT 97 } soc_port_phy_fec_t; 98 99 100 /* 101 * Port Resource 102 * 103 * Contains port resource configuration used for FlexPort operations. 104 */ 105 typedef struct soc_port_resource_s { 106 uint32 flags; 107 uint32 op; /* BCMI_XGS5_PORT_RESOURCE_OP_XXX */ 108 int logical_port; /* Logical port associated to physical port */ 109 int physical_port; /* Physical port associated logical port */ 110 int mmu_port; /* MMU port associated to logical port */ 111 int idb_port; /* IDB port associated to logical port */ 112 int pipe; /* Pipe number of the port */ 113 int speed; /* Initial speed after FlexPort operation */ 114 int mode; /* Port mode: single, dual, quad, tri012, ... */ 115 int num_lanes; /* Number of PHY lanes */ 116 soc_port_lane_info_t *lane_info[SOC_PORT_RESOURCE_LANES_MAX]; 117 /* Lane information array */ 118 soc_encap_mode_t encap; /* Encapsulation mode for port */ 119 int oversub; /* Indicates if port has oversub enabled */ 120 uint16 prio_mask; /* Packet priority to priority group mapping mask */ 121 uint8 hsp; /* Indicates if port is high speed port */ 122 uint32 cl91_enabled; /* Indicates if port has CL91 enabled */ 123 soc_port_phy_fec_t fec_type; /* fec_type for port */ 124 int phy_lane_config; /* serdes pmd lane config for port */ 125 int link_training; /* link training on or off */ 126 int roe_compression; /* roe_compression */ 127 } soc_port_resource_t; 128 129 130 /*** START SDK API COMMON CODE ***/ 131 132 #define MAX_SCH_SLICES 2 133 #define MAX_NUM_FLEXPORTS 288 134 #define MAX_CAL_LEN 512 135 #define MAX_NUM_OVS_GRPS 32 136 #define MAX_OVS_GRP_LEN 64 137 #define MAX_NUM_OVS_SPC_GRP 32 138 #define MAX_OVS_SPC_LEN 200 139 #define CLMAC_AVERAGE_IPG_DEFAULT 12 140 #define CLMAC_AVERAGE_IPG_HIGIG 8 141 142 #define MAX_FLEX_PHASES 25 143 144 /* 145 * ASF (Cut-Through forwarding) 146 */ 147 148 /* ASF Modes */ 149 typedef enum { 150 _SOC_ASF_MODE_SAF = 0, /* store-and-forward */ 151 _SOC_ASF_MODE_SAME_SPEED = 1, /* same speed CT */ 152 _SOC_ASF_MODE_SLOW_TO_FAST = 2, /* slow to fast CT */ 153 _SOC_ASF_MODE_FAST_TO_SLOW = 3, /* fast to slow CT */ 154 _SOC_ASF_MODE_CFG_UPDATE = 4, /* internal cfg updates */ 155 _SOC_ASF_MODE_UNSUPPORTED = 5 156 } soc_asf_mode_e; 157 158 /* ASF MMU Cell Buffer Allocation Profiles */ 159 typedef enum { 160 _SOC_ASF_MEM_PROFILE_NONE = 0, /* No cut-through support */ 161 _SOC_ASF_MEM_PROFILE_SIMILAR = 1, /* Similar Speed Alloc Profile */ 162 _SOC_ASF_MEM_PROFILE_EXTREME = 2, /* Extreme Speed Alloc Profile */ 163 _SOC_ASF_MEM_PROFILE_END = 3 164 } soc_asf_mem_profile_e; 165 166 typedef struct soc_asf_prop_s { 167 int switch_bypass_mode; /* Indicate latency modes. */ 168 soc_asf_mode_e asf_modes[SOC_MAX_NUM_PORTS]; /* Per-port CT mode. */ 169 soc_asf_mem_profile_e asf_mem_prof; /* MMU cell buffer allocation profile. */ 170 } soc_asf_prop_t; 171 172 typedef struct soc_port_map_type_s { 173 enum port_speed_e log_port_speed[SOC_MAX_NUM_PORTS]; /* Logical port speed. */ 174 175 /* Physical-to-logical port map. From soc_info_t. */ 176 int port_p2l_mapping[SOC_MAX_NUM_PORTS]; 177 /* Logical-to-physical port map. From soc_info_t. */ 178 int port_l2p_mapping[SOC_MAX_NUM_PORTS]; 179 /* Physical-to-MMU port map. From soc_info_t. */ 180 int port_p2m_mapping[SOC_MAX_NUM_PORTS]; 181 /* MMU-to-physical port map. From soc_info_t. */ 182 int port_m2p_mapping[SOC_MAX_NUM_MMU_PORTS]; 183 /* Logical-to-IDB port map. From soc_info_t. */ 184 int port_l2i_mapping[SOC_MAX_NUM_PORTS]; 185 /* Logical port to number of SERDES lanes information. From soc_info_t. */ 186 int port_num_lanes[SOC_MAX_NUM_PORTS]; 187 /* Physical port to port-block (PBLK, a permutation of PM instances) */ 188 /* instance mapping for the full-chip. N PMs per pipe. (N=16 in TH2.) */ 189 int port_p2PBLK_inst_mapping[SOC_MAX_NUM_PORTS]; 190 191 pbmp_t physical_pbm; /* Physical port bitmap. From soc_info_t. */ 192 pbmp_t hg2_pbm; /* HiGig2 port bitmap. From soc_info_t. */ 193 pbmp_t management_pbm; /* Management port bitmap. From soc_info_t. */ 194 pbmp_t oversub_pbm; /* Oversubscribed port bitmap. From soc_info_t. */ 195 196 } soc_port_map_type_t; 197 198 199 typedef struct soc_tdm_schedule_s { 200 int cal_len; /* Length of linerate TDM calendar. */ 201 int linerate_schedule[MAX_CAL_LEN]; /* One array holding the TDM calendar. */ 202 203 int num_ovs_groups; /* Number of oversubscription groups. */ 204 int ovs_group_len; /* Oversubscription group length. */ 205 /* An array of arrays holding the oversubscription */ 206 /* schedule for multiple oversubscription groups. */ 207 int oversub_schedule[MAX_NUM_OVS_GRPS][MAX_OVS_GRP_LEN]; 208 209 int num_pkt_sch_or_ovs_space; /* Number of packet scheduler or spacing groups. */ 210 int pkt_sch_or_ovs_space_len; /* Packet scheduler or spacing group length. */ 211 /* An array of arrays holding either the oversubscription */ 212 /* spacings for multiple oversubscription groups or */ 213 /* the packet scheduling calendar information. */ 214 int pkt_sch_or_ovs_space[MAX_NUM_OVS_SPC_GRP][MAX_OVS_SPC_LEN]; 215 } soc_tdm_schedule_t; 216 217 218 typedef struct soc_tdm_schedule_pipe_s { 219 int num_slices; /* Set to 1 where the chip does not have separate */ 220 /* physical tables for half-pipes (or slices). */ 221 soc_tdm_schedule_t tdm_schedule_slice[MAX_SCH_SLICES]; /* TDM schedule per-slice. */ 222 223 } soc_tdm_schedule_pipe_t; 224 225 226 typedef struct soc_port_schedule_state_s { 227 int nport; /* Number of ports to be flexed. From BCM. RO. */ 228 soc_port_resource_t resource[MAX_NUM_FLEXPORTS]; /* Port reconfiguration information. From BCM. RO. */ 229 int frequency; /* Core clock frequency. From soc_info_t. RO. */ 230 int bandwidth; /* Maximum core bandwidth. From soc_info_t. RO. */ 231 int io_bandwidth; /* Maximum IO bandwidth. From soc_info_t. RO. */ 232 int lossless; /* Configurations - 1: Lossless; 0: Lossy. RO. */ 233 int is_flexport; /* Call context - 1: FlexPort; 0: Initial TDM. RO. */ 234 int calendar_type; /* TDM calendar type - 0: Universal; 1: Ethernet optimized*/ 235 236 soc_asf_prop_t cutthru_prop; /* Cut-Through setting */ 237 soc_port_map_type_t in_port_map; /* Input port map. From soc_info_t. RO. */ 238 soc_port_map_type_t out_port_map; /* Output port map. From soc_info_t. */ 239 240 soc_tdm_schedule_pipe_t tdm_ingress_schedule_pipe[SOC_MAX_NUM_PIPES]; 241 soc_tdm_schedule_pipe_t tdm_egress_schedule_pipe[SOC_MAX_NUM_PIPES]; 242 /* Scratch pad locals. Caller must not allocate. */ 243 /* Callee allocates at entry and deallocates */ 244 /* before return. */ 245 void *cookie; 246 } soc_port_schedule_state_t; 247 248 /*** END SDK API COMMON CODE ***/ 249 250 extern int soc_port_speed_higig2eth(int speed); 251 extern int soc_port_speed_to_mask(int unit, int speed, uint32 *speed_mask, 252 int *is_hg_speed); 253 254 /*** END SDK API COMMON CODE ***/ 255 extern int soc_port_sister_validate(int unit, uint32 pm_port_num); 256 extern int soc_port_speed_encap_validate(int unit); 257 258 typedef enum soc_port_phy_tx_tap_mode_e { 259 socPortPhyTxTapMode3Tap = _SHR_PORT_PHY_TX_TAP_MODE_3_TAP, 260 socPortPhyTxTapMode6Tap = _SHR_PORT_PHY_TX_TAP_MODE_6_TAP 261 } soc_port_phy_tx_tap_mode_t; 262 263 typedef enum soc_port_phy_signalling_mode_e { 264 socPortPhySignallingModeNRZ = _SHR_PORT_PHY_SIGNALLING_MODE_NRZ, 265 socPortPhySignallingModePAM4 = _SHR_PORT_PHY_SIGNALLING_MODE_PAM4 266 } soc_port_phy_signalling_mode_t; 267 268 typedef _shr_port_phy_tx_t soc_port_phy_tx_t; 269 typedef _shr_port_rlm_config_t soc_port_rlm_config_t; 270 #endif /* _SOC_ESW_PORT_H_ */