drv.h (320235B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * This file contains structure and routine declarations for the 8 * Switch-on-a-Chip Driver. 9 * 10 * This file also includes the more common include files so the 11 * individual driver files don't have to include as much. 12 */ 13 14 #ifndef _SOC_DRV_H 15 #define _SOC_DRV_H 16 17 #ifdef DNX_DATA_INTERNAL 18 #error "DNX DATA INTERNAL" 19 #endif 20 21 #include <sal/core/time.h> 22 #include <sal/core/boot.h> 23 24 #include <assert.h> 25 26 #include <shared/avl.h> 27 #include <shared/bitop.h> 28 #include <shared/fifo.h> 29 #include <shared/switch.h> 30 #include <shared/gport.h> 31 32 #include <soc/util.h> 33 #include <soc/error.h> 34 #include <soc/cm.h> 35 #include <soc/feature.h> 36 #include <soc/property.h> 37 #include <soc/dport.h> 38 39 #include <shared/alloc.h> 40 #include <sal/core/spl.h> 41 #include <sal/core/sync.h> 42 #include <sal/core/thread.h> 43 44 #include <soc/chip.h> 45 #include <soc/register.h> 46 #include <soc/memory.h> 47 #include <soc/error.h> 48 #include <soc/dma.h> 49 #include <soc/enet.h> 50 #include <soc/counter.h> 51 #include <soc/mmuerr.h> 52 #include <soc/types.h> 53 #include <soc/macipadr.h> 54 #include <soc/ll.h> 55 #include <soc/axp.h> 56 #include <soc/intr.h> 57 #include <soc/mem.h> 58 #include <soc/ser.h> 59 #include <soc/timesync.h> 60 61 #ifdef CRASH_RECOVERY_SUPPORT 62 #include <soc/hwstate/hw_log.h> 63 #endif /* CRASH_RECOVERY_SUPPORT */ 64 65 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 66 #include <soc/mcm/memregs.h> 67 #endif 68 69 #ifdef BCM_ISM_SUPPORT 70 #include <soc/ism.h> 71 #include <soc/ism_hash.h> 72 #endif 73 #ifdef BCM_CMICM_SUPPORT 74 #include <soc/shared/mos_intr_common.h> 75 #include <soc/shared/mos_msg_common.h> 76 #ifdef BCM_RCPU_SUPPORT 77 #include <soc/rcpu.h> 78 #endif 79 #endif 80 81 #ifdef BCM_CMICX_SUPPORT 82 #include <shared/cmicfw/iproc_m0ssq.h> 83 #include <shared/cmicfw/iproc_mbox.h> 84 #endif /* BCM_CMICX_SUPPORT */ 85 86 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_IPROC_SUPPORT) || defined(BCM_UC_MHOST_SUPPORT) 87 #include <soc/uc_msg.h> 88 #endif 89 90 #ifdef BCM_SBUSDMA_SUPPORT 91 #include <soc/sbusdma.h> 92 #endif 93 94 #ifdef BCM_CCMDMA_SUPPORT 95 #include <soc/ccmdma.h> 96 #endif 97 98 #ifdef BCM_FIFODMA_SUPPORT 99 #include <soc/fifodma.h> 100 #endif 101 102 /**************************************************************** 103 * UNIT DRIVER ACCESS MACROS 104 * 105 * MACRO EVALUATES TO 106 * ________________________________________________________________ 107 * SOC_DRIVER(unit) Chip driver structure 108 * SOC_INFO(unit) SOC Info structure 109 * SOC_MEM_INFO(unit,mem) Memory info structure 110 * SOC_REG_INFO(unit,reg) Register info structure 111 * SOC_BLOCK_INFO(unit,blk) Block info structure 112 * SOC_PORT_INFO(unit,port) Port info structure 113 * SOC_BLOCK2SCH(unit,blk) Integer schan num for block 114 * SOC_BLOCK2OFFSET(unit,blk) Block to idx for cmic cmds 115 * SOC_HAS_CTR_TYPE(unit, ctype) Does the device have a given 116 * counter map defined? 117 * SOC_CTR_DMA_MAP(unit, ctype) Return pointer to the counter 118 * map of the indicated type. 119 * SOC_CTR_TO_REG(unit, ctype, ind) Return the register index for 120 * a given counter index. 121 * SOC_CTR_MAP_SIZE(unit, ctype) How many entries in a given 122 * counter map. 123 */ 124 125 #define SOC_CONTROL(unit) (soc_control[unit]) 126 #define SOC_DRIVER(unit) (SOC_CONTROL(unit)->chip_driver) 127 #define SOC_FUNCTIONS(unit) (SOC_CONTROL(unit)->soc_functions) 128 #define SOC_PORTCTRL_FUNCTIONS(unit) (SOC_CONTROL(unit)->soc_portctrl_functions) 129 #define SOC_INFO(unit) (SOC_CONTROL(unit)->info) 130 #define SOC_STAT(unit) (&(SOC_CONTROL(unit)->stat)) 131 #define SOC_REG_MASK_SUBSET(unit) (SOC_CONTROL(unit)->reg_subset_mask) 132 133 #define DRV_SERVICES(unit) (SOC_DRIVER(unit)->services) 134 #define SOC_MEM_INFO(unit, mem) (*SOC_DRIVER(unit)->mem_info[mem]) 135 #define SOC_MEM_AGGR(unit, index) (SOC_DRIVER(unit)->mem_aggr[index]) 136 #define SOC_MEM_UNIQUE_ACC(unit, mem) \ 137 (SOC_DRIVER(unit)->mem_unique_acc ? \ 138 (SOC_DRIVER(unit)->mem_unique_acc[mem]) : NULL) 139 #define SOC_MEM_PTR(unit, mem) (SOC_DRIVER(unit)->mem_info[mem]) 140 #define SOC_REG_INFO(unit, reg) (*SOC_DRIVER(unit)->reg_info[reg]) 141 #define SOC_REG_STAGE(unit, reg) ((SOC_REG_INFO(unit, reg).offset >> 26) & 0x3F) 142 #define SOC_REG_UNIQUE_ACC(unit, reg) (SOC_DRIVER(unit)->reg_unique_acc[reg]) 143 #define SOC_REG_ABOVE_64_INFO(unit, reg) (*SOC_DRIVER(unit)->reg_above_64_info[reg]) 144 #define SOC_REG_ARRAY_INFO(unit, reg) (*SOC_DRIVER(unit)->reg_array_info[reg]) 145 #define SOC_REG_ARRAY_INFOP(unit, reg) (SOC_DRIVER(unit)->reg_array_info[reg]) 146 #define SOC_MEM_ARRAY_INFO(unit, mem) (*SOC_DRIVER(unit)->mem_array_info[mem]) 147 #define SOC_MEM_ARRAY_INFOP(unit, mem) (SOC_DRIVER(unit)->mem_array_info[mem]) 148 #define SOC_REG_PTR(unit, reg) (SOC_DRIVER(unit)->reg_info[reg]) 149 #define SOC_BLOCK_INFO(unit, blk) (SOC_DRIVER(unit)->block_info[blk]) 150 #define SOC_FORMAT_INFO(unit, format) (*SOC_DRIVER(unit)->format_info[format]) 151 #define SOC_FORMAT_PTR(unit, format) (SOC_DRIVER(unit)->format_info[format]) 152 #define SOC_DOP_INFO(unit) (SOC_DRIVER(unit)->dop_info) 153 154 /* Default until maximized below */ 155 #define SOC_MAX_LATENCY_MONITOR_COUNT (0) 156 157 #ifdef BCM_TOMAHAWK3_SUPPORT 158 #if 4 > SOC_MAX_LATENCY_MONITOR_COUNT 159 #undef SOC_MAX_LATENCY_MONITOR_COUNT 160 #define SOC_MAX_LATENCY_MONITOR_COUNT (4) 161 #endif 162 #endif 163 164 #ifdef BCM_TOMAHAWK3_SUPPORT 165 #define SOC_LATENCY_MONITOR_INFO(unit, monitor_id) (SOC_CONTROL(unit)->latency_monitor_info[monitor_id]) 166 #define SOC_MAX_LATENCY_MONITOR_COUNT (4) 167 #endif /* BCM_TOMAHAWK3_SUPPORT */ 168 169 #define SOC_PORT_IDX_INFO(unit, port, idx) \ 170 (SOC_DRIVER(unit)->port_info[SOC_DRIVER(unit)->port_num_blktype > 1 ? \ 171 (port) * SOC_DRIVER(unit)->port_num_blktype + \ 172 (idx) : (port)]) 173 #define SOC_PORT_INFO(unit, port) SOC_PORT_IDX_INFO(unit, port, 0) 174 175 #define SOC_CHIP_STRING(unit) (SOC_DRIVER(unit)->chip_string) 176 #define SOC_ORIGIN(unit) (SOC_DRIVER(unit)->origin) 177 #define SOC_PCI_VENDOR(unit) (SOC_DRIVER(unit)->pci_vendor) 178 #define SOC_PCI_DEVICE(unit) (SOC_DRIVER(unit)->pci_device) 179 #define SOC_PCI_REVISION(unit) (SOC_DRIVER(unit)->pci_revision) 180 #define SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, mem, xpe, pipe) \ 181 (SOC_DRIVER(unit)->mem_unique_acc[mem])[(xpe * NUM_XPE(unit)) + pipe] 182 #define SOC_MEM_UNIQUE_ACC_ITM_PIPE(unit, mem, itm, pipe) \ 183 (SOC_DRIVER(unit)->mem_unique_acc[mem])[(itm * NUM_ITM(unit)) + pipe] 184 #define SOC_MEM_UNIQUE_ACC_EB_PIPE(unit, mem, eb, pipe) \ 185 (SOC_DRIVER(unit)->mem_unique_acc[mem])[(eb * NUM_PIPE(unit)) + pipe] 186 #define SOC_MEM_UNIQUE_ACC_EB_ITM(unit, mem, eb, itm) \ 187 (SOC_DRIVER(unit)->mem_unique_acc[mem])[(eb * NUM_PIPE(unit)) + itm] 188 189 #define SOC_MEM_UNIQUE_ACC_PIPE(unit, mem, pipe) \ 190 (SOC_DRIVER(unit)->mem_unique_acc[mem])[pipe] 191 #define SOC_MEM_UNIQUE_ACC_XPE(unit, mem, xpe) \ 192 (SOC_DRIVER(unit)->mem_unique_acc[mem])[xpe] 193 #define SOC_MEM_UNIQUE_ACC_SC(unit, mem, sc) \ 194 (SOC_DRIVER(unit)->mem_unique_acc[mem])[sc] 195 #define SOC_MEM_UNIQUE_ACC_ITM(unit, mem, itm) \ 196 (SOC_DRIVER(unit)->mem_unique_acc[mem])[itm] 197 198 #define SOC_REG_UNIQUE_ACC_PIPE(unit, reg, pipe) \ 199 (SOC_DRIVER(unit)->reg_unique_acc[reg])[pipe] 200 #define SOC_REG_UNIQUE_ACC_XPE(unit, reg, xpe) \ 201 (SOC_DRIVER(unit)->reg_unique_acc[reg])[xpe] 202 #define SOC_REG_UNIQUE_ACC_ITM(unit, reg, itm) \ 203 (SOC_DRIVER(unit)->reg_unique_acc[reg])[itm] 204 205 #define SOC_SER_INFO(unit) (SOC_DRIVER(unit)->ser_info) 206 #define SOC_IP_MEM_SER_INFO(unit) (SOC_SER_INFO(unit)->ip_mem_ser_info) 207 #define SOC_IP_REG_SER_INFO(unit) (SOC_SER_INFO(unit)->ip_reg_ser_info) 208 #define SOC_EP_MEM_SER_INFO(unit) (SOC_SER_INFO(unit)->ep_mem_ser_info) 209 #define SOC_EP_REG_SER_INFO(unit) (SOC_SER_INFO(unit)->ep_reg_ser_info) 210 #define SOC_MMU_MEM_SER_INFO(unit) (SOC_SER_INFO(unit)->mmu_mem_ser_info) 211 212 213 #define SOC_REG_ADDR_STAGE(addr) ((addr >> 26) & 0x3F) 214 #define SOC_MEM_ADDR_OFFSET(_addr) ((_addr) & 0x000fffff) 215 #define SOC_MEM_ADDR_STAGE(_addr) (((_addr) >> 24) & 0x3f) 216 #ifdef BCM_EXTND_SBUS_SUPPORT 217 #define SOC_MEM_ADDR_NUM_EXTENDED(_addr) (((_addr) >> 18) & 0xff) 218 #define SOC_MEM_ADDR_OFFSET_EXTENDED_IPIPE(_addr) ((_addr) & 0x0003ffff) 219 #define SOC_MEM_ADDR_OFFSET_EXTENDED(_addr) ((_addr) & 0x03ffffff) 220 #define SOC_MEM_ADDR_STAGE_EXTENDED(_addr) (((_addr) >> 26) & 0x3f) 221 #endif 222 223 #define SOC_BLOCK2SCH(unit, blk) (SOC_BLOCK_INFO(unit,blk).schan) 224 #define SOC_BLOCK2OFFSET(unit, blk) (SOC_BLOCK_INFO(unit,blk).cmic) 225 226 #define SOC_PERSIST(unit) (soc_persist[unit]) 227 228 #define SOC_IRQ_MASK(unit) (SOC_CONTROL(unit)->irq_mask) 229 #define SOC_IRQ1_MASK(unit) (SOC_CONTROL(unit)->irq1_mask) 230 #define SOC_IRQ2_MASK(unit) (SOC_CONTROL(unit)->irq2_mask) 231 232 #define SOC_SWITCH_EVENT_NOMINAL_STORM(unit) (SOC_CONTROL(unit)->switch_event_nominal_storm) 233 234 #define SOC_CMCS_NUM(unit) (SOC_CONTROL(unit)->cmc_num) 235 #define SOC_PCI_CMCS_NUM(unit) (SOC_CONTROL(unit)->pci_cmc_num) 236 #define SOC_PCI_CMC(unit) (SOC_CONTROL(unit)->pci_cmc) 237 #define SOC_CMC_SBUSDMA_INTR(unit, cmc, ch) (SOC_CONTROL(unit)->sbusDmaIntrs[cmc][ch]) 238 #ifdef BCM_CMICM_SUPPORT 239 #define SOC_CMCx_IRQ0_MASK(unit,cmc) (SOC_CONTROL(unit)->cmc_irq0_mask[cmc]) 240 #define SOC_CMCx_IRQ1_MASK(unit,cmc) (SOC_CONTROL(unit)->cmc_irq1_mask[cmc]) 241 #define SOC_CMCx_IRQ2_MASK(unit,cmc) (SOC_CONTROL(unit)->cmc_irq2_mask[cmc]) 242 #define SOC_CMCx_IRQ3_MASK(unit,cmc) (SOC_CONTROL(unit)->cmc_irq3_mask[cmc]) 243 #define SOC_CMCx_IRQ4_MASK(unit,cmc) (SOC_CONTROL(unit)->cmc_irq4_mask[cmc]) 244 #define SOC_CMCx_IRQ5_MASK(unit,cmc) (SOC_CONTROL(unit)->cmc_irq5_mask[cmc]) 245 #define SOC_CMCx_IRQ6_MASK(unit,cmc) (SOC_CONTROL(unit)->cmc_irq6_mask[cmc]) 246 247 #ifdef BCM_RCPU_SUPPORT 248 #define SOC_RCPU_IRQ0_MASK(unit) (SOC_CONTROL(unit)->rpe_irq0_mask) 249 #define SOC_RCPU_IRQ1_MASK(unit) (SOC_CONTROL(unit)->rpe_irq1_mask) 250 #define SOC_RCPU_IRQ2_MASK(unit) (SOC_CONTROL(unit)->rpe_irq2_mask) 251 #define SOC_RCPU_IRQ3_MASK(unit) (SOC_CONTROL(unit)->rpe_irq3_mask) 252 #define SOC_RCPU_IRQ4_MASK(unit) (SOC_CONTROL(unit)->rpe_irq4_mask) 253 #define SOC_RCPU_IRQ5_MASK(unit) (SOC_CONTROL(unit)->rpe_irq5_mask) 254 #define SOC_RCPU_CMC0_IRQ0_MASK(unit) (SOC_CONTROL(unit)->rpe_pcie_irq0_mask) 255 #define SOC_RCPU_CMC1_IRQ0_MASK(unit) (SOC_CONTROL(unit)->rpe_uc0_irq0_mask) 256 #define SOC_RCPU_CMC2_IRQ0_MASK(unit) (SOC_CONTROL(unit)->rpe_uc1_irq0_mask) 257 #endif /* BCM_RCPU_SUPPORT */ 258 259 #else 260 #ifndef BCM_CMICX_SUPPORT 261 #define SOC_CMCS_NUM_MAX (1) 262 #endif 263 #endif /* BCM_CMICM_SUPPORT */ 264 265 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 266 #define SOC_CMCx_NUM_SBUSDMA (3) 267 #define SOC_ARM_CMC(unit, arm) (SOC_CONTROL(unit)->arm_cmc[(arm)]) 268 #define CPU_ARM_QUEUE_BITMAP(unit,cmc) (SOC_CONTROL(unit)->cpu_arm_queues[cmc]) 269 #define CPU_ARM_RSVD_QUEUE_BITMAP(unit,cmc) (SOC_CONTROL(unit)->cpu_arm_reserved_queues[cmc]) 270 #define NUM_CPU_ARM_COSQ(unit, cmc) (SOC_CONTROL(unit)->num_cpu_arm_cosq[cmc]) 271 #define SOC_VCHAN_NUM(unit) (SOC_CONTROL(unit)->soc_max_channels) 272 #define SOC_DCHAN_NUM(unit) (SOC_CONTROL(unit)->soc_dma_channels) 273 274 #ifdef BCM_SBUSDMA_SUPPORT 275 #define SOC_SBUSDMA_INFO(unit) (SOC_CONTROL(unit)->sbd_dm_inf) 276 #endif /* BCM_SBUSDMA_SUPPORT */ 277 278 #endif /* BCM_CMICM_SUPPORT or BCM_CMICX_SUPPORT */ 279 280 #ifdef BCM_ISM_SUPPORT 281 #define SOC_ISM_INFO(unit) (SOC_CONTROL(unit)->ism) 282 #define SOC_ISM_INFO_MAX_BANKS(unit) (SOC_ISM_INFO(unit)->max_banks) 283 #define SOC_ISM_HASH_INFO(unit) (SOC_CONTROL(unit)->ism_hash) 284 #endif /* BCM_ISM_SUPPORT */ 285 #ifdef BCM_DDR3_SUPPORT 286 #define SOC_DDR3_NUM_COLUMNS(unit) (SOC_CONTROL(unit)->ddr3_num_columns) 287 #define SOC_DDR3_NUM_ROWS(unit) (SOC_CONTROL(unit)->ddr3_num_rows) 288 #define SOC_DDR3_NUM_BANKS(unit) (SOC_CONTROL(unit)->ddr3_num_banks) 289 #define SOC_DDR3_NUM_MEMORIES(unit) (SOC_CONTROL(unit)->ddr3_num_memories) 290 #define SOC_DDR3_CLOCK_MHZ(unit) (SOC_CONTROL(unit)->ddr3_clock_mhz) 291 #define SOC_DDR3_MEM_GRADE(unit) (SOC_CONTROL(unit)->ddr3_mem_grade) 292 #define SOC_DDR3_OFFSET_WR_DQ_CI02_WL0(unit) (SOC_CONTROL(unit)->ddr3_offset_wr_dq_ci02_wl0) 293 #define SOC_DDR3_OFFSET_WR_DQ_CI00_WL1(unit) (SOC_CONTROL(unit)->ddr3_offset_wr_dq_ci00_wl1) 294 #endif /* BCM_DDR3_SUPPORT */ 295 #define SOC_IS_RCPU_UNIT(unit) (SOC_CONTROL(unit)->remote_cpu) 296 #define SOC_IS_RCPU_SCHAN(unit) (SOC_CONTROL(unit)->soc_flags & SOC_F_RCPU_SCHAN) 297 #define SOC_IS_RCPU_ONLY(unit) (SOC_CONTROL(unit)->soc_flags & SOC_F_RCPU_ONLY) 298 #define SOC_DPORT_MAP(unit) (SOC_CONTROL(unit)->dport_map) 299 #define SOC_DPORT_RMAP(unit) (SOC_CONTROL(unit)->dport_rmap) 300 #define SOC_DPORT_MAP_FLAGS(unit) (SOC_CONTROL(unit)->dport_map_flags) 301 302 /*Linkscan*/ 303 #ifdef BCM_LINKSCAN_LOCK_PER_UNIT 304 #define SOC_LINKSCAN_LOCK(unit, s) \ 305 if (soc_feature(unit, soc_feature_linkscan_lock_per_unit)) { \ 306 sal_mutex_take(SOC_CONTROL(unit)->linkscan_mutex, sal_mutex_FOREVER); \ 307 s = 0; \ 308 } else { \ 309 s = sal_splhi(); \ 310 } 311 312 #define SOC_LINKSCAN_UNLOCK(unit, s) \ 313 if (soc_feature(unit, soc_feature_linkscan_lock_per_unit)) { \ 314 sal_mutex_give(SOC_CONTROL(unit)->linkscan_mutex); \ 315 s = 0; \ 316 } else { \ 317 sal_spl(s); \ 318 } 319 #else 320 #define SOC_LINKSCAN_LOCK(unit, s) \ 321 s = sal_splhi(); 322 #define SOC_LINKSCAN_UNLOCK(unit, s) \ 323 sal_spl(s); 324 #endif /*BCM_LINKSCAN_LOCK_PER_UNIT*/ 325 326 327 #ifdef BCM_TIMESYNC_SUPPORT 328 #define SOC_TIMESYNC_PLL_CLOCK_NS(unit) \ 329 (SOC_CONTROL(unit)->timesync_pll_clock_ns) 330 #endif /* BCM_TIMESYNC_SUPPORT */ 331 /* rval must be 64-bit value */ 332 #define SOC_REG_RST_VAL_GET(unit, reg, rval) \ 333 if(!SOC_REG_IS_ABOVE_64(unit, reg)) {\ 334 COMPILER_64_SET(rval, SOC_REG_INFO(unit, reg).rst_val_hi, SOC_REG_INFO(unit, reg).rst_val_lo); \ 335 } else { \ 336 COMPILER_64_SET(rval, 0, 0); \ 337 } 338 339 #define SOC_REG_RST_MSK_GET(unit, reg, rmsk) \ 340 if(!SOC_REG_IS_ABOVE_64(unit, reg)) {\ 341 COMPILER_64_SET(rmsk, SOC_REG_INFO(unit, reg).rst_mask_hi, SOC_REG_INFO(unit, reg).rst_mask_lo); \ 342 } else { \ 343 COMPILER_64_SET(rmsk, 0, 0); \ 344 } 345 346 /* rval for above 64-bit value */ 347 /* Coverity fix 21831 and 21832 : SOC_REG_ABOVE_64_CLEAR is removed in else part as rval is not above 64 bit & SOC_REG_ABOVE_64_CLEAR results in out of bounds access while doing memset 348 */ 349 #define SOC_REG_ABOVE_64_RST_VAL_GET(unit, reg, rval) \ 350 if(SOC_REG_IS_ABOVE_64(unit, reg)) {\ 351 SOC_REG_ABOVE_64_CLEAR(rval); \ 352 SHR_BITCOPY_RANGE(rval, 0, SOC_REG_ABOVE_64_INFO(unit, reg).reset, 0, SOC_REG_ABOVE_64_INFO(unit, reg).size*32); \ 353 } else { \ 354 /* SOC_REG_ABOVE_64_CLEAR(rval); Coverity fix */ \ 355 rval[0] = SOC_REG_INFO(unit, reg).rst_val_lo; \ 356 rval[1] = SOC_REG_INFO(unit, reg).rst_val_hi; \ 357 } 358 359 360 #define SOC_REG_ABOVE_64_RST_MSK_GET(unit, reg, rmsk) \ 361 if(SOC_REG_IS_ABOVE_64(unit, reg)) {\ 362 SOC_REG_ABOVE_64_CLEAR(rmsk); \ 363 SHR_BITCOPY_RANGE(rmsk, 0, SOC_REG_ABOVE_64_INFO(unit, reg).mask, 0, SOC_REG_ABOVE_64_INFO(unit, reg).size*32); \ 364 } else { \ 365 SOC_REG_ABOVE_64_CLEAR(rmsk); \ 366 rmsk[0] = SOC_REG_INFO(unit, reg).rst_mask_lo; \ 367 rmsk[1] = SOC_REG_INFO(unit, reg).rst_mask_hi; \ 368 } 369 /* 370 * Counter map macros 371 * Assumes "ctype" is of SOC_CTR_TYPE_xxx 372 */ 373 #define SOC_HAS_CTR_TYPE(unit, ctype) \ 374 (SOC_DRIVER(unit)->counter_maps[ctype].cmap_base != NULL) 375 /* Reference to array of counters */ 376 #define SOC_CTR_DMA_MAP(unit, ctype) \ 377 (SOC_DRIVER(unit)->counter_maps[ctype]) 378 /* Map a counter index to a register index */ 379 #define SOC_CTR_TO_REG(unit, ctype, ind) \ 380 (SOC_DRIVER(unit)->counter_maps[ctype].cmap_base[ind].reg) 381 #define SOC_CTR_TO_REG_IDX(unit, ctype, ind) \ 382 (SOC_DRIVER(unit)->counter_maps[ctype].cmap_base[ind].index) 383 /* Right now, this is really per chip, not per counter type. */ 384 #define SOC_CTR_MAP_SIZE(unit, ctype) \ 385 (SOC_DRIVER(unit)->counter_maps[ctype].cmap_size) 386 387 #define SOC_CTR_TBL_INFO(unit) \ 388 (SOC_DRIVER(unit)->ctr_tbl_info) 389 390 #define SOC_REG_CTR_IDX(unit, reg) \ 391 (SOC_REG_INFO(unit, reg).ctr_idx) 392 393 #define SOC_REG_NUMELPORTLIST_IDX(unit, reg) \ 394 (SOC_REG_INFO(unit, reg).numelportlist_idx) 395 396 397 #define SOC_MEM_IS_VALID(unit, mem) \ 398 ((mem >= 0 && mem < NUM_SOC_MEM) && \ 399 (SOC_CONTROL(unit) != NULL) && \ 400 (SOC_DRIVER(unit) != NULL) && \ 401 (SOC_MEM_PTR(unit, mem) != NULL) && \ 402 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_VALID)) 403 404 #define SOC_FORMAT_IS_VALID(unit, format) \ 405 ((format >= 0 && format < NUM_SOC_FORMAT) && \ 406 (SOC_CONTROL(unit) != NULL) && \ 407 (SOC_DRIVER(unit) != NULL) && \ 408 (SOC_FORMAT_PTR(unit, format) != NULL)) 409 410 411 #define SOC_MEM_IS_ENABLED(unit, mem) \ 412 (SOC_MEM_IS_VALID(unit, mem) && \ 413 !(SOC_MEM_INFO(unit, mem).flags & \ 414 SOC_CONTROL(unit)->disabled_mem_flags)) 415 416 #define SOC_MEM_IS_VIEW(unit, mem) \ 417 ((mem >= NUM_SOC_MEM) ? 1 : 0) 418 419 #define SOC_MEM_IS_ARRAY(unit, mem) \ 420 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_IS_ARRAY) 421 #define SOC_MEM_IS_ARRAY_SAFE(unit, mem) \ 422 ( SOC_MEM_IS_ARRAY(unit, mem) && SOC_MEM_ARRAY_INFOP(unit, mem) ) 423 #define SOC_MEM_ELEM_SKIP(unit, mem) \ 424 ((SOC_IS_ARAD(unit) && (mem == NBI_TBINS_MEMm || mem == NBI_RBINS_MEMm))? \ 425 (SOC_MEM_INFO(unit, mem).index_max - SOC_MEM_INFO(unit, mem).index_min + 1) : (SOC_MEM_ARRAY_INFO(unit, mem).element_skip)) 426 #define SOC_MEM_NUMELS(unit, mem) \ 427 (SOC_MEM_ARRAY_INFO(unit, mem).numels) 428 #define SOC_MEM_FIRST_ARRAY_INDEX(unit, mem) \ 429 (SOC_MEM_ARRAY_INFO(unit, mem).first_array_index) 430 #define SOC_MEM_ELEM_SKIP_SAFE(unit, mem) \ 431 ( SOC_MEM_ARRAY_INFOP(unit, mem) ? SOC_MEM_ARRAY_INFOP(unit, mem)->element_skip : 0 ) 432 #define SOC_MEM_NUMELS_SAFE(unit, mem) \ 433 ( SOC_MEM_ARRAY_INFOP(unit, mem) ? SOC_MEM_ARRAY_INFOP(unit, mem)->numels : 1 ) 434 435 436 437 #define SOC_REG_IS_VALID(unit, reg) \ 438 ((reg >= 0 && reg < NUM_SOC_REG) && \ 439 (SOC_REG_PTR(unit, reg) != NULL) && \ 440 (SOC_REG_INFO(unit, reg).regtype != soc_invalidreg)) 441 442 #define SOC_MAX_COUNTER_NUM(unit) \ 443 ((IS_FE_PORT(unit,0)) ? SOC_CTR_MAP_SIZE(unit,SOC_CTR_TYPE_FE) : \ 444 SOC_CTR_MAP_SIZE(unit, SOC_CTR_TYPE_GE)) 445 446 447 #define SOC_REG_IS_ENABLED(unit, reg) \ 448 (SOC_REG_IS_VALID(unit, reg) && \ 449 !(SOC_REG_INFO(unit, reg).flags & \ 450 SOC_CONTROL(unit)->disabled_reg_flags)) 451 452 #define SOC_MEM_BYTES(unit, mem) (SOC_MEM_INFO(unit, mem).bytes) 453 #define SOC_MEM_WORDS(unit, mem) (BYTES2WORDS(SOC_MEM_BYTES(unit, mem))) 454 455 #define SOC_MEM_BASE(unit, mem) (SOC_MEM_INFO(unit, mem).base) 456 #define SOC_MEM_SIZE(unit, mem) \ 457 (SOC_MEM_INFO(unit, mem).index_max - \ 458 SOC_MEM_INFO(unit, mem).index_min + 1) 459 #define SOC_MEM_TABLE_BYTES(unit, mem) \ 460 (4 * SOC_MEM_WORDS(unit, mem) * \ 461 (SOC_MEM_INFO(unit, mem).index_max - \ 462 SOC_MEM_INFO(unit, mem).index_min + 1)) 463 464 #define SOC_REG_TYPE(unit, reg) \ 465 (SOC_REG_INFO(unit, reg).regtype) 466 467 #define SOC_REG_IS_WRITE_ONLY(unit, reg) \ 468 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_WO) 469 470 #define SOC_REG_IS_ABOVE_64(unit, reg) \ 471 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_ABOVE_64_BITS) 472 473 #define SOC_REG_IS_64(unit, reg) \ 474 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_64_BITS) 475 476 #define SOC_REG_IS_ABOVE_32(unit, reg) \ 477 (SOC_REG_INFO(unit, reg).flags & (SOC_REG_FLAG_64_BITS | SOC_REG_FLAG_ABOVE_64_BITS)) 478 479 #define SOC_REG_IS_32(unit, reg) \ 480 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_32_BITS) 481 482 #define SOC_REG_IS_16(unit, reg) \ 483 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_16_BITS) 484 485 #define SOC_REG_IS_8(unit, reg) \ 486 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_8_BITS) 487 488 /* Register requires special processing */ 489 #define SOC_REG_IS_SPECIAL(unit, reg) \ 490 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_SPECIAL) 491 492 #define SOC_REG_ARRAY(unit, reg) \ 493 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_ARRAY) 494 #define SOC_REG_ARRAY2(unit, reg) \ 495 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_ARRAY2) 496 #define SOC_REG_ARRAY4(unit, reg) \ 497 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_ARRAY4) 498 #define SOC_REG_IS_ARRAY(unit, reg) \ 499 (SOC_REG_INFO(unit, reg).flags & SOC_REG_FLAG_REG_ARRAY) 500 501 #define SOC_REG_IS_CCH(unit, reg) \ 502 (SOC_REG_INFO(unit, reg).flags1 & SOC_REG_FLAG_CCH) 503 504 #define SOC_REG_BASE(unit, reg) \ 505 (SOC_REG_INFO(unit, reg).offset) 506 #define SOC_REG_NUMELS(unit, reg) \ 507 (SOC_REG_INFO(unit, reg).numels) 508 #define SOC_REG_FIRST_ARRAY_INDEX(unit, reg) \ 509 (SOC_REG_INFO(unit, reg).first_array_index) 510 #define SOC_REG_GRAN(unit, reg) \ 511 (soc_regtype_gran[SOC_REG_INFO(unit, reg).regtype]) 512 #define SOC_REG_PAGE(unit, reg) \ 513 (SOC_REG_INFO(unit, reg).page) 514 #define SOC_REG_ELEM_SKIP(unit, reg) \ 515 (SOC_REG_ARRAY_INFO(unit, reg).element_skip) 516 517 #define SOC_CHIP_TYPE(unit) (SOC_INFO(unit).driver_type) 518 #define SOC_CHIP_GROUP(unit) (SOC_INFO(unit).driver_group) 519 520 #define SOC_IS_DIRECT_PORT(unit, port) \ 521 (port>=SOC_INFO(unit).physical_port_offset && \ 522 SOC_PBMP_MEMBER(SOC_INFO(unit).physical_pbm, port-SOC_INFO(unit).physical_port_offset+1)) 523 524 /* 525 * SOC_IS_* Macros. If support for the chip is defined out of the 526 * build, they are defined as zero to let the optimizer remove 527 * code. 528 */ 529 530 /* Not supported in this version of SDK */ 531 #define SOC_IS_DRACO1(unit) (0) 532 #define SOC_IS_DRACO15(unit) (0) 533 #define SOC_IS_DRACO(unit) (0) 534 #define SOC_IS_HERCULES1(unit) (0) 535 #define SOC_IS_LYNX(unit) (0) 536 #define SOC_IS_TUCANA(unit) (0) 537 #define SOC_IS_XGS12_SWITCH(unit) (0) 538 539 #ifdef BCM_HERCULES_SUPPORT 540 #ifdef BCM_HERCULES15_SUPPORT 541 #define SOC_IS_HERCULES15(unit) ((!SOC_INFO(unit).spi_device) && \ 542 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HERCULES15)) 543 #else 544 #define SOC_IS_HERCULES15(unit) (0) 545 #endif 546 #define SOC_IS_HERCULES(unit) ((!SOC_INFO(unit).spi_device) && \ 547 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HERCULES)) 548 #else 549 #define SOC_IS_HERCULES15(unit) (0) 550 #define SOC_IS_HERCULES(unit) (0) 551 #endif 552 553 #ifdef BCM_FIREBOLT_SUPPORT 554 #define SOC_IS_FIREBOLT(unit) ((!SOC_INFO(unit).spi_device) && \ 555 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FIREBOLT)) 556 #define SOC_IS_FB(unit) ((!SOC_INFO(unit).spi_device) && \ 557 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FB)) 558 #define SOC_IS_FB_FX_HX(unit) ((!SOC_INFO(unit).spi_device) && \ 559 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FB_FX_HX)) 560 #define SOC_IS_HB_GW(unit) ((!SOC_INFO(unit).spi_device) && \ 561 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HB_GW)) 562 #define SOC_IS_HBX(unit) ((!SOC_INFO(unit).spi_device) && \ 563 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HBX)) 564 #define SOC_IS_FBX(unit) ((!SOC_INFO(unit).spi_device) && \ 565 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_FBX) || \ 566 (SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA2) || \ 567 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HELIX4) || \ 568 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE2) || \ 569 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND) || \ 570 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) || \ 571 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE) || \ 572 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY) || \ 573 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HURRICANE3) || \ 574 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS) || \ 575 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) || \ 576 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) || \ 577 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2) ||\ 578 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3) || \ 579 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND2) || \ 580 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5) || \ 581 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2))) 582 #else 583 #define SOC_IS_FIREBOLT(unit) (0) 584 #define SOC_IS_FB(unit) (0) 585 #define SOC_IS_FB_FX_HX(unit) (0) 586 #define SOC_IS_HB_GW(unit) (0) 587 #define SOC_IS_HBX(unit) (0) 588 #define SOC_IS_FBX(unit) (0) 589 #endif 590 591 #ifdef BCM_HURRICANE2_SUPPORT 592 #define SOC_IS_HURRICANE2(unit) ((!SOC_INFO(unit).spi_device) && \ 593 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE2)) 594 #else 595 #define SOC_IS_HURRICANE2(unit) (0) 596 #endif 597 598 #ifdef BCM_GREYHOUND_SUPPORT 599 #define SOC_IS_GREYHOUND(unit) ((!SOC_INFO(unit).spi_device) && \ 600 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND)) 601 #else 602 #define SOC_IS_GREYHOUND(unit) (0) 603 #endif 604 605 #ifdef BCM_HURRICANE3_SUPPORT 606 #define SOC_IS_HURRICANE3(unit) ((!SOC_INFO(unit).spi_device) && \ 607 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HURRICANE3)) 608 #else 609 #define SOC_IS_HURRICANE3(unit) (0) 610 #endif 611 612 #ifdef BCM_TRIDENT3_SUPPORT 613 #define SOC_IS_TRIDENT3(unit) ((!SOC_INFO(unit).spi_device) && \ 614 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3)) 615 #define SOC_IS_TRIDENT3X(unit) ((!SOC_INFO(unit).spi_device) && \ 616 ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) || \ 617 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5) || \ 618 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2))) 619 #else 620 #define SOC_IS_TRIDENT3(unit) (0) 621 #define SOC_IS_TRIDENT3X(unit) (0) 622 #endif 623 #ifdef BCM_GREYHOUND2_SUPPORT 624 #define SOC_IS_GREYHOUND2(unit) ((!SOC_INFO(unit).spi_device) && \ 625 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND2)) 626 #else 627 #define SOC_IS_GREYHOUND2(unit) (0) 628 #endif 629 630 #ifdef BCM_HELIX5_SUPPORT 631 #define SOC_IS_HELIX5(unit) ((!SOC_INFO(unit).spi_device) && \ 632 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5)) 633 #else 634 #define SOC_IS_HELIX5(unit) (0) 635 #endif 636 637 #ifdef BCM_MAVERICK2_SUPPORT 638 #define SOC_IS_MAVERICK2(unit) ((!SOC_INFO(unit).spi_device) && \ 639 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2)) 640 #else 641 #define SOC_IS_MAVERICK2(unit) (0) 642 #endif 643 644 645 #ifdef BCM_HELIX_SUPPORT 646 #define SOC_IS_HELIX1(unit) ((!SOC_INFO(unit).spi_device) && \ 647 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FHX) && \ 648 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_FELIX)) 649 #define SOC_IS_HELIX15(unit) ((!SOC_INFO(unit).spi_device) && \ 650 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FHX) && \ 651 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX15)) 652 #define SOC_IS_HELIX(unit) ((!SOC_INFO(unit).spi_device) && \ 653 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FHX) && \ 654 ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX) || \ 655 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX15))) 656 #else 657 #define SOC_IS_HELIX(unit) (0) 658 #define SOC_IS_HELIX1(unit) (0) 659 #define SOC_IS_HELIX15(unit) (0) 660 #endif 661 #ifdef BCM_FELIX_SUPPORT 662 #define SOC_IS_FELIX1(unit) ((!SOC_INFO(unit).spi_device) && \ 663 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FHX) && \ 664 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_FELIX)) 665 #define SOC_IS_FELIX15(unit) ((!SOC_INFO(unit).spi_device) && \ 666 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FHX) && \ 667 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_FELIX15)) 668 #define SOC_IS_FELIX(unit) ((!SOC_INFO(unit).spi_device) && \ 669 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FHX) && \ 670 ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_FELIX) || \ 671 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_FELIX15))) 672 #else 673 #define SOC_IS_FELIX(unit) (0) 674 #define SOC_IS_FELIX1(unit) (0) 675 #define SOC_IS_FELIX15(unit) (0) 676 #endif 677 #ifdef BCM_RAPTOR_SUPPORT 678 #define SOC_IS_RAPTOR(unit) ((!SOC_INFO(unit).spi_device) && \ 679 (SOC_INFO(unit).chip & SOC_INFO_CHIP_RAPTOR)) 680 #define SOC_IS_RAVEN(unit) ((!SOC_INFO(unit).spi_device) && \ 681 (SOC_INFO(unit).chip & SOC_INFO_CHIP_RAVEN)) 682 #define SOC_IS_HAWKEYE(unit) ((!SOC_INFO(unit).spi_device) && \ 683 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HAWKEYE)) 684 #else 685 #define SOC_IS_RAPTOR(unit) (0) 686 #define SOC_IS_RAVEN(unit) (0) 687 #define SOC_IS_HAWKEYE(unit) (0) 688 #endif 689 #if defined(BCM_HELIX_SUPPORT) || defined(BCM_FELIX_SUPPORT) 690 #define SOC_IS_FX_HX(unit) ((!SOC_INFO(unit).spi_device) && \ 691 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FX_HX)) 692 #else 693 #define SOC_IS_FX_HX(unit) (0) 694 #endif 695 696 #ifdef BCM_GOLDWING_SUPPORT 697 #define SOC_IS_GOLDWING(unit) ((!SOC_INFO(unit).spi_device) && \ 698 (SOC_INFO(unit).chip & SOC_INFO_CHIP_GOLDWING)) 699 #else 700 #define SOC_IS_GOLDWING(unit) (0) 701 #endif 702 703 #ifdef BCM_HUMV_SUPPORT 704 #define SOC_IS_HUMV(unit) ((!SOC_INFO(unit).spi_device) && \ 705 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HUMV)) 706 #else 707 #define SOC_IS_HUMV(unit) (0) 708 #endif 709 710 #ifdef BCM_BRADLEY_SUPPORT 711 #define SOC_IS_BRADLEY(unit) ((!SOC_INFO(unit).spi_device) && \ 712 (SOC_INFO(unit).chip & SOC_INFO_CHIP_BRADLEY)) 713 #else 714 #define SOC_IS_BRADLEY(unit) (0) 715 #endif 716 717 #ifdef BCM_FIREBOLT2_SUPPORT 718 #define SOC_IS_FIREBOLT2(unit) ((!SOC_INFO(unit).spi_device) && \ 719 (SOC_INFO(unit).chip & SOC_INFO_CHIP_FIREBOLT2)) 720 #else 721 #define SOC_IS_FIREBOLT2(unit) (0) 722 #endif 723 724 #ifdef BCM_TRIUMPH_SUPPORT 725 #define SOC_IS_TRIUMPH(unit) ((!SOC_INFO(unit).spi_device) && \ 726 (SOC_INFO(unit).chip & SOC_INFO_CHIP_TRIUMPH)) 727 #define SOC_IS_ENDURO(unit) ((!SOC_INFO(unit).spi_device) && \ 728 (SOC_INFO(unit).chip & SOC_INFO_CHIP_ENDURO)) 729 #define SOC_IS_HURRICANE(unit) ((!SOC_INFO(unit).spi_device) && \ 730 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE)) 731 #define SOC_IS_HURRICANEX(unit) ((!SOC_INFO(unit).spi_device) && \ 732 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE) || \ 733 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE2) || \ 734 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HURRICANE3))) 735 #define SOC_IS_TR_VL(unit) ((!SOC_INFO(unit).spi_device) && \ 736 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TR_VL) || \ 737 (SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA2) || \ 738 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HELIX4) || \ 739 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE2) || \ 740 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND) || \ 741 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) || \ 742 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE) || \ 743 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY) || \ 744 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HURRICANE3) || \ 745 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS) || \ 746 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) || \ 747 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) || \ 748 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2) ||\ 749 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3) || \ 750 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND2) || \ 751 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5) || \ 752 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2))) 753 #else 754 #define SOC_IS_TRIUMPH(unit) (0) 755 #define SOC_IS_ENDURO(unit) (0) 756 #define SOC_IS_HURRICANE(unit) (0) 757 #define SOC_IS_HURRICANEX(unit) (0) 758 #define SOC_IS_TR_VL(unit) (0) 759 #endif 760 761 #ifdef BCM_VALKYRIE_SUPPORT 762 #define SOC_IS_VALKYRIE(unit) ((!SOC_INFO(unit).spi_device) && \ 763 (SOC_INFO(unit).chip & SOC_INFO_CHIP_VALKYRIE)) 764 #else 765 #define SOC_IS_VALKYRIE(unit) (0) 766 #endif 767 768 #ifdef BCM_SCORPION_SUPPORT 769 #define SOC_IS_SCORPION(unit) ((!SOC_INFO(unit).spi_device) && \ 770 (SOC_INFO(unit).chip & SOC_INFO_CHIP_SCORPION)) 771 #define SOC_IS_SC_CQ(unit) ((!SOC_INFO(unit).spi_device) && \ 772 (SOC_INFO(unit).chip & SOC_INFO_CHIP_SC_CQ)) 773 #else 774 #define SOC_IS_SCORPION(unit) (0) 775 #define SOC_IS_SC_CQ(unit) (0) 776 #endif 777 778 #ifdef BCM_CONQUEROR_SUPPORT 779 #define SOC_IS_CONQUEROR(unit) ((!SOC_INFO(unit).spi_device) && \ 780 (SOC_INFO(unit).chip & SOC_INFO_CHIP_CONQUEROR)) 781 #else 782 #define SOC_IS_CONQUEROR(unit) (0) 783 #endif 784 785 #ifdef BCM_TRIUMPH2_SUPPORT 786 #define SOC_IS_TRIUMPH2(unit) ((!SOC_INFO(unit).spi_device) && \ 787 (SOC_INFO(unit).chip & SOC_INFO_CHIP_TRIUMPH2)) 788 #else 789 #define SOC_IS_TRIUMPH2(unit) (0) 790 #endif 791 792 #ifdef BCM_APOLLO_SUPPORT 793 #define SOC_IS_APOLLO(unit) ((!SOC_INFO(unit).spi_device) && \ 794 (SOC_INFO(unit).chip & SOC_INFO_CHIP_APOLLO)) 795 #else 796 #define SOC_IS_APOLLO(unit) (0) 797 #endif 798 799 #ifdef BCM_VALKYRIE2_SUPPORT 800 #define SOC_IS_VALKYRIE2(unit) ((!SOC_INFO(unit).spi_device) && \ 801 (SOC_INFO(unit).chip & SOC_INFO_CHIP_VALKYRIE2)) 802 #else 803 #define SOC_IS_VALKYRIE2(unit) (0) 804 #endif 805 806 #ifdef BCM_TRIDENT_SUPPORT 807 #define SOC_IS_TRIDENT(unit) ((!SOC_INFO(unit).spi_device) && \ 808 (SOC_INFO(unit).chip & SOC_INFO_CHIP_TRIDENT)) 809 #define SOC_IS_TITAN(unit) ((!SOC_INFO(unit).spi_device) && \ 810 (SOC_INFO(unit).chip & SOC_INFO_CHIP_TITAN)) 811 #define SOC_IS_TD_TT(unit) ((!SOC_INFO(unit).spi_device) && \ 812 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TD_TT) || \ 813 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) || \ 814 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY) || \ 815 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE) || \ 816 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS) || \ 817 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) || \ 818 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2) || \ 819 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3) || \ 820 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) || \ 821 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5) || \ 822 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2))) 823 #else 824 #define SOC_IS_TRIDENT(unit) (0) 825 #define SOC_IS_TITAN(unit) (0) 826 #define SOC_IS_TD_TT(unit) (0) 827 #endif 828 829 #ifdef BCM_SHADOW_SUPPORT 830 #define SOC_IS_SHADOW(unit) ((!SOC_INFO(unit).spi_device) && \ 831 (SOC_INFO(unit).chip & SOC_INFO_CHIP_SHADOW)) 832 #else 833 #define SOC_IS_SHADOW(unit) (0) 834 #endif 835 836 #ifdef BCM_TRIUMPH3_SUPPORT 837 #define SOC_IS_TRIUMPH3(unit) ((!SOC_INFO(unit).spi_device) && \ 838 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TRIUMPH3) || \ 839 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HELIX4))) 840 #else 841 #define SOC_IS_TRIUMPH3(unit) (0) 842 #endif 843 844 #ifdef BCM_HELIX4_SUPPORT 845 #define SOC_IS_HELIX4(unit) (SOC_INFO(unit).chip & SOC_INFO_CHIP_HELIX4) 846 #else 847 #define SOC_IS_HELIX4(unit) (0) 848 #endif 849 850 #ifdef BCM_KATANA_SUPPORT 851 #define SOC_IS_KATANA(unit) ((!SOC_INFO(unit).spi_device) && \ 852 (SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA)) 853 #define SOC_IS_KATANAX(unit) ((!SOC_INFO(unit).spi_device) && \ 854 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA) || \ 855 (SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA2))) 856 #else 857 #define SOC_IS_KATANA(unit) (0) 858 #define SOC_IS_KATANAX(unit) (0) 859 #endif 860 861 #ifdef BCM_KATANA2_SUPPORT 862 #define SOC_IS_KATANA2(unit) ((!SOC_INFO(unit).spi_device) && \ 863 (SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA2)) 864 #else 865 #define SOC_IS_KATANA2(unit) (0) 866 #endif 867 868 #ifdef BCM_SABER2_SUPPORT 869 #define SOC_IS_SABER2(unit) ((!SOC_INFO(unit).spi_device) && \ 870 ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_SABER2) || \ 871 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_METROLITE))) 872 #else 873 #define SOC_IS_SABER2(unit) (0) 874 #endif 875 876 #ifdef BCM_METROLITE_SUPPORT 877 #define SOC_IS_METROLITE(unit) ((!SOC_INFO(unit).spi_device) && \ 878 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_METROLITE)) 879 #define SOC_PORT_PP_BITMAP(unit, port) (SOC_INFO(unit).pp_port_bitmap[port]) 880 #else 881 #define SOC_IS_METROLITE(unit) (0) 882 #endif 883 884 #ifdef BCM_TRIDENT2_SUPPORT 885 #define SOC_IS_TRIDENT2(unit) ((!SOC_INFO(unit).spi_device) && \ 886 (SOC_INFO(unit).chip & SOC_INFO_CHIP_TRIDENT2)) 887 #define SOC_IS_TITAN2(unit) ((!SOC_INFO(unit).spi_device) && \ 888 (SOC_INFO(unit).chip & SOC_INFO_CHIP_TITAN2)) 889 #define SOC_IS_TD2_TT2(unit) ((!SOC_INFO(unit).spi_device) && \ 890 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TD2_TT2) || \ 891 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) || \ 892 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY) || \ 893 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE) || \ 894 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS) || \ 895 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) || \ 896 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2) || \ 897 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3) || \ 898 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) || \ 899 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5) || \ 900 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2))) 901 #define SOC_IS_TRIDENT2X(unit) ((!SOC_INFO(unit).spi_device) && \ 902 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TRIDENT2X) || \ 903 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY) || \ 904 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE))) 905 #define SOC_IS_TITAN2X(unit) ((!SOC_INFO(unit).spi_device) && \ 906 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TITAN2) || \ 907 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS))) 908 #else 909 #define SOC_IS_TRIDENT2(unit) (0) 910 #define SOC_IS_TITAN2(unit) (0) 911 #define SOC_IS_TD2_TT2(unit) (0) 912 #define SOC_IS_TRIDENT2X(unit) (0) 913 #define SOC_IS_TITAN2X(unit) (0) 914 #endif 915 916 #ifdef BCM_TRIDENT2PLUS_SUPPORT 917 #define SOC_IS_TRIDENT2PLUS(unit) ((!SOC_INFO(unit).spi_device) && \ 918 (SOC_INFO(unit).chip & SOC_INFO_CHIP_TRIDENT2PLUS)) 919 #define SOC_IS_TITAN2PLUS(unit) ((!SOC_INFO(unit).spi_device) && \ 920 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS)) 921 #define SOC_IS_TD2P_TT2P(unit) ((!SOC_INFO(unit).spi_device) && \ 922 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TRIDENT2PLUS) || \ 923 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS))) 924 #else 925 #define SOC_IS_TRIDENT2PLUS(unit) (0) 926 #define SOC_IS_TITAN2PLUS(unit) (0) 927 #define SOC_IS_TD2P_TT2P(unit) (0) 928 #endif 929 930 #ifdef BCM_TOMAHAWK_SUPPORT 931 #define SOC_IS_TOMAHAWK(unit) ((!SOC_INFO(unit).spi_device) && \ 932 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TOMAHAWK) || \ 933 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS))) 934 #define SOC_IS_TOMAHAWKX(unit) ((!SOC_INFO(unit).spi_device) && \ 935 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TOMAHAWK) || \ 936 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS) || \ 937 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) || \ 938 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2) || \ 939 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3))) 940 #else 941 #define SOC_IS_TOMAHAWK(unit) (0) 942 #define SOC_IS_TOMAHAWKX(unit) (0) 943 #endif 944 945 #ifdef BCM_TOMAHAWKPLUS_SUPPORT 946 #define SOC_IS_TOMAHAWKPLUS(unit) ((!SOC_INFO(unit).spi_device) && \ 947 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS)) 948 #else 949 #define SOC_IS_TOMAHAWKPLUS(unit) (0) 950 #endif 951 952 #ifdef BCM_TOMAHAWK2_SUPPORT 953 #define SOC_IS_TOMAHAWK2(unit) ((!SOC_INFO(unit).spi_device) && \ 954 ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) || \ 955 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2))) 956 #else 957 #define SOC_IS_TOMAHAWK2(unit) (0) 958 #endif 959 960 #ifdef BCM_TOMAHAWK3_SUPPORT 961 #define SOC_IS_TOMAHAWK3(unit) ((!SOC_INFO(unit).spi_device) && \ 962 ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3))) 963 #else 964 #define SOC_IS_TOMAHAWK3(unit) (0) 965 #endif 966 967 #ifdef BCM_APACHE_SUPPORT 968 #define SOC_IS_APACHE(unit) ((!SOC_INFO(unit).spi_device) && \ 969 ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE) || \ 970 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY))) 971 #define SOC_IS_MONTEREY(unit) ((!SOC_INFO(unit).spi_device) && \ 972 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY)) 973 #else 974 #define SOC_IS_APACHE(unit) (0) 975 #define SOC_IS_MONTEREY(unit) (0) 976 #endif 977 978 #ifdef BCM_TRX_SUPPORT 979 #define SOC_IS_TRX(unit) ((!SOC_INFO(unit).spi_device) && \ 980 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_TRX) || \ 981 (SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA2) || \ 982 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HELIX4) || \ 983 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE2)||\ 984 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND) || \ 985 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) || \ 986 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE) || \ 987 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY) || \ 988 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HURRICANE3) || \ 989 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS) || \ 990 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) || \ 991 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) || \ 992 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2) ||\ 993 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3) || \ 994 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND2) || \ 995 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5) || \ 996 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2))) 997 #else 998 #define SOC_IS_TRX(unit) (0) 999 #endif 1000 1001 #ifdef BCM_XGS_SUPPORT 1002 #define SOC_IS_XGS(unit) ((!SOC_INFO(unit).spi_device) && \ 1003 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_XGS) || \ 1004 (SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA2) || \ 1005 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HELIX4) || \ 1006 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE2) ||\ 1007 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND) || \ 1008 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) || \ 1009 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE) || \ 1010 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY) || \ 1011 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HURRICANE3) || \ 1012 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) ||\ 1013 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2) ||\ 1014 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND2) || \ 1015 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) || \ 1016 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3) || \ 1017 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) || \ 1018 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5) || \ 1019 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2))) 1020 #else 1021 #define SOC_IS_XGS(unit) (0) 1022 #endif 1023 #ifdef BCM_XGS_FABRIC_SUPPORT 1024 #define SOC_IS_XGS_FABRIC(unit) ((!SOC_INFO(unit).spi_device) && \ 1025 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_XGS_FABRIC) || \ 1026 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) ||\ 1027 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2))) 1028 #define SOC_IS_XGS_FABRIC_TITAN(unit) ((!SOC_INFO(unit).spi_device) && \ 1029 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_XGS_FABRIC) || \ 1030 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK) ||\ 1031 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2))) 1032 #else 1033 #define SOC_IS_XGS_FABRIC(unit) (0) 1034 #define SOC_IS_XGS_FABRIC_TITAN(unit) (0) 1035 #endif 1036 #ifdef BCM_XGS_SWITCH_SUPPORT 1037 #define SOC_IS_XGS_SWITCH(unit) ((!SOC_INFO(unit).spi_device) && \ 1038 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_XGS_SWITCH) || \ 1039 (SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA2) || \ 1040 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HELIX4) || \ 1041 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE2)||\ 1042 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND) || \ 1043 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) || \ 1044 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE) || \ 1045 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY) || \ 1046 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HURRICANE3) || \ 1047 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) || \ 1048 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) ||\ 1049 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2) ||\ 1050 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND2) || \ 1051 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3) || \ 1052 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5) || \ 1053 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2))) 1054 #else 1055 #define SOC_IS_XGS_SWITCH(unit) (0) 1056 #endif 1057 #ifdef BCM_XGS12_FABRIC_SUPPORT 1058 #define SOC_IS_XGS12_FABRIC(unit) ((!SOC_INFO(unit).spi_device) && \ 1059 (SOC_INFO(unit).chip & SOC_INFO_CHIP_XGS12_FABRIC)) 1060 #else 1061 #define SOC_IS_XGS12_FABRIC(unit) (0) 1062 #endif 1063 #ifdef BCM_XGS3_SWITCH_SUPPORT 1064 #define SOC_IS_XGS3_SWITCH(unit) ((!SOC_INFO(unit).spi_device) && \ 1065 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_XGS3_SWITCH) || \ 1066 (SOC_INFO(unit).chip & SOC_INFO_CHIP_KATANA2) || \ 1067 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HELIX4) || \ 1068 (SOC_INFO(unit).chip & SOC_INFO_CHIP_HURRICANE2)|| \ 1069 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND) || \ 1070 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) || \ 1071 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_APACHE) || \ 1072 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MONTEREY) || \ 1073 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HURRICANE3) || \ 1074 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS) || \ 1075 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TRIDENT3) || \ 1076 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK2) ||\ 1077 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2) ||\ 1078 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TOMAHAWK3) ||\ 1079 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_GREYHOUND2) || \ 1080 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_HELIX5) || \ 1081 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_MAVERICK2))) 1082 #else 1083 #define SOC_IS_XGS3_SWITCH(unit) (0) 1084 #endif 1085 #ifdef BCM_XGS3_FABRIC_SUPPORT 1086 #define SOC_IS_XGS3_FABRIC(unit) ((!SOC_INFO(unit).spi_device) && \ 1087 ((SOC_INFO(unit).chip & SOC_INFO_CHIP_XGS3_FABRIC) || \ 1088 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITAN2PLUS) ||\ 1089 (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_TITANHAWK2))) 1090 1091 #else 1092 #define SOC_IS_XGS3_FABRIC(unit) (0) 1093 #endif 1094 1095 #ifdef BCM_PETRA_SUPPORT 1096 #define SOC_IS_ARDON(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_ARDON) 1097 #define SOC_IS_ARADPLUS(unit) ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_ARADPLUS) || (SOC_IS_ARDON(unit)) || (SOC_IS_JERICHO(unit))) 1098 #define SOC_IS_ARAD(unit) ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_ARAD) || (SOC_IS_ARADPLUS(unit))) /* SOC_IS_ARADPLUS already 1099 includes all chips above it. */ 1100 #if 1 1101 #define SOC_IS_ARAD_A0(unit) (SOC_IS_ARAD(unit) && (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88650_A0)) 1102 #define SOC_IS_ARAD_B0(unit) (SOC_IS_ARAD(unit) && (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88650_B0)) 1103 #define SOC_IS_ARAD_B1(unit) (SOC_IS_ARAD(unit) && (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88650_B1)) 1104 #define SOC_IS_ARADPLUS_A0(unit) (SOC_IS_ARADPLUS(unit) && (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88660_A0)) 1105 #define SOC_IS_ARDON_A0(unit) (SOC_IS_ARDON(unit) && (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88202_A0)) 1106 #endif 1107 #define SOC_IS_ARAD_B0_AND_ABOVE(unit) (SOC_IS_ARAD(unit) && (!SOC_IS_ARAD_A0(unit))) 1108 #define SOC_IS_ARAD_B1_AND_BELOW(unit) (SOC_IS_ARAD(unit) && (!SOC_IS_ARADPLUS(unit))) 1109 #define SOC_IS_ARADPLUS_AND_BELOW(unit) (SOC_IS_ARAD(unit) && (!SOC_IS_JERICHO(unit))) 1110 #define SOC_IS_ACP(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_ACP) 1111 #else 1112 #define SOC_IS_ARAD(unit) (0) 1113 #define SOC_IS_ARADPLUS(unit) (0) 1114 #define SOC_IS_ARDON(unit) (0) 1115 #define SOC_IS_ARAD_A0(unit) (0) 1116 #define SOC_IS_ARAD_B0(unit) (0) 1117 #define SOC_IS_ARAD_B1(unit) (0) 1118 #define SOC_IS_ARADPLUS_A0(unit) (0) 1119 #define SOC_IS_ARAD_B0_AND_ABOVE(unit) (0) 1120 #define SOC_IS_ARAD_B1_AND_BELOW(unit) (0) 1121 #define SOC_IS_ARADPLUS_AND_BELOW(unit) (0) 1122 #define SOC_IS_ACP(unit) (0) 1123 #endif 1124 1125 #ifdef BCM_JERICHO_SUPPORT 1126 #define SOC_IS_QMX(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_QMX) 1127 #define SOC_IS_JERICHO(unit) ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_JERICHO) || (SOC_IS_QMX(unit)) || (SOC_IS_QMX_B0(unit)) || (SOC_IS_QAX(unit)) || (SOC_IS_JERICHO_A0(unit)) || (SOC_IS_JERICHO_B0(unit)) || (SOC_IS_JERICHO_PLUS(unit)) || (SOC_IS_FLAIR(unit))) 1128 #define SOC_IS_QMX_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88375_A0) 1129 #define SOC_IS_QMX_B0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88375_B0) 1130 #define SOC_IS_JERICHO_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88675_A0) 1131 #define SOC_IS_JERICHO_B0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88675_B0) 1132 #define SOC_IS_JERICHO_AND_BELOW(unit) (SOC_IS_ARAD(unit) && !SOC_IS_QAX(unit) && !SOC_IS_JERICHO_PLUS(unit)) 1133 #define SOC_IS_JERICHO_B0_AND_ABOVE(unit) (SOC_IS_JERICHO_B0(unit) || SOC_IS_QMX_B0(unit) || SOC_IS_JERICHO_PLUS(unit) || SOC_IS_QAX(unit)) 1134 1135 #else 1136 #define SOC_IS_QMX(unit) (0) 1137 #define SOC_IS_JERICHO(unit) (0) 1138 #define SOC_IS_QMX_A0(unit) (0) 1139 #define SOC_IS_QMX_B0(unit) (0) 1140 #define SOC_IS_JERICHO_A0(unit) (0) 1141 #define SOC_IS_JERICHO_B0(unit) (0) 1142 #define SOC_IS_JERICHO_AND_BELOW(unit) (SOC_IS_ARAD(unit) && !SOC_IS_QAX(unit) && !SOC_IS_JERICHO_PLUS(unit)) 1143 #define SOC_IS_JERICHO_B0_AND_ABOVE(unit) (0) 1144 #endif 1145 1146 #ifdef BCM_QAX_SUPPORT 1147 #define SOC_IS_QAX(unit) ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_QAX) || (SOC_IS_KALIA(unit)) || SOC_IS_QUX(unit)) 1148 #define SOC_IS_QAX_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88470_A0) 1149 #define SOC_IS_QAX_B0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88470_B0) 1150 #define SOC_IS_KALIA(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_KALIA) 1151 #define SOC_IS_QAX_WITH_FABRIC_ENABLED(unit) (SOC_IS_KALIA(unit) || (SOC_IS_QAX(unit) && SOC_DPP_IS_MESH(unit)) || soc_feature(unit, soc_feature_packet_tdm_marking)) 1152 #else 1153 #define SOC_IS_QAX(unit) (0) 1154 #define SOC_IS_QAX_A0(unit) (0) 1155 #define SOC_IS_QAX_B0(unit) (0) 1156 #define SOC_IS_KALIA(unit) (0) 1157 #define SOC_IS_QAX_WITH_FABRIC_ENABLED(unit) (0) 1158 #endif 1159 1160 1161 #ifdef BCM_QUX_SUPPORT 1162 #define SOC_IS_QUX(unit) ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_QUX)) 1163 #define SOC_IS_QUX_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88270_A0) 1164 #else 1165 #define SOC_IS_QUX(unit) (0) 1166 #define SOC_IS_QUX_A0(unit) (0) 1167 #endif 1168 1169 #ifdef BCM_FLAIR_SUPPORT 1170 #define SOC_IS_FLAIR(unit) ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_FLAIR)) 1171 #define SOC_IS_FLAIR_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM8206_A0) 1172 #else 1173 #define SOC_IS_FLAIR(unit) (0) 1174 #define SOC_IS_FLAIR_A0(unit) (0) 1175 #endif 1176 1177 #ifdef BCM_JERICHO_PLUS_SUPPORT 1178 #define SOC_IS_JERICHO_PLUS(unit) ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_JERICHO_PLUS) || (SOC_IS_QAX(unit))) 1179 #define SOC_IS_JERICHO_PLUS_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88680_A0) 1180 #define SOC_IS_JERICHO_PLUS_AND_BELOW(unit) (SOC_IS_ARAD(unit) && !SOC_IS_QAX(unit)) 1181 #define SOC_IS_JERICHO_PLUS_ONLY(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_JERICHO_PLUS) 1182 #else 1183 #define SOC_IS_JERICHO_PLUS(unit) (0) 1184 #define SOC_IS_JERICHO_PLUS_A0(unit) (0) 1185 #define SOC_IS_JERICHO_PLUS_AND_BELOW(unit) (SOC_IS_ARAD(unit) && !SOC_IS_QAX(unit)) 1186 #define SOC_IS_JERICHO_PLUS_ONLY(unit) (0) 1187 #endif 1188 1189 #ifdef BCM_DNX_SUPPORT 1190 #define SOC_IS_DNX(unit) ((SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_JERICHO_2) || (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_J2C)) 1191 #define SOC_IS_DNX_TYPE(dev_type) (SOC_IS_JERICHO_2_TYPE(dev_type) || SOC_IS_J2C_TYPE(dev_type)) 1192 #define SOC_IS_JERICHO_2_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88690_A0) 1193 #define SOC_IS_JERICHO_2_B(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88690_B0) 1194 #define SOC_IS_JERICHO_2_B1_ONLY(unit) ((SOC_INFO(unit).driver_type == SOC_CHIP_BCM88690_B0) && CMDEV(unit).dev.rev_id == BCM88690_B1_REV_ID) 1195 #define SOC_IS_JERICHO_2_B0_ONLY(unit) ((SOC_INFO(unit).driver_type == SOC_CHIP_BCM88690_B0) && CMDEV(unit).dev.rev_id == BCM88690_B0_REV_ID) 1196 #define SOC_IS_JERICHO_2_ONLY(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_JERICHO_2) 1197 /* SKU Support*/ 1198 /* Returns TRUE for all devices with DEV_ID from 0x8690 to 0x869F*/ 1199 #define SOC_IS_JERICHO_2_TYPE(dev_type) (((dev_type) & BCM_JR2_DEVID_MASK) == (BCM88690_DEVICE_ID & BCM_JR2_DEVID_MASK)) 1200 #define SOC_IS_J2C(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_J2C) 1201 #define SOC_IS_J2C_TYPE(dev_type) ((dev_type) == BCM88800_DEVICE_ID) 1202 #else 1203 #define SOC_IS_DNX(unit) (0) 1204 #define SOC_IS_DNX_TYPE(dev_type) (0) 1205 #define SOC_IS_JERICHO_2_A0(unit) (0) 1206 #define SOC_IS_JERICHO_2_B(unit) (0) 1207 #define SOC_IS_JERICHO_2_B1_ONLY(unit) (0) 1208 #define SOC_IS_JERICHO_2_B0_ONLY(unit) (0) 1209 #define SOC_IS_JERICHO_2_ONLY(unit) (0) 1210 #define SOC_IS_JERICHO_2_TYPE(dev_type) (0) 1211 #define SOC_IS_J2C(unit) (0) 1212 #define SOC_IS_J2C_TYPE(unit) (0) 1213 #endif 1214 1215 #if defined(DNX_TEST_BOARD) && (defined(BCM_83207_A0) || defined(BCM_83208_A0)) 1216 #define DNX_TEST_CHIPS_SUPPORT 1217 #define SOC_IS_SAMAR(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_SAMAR) 1218 #define SOC_IS_SINAI(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_SINAI) 1219 #define SOC_IS_DNX_TEST_DEVICE(unit) (SOC_IS_SAMAR(unit) || SOC_IS_SINAI(unit)) 1220 #else 1221 #define SOC_IS_SAMAR(unit) 0 1222 #define SOC_IS_SINAI(unit) 0 1223 #define SOC_IS_DNX_TEST_DEVICE(unit) 0 1224 #endif 1225 1226 1227 #ifdef BCM_DFE_SUPPORT 1228 #define SOC_IS_FE1600(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_FE1600) 1229 #define SOC_IS_FE1600_REDUCED(unit) (CMDEV(unit).dev.dev_id == BCM88755_DEVICE_ID) 1230 #define SOC_IS_BCM88754_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88754_A0) 1231 #define SOC_IS_BCM88753(unit) (CMDEV(unit).dev.dev_id == BCM88753_DEVICE_ID) 1232 #define SOC_IS_BCM88753_B0(unit) (CMDEV(unit).dev.dev_id == BCM88753_DEVICE_ID && CMDEV(unit).dev.rev_id == BCM88750_B0_REV_ID) 1233 #define SOC_IS_BCM88773(unit) (CMDEV(unit).dev.dev_id == BCM88773_DEVICE_ID || CMDEV(unit).dev.dev_id == BCM88953_DEVICE_ID) 1234 #define SOC_IS_BCM88773_A1(unit) ((CMDEV(unit).dev.dev_id == BCM88773_DEVICE_ID || CMDEV(unit).dev.dev_id == BCM88953_DEVICE_ID) && CMDEV(unit).dev.rev_id == BCM88773_A1_REV_ID) 1235 #define SOC_IS_BCM88774(unit) (CMDEV(unit).dev.dev_id == BCM88774_DEVICE_ID || CMDEV(unit).dev.dev_id == BCM88954_DEVICE_ID) 1236 #define SOC_IS_BCM88774_A1(unit) ((CMDEV(unit).dev.dev_id == BCM88774_DEVICE_ID || CMDEV(unit).dev.dev_id == BCM88954_DEVICE_ID) && CMDEV(unit).dev.rev_id == BCM88774_A1_REV_ID) 1237 #define SOC_IS_BCM88775(unit) (CMDEV(unit).dev.dev_id == BCM88775_DEVICE_ID || CMDEV(unit).dev.dev_id == BCM88955_DEVICE_ID) 1238 #define SOC_IS_BCM88775_A1(unit) ((CMDEV(unit).dev.dev_id == BCM88775_DEVICE_ID || CMDEV(unit).dev.dev_id == BCM88955_DEVICE_ID) && CMDEV(unit).dev.rev_id == BCM88775_A1_REV_ID) 1239 #define SOC_IS_BCM88776(unit) (CMDEV(unit).dev.dev_id == BCM88776_DEVICE_ID || CMDEV(unit).dev.dev_id == BCM88956_DEVICE_ID) 1240 #define SOC_IS_BCM88776_A1(unit) ((CMDEV(unit).dev.dev_id == BCM88776_DEVICE_ID || CMDEV(unit).dev.dev_id == BCM88956_DEVICE_ID) && CMDEV(unit).dev.rev_id == BCM88776_A1_REV_ID) 1241 #define SOC_IS_FE3200(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_FE3200) 1242 #define SOC_IS_FE3200_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88950_A0) 1243 #if 1 1244 #define SOC_IS_FE1600_A0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88750_A0|| SOC_INFO(unit).driver_type == SOC_CHIP_BCM88752_A0) 1245 #define SOC_IS_FE1600_B0(unit) (SOC_INFO(unit).driver_type == SOC_CHIP_BCM88750_B0 || SOC_INFO(unit).driver_type == SOC_CHIP_BCM88754_A0|| SOC_INFO(unit).driver_type == SOC_CHIP_BCM88752_B0) 1246 #define SOC_IS_DFE_TYPE(dev_type) ( (dev_type) == BCM88772_DEVICE_ID || (dev_type) == BCM88752_DEVICE_ID || (dev_type) == BCM88952_DEVICE_ID || (dev_type) == BCM88750_DEVICE_ID || (dev_type) == BCM88753_DEVICE_ID || (dev_type) == BCM88754_DEVICE_ID || (dev_type) == BCM88755_DEVICE_ID || (dev_type) == BCM88770_DEVICE_ID || (dev_type) == BCM88773_DEVICE_ID || (dev_type) == BCM88774_DEVICE_ID || (dev_type) == BCM88775_DEVICE_ID || (dev_type) == BCM88776_DEVICE_ID || (dev_type) == BCM88777_DEVICE_ID || (dev_type) == BCM88950_DEVICE_ID || (dev_type) == BCM88953_DEVICE_ID || (dev_type) == BCM88954_DEVICE_ID || (dev_type) == BCM88955_DEVICE_ID || (dev_type) == BCM88956_DEVICE_ID) 1247 #endif 1248 1249 #define SOC_IS_FE1600_B0_AND_ABOVE(unit) (SOC_IS_FE1600(unit) && !SOC_IS_FE1600_A0(unit)) 1250 #else /*!BCM_DFE_SUPPORT*/ 1251 #define SOC_IS_FE1600_A0(unit) (0) 1252 #define SOC_IS_FE1600_B0(unit) (0) 1253 #define SOC_IS_FE1600_B0_AND_ABOVE(unit)(0) 1254 #define SOC_IS_FE1600(unit) (0) 1255 #define SOC_IS_FE3200(unit) (0) 1256 #define SOC_IS_FE3200_A0(unit) (0) 1257 #define SOC_IS_DFE_TYPE(dev_type) (0) 1258 #define SOC_IS_FE1600_REDUCED(unit) (0) 1259 #define SOC_IS_BCM88754_A0(unit) (0) 1260 #endif /*BCM_DFE_SUPPORT*/ 1261 1262 #ifdef BCM_DNXF_SUPPORT 1263 #define SOC_IS_RAMON(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_RAMON) 1264 #define SOC_IS_RAMON_A0(unit) (SOC_IS_RAMON(unit) && CMDEV(unit).dev.rev_id == BCM88790_A0_REV_ID) 1265 #define SOC_IS_RAMON_A1(unit) (SOC_IS_RAMON(unit) && CMDEV(unit).dev.rev_id == DNXC_A1_REV_ID) 1266 #define SOC_IS_RAMON_B0(unit) (SOC_IS_RAMON(unit) && CMDEV(unit).dev.rev_id == BCM88790_B0_REV_ID) 1267 /* SKU Support*/ 1268 /* Returns TRUE for all devices with DEV_ID from 0x8790 to 0x879F*/ 1269 #define SOC_IS_RAMON_TYPE(dev_type) (((dev_type) & BCM_DNXF_DEVID_MASK) == BCM88790_DEVICE_ID) 1270 1271 #define SOC_IS_DNXF(unit) (SOC_INFO(unit).chip_type == SOC_INFO_CHIP_TYPE_RAMON) 1272 #define SOC_IS_DNXF_TYPE(dev_type) (SOC_IS_RAMON_TYPE(dev_type)) 1273 #else 1274 #define SOC_IS_DNXF(unit) (0) 1275 #define SOC_IS_DNXF_TYPE(dev_type) (0) 1276 #define SOC_IS_RAMON(unit) (0) 1277 #define SOC_IS_RAMON_A0(unit) (0) 1278 #define SOC_IS_RAMON_A1(unit) (0) 1279 #define SOC_IS_RAMON_B0(unit) (0) 1280 #endif /*BCM_DNXF_SUPPORT*/ 1281 1282 #define SOC_IS_DPP(unit) (SOC_IS_ARAD(unit) || SOC_IS_ACP(unit) || SOC_IS_ARDON(unit) || SOC_IS_QAX(unit) || SOC_IS_JERICHO_PLUS(unit) || SOC_IS_DNX_TEST_DEVICE(unit)) 1283 #define SOC_IS_DFE(unit) (SOC_IS_FE1600(unit) || SOC_IS_FE3200(unit)) 1284 #define SOC_IS_SAND(unit) (SOC_IS_DPP(unit) || SOC_IS_DFE(unit) || SOC_IS_DNX(unit) || SOC_IS_DNXF(unit)) 1285 1286 #define SOC_IS_DPP_DRC_COMBO28(unit) (SOC_IS_ARDON(unit) || SOC_IS_JERICHO(unit) || SOC_IS_DNX_TEST_DEVICE(unit)) 1287 1288 #ifdef BCM_PETRA_SUPPORT 1289 #define SOC_BLOCK_BY_DEVICE(unit, core) ((SOC_DPP_DEFS_GET(unit, nof_cores) > 1) ? core : SOC_BLOCK_ALL) 1290 #else /* BCM_PETRA_SUPPORT */ 1291 #define SOC_BLOCK_BY_DEVICE(unit, core) 0 1292 #endif 1293 1294 /* 1295 * Buffer size to store port name 1296 */ 1297 #define SOC_DRV_PORT_NAME_MAX (14) 1298 1299 /* 1300 * Note: ESW devices need similar SOC_IS definitions 1301 */ 1302 typedef enum { 1303 SOC_INFO_CHIP_TYPE_HERCULES15 = 1, /* only use non-zero values to be able to skip further compares */ 1304 SOC_INFO_CHIP_TYPE_FIREBOLT, 1305 SOC_INFO_CHIP_TYPE_FELIX, 1306 SOC_INFO_CHIP_TYPE_HELIX, /* 5630x */ 1307 SOC_INFO_CHIP_TYPE_GOLDWING, 1308 SOC_INFO_CHIP_TYPE_HUMV, 1309 SOC_INFO_CHIP_TYPE_BRADLEY, 1310 SOC_INFO_CHIP_TYPE_RAPTOR, 1311 SOC_INFO_CHIP_TYPE_FELIX15, /* 5611x */ 1312 SOC_INFO_CHIP_TYPE_HELIX15, /* 5631x */ 1313 SOC_INFO_CHIP_TYPE_FIREBOLT2, 1314 SOC_INFO_CHIP_TYPE_TRIUMPH, 1315 SOC_INFO_CHIP_TYPE_SHADOW, 1316 SOC_INFO_CHIP_TYPE_TRIUMPH3, 1317 SOC_INFO_CHIP_TYPE_HELIX4, 1318 SOC_INFO_CHIP_TYPE_SABER2, 1319 SOC_INFO_CHIP_TYPE_METROLITE, 1320 SOC_INFO_CHIP_TYPE_RAVEN, 1321 SOC_INFO_CHIP_TYPE_GREYHOUND, 1322 SOC_INFO_CHIP_TYPE_TRIDENT3, 1323 SOC_INFO_CHIP_TYPE_TOMAHAWK3, 1324 SOC_INFO_CHIP_TYPE_HELIX5, 1325 SOC_INFO_CHIP_TYPE_MAVERICK2, 1326 SOC_INFO_CHIP_TYPE_ARAD, 1327 SOC_INFO_CHIP_TYPE_ARADPLUS, 1328 SOC_INFO_CHIP_TYPE_JERICHO, 1329 SOC_INFO_CHIP_TYPE_QMX, 1330 SOC_INFO_CHIP_TYPE_QAX, 1331 SOC_INFO_CHIP_TYPE_KALIA, 1332 SOC_INFO_CHIP_TYPE_QUX, 1333 SOC_INFO_CHIP_TYPE_FLAIR, 1334 SOC_INFO_CHIP_TYPE_JERICHO_PLUS, 1335 SOC_INFO_CHIP_TYPE_JERICHO_2, 1336 SOC_INFO_CHIP_TYPE_J2C, 1337 SOC_INFO_CHIP_TYPE_ARDON, 1338 SOC_INFO_CHIP_TYPE_FE1600, 1339 SOC_INFO_CHIP_TYPE_FE3200, 1340 SOC_INFO_CHIP_TYPE_RAMON, 1341 SOC_INFO_CHIP_TYPE_SAMAR, 1342 SOC_INFO_CHIP_TYPE_SINAI, 1343 SOC_INFO_CHIP_TYPE_TKDUMMY, 1344 SOC_INFO_CHIP_TYPE_SCORPION, 1345 SOC_INFO_CHIP_TYPE_ACP, 1346 SOC_INFO_CHIP_TYPE_APACHE, 1347 SOC_INFO_CHIP_TYPE_HURRICANE3, 1348 SOC_INFO_CHIP_TYPE_GREYHOUND2, 1349 /* TRIDENT2PLUS variants */ 1350 SOC_INFO_CHIP_TYPE_TITAN2PLUS, 1351 /* TITANHAWK variants */ 1352 SOC_INFO_CHIP_TYPE_TITANHAWK, 1353 SOC_INFO_CHIP_TYPE_TOMAHAWKPLUS, 1354 SOC_INFO_CHIP_TYPE_MONTEREY, 1355 SOC_INFO_CHIP_TYPE_TOMAHAWK2, 1356 SOC_INFO_CHIP_TYPE_TITANHAWK2 1357 } soc_chip_e; 1358 1359 #define SOC_IS_ESW(unit) (!SOC_IS_SAND(unit)) 1360 1361 /* Some devices need a register updated before starting a DMA TX operation */ 1362 #if defined(BCM_DRACO1_SUPPORT) || \ 1363 defined(BCM_LYNX_SUPPORT) || \ 1364 defined(BCM_TUCANA_SUPPORT) 1365 #define SOC_TX_PKT_PROPERTIES 1366 #endif 1367 1368 1369 #define SOC_UNIT_NUM_VALID(unit) (((unit) >= 0) && \ 1370 ((unit) < SOC_MAX_NUM_DEVICES)) 1371 1372 #define SOC_UNIT_VALID(unit) (SOC_UNIT_NUM_VALID(unit) && \ 1373 (SOC_CONTROL(unit) != NULL)) 1374 1375 /* Indicates port lies in module 1. Currently applies only to Tucana */ 1376 #ifdef BCM_TUCANA_SUPPORT 1377 #define SOC_PORT_MOD1(unit, port) ((((port) & 0x20) != 0) && \ 1378 (soc_feature(unit, soc_feature_mod1))) 1379 1380 /* 1381 * This macro returns the memory table (soc_mem_t) associated with 1382 * the given unit/port for Tucana. It returns a memory valid for 1383 * other chips as well. 1384 */ 1385 #define SOC_PORT_MEM_TAB(unit, port) \ 1386 (SOC_PORT_MOD1(unit, port) ? PORT_TAB1m : PORT_TABm) 1387 1388 1389 /* 1390 * Macro: 1391 * SOC_PORT_MOD_OFFSET 1392 * Purpose: 1393 * Maps a port to its offset in its module on Tucana. 1394 * (Lower 5 bits: port % 32) 1395 * Example: 7 -> 7, 32 -> 0, 35 -> 3. 1396 */ 1397 #define SOC_PORT_MOD_OFFSET(unit, port) ((soc_feature(unit, soc_feature_mod1) ? \ 1398 (port & 0x1f) : port)) 1399 1400 /* 1401 * Read/write macros for accessing proper port table w/ proper index 1402 */ 1403 #define READ_PORT_TAB_MOD_CHK(unit, block, port, val_p) \ 1404 (SOC_PORT_MOD1(unit, port) ? \ 1405 READ_PORT_TAB1m(unit, block, (port) & 0x1f, val_p) : \ 1406 READ_PORT_TABm(unit, block, port, val_p)) 1407 1408 #define WRITE_PORT_TAB_MOD_CHK(unit, block, port, val_p) \ 1409 (SOC_PORT_MOD1(unit, port) ? \ 1410 WRITE_PORT_TAB1m(unit, block, (port) & 0x1f, val_p) : \ 1411 WRITE_PORT_TABm(unit, block, port, val_p)) 1412 1413 /* Forces port to lie in module 1. Currently applies only to Tucana */ 1414 #define SOC_PORT_IN_MOD1(unit, port) ((port) | 0x20) 1415 1416 #else /* BCM_TUCANA_SUPPORT */ 1417 #define SOC_PORT_MOD1(unit, port) (0) 1418 #define SOC_PORT_MEM_TAB(unit, port) (PORT_TABm) 1419 #define SOC_PORT_MOD_OFFSET(unit, port) (port) 1420 #define READ_PORT_TAB_MOD_CHK(unit, block, port, val_p) \ 1421 (READ_PORT_TABm(unit, block, port, val_p)) 1422 1423 #define WRITE_PORT_TAB_MOD_CHK(unit, block, port, val_p) \ 1424 (WRITE_PORT_TABm(unit, block, port, val_p)) 1425 #define SOC_PORT_IN_MOD1(unit, port) (port) 1426 1427 #endif /* BCM_TUCANA_SUPPORT */ 1428 1429 #if defined(BCM_TOMAHAWK_SUPPORT) && (226 > SOC_MAX_NUM_PORTS) 1430 #define SOC_MAX_NUM_MMU_PORTS 226 1431 #else 1432 #define SOC_MAX_NUM_MMU_PORTS SOC_MAX_NUM_PORTS 1433 #endif 1434 1435 #define SOC_MAX_NUM_DEVICE_PORTS _SHR_PBMP_PORT_MAX 1436 1437 #if defined(BCM_TOMAHAWK_SUPPORT) 1438 #define _SOC_UPDATE_PORT_TYPE_INFO(ptype, port_num) \ 1439 si->ptype.num = 0; \ 1440 si->ptype.min = si->ptype.max = -1; \ 1441 PBMP_ITER(si->ptype.bitmap, port_num) { \ 1442 si->ptype.port[si->ptype.num++] = port_num; \ 1443 if (si->ptype.min < 0) { \ 1444 si->ptype.min = port_num; \ 1445 } \ 1446 if (it_port > si->ptype.max) { \ 1447 si->ptype.max = port_num; \ 1448 } \ 1449 } 1450 #endif 1451 1452 1453 #define SOC_PORT_VALID_RANGE(unit,port) \ 1454 ((port) >= 0 && \ 1455 ((port) < ((SOC_MAX_NUM_PP_PORTS > SOC_MAX_NUM_PORTS) ? \ 1456 SOC_MAX_NUM_PP_PORTS : SOC_MAX_NUM_PORTS)) && \ 1457 ((port) < SOC_MAX_NUM_DEVICE_PORTS)) 1458 1459 /* Holes in the port list shall be detected by port type */ 1460 1461 #if defined(BCM_ESW_SUPPORT) 1462 #define SOC_PP_PORT_VALID(unit, port) \ 1463 ((soc_feature(unit, soc_feature_linkphy_coe) && \ 1464 SOC_PBMP_MEMBER(SOC_INFO(unit).linkphy_pp_port_pbm, port)) || \ 1465 (soc_feature(unit, soc_feature_subtag_coe) && \ 1466 SOC_PBMP_MEMBER(SOC_INFO(unit).subtag_pp_port_pbm, port)) || \ 1467 (soc_feature(unit, soc_feature_general_cascade) && \ 1468 SOC_PBMP_MEMBER(SOC_INFO(unit).general_pp_port_pbm, port))) 1469 1470 #define SOC_PORT_VALID(unit,port) \ 1471 (SOC_PORT_VALID_RANGE(unit, port) && \ 1472 ((SOC_PORT_TYPE(unit, port) != 0) || \ 1473 SOC_PP_PORT_VALID(unit, port))) 1474 #else 1475 #define SOC_PP_PORT_VALID(unit, port) (0) 1476 #define SOC_PORT_VALID(unit,port) ((SOC_PORT_VALID_RANGE(unit, port)) && \ 1477 (SOC_PORT_TYPE(unit, port) != 0)) 1478 1479 #endif 1480 #define SOC_PORT_CLASS_VALID(unit, port_class) ((port_class) >= 0 && \ 1481 (port_class) < SOC_INFO(unit).port_class_max) 1482 1483 1484 #define SOC_PORT_NAME(unit,port) (SOC_INFO(unit).port_name[port]) 1485 #define SOC_PORT_NAME_ALTER(unit,port) (SOC_INFO(unit).port_name_alter[port]) 1486 #define SOC_PORT_NAME_ALTER_VALID(unit,port) (SOC_INFO(unit).port_name_alter_valid[port]) 1487 #define SOC_PORT_OFFSET(unit,port) (SOC_INFO(unit).port_offset[port]) 1488 #define SOC_PORT_TYPE(unit,port) (SOC_INFO(unit).port_type[port]) 1489 #define SOC_PORT_SPEED_MAX_SET(unit,port,speed) \ 1490 if (SOC_PORT_VALID_RANGE(unit,port)) { \ 1491 SOC_INFO(unit).port_speed_max[port] = speed; \ 1492 } 1493 #define SOC_PORT_GROUP_SET(unit,port,group) \ 1494 if (SOC_PORT_VALID_RANGE(unit,port)) { \ 1495 SOC_INFO(unit).port_group[port] = group; \ 1496 } 1497 #define SOC_PORT_SERDES_SET(unit,port,serdes) \ 1498 if (SOC_PORT_VALID_RANGE(unit,port)) { \ 1499 SOC_INFO(unit).port_serdes[port] = serdes; \ 1500 } 1501 #define SOC_PORT_NUM_LANES_SET(unit,port,num) \ 1502 if (SOC_PORT_VALID_RANGE(unit,port)) { \ 1503 SOC_INFO(unit).port_num_lanes[port] = num; \ 1504 } 1505 #define SOC_PORT_P2L_MAPPING_SET(unit,phy_port,port) \ 1506 if (SOC_PORT_VALID_RANGE(unit,phy_port)) { \ 1507 SOC_INFO(unit).port_p2l_mapping[phy_port] = port; \ 1508 } 1509 #define SOC_PORT_L2P_MAPPING_SET(unit,port,phy_port) \ 1510 if (SOC_PORT_VALID_RANGE(unit,port)) { \ 1511 SOC_INFO(unit).port_l2p_mapping[port] = phy_port; \ 1512 } 1513 #define SOC_PORT_P2M_MAPPING_SET(unit,phy_port,mmu_port) \ 1514 if (SOC_PORT_VALID_RANGE(unit,phy_port)) { \ 1515 SOC_INFO(unit).port_p2m_mapping[phy_port] = mmu_port; \ 1516 } 1517 #define SOC_PORT_M2P_MAPPING_SET(unit,mmu_port,phy_port) \ 1518 if ((mmu_port) >= 0 && (mmu_port) < SOC_MAX_NUM_MMU_PORTS) { \ 1519 SOC_INFO(unit).port_m2p_mapping[mmu_port] = phy_port; \ 1520 } 1521 /* NOTE: The param 'port' is physical port in the following */ 1522 #define SOC_PORT_IDX_BLOCK(unit, port, idx) \ 1523 (SOC_PORT_IDX_INFO(unit, port, idx).blk) 1524 #define SOC_PORT_IDX_BINDEX(unit, port, idx) \ 1525 (SOC_PORT_IDX_INFO(unit, port, idx).bindex) 1526 #define SOC_PORT_BLOCK(unit, port) SOC_PORT_IDX_BLOCK(unit, port, 0) 1527 #define SOC_PORT_BINDEX(unit, port) SOC_PORT_IDX_BINDEX(unit, port, 0) 1528 #define SOC_PIPE_ANY -1 1529 1530 /* Number of Queues for a given port */ 1531 #define SOC_PORT_NUM_COSQ(unit, port) (SOC_INFO(unit).port_num_cosq[port]) 1532 1533 /* 1534 * In blocks with an instance per core, used to select all instance for writes, and any instance for reads. 1535 * In register access used as the port parameter. 1536 * In memory access used either as the block parameter or as <block>_BLOCK(unit, SOC_CORE_ALL). 1537 */ 1538 #define SOC_CORE_DEFAULT 0 1539 #define SOC_CORE_INVALID -1 1540 #define SOC_CORE_ALL _SHR_CORE_ALL 1541 #define MAX_NUM_OF_CORES 2 1542 #define MAX_PORTS_IN_CORE 256 1543 1544 /* used as the block parameter in memory access */ 1545 #define SOC_BLOCK_ANY -1 /* for reading */ 1546 #define SOC_BLOCK_ALL -1 /* for writing */ 1547 #define SOC_BLOCK_NAME(unit,blk) ((int)blk == SOC_BLOCK_ALL ? \ 1548 "*" : \ 1549 SOC_INFO(unit).block_name[blk]) 1550 1551 /* macros given block instance as argument */ 1552 #define SOC_BLOCK_PORT(unit, blk) (SOC_INFO(unit).block_port[blk]) 1553 #define SOC_BLOCK_BITMAP(unit, blk) (SOC_INFO(unit).block_bitmap[blk]) 1554 #define SOC_BLOCK_TYPE(unit, blk) (SOC_BLOCK_INFO(unit, blk).type) 1555 #define SOC_BLOCK_NUMBER(unit, blk) (SOC_BLOCK_INFO(unit, blk).number) 1556 /* macros for broadcast blocks */ 1557 #define SOC_BLOCK_IS_BROADCAST(unit, blk) ((blk >= 0) && (SOC_INFO(unit).broadcast_blocks[blk])) 1558 #define SOC_BLOCK_BROADCAST_SIZE(unit, blk) (SOC_INFO(unit).broadcast_blocks_size[blk]) 1559 #define SOC_BLOCK_BROADCAST_MEMBER(unit, blk, index) (SOC_INFO(unit).broadcast_blocks[blk][index]) 1560 1561 #define SOC_BLOCK_IS(blk, type) (blk[0] == type) 1562 /* Used for regs in a single block only */ 1563 #define SOC_REG_BLOCK_IS(unit, reg, type) \ 1564 SOC_BLOCK_IS(SOC_REG_INFO(unit, reg).block, type) 1565 1566 extern int SOC_BLOCK_IN_LIST(int *blk, int type); 1567 /* Used for regs in multiple blocks */ 1568 #define SOC_REG_BLOCK_IN_LIST(unit, reg, type) \ 1569 SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, reg).block, type) 1570 1571 /* 1572 * Macros to get the device block type, number (instance) and index 1573 * within block for a given port 1574 */ 1575 #define SOC_PORT_BLOCK_TYPE(unit, port) \ 1576 (SOC_BLOCK_TYPE(unit, SOC_PORT_BLOCK(unit, port))) 1577 1578 #define SOC_PORT_BLOCK_NUMBER(unit, port) \ 1579 (SOC_BLOCK_NUMBER(unit, SOC_PORT_BLOCK(unit, port))) 1580 1581 #define SOC_PORT_BLOCK_INDEX(unit, port) (SOC_PORT_BINDEX(unit, port)) 1582 1583 #define NUM_PIPE(unit) (SOC_INFO(unit).num_pipe) 1584 #define NUM_XPE(unit) (SOC_INFO(unit).num_xpe) 1585 #define NUM_ITM(unit) (SOC_INFO(unit).num_itm) 1586 #define NUM_EB(unit) (SOC_INFO(unit).num_eb) 1587 #define NUM_SLICE(unit) (SOC_INFO(unit).num_slice) 1588 #define NUM_SED(unit) (SOC_INFO(unit).num_sed) 1589 #define NUM_LAYER(unit) (SOC_INFO(unit).num_layer) 1590 /*TH3_MMU: defines for MMU. Num EBs same as num_pipes*/ 1591 #define NUM_ITM(unit) (SOC_INFO(unit).num_itm) 1592 1593 #define NUM_COS(unit) (SOC_DRIVER(unit)->num_cos) 1594 #define NUM_CPU_COSQ(unit) (SOC_INFO(unit).num_cpu_cosq) 1595 #define NUM_CPU_COSQ_DEF (16) 1596 #define NUM_CPU_COSQ_MAX (64) 1597 1598 1599 #define NUM_TIME_INTERFACE(unit) (SOC_INFO(unit).num_time_interface) 1600 1601 #define SFLOW_RANGE_MAX(unit) (SOC_INFO(unit).sflow_range_max) 1602 #define NAT_ID_MAX(unit) (SOC_INFO(unit).nat_id_max) 1603 1604 #define NUM_MODID(unit) (SOC_INFO(unit).modid_count) 1605 #define SOC_MODPORT_MAX(unit) (SOC_INFO(unit).modport_max) 1606 #define SOC_MODPORT_MAX_FIRST(unit) (SOC_INFO(unit).modport_max_first) 1607 #define PORT_DUALMODID_VALID(_u_, _p_) \ 1608 if ((NUM_MODID(_u_) > 1) && ((_p_ > SOC_INFO(_u_).modport_max) || \ 1609 (_p_ < -1))) \ 1610 {return SOC_E_PORT;} 1611 1612 #define SOC_BASE_MODID(unit) SOC_CONTROL(unit)->base_modid 1613 #define SOC_BASE_MODID_SET(unit, value) \ 1614 SOC_CONTROL(unit)->base_modid = value 1615 1616 #define SOC_VLAN_XLATE_GLP_WILDCARD(unit) (SOC_INFO(unit).vlan_xlate_glp_wildcard) 1617 #define SOC_MODID_MAX(unit) (SOC_INFO(unit).modid_max) 1618 #define SOC_TRUNK_BIT_POS(unit) (SOC_INFO(unit).trunk_bit_pos) 1619 #define SOC_PORT_ADDR_MAX(unit) (SOC_INFO(unit).port_addr_max) 1620 #define SOC_HG_OFFSET(unit) (SOC_INFO(unit).hg_offset) 1621 #define SOC_PORT_ADDRESSABLE(unit,port) (port >= 0 && port <= \ 1622 SOC_INFO(unit).port_addr_max) 1623 #define SOC_MODID_ADDRESSABLE(unit,mod) (mod >= 0 && mod <= \ 1624 SOC_INFO(unit).modid_max) 1625 1626 #define SOC_PORT(unit,ptype,pno) (SOC_INFO(unit).ptype.port[pno]) 1627 #define SOC_PORT_NUM(unit,ptype) (SOC_INFO(unit).ptype.num) 1628 #define SOC_PORT_MIN(unit,ptype) (SOC_INFO(unit).ptype.min) 1629 #define SOC_PORT_MAX(unit,ptype) (SOC_INFO(unit).ptype.max) 1630 #define SOC_PORT_BITMAP(unit,ptype) (SOC_INFO(unit).ptype.bitmap) 1631 #define SOC_PORT_DISABLED_BITMAP(unit,ptype) \ 1632 (SOC_INFO(unit).ptype.disabled_bitmap) 1633 1634 #define NUM_OLP_PORT(unit) (SOC_INFO(unit).olp_port[0] > 0 ? 1 : 0) 1635 #define NUM_ERP_PORT(unit) (SOC_INFO(unit).erp_port[0] > 0 ? 1 : 0) 1636 #define NUM_OAMP_PORT(unit) (SOC_INFO(unit).oamp_port[0] > 0 ? 1 : 0) 1637 #define NUM_RCY_PORT(unit) SOC_PORT_NUM(unit,rcy) 1638 #define NUM_FE_PORT(unit) SOC_PORT_NUM(unit,fe) 1639 #define NUM_GE_PORT(unit) SOC_PORT_NUM(unit,ge) 1640 #define NUM_LLID_PORT(unit) SOC_PORT_NUM(unit,llid) 1641 #define NUM_PON_PORT(unit) SOC_PORT_NUM(unit,pon) 1642 #define NUM_XE_PORT(unit) SOC_PORT_NUM(unit,xe) 1643 #define NUM_HG_PORT(unit) SOC_PORT_NUM(unit,hg) 1644 #define NUM_HG_SUBPORT_PORT(unit) SOC_PORT_NUM(unit,hg_subport) 1645 #define NUM_HL_PORT(unit) SOC_PORT_NUM(unit,hl) 1646 #define NUM_IL_PORT(unit) SOC_PORT_NUM(unit,il) 1647 #define NUM_SCH_PORT(unit) SOC_PORT_NUM(unit,sch) 1648 #define NUM_ST_PORT(unit) SOC_PORT_NUM(unit,st) 1649 #define NUM_GX_PORT(unit) SOC_PORT_NUM(unit,gx) 1650 #define NUM_XL_PORT(unit) SOC_PORT_NUM(unit,xl) 1651 #define NUM_XLB0_PORT(unit) SOC_PORT_NUM(unit,xlb0) 1652 #define NUM_MXQ_PORT(unit) SOC_PORT_NUM(unit,mxq) 1653 #define NUM_XG_PORT(unit) SOC_PORT_NUM(unit,xg) 1654 #define NUM_XQ_PORT(unit) SOC_PORT_NUM(unit,xq) 1655 #define NUM_HYPLITE_PORT(unit) SOC_PORT_NUM(unit,hyplite) 1656 #define NUM_SPI_PORT(unit) SOC_PORT_NUM(unit,spi) 1657 #define NUM_SPI_SUBPORT_PORT(unit) SOC_PORT_NUM(unit,spi_subport) 1658 #define NUM_SCI_PORT(unit) SOC_PORT_NUM(unit,sci) 1659 #define NUM_SFI_PORT(unit) SOC_PORT_NUM(unit,sfi) 1660 #define NUM_REQ_PORT(unit) SOC_PORT_NUM(unit,req) 1661 #define NUM_FAB_PORT(unit) SOC_PORT_NUM(unit,fab) 1662 #define NUM_E_PORT(unit) SOC_PORT_NUM(unit,ether) 1663 #define NUM_LP_PORT(unit) SOC_PORT_NUM(unit,lp) 1664 #define NUM_SUBTAG_PORT(unit) SOC_PORT_NUM(unit,subtag) 1665 #define NUM_PORT(unit) SOC_PORT_NUM(unit,port) 1666 #define NUM_ALL_PORT(unit) SOC_PORT_NUM(unit,all) 1667 1668 #define MAX_PORT(unit) (SOC_INFO(unit).port_num) 1669 #define LB_PORT(unit) (SOC_INFO(unit).lb_port) 1670 #define RDB_PORT(unit) (SOC_INFO(unit).rdb_port) 1671 #define FAE_PORT(unit) (SOC_INFO(unit).fae_port) 1672 #define MACSEC_PORT(unit) (SOC_INFO(unit).macsec_port) 1673 #define AXP_PORT(unit, type) (SOC_INFO(unit).axp_port[type]) 1674 #define IPIC_PORT(unit) (SOC_INFO(unit).ipic_port) 1675 #define IPIC_BLOCK(unit) (SOC_INFO(unit).ipic_block) 1676 #define CMIC_PORT(unit) (SOC_INFO(unit).cmic_port) 1677 #define CMIC_BLOCK(unit) (SOC_INFO(unit).cmic_block) 1678 #define RCPU_PORT(unit) (SOC_INFO(unit).rcpu_port) 1679 #define ARL_BLOCK(unit) (SOC_INFO(unit).arl_block) 1680 #define MMU_BLOCK(unit) (SOC_INFO(unit).mmu_block) 1681 #define MMU_GLB_BLOCK(unit) (SOC_INFO(unit).mmu_glb_block) 1682 #define MMU_XPE_BLOCK(unit) (SOC_INFO(unit).mmu_xpe_block) 1683 #define MMU_SED_BLOCK(unit) (SOC_INFO(unit).mmu_sed_block) 1684 #define MMU_SC_BLOCK(unit) (SOC_INFO(unit).mmu_sc_block) 1685 #define MMU_SED_BLOCK(unit) (SOC_INFO(unit).mmu_sed_block) 1686 #define MMU_ITM_BLOCK(unit) (SOC_INFO(unit).mmu_itm_block) 1687 #define MMU_EB_BLOCK(unit) (SOC_INFO(unit).mmu_eb_block) 1688 #define CEV_BLOCK(unit) (SOC_INFO(unit).cev_block) 1689 #define MCU_BLOCK(unit) (SOC_INFO(unit).mcu_block) 1690 #define IPIPE_BLOCK(unit) (SOC_INFO(unit).ipipe_block) 1691 #define IPIPE_HI_BLOCK(unit) (SOC_INFO(unit).ipipe_hi_block) 1692 #define EPIPE_BLOCK(unit) (SOC_INFO(unit).epipe_block) 1693 #define EPIPE_HI_BLOCK(unit) (SOC_INFO(unit).epipe_hi_block) 1694 #define IGR_BLOCK(unit) (SOC_INFO(unit).igr_block) 1695 #define EGR_BLOCK(unit) (SOC_INFO(unit).egr_block) 1696 #define BSE_BLOCK(unit) (SOC_INFO(unit).bse_block) 1697 #define CSE_BLOCK(unit) (SOC_INFO(unit).cse_block) 1698 #define HSE_BLOCK(unit) (SOC_INFO(unit).hse_block) 1699 #define BSAFE_BLOCK(unit) (SOC_INFO(unit).bsafe_block) 1700 #define SOC_MAX_NUM_OTPC_BLKS (2) 1701 #define OTPC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_OTPC_BLKS)) ? SOC_INFO(unit).otpc_block[(instance)] : (-1)) 1702 #define ESM_BLOCK(unit) (SOC_INFO(unit).esm_block) 1703 #define PGW_CL_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 8)) ? SOC_INFO(unit).pgw_cl_block[(instance)] : (-1)) 1704 #define PG4_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 2)) ? SOC_INFO(unit).pg4_block[(instance)] : (-1)) 1705 #define PG5_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 2)) ? SOC_INFO(unit).pg5_block[(instance)] : (-1)) 1706 #define EXTERN_BLOCK(unit) (SOC_INFO(unit).exter_block) 1707 #define TOP_BLOCK(unit) (SOC_INFO(unit).top_block) 1708 #define SER_BLOCK(unit) (SOC_INFO(unit).ser_block) 1709 #define AVS_BLOCK(unit) (SOC_INFO(unit).avs_block) 1710 #define AXP_BLOCK(unit) (SOC_INFO(unit).axp_block) 1711 #define ISM_BLOCK(unit) (SOC_INFO(unit).ism_block) 1712 #define ETU_BLOCK(unit) (SOC_INFO(unit).etu_block) 1713 #define ETU_WRAP_BLOCK(unit) (SOC_INFO(unit).etu_wrap_block) 1714 #define IBOD_BLOCK(unit) (SOC_INFO(unit).ibod_block) 1715 #define MACSEC_BLOCK(unit) (SOC_INFO(unit).macsec_block) 1716 #define LLS_BLOCK(unit) (SOC_INFO(unit).lls_block) 1717 #define CES_BLOCK(unit) (SOC_INFO(unit).ces_block) 1718 #define IPROC_BLOCK(unit) (SOC_INFO(unit).iproc_block) 1719 #define CRYPTO_BLOCK(unit) (SOC_INFO(unit).crypto_block) 1720 #define SOC_MAX_NUM_PMQ_BLKS 6 1721 #define PMQ_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_INFO(unit).nof_pmqs)) ? SOC_INFO(unit).pmq_block[(instance)] : (-1)) 1722 #define PGW_GE_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 3)) ? SOC_INFO(unit).pgw_ge_block[(instance)] : (-1)) 1723 1724 #define MS_ISEC0_BLOCK(unit) (SOC_INFO(unit).ms_isec_block[0]) 1725 #define MS_ISEC1_BLOCK(unit) (SOC_INFO(unit).ms_isec_block[1]) 1726 #define MS_ISEC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 2)) ? SOC_INFO(unit).ms_isec_block[(instance)] : (-1)) 1727 #define MS_ESEC0_BLOCK(unit) (SOC_INFO(unit).ms_esec_block[0]) 1728 #define MS_ESEC1_BLOCK(unit) (SOC_INFO(unit).ms_esec_block[1]) 1729 #define MS_ESEC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 2)) ? SOC_INFO(unit).ms_esec_block[(instance)] : (-1)) 1730 #define IL0_BLOCK(unit) (SOC_INFO(unit).il_block[0]) 1731 #define IL1_BLOCK(unit) (SOC_INFO(unit).il_block[1]) 1732 #define IL_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 2)) ? SOC_INFO(unit).il_block[(instance)] : (-1)) 1733 #define CW_BLOCK(unit) (SOC_INFO(unit).cw) 1734 1735 #define TAF_BLOCK(unit) (SOC_INFO(unit).taf_block) 1736 1737 #define SOC_MAX_NUM_CI_BLKS (15) 1738 #define CI0_BLOCK(unit) (SOC_INFO(unit).ci_block[0]) 1739 #define CI1_BLOCK(unit) (SOC_INFO(unit).ci_block[1]) 1740 #define CI2_BLOCK(unit) (SOC_INFO(unit).ci_block[2]) 1741 #define CI3_BLOCK(unit) (SOC_INFO(unit).ci_block[3]) 1742 #define CI4_BLOCK(unit) (SOC_INFO(unit).ci_block[4]) 1743 #define CI5_BLOCK(unit) (SOC_INFO(unit).ci_block[5]) 1744 #define CI6_BLOCK(unit) (SOC_INFO(unit).ci_block[6]) 1745 #define CI7_BLOCK(unit) (SOC_INFO(unit).ci_block[7]) 1746 #define CI8_BLOCK(unit) (SOC_INFO(unit).ci_block[8]) 1747 #define CI9_BLOCK(unit) (SOC_INFO(unit).ci_block[9]) 1748 #define CI9_BLOCK(unit) (SOC_INFO(unit).ci_block[9]) 1749 #define CI10_BLOCK(unit) (SOC_INFO(unit).ci_block[10]) 1750 #define CI11_BLOCK(unit) (SOC_INFO(unit).ci_block[11]) 1751 #define CI12_BLOCK(unit) (SOC_INFO(unit).ci_block[12]) 1752 #define CI13_BLOCK(unit) (SOC_INFO(unit).ci_block[13]) 1753 #define CI14_BLOCK(unit) (SOC_INFO(unit).ci_block[14]) 1754 #define CI_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CI_BLKS)) ? \ 1755 SOC_INFO(unit).ci_block[(instance)] : (-1)) 1756 1757 #define MS_ISEC0_BLOCK(unit) (SOC_INFO(unit).ms_isec_block[0]) 1758 #define MS_ISEC1_BLOCK(unit) (SOC_INFO(unit).ms_isec_block[1]) 1759 #define MS_ISEC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 2)) ? SOC_INFO(unit).ms_isec_block[(instance)] : (-1)) 1760 #define MS_ESEC0_BLOCK(unit) (SOC_INFO(unit).ms_esec_block[0]) 1761 #define MS_ESEC1_BLOCK(unit) (SOC_INFO(unit).ms_esec_block[1]) 1762 #define MS_ESEC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 2)) ? SOC_INFO(unit).ms_esec_block[(instance)] : (-1)) 1763 #define IL0_BLOCK(unit) (SOC_INFO(unit).il_block[0]) 1764 #define IL1_BLOCK(unit) (SOC_INFO(unit).il_block[1]) 1765 #define IL_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < 2)) ? SOC_INFO(unit).il_block[(instance)] : (-1)) 1766 #define CW_BLOCK(unit) (SOC_INFO(unit).cw) 1767 1768 #ifdef BCM_DNX_SUPPORT 1769 #define SOC_MAX_NUM_CLPORT_BLKS 24 1770 #define CLPORT_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CLPORT_BLKS)) ? SOC_INFO(unit).clport_block[instance] : (-1)) 1771 #else 1772 #define SOC_MAX_NUM_CLPORT_BLKS (2) 1773 #define CLPORT0_BLOCK(unit) (SOC_INFO(unit).clport_block[0]) 1774 #define CLPORT1_BLOCK(unit) (SOC_INFO(unit).clport_block[1]) 1775 #define CLPORT_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CLPORT_BLKS)) ? \ 1776 SOC_INFO(unit).clport_block[(instance)] : (-1)) 1777 1778 #define SOC_MAX_NUM_CLPORT0_BLKS (1) 1779 #endif 1780 #define SOC_MAX_NUM_ILPORT_BLKS (2) 1781 1782 #define SOC_MAX_NUM_TXLP_BLKS (2) 1783 #define SOC_MAX_NUM_RXLP_BLKS (2) 1784 #define TXLP0_BLOCK(unit) (SOC_INFO(unit).txlp_block[0]) 1785 #define TXLP1_BLOCK(unit) (SOC_INFO(unit).txlp_block[1]) 1786 #define RXLP0_BLOCK(unit) (SOC_INFO(unit).rxlp_block[0]) 1787 #define RXLP1_BLOCK(unit) (SOC_INFO(unit).rxlp_block[1]) 1788 #define TXLP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_TXLP_BLKS)) ? \ 1789 SOC_INFO(unit).txlp_block[(instance)] : (-1)) 1790 #define RXLP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_RXLP_BLKS)) ? \ 1791 SOC_INFO(unit).rxlp_block[(instance)] : (-1)) 1792 1793 #define SOC_MAX_NUM_IECELL_BLKS (2) 1794 #define IECELL0_BLOCK(unit) (SOC_INFO(unit).iecell_block[0]) 1795 #define IECELL1_BLOCK(unit) (SOC_INFO(unit).iecell_block[1]) 1796 #define IECELL_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IECELL_BLKS)) ? \ 1797 SOC_INFO(unit).iecell_block[(instance)] : (-1)) 1798 1799 /* DPP blocks */ 1800 #define SOC_MAX_NUM_DPP_PIPES 2 1801 #define SOC_MAX_NUM_CGM_BLKS SOC_MAX_NUM_DPP_PIPES 1802 #define SOC_MAX_NUM_EGQ_BLKS SOC_MAX_NUM_DPP_PIPES 1803 #define SOC_MAX_NUM_EPNI_BLKS SOC_MAX_NUM_DPP_PIPES 1804 #define SOC_MAX_NUM_IHB_BLKS SOC_MAX_NUM_DPP_PIPES 1805 #define SOC_MAX_NUM_IHP_BLKS SOC_MAX_NUM_DPP_PIPES 1806 #define SOC_MAX_NUM_IPS_BLKS SOC_MAX_NUM_DPP_PIPES 1807 #define SOC_MAX_NUM_IQM_BLKS SOC_MAX_NUM_DPP_PIPES 1808 #define SOC_MAX_NUM_SCH_BLKS SOC_MAX_NUM_DPP_PIPES 1809 #define SOC_MAX_NUM_CFC_BLKS 2 1810 #define CFC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CFC_BLKS)) ? SOC_INFO(unit).cfc_block[instance] : -1) 1811 #define SOC_MAX_NUM_OCB_BLKS 2 1812 #define OCB_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_OCB_BLKS)) ? SOC_INFO(unit).ocb_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1813 #define SOC_MAX_NUM_EPRE_BLKS 2 1814 #define EPRE_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_EPRE_BLKS)) ? SOC_INFO(unit).epre_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1815 #define SOC_MAX_NUM_IPPF_BLKS 2 1816 #define IPPF_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IPPF_BLKS)) ? SOC_INFO(unit).ippf_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1817 #define SOC_MAX_NUM_CDPORT_BLKS 12 1818 #define CDPORT_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CDPORT_BLKS)) ? SOC_INFO(unit).cdport_block[instance] : (-1)) 1819 #define SOC_MAX_NUM_CDMAC_BLKS 24 1820 #define CDMAC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CDMAC_BLKS)) ? SOC_INFO(unit).cdmac_block[instance] : (-1)) 1821 #define MDB_ARM_BLOCK(unit) (SOC_INFO(unit).mdb_arm_block) 1822 #define FDTL_BLOCK(unit) (SOC_INFO(unit).fdtl_block) 1823 #define SOC_MAX_NUM_CRPS_BLKS SOC_MAX_NUM_DPP_PIPES 1824 #define CRPS_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CRPS_BLKS)) ? SOC_INFO(unit).crps_blocks[instance] : -1) 1825 #define ECI_BLOCK(unit) (SOC_INFO(unit).eci_block) 1826 #define SOC_MAX_NUM_EDB_BLKS SOC_MAX_NUM_DPP_PIPES 1827 #define EDB_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_EDB_BLKS)) ? SOC_INFO(unit).edb_blocks[instance] : -1) 1828 #define ILKN_PMH_BLOCK(unit) (SOC_INFO(unit).ilkn_pmh_block) 1829 #define IPST_BLOCK(unit) (SOC_INFO(unit).ipst_block) 1830 #define ILKN_PML_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ILKN_PML_BLKS)) ? SOC_INFO(unit).ilkn_pml_block[instance] : (-1)) 1831 #define IQMT_BLOCK(unit) (SOC_INFO(unit).iqmt_block) 1832 #define SOC_MAX_NUM_KAPS_BLKS SOC_MAX_NUM_DPP_PIPES 1833 #define KAPS_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_KAPS_BLKS)) ? SOC_INFO(unit).kaps_blocks[instance] : -1) 1834 #define SOC_MAX_NUM_KAPS_MI_BLKS 4 1835 #define KAPS_MI_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_KAPS_MI_BLKS)) ? SOC_INFO(unit).kaps_mi_block[instance] : (-1)) 1836 1837 #define ILB_BLOCK(unit) (SOC_INFO(unit).ilb_block) 1838 #define IEP_BLOCK(unit) (SOC_INFO(unit).iep_block) 1839 #define IMP_BLOCK(unit) (SOC_INFO(unit).imp_block) 1840 #define SOC_MAX_NUM_SPB_BLKS SOC_MAX_NUM_DPP_PIPES 1841 #define SPB_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_SPB_BLKS)) ? SOC_INFO(unit).spb_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1842 #define ITE_BLOCK(unit) (SOC_INFO(unit).ite_block) 1843 #define SOC_MAX_NUM_DDP_BLKS SOC_MAX_NUM_DPP_PIPES 1844 #define DDP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DDP_BLKS)) ? SOC_INFO(unit).ddp_blocks[instance] : -1) 1845 #define TXQ_BLOCK(unit) (SOC_INFO(unit).txq_block) 1846 #define TAR_BLOCK(unit) (SOC_INFO(unit).tar_block) 1847 #define PTS_BLOCK(unit) (SOC_INFO(unit).pts_block) 1848 #define SOC_MAX_NUM_SQM_BLKS SOC_MAX_NUM_DPP_PIPES 1849 #define SQM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_SQM_BLKS)) ? SOC_INFO(unit).sqm_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1850 #define IPSEC_BLOCK(unit) (SOC_INFO(unit).ipsec_block) 1851 #define SOC_MAX_NUM_IPSEC_SPU_WRAPPER_TOP_BLKS 2 1852 #define IPSEC_SPU_WRAPPER_TOP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IPSEC_SPU_WRAPPER_TOP_BLKS)) ? SOC_INFO(unit).ipsec_spu_wrapper_top_blocks[instance] : \ 1853 ((instance) == SOC_CORE_ALL ? SOC_INFO(unit).brdc_ipsec_spu_wrapper_top_block : -1)) 1854 #define SOC_MAX_NUM_MXQ_BLKS 7 1855 #define MXQ_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_MXQ_BLKS)) ? SOC_INFO(unit).mxq_block[instance] : (-1)) 1856 #define SOC_MAX_NUM_KAPS_BBS_BLKS 3 1857 #define PLL_BLOCK(unit) (SOC_INFO(unit).pll_block) 1858 #define SOC_MAX_NUM_DQM_BLKS SOC_MAX_NUM_DPP_PIPES 1859 #define DQM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DQM_BLKS)) ? SOC_INFO(unit).dqm_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1860 #define SOC_MAX_NUM_ECGM_BLKS SOC_MAX_NUM_DPP_PIPES 1861 #define ECGM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ECGM_BLKS)) ? SOC_INFO(unit).ecgm_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1862 #define IDB_BLOCK(unit) (SOC_INFO(unit).idb_block) 1863 #define SOC_MAX_NUM_PEM_BLKS 8 1864 #define PEM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_PEM_BLKS)) ? SOC_INFO(unit).pem_blocks[instance] : -1) 1865 1866 #define PPDB_A_BLOCK(unit) (SOC_INFO(unit).ppdb_a_block) 1867 #define PPDB_B_BLOCK(unit) (SOC_INFO(unit).ppdb_b_block) 1868 #define SOC_MAX_NUM_NBIL_BLKS 2 1869 #define NBIL_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_NBIL_BLKS)) ? SOC_INFO(unit).nbil_block[instance] : (-1)) 1870 #define NBIH_BLOCK(unit) (SOC_INFO(unit).nbih_block) 1871 #define NIF_BLOCK(unit) (SOC_INFO(unit).nif_block) 1872 #define FCR_BLOCK(unit) (SOC_INFO(unit).fcr_block) 1873 #define FCT_BLOCK(unit) (SOC_INFO(unit).fct_block) 1874 #define SOC_MAX_NUM_FDR_BLKS SOC_MAX_NUM_DPP_PIPES 1875 #define FDR_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_FDR_BLKS)) ? SOC_INFO(unit).fdr_blocks[instance] : -1) 1876 #define FDA_BLOCK(unit) (SOC_INFO(unit).fda_block) 1877 #define FDT_BLOCK(unit) (SOC_INFO(unit).fdt_block) 1878 #define MESH_TOPOLOGY_BLOCK(unit) (SOC_INFO(unit).mesh_topology_block) 1879 #define IDR_BLOCK(unit) (SOC_INFO(unit).idr_block) 1880 #define SOC_MAX_NUM_IPT_BLKS SOC_MAX_NUM_DPP_PIPES 1881 #define IPT_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IPT_BLKS)) ? SOC_INFO(unit).ipt_blocks[instance] : -1) 1882 #define SOC_MAX_NUM_IRE_BLKS SOC_MAX_NUM_DPP_PIPES 1883 #define IRE_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IRE_BLKS)) ? SOC_INFO(unit).ire_blocks[instance] : -1) 1884 #define IRR_BLOCK(unit) (SOC_INFO(unit).irr_block) 1885 #ifdef BCM_88790_A0 1886 #define SOC_MAX_NUM_FMAC_BLKS 48 1887 #else 1888 #define SOC_MAX_NUM_FMAC_BLKS 36 1889 #endif 1890 #define FMAC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_FMAC_BLKS)) ? SOC_INFO(unit).fmac_block[instance] : (-1)) 1891 #define SOC_MAX_NUM_XLP_BLKS 12 1892 #define XLP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_XLP_BLKS)) ? SOC_INFO(unit).xlp_block[instance] : (-1)) 1893 #define SOC_MAX_NUM_CLP_BLKS 12 1894 #define CLP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CLP_BLKS)) ? SOC_INFO(unit).clp_block[instance] : (-1)) 1895 #define NBI_BLOCK(unit) (SOC_INFO(unit).nbi_block) 1896 #define OAMP_BLOCK(unit) (SOC_INFO(unit).oamp_block) 1897 #define OLP_BLOCK(unit) (SOC_INFO(unit).olp_block) 1898 #define SOC_MAX_NUM_PQP_BLKS 2 1899 #define PQP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_PQP_BLKS)) ? SOC_INFO(unit).pqp_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1900 #define SOC_MAX_NUM_SIF_BLKS 2 1901 #define SIF_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_SIF_BLKS)) ? SOC_INFO(unit).sif_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1902 #define SOC_MAX_NUM_MCP_BLKS 2 1903 #define MCP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_MCP_BLKS)) ? SOC_INFO(unit).mcp_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1904 #define SOC_MAX_NUM_ITPP_BLKS 2 1905 #define ITPP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ITPP_BLKS)) ? SOC_INFO(unit).itpp_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1906 #define SOC_MAX_NUM_ITPPD_BLKS 2 1907 #define ITPPD_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ITPPD_BLKS)) ? SOC_INFO(unit).itppd_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1908 #define SOC_MAX_NUM_PDM_BLKS 2 1909 #define PDM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_PDM_BLKS)) ? SOC_INFO(unit).pdm_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1910 #define SOC_MAX_NUM_BDM_BLKS 2 1911 #define BDM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_BDM_BLKS)) ? SOC_INFO(unit).bdm_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1912 #define SOC_MAX_NUM_CDU_BLKS 10 1913 #define CDU_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CDU_BLKS)) ? SOC_INFO(unit).cdu_block[instance] : (-1)) 1914 #define SOC_MAX_NUM_CDUM_BLKS 2 1915 #define CDUM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CDUM_BLKS)) ? SOC_INFO(unit).cdum_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1916 #define SOC_MAX_NUM_ALL_CDU_BLKS SOC_MAX_NUM_CDUM_BLKS + SOC_MAX_NUM_CDU_BLKS 1917 #define ALL_CDU_BLOCK(unit, instance) ((((instance) == 0) || ((instance) == SOC_MAX_NUM_ALL_CDU_BLKS/2)) ? CDUM_BLOCK(unit, instance / (SOC_MAX_NUM_ALL_CDU_BLKS/2)) : \ 1918 ((instance < SOC_MAX_NUM_ALL_CDU_BLKS/2) ? CDU_BLOCK(unit, instance - 1) : CDU_BLOCK(unit, instance - 2))) 1919 #define SOC_MAX_NUM_EPS_BLKS 2 1920 #define EPS_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_EPS_BLKS)) ? SOC_INFO(unit).eps_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1921 #define SOC_MAX_NUM_HBMC_BLKS 2 1922 #define HBMC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_HBMC_BLKS)) ? SOC_INFO(unit).hbmc_block[instance] : (-1)) 1923 #ifdef BCM_88800_A0 1924 #define SOC_MAX_NUM_ILU_BLKS 8 1925 #else 1926 #define SOC_MAX_NUM_ILU_BLKS 4 1927 #endif 1928 #define ILU_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ILU_BLKS)) ? SOC_INFO(unit).ilu_block[instance] : (-1)) 1929 #define SOC_MAX_NUM_NMG_BLKS 2 1930 #define NMG_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_NMG_BLKS)) ? SOC_INFO(unit).nmg_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1931 1932 #define SOC_MAX_NUM_DDHA_BLKS 2 1933 #define DDHA_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DDHA_BLKS)) ? SOC_INFO(unit).ddha_block[instance] : (-1)) 1934 #define SOC_MAX_NUM_DDHB_BLKS 4 1935 #define DDHB_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DDHB_BLKS)) ? SOC_INFO(unit).ddhb_block[instance] : (-1)) 1936 #define SOC_MAX_NUM_DHC_BLKS 12 1937 #define DHC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DHC_BLKS)) ? SOC_INFO(unit).dhc_block[instance] : (-1)) 1938 #define SOC_MAX_NUM_DMU_BLKS 1 1939 #define DMU_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DMU_BLKS)) ? SOC_INFO(unit).dmu_block[instance] : (-1)) 1940 #define SOC_MAX_NUM_ETPPC_BLKS 2 1941 #define ETPPC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ETPPC_BLKS)) ? SOC_INFO(unit).etppc_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1942 #define SOC_MAX_NUM_EVNT_BLKS 1 1943 #define EVNT_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_EVNT_BLKS)) ? SOC_INFO(unit).evnt_block[instance] : (-1)) 1944 #define SOC_MAX_NUM_HBC_BLKS 16 1945 #define HBC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_HBC_BLKS)) ? SOC_INFO(unit).hbc_block[instance] : (-1)) 1946 #ifdef BCM_88800_A0 1947 #define SOC_MAX_NUM_ILE_BLKS 8 1948 #else 1949 #define SOC_MAX_NUM_ILE_BLKS 6 1950 #endif 1951 #define ILE_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ILE_BLKS)) ? SOC_INFO(unit).ile_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1952 #define SOC_MAX_NUM_CLU_BLKS 6 1953 #define CLU_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CLU_BLKS)) ? SOC_INFO(unit).clu_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1954 #define SOC_MAX_NUM_CLUP_BLKS 6 1955 #define CLUP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CLUP_BLKS)) ? SOC_INFO(unit).clup_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1956 #define SOC_MAX_NUM_CLMAC_BLKS 24 1957 #define CLMAC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CLMAC_BLKS)) ? SOC_INFO(unit).clmac_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1958 #define ESB_BLOCK(unit) (SOC_INFO(unit).esb_block) 1959 #define SOC_MAX_NUM_IPPE_BLKS 2 1960 #define IPPE_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IPPE_BLKS)) ? SOC_INFO(unit).ippe_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1961 #define SOC_MAX_NUM_TCAM_BLKS 2 1962 #define TCAM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_TCAM_BLKS)) ? SOC_INFO(unit).tcam_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1963 #define SOC_MAX_NUM_TDU_BLKS 2 1964 #define TDU_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_TDU_BLKS)) ? SOC_INFO(unit).tdu_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1965 1966 #define MTM_BLOCK(unit) (SOC_INFO(unit).mtm_block) 1967 #define SOC_MAX_NUM_HBM_BLKS 16 1968 #define HBM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_HBM_BLKS)) ? SOC_INFO(unit).hbm_block[instance] : (-1)) 1969 #define SOC_MAX_NUM_RQP_BLKS 2 1970 #define RQP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_RQP_BLKS)) ? SOC_INFO(unit).rqp_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1971 #define SOC_MAX_NUM_FQP_BLKS 2 1972 #define FQP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_FQP_BLKS)) ? SOC_INFO(unit).fqp_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1973 #define MDB_BLOCK(unit) (SOC_INFO(unit).mdb_block) 1974 #define SOC_MAX_NUM_ERPP_BLKS 2 1975 #define ERPP_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ERPP_BLKS)) ? SOC_INFO(unit).erpp_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1976 #define SOC_MAX_NUM_ETPPA_BLKS 2 1977 #define ETPPA_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ETPPA_BLKS)) ? SOC_INFO(unit).etppa_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1978 #define SOC_MAX_NUM_ETPPB_BLKS 2 1979 #define ETPPB_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_ETPPB_BLKS)) ? SOC_INFO(unit).etppb_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1980 #define MACT_BLOCK(unit) (SOC_INFO(unit).mact_block) 1981 #define SOC_MAX_NUM_IPPA_BLKS 2 1982 #define IPPA_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IPPA_BLKS)) ? SOC_INFO(unit).ippa_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1983 #define SOC_MAX_NUM_IPPB_BLKS 2 1984 #define IPPB_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IPPB_BLKS)) ? SOC_INFO(unit).ippb_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1985 #define SOC_MAX_NUM_IPPC_BLKS 2 1986 #define IPPC_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IPPC_BLKS)) ? SOC_INFO(unit).ippc_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1987 #define SOC_MAX_NUM_IPPD_BLKS 2 1988 #define IPPD_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_IPPD_BLKS)) ? SOC_INFO(unit).ippd_blocks[instance] : (instance == SOC_CORE_ALL ? SOC_CORE_ALL : -1)) 1989 #ifdef BCM_88790_A0 1990 #define SOC_MAX_NUM_FSRD_BLKS 24 1991 #else 1992 #define SOC_MAX_NUM_FSRD_BLKS 14 1993 #endif 1994 #define SOC_MAX_NUM_ILKN_PML_BLKS 2 1995 #define FSRD_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_FSRD_BLKS)) ? SOC_INFO(unit).fsrd_block[instance] : (-1)) 1996 #define RTP_BLOCK(unit) (SOC_INFO(unit).rtp_block) 1997 #define DRCA_BLOCK(unit) (SOC_INFO(unit).drca_block) 1998 #define DRCB_BLOCK(unit) (SOC_INFO(unit).drcb_block) 1999 #define DRCC_BLOCK(unit) (SOC_INFO(unit).drcc_block) 2000 #define DRCD_BLOCK(unit) (SOC_INFO(unit).drcd_block) 2001 #define DRCE_BLOCK(unit) (SOC_INFO(unit).drce_block) 2002 #define DRCF_BLOCK(unit) (SOC_INFO(unit).drcf_block) 2003 #define DRCG_BLOCK(unit) (SOC_INFO(unit).drcg_block) 2004 #define DRCH_BLOCK(unit) (SOC_INFO(unit).drch_block) 2005 #define DRCBROADCAST_BLOCK(unit) (SOC_INFO(unit).drcbroadcast_block) 2006 #define OCCG_BLOCK(unit) (SOC_INFO(unit).occg_block) 2007 #define SOC_MAX_NUM_MRPS_BLKS 2 2008 #define SOC_MAX_NUM_MTRPS_EM_BLKS 2 2009 #ifdef BCM_88790_A0 2010 #define SOC_MAX_NUM_DCH_BLKS 8 2011 #else 2012 #define SOC_MAX_NUM_DCH_BLKS 4 2013 #endif 2014 #define DCH_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DCH_BLKS)) ? SOC_INFO(unit).dch_block[instance] : (-1)) 2015 #define SOC_MAX_NUM_DCL_BLKS 4 2016 #define DCL_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DCL_BLKS)) ? SOC_INFO(unit).dcl_block[instance] : (-1)) 2017 #define SOC_MAX_NUM_DCMA_BLKS 2 2018 #define DCMA_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DCMA_BLKS)) ? SOC_INFO(unit).dcma_block[instance] : (-1)) 2019 #define SOC_MAX_NUM_DCMB_BLKS 2 2020 #define DCMB_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DCMB_BLKS)) ? SOC_INFO(unit).dcmb_block[instance] : (-1)) 2021 #define DCMC_BLOCK(unit) (SOC_INFO(unit).dcmc_block) 2022 #define SOC_MAX_NUM_CCS_BLKS 4 2023 #define CCS_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_CCS_BLKS)) ? SOC_INFO(unit).ccs_block[instance] : (-1)) 2024 #define SOC_MAX_NUM_DCM_BLKS 4 2025 #define DCM_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_DCM_BLKS)) ? SOC_INFO(unit).dcm_block[instance] : (-1)) 2026 2027 #define SOC_MAX_NUM_GPORT_BLKS 12 2028 #define GPORT_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_GPORT_BLKS)) ? SOC_INFO(unit).gport_block[instance] : (-1)) 2029 2030 #define KAPS_BBS_BLOCK(unit, instance) \ 2031 ( ((instance >= 0) && (instance < SOC_MAX_NUM_KAPS_BBS_BLKS)) ? \ 2032 SOC_INFO(unit).kaps_bbs_blocks[instance] : \ 2033 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_kaps_bbs_block : -1)) 2034 2035 #define MRPS_BLOCK(unit, instance) \ 2036 ( ((instance >= 0) && (instance < SOC_MAX_NUM_MRPS_BLKS)) ? \ 2037 SOC_INFO(unit).mrps_blocks[instance] : \ 2038 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_mrps_block : -1)) 2039 2040 #define MTRPS_EM_BLOCK(unit, instance) \ 2041 ( ((instance >= 0) && (instance < SOC_MAX_NUM_MTRPS_EM_BLKS)) ? \ 2042 SOC_INFO(unit).mtrps_em_blocks[instance] : \ 2043 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_mtrps_em_block : -1)) 2044 2045 #define CGM_BLOCK(unit, instance) \ 2046 ( ((instance >= 0) && (instance < SOC_MAX_NUM_CGM_BLKS)) ? \ 2047 SOC_INFO(unit).cgm_blocks[instance] : \ 2048 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_cgm_block : -1)) 2049 2050 #define IPS_BLOCK(unit, instance) \ 2051 ( ((instance >= 0) && (instance < SOC_MAX_NUM_IPS_BLKS)) ? \ 2052 SOC_INFO(unit).ips_blocks[instance] : \ 2053 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_ips_block : -1)) 2054 2055 #define IHP_BLOCK(unit, instance) \ 2056 ( ((instance >= 0) && (instance < SOC_MAX_NUM_IHP_BLKS)) ? \ 2057 SOC_INFO(unit).ihp_blocks[instance] : \ 2058 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_ihp_block : -1)) 2059 2060 #define IQM_BLOCK(unit, instance) \ 2061 ( ((instance >= 0) && (instance < SOC_MAX_NUM_IQM_BLKS)) ? \ 2062 SOC_INFO(unit).iqm_blocks[instance] : \ 2063 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_iqm_block : -1)) 2064 2065 #define SCH_BLOCK(unit, instance) \ 2066 ( ((instance >= 0) && (instance < SOC_MAX_NUM_SCH_BLKS)) ? \ 2067 SOC_INFO(unit).sch_blocks[instance] : \ 2068 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_sch_block : -1)) 2069 2070 #define EPNI_BLOCK(unit, instance) \ 2071 ( ((instance >= 0) && (instance < SOC_MAX_NUM_EPNI_BLKS)) ? \ 2072 SOC_INFO(unit).epni_blocks[instance] : \ 2073 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_epni_block : -1)) 2074 2075 #define IHB_BLOCK(unit, instance) \ 2076 ( ((instance >= 0) && (instance < SOC_MAX_NUM_IHB_BLKS)) ? \ 2077 SOC_INFO(unit).ihb_blocks[instance] : \ 2078 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_ihb_block : -1)) 2079 2080 #define EGQ_BLOCK(unit, instance) \ 2081 ( ((instance >= 0) && (instance < SOC_MAX_NUM_EGQ_BLKS)) ? \ 2082 SOC_INFO(unit).egq_blocks[instance] : \ 2083 (instance == SOC_CORE_ALL ? SOC_INFO(unit).brdc_egq_block : -1)) 2084 2085 #define SOC_MAX_NUM_DCML_BLKS 8 2086 #define DCML_BLOCK(unit, instance) \ 2087 ( ((instance >= 0) && (instance < SOC_MAX_NUM_DCML_BLKS)) ? \ 2088 SOC_INFO(unit).dcml_block[instance] : (-1)) 2089 #define SOC_MAX_NUM_QRH_BLKS 8 2090 #define QRH_BLOCK(unit, instance) \ 2091 ( ((instance >= 0) && (instance < SOC_MAX_NUM_QRH_BLKS)) ? \ 2092 SOC_INFO(unit).qrh_block[instance] : (-1)) 2093 #define SOC_MAX_NUM_CCH_BLKS 8 2094 #define CCH_BLOCK(unit, instance) \ 2095 ( ((instance >= 0) && (instance < SOC_MAX_NUM_CCH_BLKS)) ? \ 2096 SOC_INFO(unit).cch_block[instance] : (-1)) 2097 #define SOC_MAX_NUM_LCM_BLKS 8 2098 #define LCM_BLOCK(unit, instance) \ 2099 ( ((instance >= 0) && (instance < SOC_MAX_NUM_LCM_BLKS)) ? \ 2100 SOC_INFO(unit).lcm_block[instance] : (-1)) 2101 2102 #define MCT_BLOCK(unit) (SOC_INFO(unit).mct_block) 2103 #define BRDC_CCH_BLOCK(unit) (SOC_INFO(unit).brdc_cch_block) 2104 #define BRDC_DCML_BLOCK(unit) (SOC_INFO(unit).brdc_dcml_block) 2105 #define BRDC_LCM_BLOCK(unit) (SOC_INFO(unit).brdc_lcm_block) 2106 #define BRDC_QRH_BLOCK(unit) (SOC_INFO(unit).brdc_qrh_block) 2107 #define BRDC_FMACH_BLOCK(unit) (SOC_INFO(unit).brdc_fmach_block) 2108 #define BRDC_FMACL_BLOCK(unit) (SOC_INFO(unit).brdc_fmacl_block) 2109 #define BRDC_FSRD_BLOCK(unit) (SOC_INFO(unit).brdc_fsrd_block) 2110 #define BRDC_FMAC_BLOCK(unit) (SOC_INFO(unit).brdc_fmac_block) 2111 #define BRDC_HBC_BLOCK(unit) (SOC_INFO(unit).brdc_hbc_block) 2112 #define BRDC_FMAC_AC_BLOCK(unit) (SOC_INFO(unit).brdc_fmac_ac_block) 2113 #define BRDC_FMAC_BD_BLOCK(unit) (SOC_INFO(unit).brdc_fmac_bd_block) 2114 #define BRDC_DCH_BLOCK(unit) (SOC_INFO(unit).brdc_dch_block) 2115 #define BRDC_DCL_BLOCK(unit) (SOC_INFO(unit).brdc_dcl_block) 2116 #define BRDC_DCM_BLOCK(unit) (SOC_INFO(unit).brdc_dcm_block) 2117 #define BRDC_CCS_BLOCK(unit) (SOC_INFO(unit).brdc_ccs_block) 2118 #define BRDC_CGM_BLOCK(unit) (SOC_INFO(unit).brdc_cgm_block) 2119 #define BRDC_EGQ_BLOCK(unit) (SOC_INFO(unit).brdc_egq_block) 2120 #define BRDC_EPNI_BLOCK(unit) (SOC_INFO(unit).brdc_epni_block) 2121 #define BRDC_IHB_BLOCK(unit) (SOC_INFO(unit).brdc_ihb_block) 2122 #define BRDC_IHP_BLOCK(unit) (SOC_INFO(unit).brdc_ihp_block) 2123 #define BRDC_IPS_BLOCK(unit) (SOC_INFO(unit).brdc_ips_block) 2124 #define BRDC_IQM_BLOCK(unit) (SOC_INFO(unit).brdc_iqm_block) 2125 #define BRDC_SCH_BLOCK(unit) (SOC_INFO(unit).brdc_sch_block) 2126 #define BRDC_KAPS_BBS_BLOCK(unit) (SOC_INFO(unit).brdc_kaps_bbs_block) 2127 #define BRDC_MRPS_BLOCK(unit) (SOC_INFO(unit).brdc_mrps_block) 2128 #define BRDC_MTRPS_EM_BLOCK(unit) (SOC_INFO(unit).brdc_mtrps_em_block) 2129 #define BRDC_IPSEC_SPU_WRAPPER_TOP_BLOCK(unit) (SOC_INFO(unit).brdc_ipsec_spu_wrapper_top_block) 2130 #define PRM_BLOCK(unit) (SOC_INFO(unit).prm_block) 2131 #define SOC_MAX_NUM_BLH_BLKS 3 2132 #define BLH_BLOCK(unit, instance) ((((instance) >= 0) && ((instance) < SOC_MAX_NUM_BLH_BLKS)) ? SOC_INFO(unit).blh_block[instance] : (-1)) 2133 #define AM_TOP_BLOCK(unit) (SOC_INFO(unit).am_top_block) 2134 2135 /* 2136 * E is ethernet port (FE|GE|XE) 2137 * PORT is all net ports (E|HG|IL) 2138 * ALL is all ports (PORT|CMIC) 2139 */ 2140 #define PBMP_FE_ALL(unit) SOC_PORT_BITMAP(unit,fe) 2141 #define PBMP_GE_ALL(unit) SOC_PORT_BITMAP(unit,ge) 2142 #define PBMP_LLID_ALL(unit) SOC_PORT_BITMAP(unit,llid) 2143 #define PBMP_PON_ALL(unit) SOC_PORT_BITMAP(unit,pon) 2144 #define PBMP_CE_ALL(unit) SOC_PORT_BITMAP(unit,ce) 2145 #define PBMP_CDE_ALL(unit) SOC_PORT_BITMAP(unit,cde) 2146 #define PBMP_XE_ALL(unit) SOC_PORT_BITMAP(unit,xe) 2147 #define PBMP_HG_ALL(unit) SOC_PORT_BITMAP(unit,hg) 2148 #define PBMP_IL_ALL(unit) SOC_PORT_BITMAP(unit,il) 2149 #define PBMP_SCH_ALL(unit) SOC_PORT_BITMAP(unit,sch) 2150 #define PBMP_HG_SUBPORT_ALL(unit) SOC_PORT_BITMAP(unit,hg_subport) 2151 #define PBMP_HL_ALL(unit) SOC_PORT_BITMAP(unit,hl) 2152 #define PBMP_ST_ALL(unit) SOC_PORT_BITMAP(unit,st) 2153 #define PBMP_GX_ALL(unit) SOC_PORT_BITMAP(unit,gx) 2154 #define PBMP_XL_ALL(unit) SOC_PORT_BITMAP(unit,xl) 2155 #define PBMP_XLB0_ALL(unit) SOC_PORT_BITMAP(unit,xlb0) 2156 #define PBMP_XT_ALL(unit) SOC_PORT_BITMAP(unit,xt) 2157 #define PBMP_XW_ALL(unit) SOC_PORT_BITMAP(unit,xw) 2158 #define PBMP_CD_ALL(unit) SOC_PORT_BITMAP(unit,cd) 2159 #define PBMP_CL_ALL(unit) SOC_PORT_BITMAP(unit,cl) 2160 #define PBMP_CLG2_ALL(unit) SOC_PORT_BITMAP(unit,clg2) 2161 #define PBMP_CXX_ALL(unit) SOC_PORT_BITMAP(unit,cxx) 2162 #define PBMP_CPRI_ALL(unit) SOC_PORT_BITMAP(unit,cpri) 2163 #define PBMP_RSVD4_ALL(unit) SOC_PORT_BITMAP(unit,rsvd4) 2164 #define PBMP_C_ALL(unit) SOC_PORT_BITMAP(unit,c) 2165 #define PBMP_LB_ALL(unit) SOC_PORT_BITMAP(unit,lbport) 2166 #define PBMP_RDB_ALL(unit) SOC_PORT_BITMAP(unit,rdbport) 2167 #define PBMP_FAE_ALL(unit) SOC_PORT_BITMAP(unit,faeport) 2168 #define PBMP_MACSEC_ALL(unit) SOC_PORT_BITMAP(unit,macsecport) 2169 #define PBMP_AXP_ALL(unit) SOC_PORT_BITMAP(unit,axp) 2170 #define PBMP_MXQ_ALL(unit) SOC_PORT_BITMAP(unit,mxq) 2171 #define PBMP_XG_ALL(unit) SOC_PORT_BITMAP(unit,xg) 2172 #define PBMP_XQ_ALL(unit) SOC_PORT_BITMAP(unit,xq) 2173 #define PBMP_HYPLITE_ALL(unit) SOC_PORT_BITMAP(unit,hyplite) 2174 #define PBMP_SPI_ALL(unit) SOC_PORT_BITMAP(unit,spi) 2175 #define PBMP_SPI_SUBPORT_ALL(unit) SOC_PORT_BITMAP(unit,spi_subport) 2176 #define PBMP_SCI_ALL(unit) SOC_PORT_BITMAP(unit,sci) 2177 #define PBMP_SFI_ALL(unit) SOC_PORT_BITMAP(unit,sfi) 2178 #define PBMP_REQ_ALL(unit) SOC_PORT_BITMAP(unit,req) 2179 #define PBMP_FAB_ALL(unit) SOC_PORT_BITMAP(unit,fab) 2180 #define PBMP_E_ALL(unit) SOC_PORT_BITMAP(unit,ether) 2181 #define PBMP_LP_ALL(unit) SOC_PORT_BITMAP(unit,lp) 2182 #define PBMP_SUBTAG_ALL(unit) SOC_PORT_BITMAP(unit,subtag) 2183 #define PBMP_TDM_ALL(unit) SOC_PORT_BITMAP(unit,tdm) 2184 #define PBMP_RCY_ALL(unit) SOC_PORT_BITMAP(unit,rcy) 2185 #define PBMP_QSGMII_ALL(unit) SOC_PORT_BITMAP(unit,qsgmii) 2186 #define PBMP_PORT_ALL(unit) SOC_PORT_BITMAP(unit,port) 2187 #define PBMP_INTP_ALL(unit) SOC_PORT_BITMAP(unit, intp) 2188 #define PBMP_LBG_ALL(unit) SOC_PORT_BITMAP(unit, lbgport) 2189 #define PBMP_CMIC(unit) SOC_INFO(unit).cmic_bitmap 2190 #define PBMP_LB(unit) SOC_INFO(unit).lb_pbm 2191 #define PBMP_MMU(unit) SOC_INFO(unit).mmu_pbm 2192 #define PBMP_EQ(unit) SOC_INFO(unit).eq_pbm 2193 #define PBMP_MANAGEMENT(unit) SOC_INFO(unit).management_pbm 2194 #define PBMP_OVERSUB(unit) SOC_INFO(unit).oversub_pbm 2195 #define PBMP_XPIPE(unit) SOC_INFO(unit).xpipe_pbm 2196 #define PBMP_YPIPE(unit) SOC_INFO(unit).ypipe_pbm 2197 #define PBMP_TDM(unit) SOC_INFO(unit).tdm_pbm 2198 #define PBMP_RCY(unit) SOC_INFO(unit).rcy_pbm 2199 #define PBMP_SPI(unit) SOC_INFO(unit).spi_bitmap 2200 #define PBMP_PP_ALL(unit) SOC_PORT_BITMAP(unit,pp) 2201 #define PBMP_ALL(unit) SOC_PORT_BITMAP(unit,all) 2202 #define PBMP_EXT_MEM(unit) SOC_INFO(unit).pbm_ext_mem 2203 #define PBMP_PIPE(unit,pipe) SOC_INFO(unit).pipe_pbm[pipe] 2204 2205 /* use PORT_MIN/_MAX to be more efficient than PBMP_ITER */ 2206 #define _SOC_PBMP_ITER(_u,_pt,_p) \ 2207 for ((_p) = SOC_PORT_MIN(_u,_pt); \ 2208 (_p) >= 0 && (_p) <= SOC_PORT_MAX(_u,_pt); \ 2209 (_p)++) \ 2210 if (_SHR_PBMP_MEMBER(SOC_PORT_BITMAP(_u,_pt), (_p))) 2211 #define PBMP_FE_ITER(_u, _p) _SOC_PBMP_ITER(_u,fe,_p) 2212 #define PBMP_GE_ITER(_u, _p) _SOC_PBMP_ITER(_u,ge,_p) 2213 #define PBMP_LLID_ITER(_u,_p) _SOC_PBMP_ITER(_u,llid,_p) 2214 #define PBMP_PON_ITER(_u,_p) _SOC_PBMP_ITER(_u,pon,_p) 2215 #define PBMP_XE_ITER(_u, _p) _SOC_PBMP_ITER(_u,xe,_p) 2216 #define PBMP_CE_ITER(_u, _p) _SOC_PBMP_ITER(_u,ce,_p) 2217 #define PBMP_HG_ITER(_u, _p) _SOC_PBMP_ITER(_u,hg,_p) 2218 #define PBMP_IL_ITER(_u, _p) _SOC_PBMP_ITER(_u,il,_p) 2219 #define PBMP_SCH_ITER(_u, _p) _SOC_PBMP_ITER(_u,sch,_p) 2220 #define PBMP_HG_SUBPORT_ITER(_u, _p) _SOC_PBMP_ITER(_u,hg_subport,_p) 2221 #define PBMP_HL_ITER(_u, _p) _SOC_PBMP_ITER(_u,hl,_p) 2222 #define PBMP_ST_ITER(_u, _p) _SOC_PBMP_ITER(_u,st,_p) 2223 #define PBMP_GX_ITER(_u, _p) _SOC_PBMP_ITER(_u,gx,_p) 2224 #define PBMP_XL_ITER(_u, _p) _SOC_PBMP_ITER(_u,xl,_p) 2225 #define PBMP_XLB0_ITER(_u, _p) _SOC_PBMP_ITER(_u,xlb0,_p) 2226 #define PBMP_XT_ITER(_u, _p) _SOC_PBMP_ITER(_u,xt,_p) 2227 #define PBMP_CL_ITER(_u, _p) _SOC_PBMP_ITER(_u,cl,_p) 2228 #define PBMP_CLG2_ITER(_u, _p) _SOC_PBMP_ITER(_u,clg2,_p) 2229 #define PBMP_C_ITER(_u, _p) _SOC_PBMP_ITER(_u,c,_p) 2230 #define PBMP_LB_ITER(_u, _p) _SOC_PBMP_ITER(_u,lbport,_p) 2231 #define PBMP_RDB_ITER(_u, _p) _SOC_PBMP_ITER(_u,rdbport,_p) 2232 #define PBMP_FAE_ITER(_u, _p) _SOC_PBMP_ITER(_u,faeport,_p) 2233 #define PBMP_MACSEC_ITER(_u, _p) _SOC_PBMP_ITER(_u,macsecport,_p) 2234 #define PBMP_AXP_ITER(_u, _p) _SOC_PBMP_ITER(_u,axp,_p) 2235 #define PBMP_MXQ_ITER(_u, _p) _SOC_PBMP_ITER(_u,mxq,_p) 2236 #define PBMP_XG_ITER(_u, _p) _SOC_PBMP_ITER(_u,xg,_p) 2237 #define PBMP_XQ_ITER(_u, _p) _SOC_PBMP_ITER(_u,xq,_p) 2238 #define PBMP_HYPLITE_ITER(_u, _p) _SOC_PBMP_ITER(_u,hyplite,_p) 2239 #define PBMP_SPI_ITER(_u, _p) _SOC_PBMP_ITER(_u,spi,_p) 2240 #define PBMP_SPI_SUBPORT_ITER(_u, _p) _SOC_PBMP_ITER(_u,spi_subport,_p) 2241 #define PBMP_SCI_ITER(_u, _p) _SOC_PBMP_ITER(_u,sci,_p) 2242 #define PBMP_SFI_ITER(_u, _p) _SOC_PBMP_ITER(_u,sfi,_p) 2243 #define PBMP_REQ_ITER(_u, _p) _SOC_PBMP_ITER(_u,req,_p) 2244 #define PBMP_E_ITER(_u, _p) _SOC_PBMP_ITER(_u,ether,_p) 2245 #define PBMP_LP_ITER(_u, _p) _SOC_PBMP_ITER(_u,lp,_p) 2246 #define PBMP_SUBTAG_ITER(_u, _p) _SOC_PBMP_ITER(_u,subtag,_p) 2247 #define PBMP_TDM_ITER(_u, _p) _SOC_PBMP_ITER(_u,tdm,_p) 2248 #define PBMP_PORT_ITER(_u, _p) _SOC_PBMP_ITER(_u,port,_p) 2249 #define PBMP_PP_ALL_ITER(_u, _p) _SOC_PBMP_ITER(_u,pp,_p) 2250 #define PBMP_ALL_ITER(_u, _p) _SOC_PBMP_ITER(_u,all,_p) 2251 #define PMBP_INTP_ITER(_u, _p) _SOC_PBMP_ITER(_u,intp,_p) 2252 #define PBMP_LBG_ITER(_u, _p) _SOC_PBMP_ITER(_u,lbgport,_p) 2253 2254 #define IS_OLP_PORT(unit, port) \ 2255 (port == OLP_PORT(unit)) 2256 #define IS_ERP_PORT(unit, port) \ 2257 (port == ERP_PORT(unit)) 2258 #define IS_RCPU_PORT(unit, port) \ 2259 (port == RCPU_PORT(unit)) 2260 #define IS_S_PORT(unit, port) \ 2261 (SOC_PBMP_MEMBER(SOC_INFO(unit).s_pbm, port)) 2262 #define IS_GMII_PORT(unit, port) \ 2263 (SOC_PBMP_MEMBER(SOC_INFO(unit).gmii_pbm, port)) 2264 #define IS_FE_PORT(unit,port) \ 2265 (SOC_PBMP_MEMBER(PBMP_FE_ALL(unit), port)) 2266 #define IS_GE_PORT(unit,port) \ 2267 (SOC_PBMP_MEMBER(PBMP_GE_ALL(unit), port)) 2268 #define IS_LLID_PORT(unit,port) \ 2269 (SOC_PBMP_MEMBER(PBMP_LLID_ALL(unit), port)) 2270 #define IS_PON_PORT(unit,port) \ 2271 (SOC_PBMP_MEMBER(PBMP_PON_ALL(unit), port)) 2272 #define IS_XE_PORT(unit,port) \ 2273 (SOC_PBMP_MEMBER(PBMP_XE_ALL(unit), port)) 2274 #define IS_CE_PORT(unit,port) \ 2275 (SOC_PBMP_MEMBER(PBMP_CE_ALL(unit), port)) 2276 #define IS_CDE_PORT(unit,port) \ 2277 (SOC_PBMP_MEMBER(PBMP_CDE_ALL(unit), port)) 2278 #define IS_HG_PORT(unit,port) \ 2279 (SOC_PBMP_MEMBER(PBMP_HG_ALL(unit), port)) 2280 #define IS_IL_PORT(unit,port) \ 2281 (SOC_PBMP_MEMBER(PBMP_IL_ALL(unit), port)) 2282 #define IS_SCH_PORT(unit,port) \ 2283 (SOC_PBMP_MEMBER(PBMP_SCH_ALL(unit), port)) 2284 #define IS_HG_SUBPORT_PORT(unit,port) \ 2285 (SOC_PBMP_MEMBER(PBMP_HG_SUBPORT_ALL(unit), port)) 2286 #define IS_HL_PORT(unit,port) \ 2287 (SOC_PBMP_MEMBER(PBMP_HL_ALL(unit), port)) 2288 #define IS_ST_PORT(unit,port) \ 2289 (SOC_PBMP_MEMBER(PBMP_ST_ALL(unit), port)) 2290 #define IS_GX_PORT(unit,port) \ 2291 (SOC_PBMP_MEMBER(PBMP_GX_ALL(unit), port)) 2292 #define IS_XL_PORT(unit,port) \ 2293 (SOC_PBMP_MEMBER(PBMP_XL_ALL(unit), port)) 2294 #define IS_XLB0_PORT(unit,port) \ 2295 (SOC_PBMP_MEMBER(PBMP_XLB0_ALL(unit), port)) 2296 #define IS_CL_PORT(unit,port) \ 2297 (SOC_PBMP_MEMBER(PBMP_CL_ALL(unit), port)) 2298 #define IS_CD_PORT(unit,port) \ 2299 (SOC_PBMP_MEMBER(PBMP_CD_ALL(unit), port)) 2300 #define IS_CLG2_PORT(unit,port) \ 2301 (SOC_PBMP_MEMBER(PBMP_CLG2_ALL(unit), port)) 2302 #define IS_CXX_PORT(unit,port) \ 2303 (SOC_PBMP_MEMBER(PBMP_CXX_ALL(unit), port)) 2304 #define IS_CPRI_PORT(unit,port) \ 2305 (SOC_PBMP_MEMBER(PBMP_CPRI_ALL(unit), port)) 2306 #define IS_RSVD4_PORT(unit,port) \ 2307 (SOC_PBMP_MEMBER(PBMP_RSVD4_ALL(unit), port)) 2308 #define IS_C_PORT(unit,port) \ 2309 (SOC_PBMP_MEMBER(PBMP_C_ALL(unit), port)) 2310 #define IS_AXP_PORT(unit,port) \ 2311 (SOC_PBMP_MEMBER(PBMP_AXP_ALL(unit), port)) 2312 #define IS_XT_PORT(unit,port) \ 2313 (SOC_PBMP_MEMBER(PBMP_XT_ALL(unit), port)) 2314 #define IS_XW_PORT(unit,port) \ 2315 (SOC_PBMP_MEMBER(PBMP_XW_ALL(unit), port)) 2316 #define IS_MXQ_PORT(unit,port) \ 2317 (SOC_PBMP_MEMBER(PBMP_MXQ_ALL(unit), port)) 2318 #define IS_XG_PORT(unit,port) \ 2319 (SOC_PBMP_MEMBER(PBMP_XG_ALL(unit), port)) 2320 #define IS_XQ_PORT(unit,port) \ 2321 (SOC_PBMP_MEMBER(PBMP_XQ_ALL(unit), port)) 2322 #define IS_HYPLITE_PORT(unit,port) \ 2323 (SOC_PBMP_MEMBER(PBMP_HYPLITE_ALL(unit), port)) 2324 #define IS_SPI_PORT(unit,port) \ 2325 (SOC_PBMP_MEMBER(PBMP_SPI_ALL(unit), port)) 2326 #define IS_SPI_SUBPORT_PORT(unit,port) \ 2327 (SOC_PBMP_MEMBER(PBMP_SPI_SUBPORT_ALL(unit), port)) 2328 #define IS_SCI_PORT(unit,port) \ 2329 (SOC_PBMP_MEMBER(PBMP_SCI_ALL(unit), port)) 2330 #define IS_SFI_PORT(unit,port) \ 2331 (SOC_PBMP_MEMBER(PBMP_SFI_ALL(unit), port)) 2332 #define IS_REQ_PORT(unit,port) \ 2333 (SOC_PBMP_MEMBER(PBMP_REQ_ALL(unit), port)) 2334 #define IS_E_PORT(unit,port) \ 2335 (SOC_PBMP_MEMBER(PBMP_E_ALL(unit), port)) 2336 #define IS_LP_PORT(unit,port) \ 2337 (SOC_PBMP_MEMBER(PBMP_LP_ALL(unit), port)) 2338 #define IS_SUBTAG_PORT(unit, port) \ 2339 (SOC_PBMP_MEMBER(PBMP_SUBTAG_ALL(unit), port)) 2340 #define IS_RCY_PORT(unit,port) \ 2341 (SOC_PBMP_MEMBER(PBMP_RCY_ALL(unit), port)) 2342 #define IS_TDM_PORT(unit,port) \ 2343 (SOC_PBMP_MEMBER(PBMP_TDM_ALL(unit), port)) 2344 #define IS_PORT(unit,port) \ 2345 (SOC_BLOCK_IN_LIST(&(SOC_PORT_TYPE(unit, port)), SOC_BLK_NET)) 2346 #define IS_LB_PORT(unit,port) \ 2347 (SOC_PBMP_MEMBER(PBMP_LB(unit), port)) 2348 #define IS_MANAGEMENT_PORT(unit,port) \ 2349 (SOC_PBMP_MEMBER(PBMP_MANAGEMENT(unit), port)) 2350 #define IS_RDB_PORT(unit,port) \ 2351 (SOC_PBMP_MEMBER(PBMP_RDB_ALL(unit), port)) 2352 #define IS_FAE_PORT(unit,port) \ 2353 (SOC_PBMP_MEMBER(PBMP_FAE_ALL(unit), port)) 2354 #define IS_MACSEC_PORT(unit,port) \ 2355 (SOC_PBMP_MEMBER(PBMP_MACSEC_ALL(unit), port)) 2356 #define IS_MMU_PORT(unit,port) \ 2357 (SOC_PBMP_MEMBER(PBMP_MMU(unit), port)) 2358 #define IS_EXT_MEM_PORT(unit,port) \ 2359 (SOC_PBMP_MEMBER(PBMP_EXT_MEM(unit), port)) 2360 #define IS_CPU_PORT(unit,port) \ 2361 (SOC_BLOCK_IN_LIST(&(SOC_PORT_TYPE(unit, port)), SOC_BLK_CPU)) 2362 #define IS_MANAGEMENT_PORT(unit,port) \ 2363 (SOC_PBMP_MEMBER(PBMP_MANAGEMENT(unit), port)) 2364 #define IS_SPI_BLK(unit,port) \ 2365 (SOC_PORT_TYPE(unit, port) == SOC_BLK_SPI) 2366 #define IS_EXP_PORT(unit,port) \ 2367 (SOC_PORT_TYPE(unit, port) == SOC_BLK_EXP) 2368 #define IS_ALL_PORT(unit,port) \ 2369 (SOC_PORT_TYPE(unit, port) != 0) 2370 #define IS_INTP_PORT(unit, port) \ 2371 (SOC_PBMP_MEMBER(PBMP_INTP_ALL(unit), port)) 2372 #define IS_QSGMII_PORT(unit,port) \ 2373 (SOC_PBMP_MEMBER(PBMP_QSGMII_ALL(unit), port)) 2374 #define IS_LBG_PORT(unit,port) \ 2375 (SOC_PBMP_MEMBER(PBMP_LBG_ALL(unit), port)) 2376 /* Stack related macros */ 2377 2378 #define SOC_PBMP_STACK_CURRENT(unit) \ 2379 (SOC_PERSIST(unit)->stack_ports_current) 2380 #define SOC_PBMP_STACK_INACTIVE(unit) \ 2381 (SOC_PERSIST(unit)->stack_ports_inactive) 2382 #define SOC_PBMP_STACK_PREVIOUS(unit) \ 2383 (SOC_PERSIST(unit)->stack_ports_previous) 2384 2385 #define SOC_PBMP_STACK_ACTIVE_GET(unit, active) do { \ 2386 SOC_PBMP_ASSIGN(active, SOC_PBMP_STACK_CURRENT(unit)); \ 2387 SOC_PBMP_REMOVE(active, SOC_PBMP_STACK_INACTIVE(unit)); \ 2388 } while (0) 2389 2390 #define SOC_IS_STACK_PORT(unit, port) \ 2391 SOC_PBMP_MEMBER(SOC_PBMP_STACK_CURRENT(unit), port) 2392 2393 #define SOC_IS_INACTIVE_STACK_PORT(unit, port) \ 2394 SOC_PBMP_MEMBER(SOC_PBMP_STACK_INACTIVE(unit), port) 2395 2396 /* SL Mode set/get macros */ 2397 #define SOC_SL_MODE(unit) \ 2398 ((SOC_CONTROL(unit)->soc_flags & SOC_F_SL_MODE) != 0) 2399 2400 #define SOC_SL_MODE_SET(unit, sl_mode) \ 2401 if (sl_mode) SOC_CONTROL(unit)->soc_flags |= SOC_F_SL_MODE; \ 2402 else SOC_CONTROL(unit)->soc_flags &= ~SOC_F_SL_MODE 2403 2404 /* KNET Mode set/get macros */ 2405 #define SOC_KNET_MODE(unit) \ 2406 ((SOC_CONTROL(unit)->soc_flags & SOC_F_KNET_MODE) != 0) 2407 2408 #define SOC_KNET_MODE_SET(unit, knet_mode) \ 2409 if (knet_mode) SOC_CONTROL(unit)->soc_flags |= SOC_F_KNET_MODE; \ 2410 else SOC_CONTROL(unit)->soc_flags &= ~SOC_F_KNET_MODE 2411 2412 /* URPF on/off set/get macros */ 2413 #define SOC_URPF_STATUS_GET(unit) \ 2414 ((SOC_CONTROL(unit)->soc_flags & SOC_F_URPF_ENABLED) != 0) 2415 2416 #define SOC_URPF_STATUS_SET(unit, status) \ 2417 if (status) SOC_CONTROL(unit)->soc_flags |= SOC_F_URPF_ENABLED; \ 2418 else SOC_CONTROL(unit)->soc_flags &= ~SOC_F_URPF_ENABLED 2419 2420 #define SOC_L3_DEFIP_INDEX_REMAP_GET(unit) \ 2421 SOC_CONTROL(unit)->l3_defip_index_remap 2422 2423 #define SOC_L3_DEFIP_MAX_TCAMS_GET(unit) \ 2424 SOC_CONTROL(unit)->l3_defip_max_tcams 2425 2426 #define SOC_L3_DEFIP_TCAM_DEPTH_GET(unit) \ 2427 SOC_CONTROL(unit)->l3_defip_tcam_size 2428 2429 #define SOC_L3_DEFIP_LOG_TO_PHY_ARRAY(unit) \ 2430 SOC_CONTROL(unit)->defip_index_table->defip_tcam_phy_index 2431 2432 #define SOC_L3_DEFIP_PHY_TO_LOG_ARRAY(unit) \ 2433 SOC_CONTROL(unit)->defip_index_table->defip_tcam_log_index 2434 2435 #define SOC_L3_DEFIP_URPF_LOG_TO_PHY_ARRAY(unit) \ 2436 SOC_CONTROL(unit)->defip_index_table->defip_tcam_urpf_phy_index 2437 2438 #define SOC_L3_DEFIP_URPF_PHY_TO_LOG_ARRAY(unit) \ 2439 SOC_CONTROL(unit)->defip_index_table->defip_tcam_urpf_log_index 2440 2441 #define SOC_L3_DEFIP_LOG_TO_PHY_INDEX(unit, index) \ 2442 SOC_CONTROL(unit)->defip_index_table->defip_tcam_phy_index[index] 2443 2444 #define SOC_L3_DEFIP_PHY_TO_LOG_INDEX(unit, index) \ 2445 SOC_CONTROL(unit)->defip_index_table->defip_tcam_log_index[index] 2446 2447 #define SOC_L3_DEFIP_URPF_LOG_TO_PHY_INDEX(unit, index) \ 2448 SOC_CONTROL(unit)->defip_index_table->defip_tcam_urpf_phy_index[index] 2449 2450 #define SOC_L3_DEFIP_URPF_PHY_TO_LOG_INDEX(unit, index) \ 2451 SOC_CONTROL(unit)->defip_index_table->defip_tcam_urpf_log_index[index] 2452 2453 #define SOC_L3_DEFIP_PAIR_LOG_TO_PHY_ARRAY(unit) \ 2454 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_phy_index 2455 2456 #define SOC_L3_DEFIP_PAIR_PHY_TO_LOG_ARRAY(unit) \ 2457 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_log_index 2458 2459 #define SOC_L3_DEFIP_PAIR_URPF_LOG_TO_PHY_ARRAY(unit) \ 2460 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_urpf_phy_index 2461 2462 #define SOC_L3_DEFIP_PAIR_URPF_PHY_TO_LOG_ARRAY(unit) \ 2463 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_urpf_log_index 2464 2465 #define SOC_L3_DEFIP_PAIR_LOG_TO_PHY_INDEX(unit, index) \ 2466 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_phy_index[index] 2467 2468 #define SOC_L3_DEFIP_PAIR_PHY_TO_LOG_INDEX(unit, index) \ 2469 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_log_index[index] 2470 2471 #define SOC_L3_DEFIP_PAIR_URPF_LOG_TO_PHY_INDEX(unit, index) \ 2472 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_urpf_phy_index[index] 2473 2474 #define SOC_L3_DEFIP_PAIR_URPF_PHY_TO_LOG_INDEX(unit, index) \ 2475 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_urpf_log_index[index] 2476 2477 #define SOC_L3_DEFIP_ALPM_URPF_LOG_TO_PHY_ARRAY(unit) \ 2478 SOC_CONTROL(unit)->defip_index_table->defip_tcam_alpm_urpf_phy_index 2479 2480 #define SOC_L3_DEFIP_ALPM_URPF_PHY_TO_LOG_ARRAY(unit) \ 2481 SOC_CONTROL(unit)->defip_index_table->defip_tcam_alpm_urpf_log_index 2482 #define SOC_L3_DEFIP_ALPM_URPF_LOG_TO_PHY_INDEX(unit, index) \ 2483 SOC_CONTROL(unit)->defip_index_table->defip_tcam_alpm_urpf_phy_index[index] 2484 2485 #define SOC_L3_DEFIP_ALPM_URPF_PHY_TO_LOG_INDEX(unit, index) \ 2486 SOC_CONTROL(unit)->defip_index_table->defip_tcam_alpm_urpf_log_index[index] 2487 2488 #define SOC_L3_DEFIP_PAIR_ALPM_URPF_LOG_TO_PHY_ARRAY(unit) \ 2489 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_alpm_urpf_phy_index 2490 2491 #define SOC_L3_DEFIP_PAIR_ALPM_URPF_PHY_TO_LOG_ARRAY(unit) \ 2492 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_alpm_urpf_log_index 2493 2494 #define SOC_L3_DEFIP_PAIR_ALPM_URPF_LOG_TO_PHY_INDEX(unit, index) \ 2495 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_alpm_urpf_phy_index[index] 2496 2497 #define SOC_L3_DEFIP_PAIR_ALPM_URPF_PHY_TO_LOG_INDEX(unit, index) \ 2498 SOC_CONTROL(unit)->defip_index_table->defip_pair_tcam_alpm_urpf_log_index[index] 2499 2500 #define SOC_L3_DEFIP_INDEX_INIT(unit) \ 2501 SOC_CONTROL(unit)->defip_index_table 2502 2503 #define SOC_L3_DEFIP_MAX_128B_ENTRIES(unit) \ 2504 SOC_CONTROL(unit)->l3_defip_max_128b_entries 2505 2506 #define SOC_L3_DEFIP_SCACHE_HANDLE(unit) \ 2507 SOC_CONTROL(unit)->l3_defip_scache_ptr 2508 2509 #define SOC_FP_TCAM_SCACHE_HANDLE(unit) \ 2510 SOC_CONTROL(unit)->fp_tcam_scache_ptr 2511 2512 #define SOC_ALPM_128B_ENABLE(unit) \ 2513 (SOC_L3_DEFIP_MAX_128B_ENTRIES(unit) > 0 ? 1 : 0) 2514 2515 /* URPF on/off set/get macros */ 2516 #define SOC_L2X_GROUP_ENABLE_GET(_unit_) (SOC_CONTROL(_unit_)->l2x_group_enable) 2517 #define SOC_L2X_GROUP_ENABLE_SET(_unit_, _status_) \ 2518 (SOC_CONTROL(_unit_)->l2x_group_enable) = (_status_) ? TRUE : FALSE 2519 2520 2521 /* Device should use memory dma for memory clear ops */ 2522 #define SOC_MEM_CLEAR_USE_DMA(unit) \ 2523 ((SOC_CONTROL(unit)->soc_flags & SOC_F_MEM_CLEAR_USE_DMA) != 0) 2524 2525 #define SOC_MEM_CLEAR_USE_DMA_SET(unit, status) \ 2526 if (status) SOC_CONTROL(unit)->soc_flags |= SOC_F_MEM_CLEAR_USE_DMA; \ 2527 else SOC_CONTROL(unit)->soc_flags &= ~SOC_F_MEM_CLEAR_USE_DMA 2528 2529 /* Device should use hw pipe clear for memory clear ops */ 2530 #define SOC_MEM_CLEAR_HW_ACC(unit) \ 2531 ((SOC_CONTROL(unit)->soc_flags & SOC_F_MEM_CLEAR_HW_ACC) != 0) 2532 2533 #define SOC_MEM_CLEAR_HW_ACC_SET(unit, status) \ 2534 if (status) SOC_CONTROL(unit)->soc_flags |= SOC_F_MEM_CLEAR_HW_ACC; \ 2535 else SOC_CONTROL(unit)->soc_flags &= ~SOC_F_MEM_CLEAR_HW_ACC 2536 2537 /* Device should not use mem cache in mem test mode */ 2538 #define SOC_MEM_TEST_SKIP_CACHE(unit) \ 2539 (SOC_CONTROL(unit)->skip_cache_use) 2540 2541 #define SOC_MEM_TEST_SKIP_CACHE_SET(unit, enable) \ 2542 (SOC_CONTROL(unit)->skip_cache_use = enable) 2543 2544 #define SOC_MEM_FORCE_READ_THROUGH(unit) \ 2545 (SOC_CONTROL(unit)->force_read_through) 2546 2547 #define SOC_MEM_FORCE_READ_THROUGH_SET(unit, enable) \ 2548 (SOC_CONTROL(unit)->force_read_through = enable) 2549 2550 #define SOC_MEM_CACHE_COHERENCY_CHECK(unit) \ 2551 (SOC_CONTROL(unit)->cache_coherency_chk) 2552 2553 #define SOC_MEM_CACHE_COHERENCY_CHECK_SET(unit, enable) \ 2554 (SOC_CONTROL(unit)->cache_coherency_chk = enable) 2555 2556 #define SOC_SER_SUPPORT(unit) \ 2557 (SOC_CONTROL(unit)->parity_enable) 2558 2559 #define SOC_SER_CORRECTION_SUPPORT(unit) \ 2560 (SOC_CONTROL(unit)->parity_correction) 2561 2562 #define SOC_SER_COUNTER_CORRECTION(unit) \ 2563 (SOC_CONTROL(unit)->parity_counter_clear) 2564 2565 #define SOC_REG_RETURN_SER_ERROR(unit) \ 2566 (SOC_CONTROL(unit)->return_reg_error) 2567 2568 #define SOC_REG_RETURN_SER_ERROR_SET(unit, enable) \ 2569 (SOC_CONTROL(unit)->return_reg_error = enable) 2570 2571 /* Device should use gport for source/destination notation */ 2572 #define SOC_USE_GPORT(unit) \ 2573 ((SOC_CONTROL(unit)->soc_flags & SOC_F_GPORT) != 0) 2574 2575 #define SOC_USE_GPORT_SET(unit, status) \ 2576 if (status) SOC_CONTROL(unit)->soc_flags |= SOC_F_GPORT; \ 2577 else SOC_CONTROL(unit)->soc_flags &= ~SOC_F_GPORT 2578 2579 /* Maximum vrf id for the device set/get macro */ 2580 #define SOC_VRF_MAX(unit) SOC_CONTROL(unit)->max_vrf_id 2581 #define SOC_VRF_MAX_SET(unit, value) \ 2582 SOC_CONTROL(unit)->max_vrf_id = value 2583 2584 /* Maximum address class for the device set/get macro */ 2585 #define SOC_ADDR_CLASS_MAX(unit) SOC_CONTROL(unit)->max_address_class 2586 #define SOC_ADDR_CLASS_MAX_SET(unit, value) \ 2587 SOC_CONTROL(unit)->max_address_class = value 2588 2589 /* Maximum overlaid address class for the device set/get macro */ 2590 #define SOC_OVERLAID_ADDR_CLASS_MAX(unit) \ 2591 SOC_CONTROL(unit)->max_overlaid_address_class 2592 #define SOC_OVERLAID_ADDR_CLASS_MAX_SET(unit, value) \ 2593 SOC_CONTROL(unit)->max_overlaid_address_class = value 2594 2595 /* Maximum extended address class for the device set/get macro */ 2596 #define SOC_EXT_ADDR_CLASS_MAX(unit) \ 2597 SOC_CONTROL(unit)->max_extended_address_class 2598 #define SOC_EXT_ADDR_CLASS_MAX_SET(unit, value) \ 2599 SOC_CONTROL(unit)->max_extended_address_class = value 2600 2601 /* Maximum interface class for the device set/get macro */ 2602 #define SOC_INTF_CLASS_MAX(unit) SOC_CONTROL(unit)->max_interface_class 2603 #define SOC_INTF_CLASS_MAX_SET(unit, value) \ 2604 SOC_CONTROL(unit)->max_interface_class = value 2605 2606 2607 /* Device memory clear chunk size set/get macros */ 2608 #define SOC_MEM_CLEAR_CHUNK_SIZE_GET(unit) SOC_CONTROL(unit)->mem_clear_chunk_size 2609 #define SOC_MEM_CLEAR_CHUNK_SIZE_SET(unit, value) \ 2610 SOC_CONTROL(unit)->mem_clear_chunk_size = value 2611 2612 /* IPMC replication sharing set/get macros */ 2613 #define SOC_IPMCREPLSHR_GET(unit) \ 2614 ((SOC_CONTROL(unit)->soc_flags & SOC_F_IPMCREPLSHR) != 0) 2615 2616 #define SOC_IPMCREPLSHR_SET(unit, status) \ 2617 if (status) SOC_CONTROL(unit)->soc_flags |= SOC_F_IPMCREPLSHR; \ 2618 else SOC_CONTROL(unit)->soc_flags &= ~SOC_F_IPMCREPLSHR 2619 2620 /* Device should use gport for source/destination notation */ 2621 #define SOC_REMOTE_ENCAP(unit) \ 2622 ((SOC_CONTROL(unit)->soc_flags & SOC_F_REMOTE_ENCAP) != 0) 2623 2624 #define SOC_REMOTE_ENCAP_SET(unit, status) \ 2625 if (status) SOC_CONTROL(unit)->soc_flags |= SOC_F_REMOTE_ENCAP; \ 2626 else SOC_CONTROL(unit)->soc_flags &= ~SOC_F_REMOTE_ENCAP 2627 2628 /* Dual hash global maximum recursion level */ 2629 #define SOC_DUAL_HASH_MOVE_MAX(unit) \ 2630 SOC_CONTROL(unit)->dual_hash_recurse_depth 2631 /* L2X dual hash tables specific recursion level */ 2632 #define SOC_DUAL_HASH_MOVE_MAX_L2X(unit) \ 2633 SOC_CONTROL(unit)->dual_hash_recurse_depth_l2x 2634 /* MPLS dual hash tables specific recursion level */ 2635 #define SOC_DUAL_HASH_MOVE_MAX_MPLS(unit) \ 2636 SOC_CONTROL(unit)->dual_hash_recurse_depth_mpls 2637 /* VLAN dual hash tables specific recursion level */ 2638 #define SOC_DUAL_HASH_MOVE_MAX_VLAN(unit) \ 2639 SOC_CONTROL(unit)->dual_hash_recurse_depth_vlan 2640 /* EGRESS VLAN dual hash tables specific recursion level */ 2641 #define SOC_DUAL_HASH_MOVE_MAX_EGRESS_VLAN(unit) \ 2642 SOC_CONTROL(unit)->dual_hash_recurse_depth_egress_vlan 2643 #if defined(INCLUDE_L3) 2644 /* L3X dual hash tables specific recursion level */ 2645 #define SOC_DUAL_HASH_MOVE_MAX_L3X(unit) \ 2646 SOC_CONTROL(unit)->dual_hash_recurse_depth_l3x 2647 #endif 2648 #if defined(BCM_TRIUMPH3_SUPPORT) 2649 /* L3X dual hash tables specific recursion level */ 2650 #define SOC_DUAL_HASH_MOVE_MAX_WLAN_PORT(unit) \ 2651 SOC_CONTROL(unit)->dual_hash_recurse_depth_wlan_port 2652 #define SOC_DUAL_HASH_MOVE_MAX_WLAN_CLIENT(unit) \ 2653 SOC_CONTROL(unit)->dual_hash_recurse_depth_wlan_client 2654 /* FT_SESSION*m dual hash tables specific recursion level */ 2655 #define SOC_DUAL_HASH_MAX_FT_SESSION_IPV4(unit) \ 2656 SOC_CONTROL(unit)->dual_hash_recurse_depth_ft_session_ipv4 2657 #define SOC_DUAL_HASH_MAX_FT_SESSION_IPV6(unit) \ 2658 SOC_CONTROL(unit)->dual_hash_recurse_depth_ft_session_ipv6 2659 #endif 2660 /* ING_VP_VLAN_MEMBERSHIP dual hash tables specific recursion level */ 2661 #define SOC_DUAL_HASH_MOVE_MAX_ING_VP_VLAN_MEMBER(unit) \ 2662 SOC_CONTROL(unit)->dual_hash_recurse_depth_ing_vp_vlan_member 2663 /* EGR_VP_VLAN_MEMBERSHIP dual hash tables specific recursion level */ 2664 #define SOC_DUAL_HASH_MOVE_MAX_EGR_VP_VLAN_MEMBER(unit) \ 2665 SOC_CONTROL(unit)->dual_hash_recurse_depth_egr_vp_vlan_member 2666 /* ING_DNAT_ADDRESS_TYPE dual hash tables specific recursion level */ 2667 #define SOC_DUAL_HASH_MOVE_MAX_ING_DNAT_ADDRESS_TYPE(unit) \ 2668 SOC_CONTROL(unit)->dual_hash_recurse_depth_ing_dnat_address_type 2669 /* L2_ENDPOINT_ID dual hash tables specific recursion level */ 2670 #define SOC_DUAL_HASH_MOVE_MAX_L2_ENDPOINT_ID(unit) \ 2671 SOC_CONTROL(unit)->dual_hash_recurse_depth_l2_endpoint_id 2672 /* ENDPOINT_QUEUE_MAP dual hash tables specific recursion level */ 2673 #define SOC_DUAL_HASH_MOVE_MAX_ENDPOINT_QUEUE_MAP(unit) \ 2674 SOC_CONTROL(unit)->dual_hash_recurse_depth_endpoint_queue_map 2675 /* Multi hash global maximum recursion level */ 2676 #define SOC_MULTI_HASH_MOVE_MAX(unit) \ 2677 SOC_CONTROL(unit)->multi_hash_recurse_depth 2678 /* L2 multi hash tables specific recursion level */ 2679 #define SOC_MULTI_HASH_MOVE_MAX_L2(unit) \ 2680 SOC_CONTROL(unit)->multi_hash_recurse_depth_l2 2681 /* L3 multi hash tables specific recursion level */ 2682 #define SOC_MULTI_HASH_MOVE_MAX_L3(unit) \ 2683 SOC_CONTROL(unit)->multi_hash_recurse_depth_l3 2684 #define SOC_MULTI_HASH_MOVE_MAX_FPEM(unit) \ 2685 SOC_CONTROL(unit)->multi_hash_recurse_depth_fpem 2686 /* MPLS multi hash tables specific recursion level */ 2687 #define SOC_MULTI_HASH_MOVE_MAX_MPLS(unit) \ 2688 SOC_CONTROL(unit)->multi_hash_recurse_depth_mpls 2689 /* VLAN multi hash tables specific recursion level */ 2690 #define SOC_MULTI_HASH_MOVE_MAX_VLAN(unit) \ 2691 SOC_CONTROL(unit)->multi_hash_recurse_depth_vlan 2692 /* VLAN XLATE1 multi hash tables specific recursion level */ 2693 #define SOC_MULTI_HASH_MOVE_MAX_VLAN_1(unit) \ 2694 SOC_CONTROL(unit)->multi_hash_recurse_depth_vlan_1 2695 /* VLAN XLATE2 multi hash tables specific recursion level */ 2696 #define SOC_MULTI_HASH_MOVE_MAX_VLAN_2(unit) \ 2697 SOC_CONTROL(unit)->multi_hash_recurse_depth_vlan_2 2698 /* EGRESS VLAN multi hash tables specific recursion level */ 2699 #define SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN(unit) \ 2700 SOC_CONTROL(unit)->multi_hash_recurse_depth_egress_vlan 2701 /* EGRESS VLAN XLATE1 multi hash tables specific recursion level */ 2702 #define SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN_1(unit) \ 2703 SOC_CONTROL(unit)->multi_hash_recurse_depth_egress_vlan_1 2704 /* EGRESS VLAN XLATE2 multi hash tables specific recursion level */ 2705 #define SOC_MULTI_HASH_MOVE_MAX_EGRESS_VLAN_2(unit) \ 2706 SOC_CONTROL(unit)->multi_hash_recurse_depth_egress_vlan_2 2707 /* L3 Tunnel multi hash tables specific recursion level */ 2708 #define SOC_MULTI_HASH_MOVE_MAX_L3_TUNNEL(unit) \ 2709 SOC_CONTROL(unit)->multi_hash_recurse_depth_l3_tunnel 2710 2711 /* Multi hash tables specific moving recursion algorithm */ 2712 #define SOC_MULTI_HASH_MOVE_ALGORITHM(unit) \ 2713 SOC_CONTROL(unit)->multi_hash_move_algorithm 2714 2715 #define SOC_MCAST_ADD_ALL_ROUTER_PORTS(unit) \ 2716 SOC_CONTROL(unit)->mcast_add_all_router_ports 2717 2718 #ifdef BCM_CB_ABORT_ON_ERR 2719 #define SOC_CB_ABORT_ON_ERR(unit) \ 2720 SOC_CONTROL(unit)->cb_abort_on_err 2721 #endif 2722 2723 /* Switching logic bypass mode */ 2724 #define SOC_SWITCH_BYPASS_MODE_NONE 0 2725 #define SOC_SWITCH_BYPASS_MODE_L3_ONLY 1 2726 #define SOC_SWITCH_BYPASS_MODE_L3_AND_FP 2 2727 #ifdef BCM_TOMAHAWK_SUPPORT 2728 /* modes redefined for TH SKUs, values reused */ 2729 #define SOC_SWITCH_BYPASS_MODE_BALANCED 1 2730 #define SOC_SWITCH_BYPASS_MODE_LOW 2 2731 #define SOC_SWITCH_BYPASS_MODE_EFP 3 2732 #endif 2733 2734 #define SOC_SWITCH_BYPASS_MODE(unit) \ 2735 SOC_CONTROL(unit)->switch_bypass_mode 2736 2737 /* Double tag mode when it is a device-wide property */ 2738 #define SOC_DT_MODE(unit) \ 2739 SOC_CONTROL(unit)->dt_mode 2740 2741 #define SOC_MAC_LOW_POWER_ENABLED(unit) \ 2742 SOC_CONTROL(unit)->mac_low_power_enabled 2743 2744 #define SOC_AUTO_MAC_LOW_POWER(unit) \ 2745 SOC_CONTROL(unit)->auto_mac_low_power 2746 2747 #define MAC_LOW_POWER_LOCK(unit) \ 2748 sal_mutex_take(SOC_CONTROL(unit)->mac_low_power_mutex, sal_mutex_FOREVER) 2749 #define MAC_LOW_POWER_UNLOCK(unit) \ 2750 sal_mutex_give(SOC_CONTROL(unit)->mac_low_power_mutex) 2751 2752 2753 #define INT_MCU_LOCK(unit) 2754 #define INT_MCU_UNLOCK(unit) 2755 2756 2757 /* 2758 * LMD enabled ports. 2.5 Gbps stacking support 2759 */ 2760 #define SOC_LMD_PBM(unit) SOC_INFO(unit).lmd_pbm 2761 #define SOC_LMD_ENABLED_PORT_SET(unit, port) \ 2762 SOC_PBMP_PORT_SET(SOC_INFO(unit).lmd_pbm, port) 2763 #define IS_LMD_ENABLED_PORT(unit, port) \ 2764 SOC_PBMP_MEMBER(SOC_INFO(unit).lmd_pbm, port) 2765 2766 /* 2767 * Ports using HiGig2 encapsulation. 2768 * This is a cached value used for bcm_tx performance reasons. 2769 */ 2770 #define SOC_HG2_PBM(unit) SOC_INFO(unit).hg2_pbm 2771 #define SOC_HG2_ENABLED_PORT_ADD(unit, port) \ 2772 SOC_PBMP_PORT_ADD(SOC_INFO(unit).hg2_pbm, port) 2773 #define SOC_HG2_ENABLED_PORT_REMOVE(unit, port) \ 2774 SOC_PBMP_PORT_REMOVE(SOC_INFO(unit).hg2_pbm, port) 2775 #define IS_HG2_ENABLED_PORT(unit, port) \ 2776 SOC_PBMP_MEMBER(SOC_INFO(unit).hg2_pbm, port) 2777 2778 extern int SOC_BLOCK_IS_TYPE(int unit, int blk_idx, int *list); 2779 /* iterate over enabled blocks of type */ 2780 #define SOC_BLOCKS_ITER(unit, var, list) \ 2781 for ((var) = 0; SOC_BLOCK_INFO(unit, var).type >= 0; (var)++) \ 2782 if (SOC_INFO(unit).block_valid[var] && \ 2783 SOC_BLOCK_IS_TYPE(unit, var, list)) 2784 2785 #define SOC_BLOCK_IS_CMP(unit, blk, val)\ 2786 (SOC_BLOCK_TYPE(unit, blk) == val) 2787 extern int SOC_BLOCK_IS_COMPOSITE(int unit, int blk_idx, int type); 2788 /* iterate over enabled block of type(specific or composite) */ 2789 #define SOC_BLOCK_ITER(unit, var, val) \ 2790 for ((var) = 0; SOC_BLOCK_INFO(unit, var).type >= 0; (var)++) \ 2791 if (SOC_INFO(unit).block_valid[var] && \ 2792 (SOC_BLOCK_IS_CMP(unit, var, val) || \ 2793 SOC_BLOCK_IS_COMPOSITE(unit, var, val))) 2794 2795 #define SOC_BLOCK_ITER_ALL(unit, var, val) \ 2796 for ((var) = 0; SOC_BLOCK_INFO(unit, var).type >= 0; (var)++) \ 2797 if (SOC_BLOCK_IS_CMP(unit, var, val) || \ 2798 SOC_BLOCK_IS_COMPOSITE(unit, var, val)) 2799 2800 #define SOC_MEM_BLOCK_MIN(unit, mem) SOC_MEM_INFO(unit, mem).minblock 2801 #define SOC_MEM_BLOCK_MAX(unit, mem) (soc_mem_is_unified(unit, mem) ? \ 2802 SOC_MEM_INFO(unit, mem).minblock : \ 2803 SOC_MEM_INFO(unit, mem).maxblock) 2804 #define SOC_MEM_BLOCK_ANY(unit, mem) (SOC_INFO(unit).mem_block_any[mem]) 2805 2806 2807 #define SOC_MEM_BLOCK_VALID(unit, mem, blk) \ 2808 ((blk) >= 0 && \ 2809 (blk) < SOC_MAX_NUM_BLKS && \ 2810 (SOC_MAX_NUM_BLKS >= 64 || (((blk)>=32)?(SOC_MEM_INFO(unit, mem).blocks_hi & (1<<((blk)&0x1F))):(SOC_MEM_INFO(unit, mem).blocks & (1<<(blk)))))&& \ 2811 (SOC_INFO(unit).block_valid[blk])) 2812 2813 2814 2815 #define SOC_MEM_BLOCK_ITER(unit, mem, var) \ 2816 for ((var) = SOC_MEM_BLOCK_MIN(unit, mem); \ 2817 (var) <= SOC_MEM_BLOCK_MAX(unit, mem); \ 2818 (var)++) \ 2819 if ((SOC_MAX_NUM_BLKS >= 64 || (((var)>=32)?(SOC_MEM_INFO(unit, mem).blocks_hi & (1 << ((var)&0x1F))):(SOC_MEM_INFO(unit, mem).blocks & (1 << (var))))) && \ 2820 SOC_INFO(unit).block_valid[var]) 2821 2822 /* For Memory BLK > 64, bitmaps blocks_hi and blocks are not applicable */ 2823 2824 #define SOC_MEM_BLOCK_ITER2(unit, mem, var) \ 2825 for ((var) = SOC_MEM_BLOCK_MIN(unit, mem); \ 2826 (var) <= SOC_MEM_BLOCK_MAX(unit, mem); \ 2827 (var)++) \ 2828 if ((((var) >= 64) || (((var)>=32)?(SOC_MEM_INFO(unit, mem).blocks_hi & (1 << ((var)&0x1F))):(SOC_MEM_INFO(unit, mem).blocks & (1 << (var))))) && \ 2829 SOC_INFO(unit).block_valid[var]) 2830 2831 2832 /* Default dcb/dma values */ 2833 #define SOC_DEFAULT_DMA_SRCMOD_GET(_u) SOC_PERSIST(_u)->dcb_srcmod 2834 #define SOC_DEFAULT_DMA_SRCPORT_GET(_u) SOC_PERSIST(_u)->dcb_srcport 2835 #define SOC_DEFAULT_DMA_PFM_GET(_u) SOC_PERSIST(_u)->dcb_pfm 2836 #define SOC_DEFAULT_DMA_SRCMOD_SET(_u, _v) SOC_PERSIST(_u)->dcb_srcmod = (_v) 2837 #define SOC_DEFAULT_DMA_SRCPORT_SET(_u, _v) SOC_PERSIST(_u)->dcb_srcport = (_v) 2838 #define SOC_DEFAULT_DMA_PFM_SET(_u, _v) SOC_PERSIST(_u)->dcb_pfm = (_v) 2839 2840 /* Features cache */ 2841 #define SOC_FEATURE_GET(unit, feat) \ 2842 SHR_BITGET(SOC_CONTROL(unit)->features, feat) 2843 #define SOC_FEATURE_SET(unit, feat) \ 2844 SHR_BITSET(SOC_CONTROL(unit)->features, feat) 2845 #define SOC_FEATURE_CLEAR(unit, feat) \ 2846 SHR_BITCLR(SOC_CONTROL(unit)->features, feat) 2847 2848 /* 2849 * Various mutex controls 2850 */ 2851 #define SCHAN_LOCK(unit) \ 2852 sal_mutex_take(SOC_CONTROL(unit)->schanMutex, sal_mutex_FOREVER) 2853 #define SCHAN_UNLOCK(unit) \ 2854 sal_mutex_give(SOC_CONTROL(unit)->schanMutex) 2855 2856 #ifdef BCM_CMICM_SUPPORT 2857 #define FSCHAN_LOCK(unit) \ 2858 sal_mutex_take(SOC_CONTROL(unit)->fschanMutex, sal_mutex_FOREVER) 2859 #define FSCHAN_UNLOCK(unit) \ 2860 sal_mutex_give(SOC_CONTROL(unit)->fschanMutex) 2861 #endif 2862 2863 #define MIIM_LOCK(unit) \ 2864 sal_mutex_take(SOC_CONTROL(unit)->miimMutex, sal_mutex_FOREVER) 2865 #define MIIM_UNLOCK(unit) \ 2866 sal_mutex_give(SOC_CONTROL(unit)->miimMutex) 2867 2868 #define SBUS_DMA_LOCK(unit, cmc, ch) \ 2869 sal_mutex_take(SOC_CONTROL(unit)->sbusDmaMutexs[(cmc)][(ch)], sal_mutex_FOREVER) 2870 #define SBUS_DMA_UNLOCK(unit, cmc, ch) \ 2871 sal_mutex_give(SOC_CONTROL(unit)->sbusDmaMutexs[(cmc)][(ch)]) 2872 2873 #define TABLE_DMA_LOCK(unit) \ 2874 SBUS_DMA_LOCK(unit, SOC_PCI_CMC(unit), soc->tdma_ch) 2875 #define TABLE_DMA_UNLOCK(unit) \ 2876 SBUS_DMA_UNLOCK(unit, SOC_PCI_CMC(unit), soc->tdma_ch) 2877 2878 #define TSLAM_DMA_LOCK(unit) \ 2879 SBUS_DMA_LOCK(unit, SOC_PCI_CMC(unit), soc->tslam_ch) 2880 2881 #define TSLAM_DMA_UNLOCK(unit) \ 2882 SBUS_DMA_UNLOCK(unit, SOC_PCI_CMC(unit), soc->tslam_ch) 2883 2884 #define SBUSDMA_DMA_INTR_WAIT(unit, cmc, ch, to ) \ 2885 sal_sem_take(SOC_CONTROL(unit)->sbusDmaIntrs[(cmc)][(ch)], to) 2886 2887 #define TSLAM_DMA_INTR_WAIT(unit, to ) \ 2888 SBUSDMA_DMA_INTR_WAIT(unit, SOC_PCI_CMC(unit), soc->tslam_ch, to) 2889 2890 #define TABLE_DMA_INTR_WAIT(unit, to ) \ 2891 SBUSDMA_DMA_INTR_WAIT(unit, SOC_PCI_CMC(unit), soc->tdma_ch, to) 2892 2893 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 2894 #define CCM_DMA_LOCK(unit, cmc) \ 2895 sal_mutex_take(SOC_CONTROL(unit)->ccmDmaMutex[cmc], sal_mutex_FOREVER) 2896 #define CCM_DMA_UNLOCK(unit, cmc) \ 2897 sal_mutex_give(SOC_CONTROL(unit)->ccmDmaMutex[cmc]) 2898 #endif /* BCM_CMICM_SUPPORT or BCM_CMICX_SUPPORT */ 2899 2900 #ifdef BCM_SBUSDMA_SUPPORT 2901 #define SOC_SBUSDMA_DM_LOCK(unit) \ 2902 sal_mutex_take(SOC_SBUSDMA_DM_MUTEX(unit), sal_mutex_FOREVER) 2903 #define SOC_SBUSDMA_DM_UNLOCK(unit) \ 2904 sal_mutex_give(SOC_SBUSDMA_DM_MUTEX(unit)) 2905 #endif 2906 2907 #define SOC_CONTROL_LOCK(unit) \ 2908 sal_mutex_take(SOC_CONTROL(unit)->socControlMutex, sal_mutex_FOREVER) 2909 #define SOC_CONTROL_UNLOCK(unit) \ 2910 sal_mutex_give(SOC_CONTROL(unit)->socControlMutex) 2911 2912 #define SOC_MEM_SER_INFO_LOCK(unit) \ 2913 sal_mutex_take(SOC_CONTROL(unit)->mem_ser_info_lock, sal_mutex_FOREVER) 2914 #define SOC_MEM_SER_INFO_UNLOCK(unit) \ 2915 sal_mutex_give(SOC_CONTROL(unit)->mem_ser_info_lock) 2916 2917 #define COUNTER_LOCK(unit) \ 2918 sal_mutex_take(SOC_CONTROL(unit)->counterMutex, sal_mutex_FOREVER) 2919 #define COUNTER_UNLOCK(unit) \ 2920 sal_mutex_give(SOC_CONTROL(unit)->counterMutex) 2921 #define EVICT_LOCK(unit) \ 2922 sal_mutex_take(SOC_CONTROL(unit)->evictMutex, sal_mutex_FOREVER) 2923 #define EVICT_UNLOCK(unit) \ 2924 sal_mutex_give(SOC_CONTROL(unit)->evictMutex) 2925 #define SOC_COUNTER_IF_ERROR_RETURN(op) \ 2926 do { \ 2927 int __rv__; \ 2928 if (((__rv__ = (op)) < 0)) { \ 2929 COUNTER_UNLOCK(unit); \ 2930 _SHR_ERROR_TRACE(__rv__); \ 2931 return(__rv__); \ 2932 } \ 2933 } while(0) 2934 2935 2936 #define OVERRIDE_LOCK(unit) \ 2937 sal_mutex_take(SOC_CONTROL(unit)->overrideMutex, sal_mutex_FOREVER) 2938 #define OVERRIDE_UNLOCK(unit) \ 2939 sal_mutex_give(SOC_CONTROL(unit)->overrideMutex) 2940 2941 #define SPI_LOCK \ 2942 sal_mutex_take(spiMutex, sal_mutex_FOREVER) 2943 #define SPI_UNLOCK \ 2944 sal_mutex_give(spiMutex) 2945 2946 #define SOC_EGRESS_METERING_LOCK(unit) \ 2947 sal_mutex_take(SOC_CONTROL(unit)->egressMeteringMutex, \ 2948 sal_mutex_FOREVER) 2949 #define SOC_EGRESS_METERING_UNLOCK(unit) \ 2950 sal_mutex_give(SOC_CONTROL(unit)->egressMeteringMutex) 2951 2952 #define SOC_LLS_SCHEDULER_LOCK(unit) \ 2953 sal_mutex_take(SOC_CONTROL(unit)->llsMutex, \ 2954 sal_mutex_FOREVER) 2955 #define SOC_LLS_SCHEDULER_UNLOCK(unit) \ 2956 sal_mutex_give(SOC_CONTROL(unit)->llsMutex) 2957 2958 #define ARLDMA_SIZE_DEFAULT 1024 /* Size in 16-byte entries */ 2959 2960 #define IP_ARBITER_LOCK(unit) \ 2961 sal_mutex_take(SOC_CONTROL(unit)->ipArbiterMutex, sal_mutex_FOREVER) 2962 #define IP_ARBITER_UNLOCK(unit) \ 2963 sal_mutex_give(SOC_CONTROL(unit)->ipArbiterMutex) 2964 2965 #if defined(BCM_TRIUMPH3_SUPPORT) 2966 #define SOC_ESM_LOCK(unit) \ 2967 sal_mutex_take(SOC_CONTROL(unit)->esm_lock, sal_mutex_FOREVER) 2968 #define SOC_ESM_UNLOCK(unit) \ 2969 sal_mutex_give(SOC_CONTROL(unit)->esm_lock) 2970 #endif 2971 2972 #if defined(BCM_TOMAHAWK_SUPPORT) 2973 #define SOC_IDB_LOCK(unit) \ 2974 sal_mutex_take(SOC_CONTROL(unit)->idb_lock, sal_mutex_FOREVER) 2975 #define SOC_IDB_UNLOCK(unit) \ 2976 sal_mutex_give(SOC_CONTROL(unit)->idb_lock) 2977 #endif 2978 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) 2979 #define SOC_LINKSCAN_MODPORT_MAP_LOCK(unit) \ 2980 sal_mutex_take(SOC_CONTROL(unit)->linkscan_modport_map_lock, \ 2981 sal_mutex_FOREVER) 2982 #define SOC_LINKSCAN_MODPORT_MAP_UNLOCK(unit) \ 2983 sal_mutex_give(SOC_CONTROL(unit)->linkscan_modport_map_lock) 2984 #endif /* #(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) */ 2985 #ifdef INCLUDE_MEM_SCAN 2986 #define SOC_MEM_SCAN_LOCK(unit) \ 2987 sal_mutex_take(SOC_CONTROL(unit)->mem_scan_lock, sal_mutex_FOREVER) 2988 #define SOC_MEM_SCAN_UNLOCK(unit) \ 2989 sal_mutex_give(SOC_CONTROL(unit)->mem_scan_lock) 2990 #endif 2991 2992 #define SOC_SER_ERR_STAT_LOCK(unit) \ 2993 sal_mutex_take(SOC_CONTROL(unit)->ser_err_stat_lock, sal_mutex_FOREVER) 2994 #define SOC_SER_ERR_STAT_UNLOCK(unit) \ 2995 sal_mutex_give(SOC_CONTROL(unit)->ser_err_stat_lock) 2996 2997 /* 2998 * Define the default number of milliseconds before a BIST operation 2999 * times out and fails. Different values apply if the SAL boot flag 3000 * BOOT_F_QUICKTURN or BOOT_F_PLISIM are set. 3001 */ 3002 3003 #define BIST_TIMEOUT (1 * SECOND_MSEC) 3004 #define BIST_TIMEOUT_QT (1 * MINUTE_MSEC) 3005 #define BIST_TIMEOUT_PLI (20 * MINUTE_MSEC) 3006 3007 typedef struct _soc_l3_defip_index_table_s { 3008 int *defip_tcam_phy_index; /* Array holding defip phyiscal indexes 3009 * for a given logical index */ 3010 int *defip_tcam_log_index; /* Array holding defip logical indexes 3011 * for a given physical index */ 3012 int *defip_tcam_urpf_phy_index; /* Array holding defip phyiscal 3013 * indexes for a given logical 3014 * index when urpf is enabled */ 3015 int *defip_tcam_urpf_log_index; /* Array holding defip logical 3016 * indexes for a given physical 3017 * index when urpf is enabled */ 3018 int *defip_pair_tcam_phy_index; /* Array holding defip_pair 3019 * phyiscal indexes for a given 3020 * logical index */ 3021 int *defip_pair_tcam_log_index; /* Array holding defip_pair logical 3022 * indexes for a given physical 3023 * index */ 3024 int *defip_pair_tcam_urpf_phy_index; /* Array holding defip_pair 3025 * phyiscal indexes for a 3026 * given logical index when 3027 * urpf is enabled */ 3028 int *defip_pair_tcam_urpf_log_index; /* Array holding defip logical 3029 * indexes for a given 3030 * physical index when urpf is 3031 * enabled */ 3032 int *defip_tcam_alpm_urpf_phy_index; /* Array holding defip phyiscal 3033 * indexes for a given logical 3034 * index when alpm_tcam/parallel 3035 * and urpf are both enabled */ 3036 int *defip_tcam_alpm_urpf_log_index; /* Array holding defip logical 3037 * indexes for a given physical 3038 * index when alpm_tcam/parallel 3039 * and urpf are both enabled */ 3040 int *defip_pair_tcam_alpm_urpf_phy_index; /* Array holding defip phyiscal 3041 * indexes for a given logical 3042 * index when alpm_tcam/parallel 3043 * and urpf are both enabled */ 3044 int *defip_pair_tcam_alpm_urpf_log_index; /* Array holding defip logical 3045 * indexes for a given physical 3046 * index when alpm_tcam/parallel 3047 * and urpf are both enabled */ 3048 } _soc_l3_defip_index_table_t; 3049 3050 /* 3051 * Note that following enums must be in sync with BCM layer switch 3052 * block type, error type, correction type. 3053 */ 3054 /* Soc level SER block type */ 3055 typedef enum soc_ser_block_type_e { 3056 SocSerBlockTypeAll = -1, /* bcmSwitchBlockTypeAll */ 3057 SocSerBlockTypeMMU = 0, /* bcmSwitchBlockTypeMmu */ 3058 SocSerBlockTypeMMU_GLB = 1, /* bcmSwitchBlockTypeMmuGlb*/ 3059 SocSerBlockTypeMMU_XPE = 2, /* bcmSwitchBlockTypeMmuXpe */ 3060 SocSerBlockTypeMMU_SC = 3, /* bcmSwitchBlockTypeMmuSc */ 3061 SocSerBlockTypeMMU_SED = 4, /* bcmSwitchBlockTypeMmuSed */ 3062 SocSerBlockTypeIPIPE = 5, /* bcmSwitchBlockTypeIpipe */ 3063 SocSerBlockTypeEPIPE = 6, /* bcmSwitchBlockTypeEpipe */ 3064 SocSerBlockTypePGW = 7, /* bcmSwitchBlockTypePgw */ 3065 SocSerBlockTypeCLPORT = 8, /* bcmSwitchBlockTypeClport */ 3066 SocSerBlockTypeXLPORT = 9, /* bcmSwitchBlockTypeXlport */ 3067 SocSerBlockTypeMACSEC = 10, /* bcmSwitchBlockTypeMacsec */ 3068 SocSerBlockTypeCount = 11 /* bcmSwitchBlockTypeCount. */ 3069 } soc_ser_block_type_t; 3070 #define MAX_SOC_SER_BLOCK_TYPE SocSerBlockTypeCount 3071 3072 /* Soc level SER error type */ 3073 typedef enum soc_ser_error_type_e { 3074 SocSerErrorTypeAll = -1, /* bcmSwitchErrorTypeAll */ 3075 SocSerErrorTypeUnknown = 0, /* bcmSwitchErrorTypeUnknown */ 3076 SocSerErrorTypeParity = 1, /* bcmSwitchErrorTypeParity */ 3077 SocSerErrorTypeEccSingleBit = 2, /* bcmSwitchErrorTypeEccSingleBit */ 3078 SocSerErrorTypeEccDoubleBit = 3, /* bcmSwitchErrorTypeEccDoubleBit */ 3079 SocSerErrorTypeCount = 4 /* bcmSwitchErrorTypeCount. */ 3080 } soc_ser_error_type_t; 3081 #define MAX_SOC_SER_ERROR_TYPE SocSerErrorTypeCount 3082 3083 /* Soc level SER error correction type */ 3084 typedef enum soc_ser_correction_type_e { 3085 SocSerCorrectTypeAll = -1, /* bcmSwitchErrorTypeAll */ 3086 SocSerCorrectTypeNoAction = 0, /* bcmSwitchCorrectTypeNoAction */ 3087 SocSerCorrectTypeFailedToCorrect = 1, /* bcmSwitchCorrectTypeFailedToCorrect */ 3088 SocSerCorrectTypeEntryClear = 2, /* bcmSwitchCorrectTypeEntryClear */ 3089 SocSerCorrectTypeCacheRestore = 3, /* bcmSwitchCorrectTypeCacheRestore */ 3090 socSerCorrectTypeHwCacheRestore = 4, /* bcmSwitchCorrectTypeHwCacheRestore */ 3091 SocSerCorrectTypeSpecial = 5, /* bcmSwitchCorrectTypeSpecial */ 3092 SocSerCorrectTypeCount = 6 /* bcmSwitchCorrectTypeCount. */ 3093 } soc_ser_correction_type_t; 3094 #define MAX_SOC_SER_CORRECT_TYPE SocSerCorrectTypeCount 3095 3096 #define SOC_SER_STAT_TCAM 0x00000001 /* TCAM errors */ 3097 3098 /* 3099 * Typedef: soc_stat_t 3100 * Purpose: Driver statistics counts (interrupts, errors, etc). 3101 */ 3102 typedef struct soc_stat_s { 3103 uint32 intr; /* Total interrupt count */ 3104 uint32 intr_sce; /* S-Channel error interrupt count */ 3105 uint32 intr_sc; /* S-Channel interrupt count */ 3106 uint32 intr_ls; /* Link status interrupt count */ 3107 uint32 intr_gbp; /* GBP Full interrupt count */ 3108 uint32 intr_pci_fe; /* PCI Fatal Error interrupt count */ 3109 uint32 intr_pci_pe; /* PCI Parity Error interrupt count */ 3110 uint32 intr_arl_d; /* ARL message dropped interrupt count */ 3111 uint32 intr_arl_m; /* ARL message ready interrupt count */ 3112 uint32 intr_arl_x; /* ARL DMA xfer done interrupt count */ 3113 uint32 intr_arl_0; /* ARL DMA count=0 interrupt count */ 3114 uint32 intr_i2c; /* I2C controller interrupt count */ 3115 uint32 intr_mii; /* MII interrupt count */ 3116 uint32 intr_stats; /* Stats DMA interrupt count */ 3117 uint32 intr_desc; /* DMA desc done interrupt count */ 3118 uint32 pci_cmpl_timeout; /* PCI completion timeout */ 3119 uint32 intr_chain; /* DMA chain done interrupt count */ 3120 uint32 intr_reload; /* DMA reload done interrupt count */ 3121 uint32 intr_mmu; /* MMU status interrupt count */ 3122 uint32 intr_tdma; /* Table DMA complete interrupt count */ 3123 uint32 intr_tslam; /* Table SLAM DMA complete interrupt count */ 3124 uint32 intr_ccmdma; /* CCM DMA complete interrupt count */ 3125 uint32 intr_sw; /* Cross CPU S/W interrupts */ 3126 uint32 intr_mem_cmd[3]; /* Memory command complete interrupt count */ 3127 uint32 intr_chip_func[5]; /* Chip functional interrupt count */ 3128 uint32 intr_fifo_dma[4]; /* Fifo-dma interrupt count */ 3129 uint32 intr_block; /* Block interrupt count */ 3130 3131 uint32 schan_op; /* Number of S-Channel operations */ 3132 uint32 mem_cmd_op; /* Number of memory command operations */ 3133 3134 uint32 err_sdram; /* SDRAM parity error count */ 3135 uint32 err_cfap; /* CFAP oversubscribed count */ 3136 uint32 err_fcell; /* Unexpected First cell count */ 3137 uint32 err_sr; /* MMU Soft Reset count */ 3138 uint32 err_cellcrc; /* CBP cell CRC count */ 3139 uint32 err_cbphp; /* CBP header parity count */ 3140 uint32 err_npcell; /* MMU cells not in packet count */ 3141 uint32 err_mp; /* Memory parity error count */ 3142 uint32 err_pdlock; /* PLL/DLL Lock loss count */ 3143 uint32 err_cpcrc; /* Cell pointer CRC error count */ 3144 uint32 err_cdcrc; /* Cell data CRC error count */ 3145 uint32 err_fdcrc; /* Frame data CRC error count */ 3146 uint32 err_cpbcrc; /* Cell pointer block CRC error count */ 3147 uint32 err_multi; /* Multiple error count */ 3148 uint32 err_invalid; /* Invalid schan error count */ 3149 uint32 err_sc_tmo; /* S-Channel operation timeout count */ 3150 uint32 err_mii_tmo; /* MII operation timeout count */ 3151 uint32 err_mc_tmo; /* Memory command operation timeout count */ 3152 uint32 err_sbusdma_intr_res; /* SBUSDMA interrupt resource error */ 3153 3154 uint32 arl_msg_ins; /* Count of ARL insert messages processed */ 3155 uint32 arl_msg_del; /* Count of ARL delete messages processed */ 3156 uint32 arl_msg_bad; /* Count of bad messages processed */ 3157 uint32 arl_msg_tot; /* Count of all ARL messages */ 3158 3159 uint32 dma_rpkt; /* Packets received by CPU */ 3160 uint32 dma_rbyt; /* Bytes received by CPU */ 3161 uint32 dma_tpkt; /* Packets transmitted by CPU */ 3162 uint32 dma_tbyt; /* Bytes transmitted by CPU */ 3163 3164 uint32 dv_alloc; /* Number of DV alloc's */ 3165 uint32 dv_free; /* Number of DV free's */ 3166 uint32 dv_alloc_q; /* Free list satisfied DV allocs */ 3167 3168 uint32 m0_msg; /* Number of M0 messages sent */ 3169 uint32 m0_resp; /* Number of M0 responses received */ 3170 uint32 m0_intr; /* Number of M0 interrupts */ 3171 uint32 m0_u0_sw_intr; /* NUmber of M0 U0 SW prog interrupts */ 3172 uint32 m0_u1_sw_intr; /* NUmber of M0 U1 SW prog interrupts */ 3173 uint32 m0_u2_sw_intr; /* NUmber of M0 U2 SW prog interrupts */ 3174 uint32 m0_u3_sw_intr; /* NUmber of M0 U3 SW prog interrupts */ 3175 uint32 uc_sw_prg_intr; /* Number of uc sw programmable interrupts */ 3176 3177 uint32 mem_cache_count; 3178 uint32 mem_cache_size; 3179 uint32 mem_cache_vmap_size; 3180 uint32 tcam_corrupt_map_size; 3181 uint32 ser_err_int; /* Number of ser interrupt events */ 3182 uint32 ser_err_fifo; /* Number of ser fifo events */ 3183 uint32 ser_err_tcam; /* Number of ser tcam events */ 3184 uint32 ser_err_nak; /* Number of ser NAK events */ 3185 uint32 ser_err_stat; /* Number of ser stat events */ 3186 uint32 ser_err_ecc; /* Number of ser ecc events */ 3187 uint32 ser_err_corr; /* Number of ser error corrections */ 3188 uint32 ser_err_clear; /* Number of ser error reg/mem cleared */ 3189 uint32 ser_err_restor; /* Number of ser error cache restored */ 3190 uint32 ser_err_spe; /* Number of special ser errors */ 3191 uint32 ser_err_reg; /* Number of reg based ser errors */ 3192 uint32 ser_err_mem; /* Number of mem based ser errors */ 3193 uint32 ser_err_sw; /* Number of ser s/w errors */ 3194 uint32 ser_err[MAX_SOC_SER_BLOCK_TYPE][MAX_SOC_SER_ERROR_TYPE][MAX_SOC_SER_CORRECT_TYPE]; /* SER error statistics array */ 3195 uint32 ser_tcam_err[MAX_SOC_SER_BLOCK_TYPE][MAX_SOC_SER_ERROR_TYPE][MAX_SOC_SER_CORRECT_TYPE]; /* SER TCAM error statistics array */ 3196 } soc_stat_t; 3197 3198 /* 3199 * Soc SER error statistics macro definition 3200 */ 3201 3202 #define SOC_SER_ERROR_STAT(unit, btype, etype, ctype) \ 3203 (SOC_STAT(unit)->ser_err[btype][etype][ctype]) 3204 #define SOC_SER_TCAM_ERROR_STAT(unit, btype, etype, ctype) \ 3205 (SOC_STAT(unit)->ser_tcam_err[btype][etype][ctype]) 3206 3207 /* Sum error count of all block types */ 3208 #define SOC_SER_ERROR_STAT_ALL_BTYPE_SUM(unit, etype, ctype, value) \ 3209 do { \ 3210 int _i_; \ 3211 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3212 value += SOC_SER_ERROR_STAT(unit, _i_, etype, ctype); \ 3213 } \ 3214 } while(0) 3215 3216 /* Sum TCAM error count of all block types */ 3217 #define SOC_SER_TCAM_ERROR_STAT_ALL_BTYPE_SUM(unit, etype, ctype, value) \ 3218 do { \ 3219 int _i_; \ 3220 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3221 value += SOC_SER_TCAM_ERROR_STAT(unit, _i_, etype, ctype); \ 3222 } \ 3223 } while(0) 3224 3225 /* Sum error count of all error types */ 3226 #define SOC_SER_ERROR_STAT_ALL_ETYPE_SUM(unit, btype, ctype, value) \ 3227 do { \ 3228 int _i_; \ 3229 for (_i_ = SocSerErrorTypeUnknown; _i_ < SocSerErrorTypeCount; _i_++) { \ 3230 value += SOC_SER_ERROR_STAT(unit, btype, _i_, ctype); \ 3231 } \ 3232 } while(0) 3233 3234 /* Sum TCAM error count of all error types */ 3235 #define SOC_SER_TCAM_ERROR_STAT_ALL_ETYPE_SUM(unit, btype, ctype, value) \ 3236 do { \ 3237 int _i_; \ 3238 for (_i_ = SocSerErrorTypeUnknown; _i_ < SocSerErrorTypeCount; _i_++) { \ 3239 value += SOC_SER_TCAM_ERROR_STAT(unit, btype, _i_, ctype); \ 3240 } \ 3241 } while(0) 3242 3243 /* Sum error count of all correction types */ 3244 #define SOC_SER_ERROR_STAT_ALL_CTYPE_SUM(unit, btype, etype, value) \ 3245 do { \ 3246 int _i_; \ 3247 for (_i_ = SocSerCorrectTypeNoAction; _i_ < SocSerCorrectTypeCount; _i_++) { \ 3248 value += SOC_SER_ERROR_STAT(unit, btype, etype, _i_); \ 3249 } \ 3250 } while(0) 3251 3252 3253 /* Sum TCAM error count of all correction types */ 3254 #define SOC_SER_TCAM_ERROR_STAT_ALL_CTYPE_SUM(unit, btype, etype, value) \ 3255 do { \ 3256 int _i_; \ 3257 for (_i_ = SocSerCorrectTypeNoAction; _i_ < SocSerCorrectTypeCount; _i_++) { \ 3258 value += SOC_SER_TCAM_ERROR_STAT(unit, btype, etype, _i_); \ 3259 } \ 3260 } while(0) 3261 3262 3263 /* Sum error count of all block and error types */ 3264 #define SOC_SER_ERROR_STAT_ALL_BTYPE_ETYPE_SUM(unit, ctype, value) \ 3265 do { \ 3266 int _i_, _j_; \ 3267 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3268 for (_j_ = SocSerErrorTypeUnknown; _j_ < SocSerErrorTypeCount; _j_++) { \ 3269 value += SOC_SER_ERROR_STAT(unit, _i_, _j_, ctype); \ 3270 } \ 3271 } \ 3272 } while(0) 3273 3274 /* Sum TCAM error count of all block and error types */ 3275 #define SOC_SER_TCAM_ERROR_STAT_ALL_BTYPE_ETYPE_SUM(unit, ctype, value) \ 3276 do { \ 3277 int _i_, _j_; \ 3278 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3279 for (_j_ = SocSerErrorTypeUnknown; _j_ < SocSerErrorTypeCount; _j_++) { \ 3280 value += SOC_SER_TCAM_ERROR_STAT(unit, _i_, _j_, ctype); \ 3281 } \ 3282 } \ 3283 } while(0) 3284 3285 /* Sum error count of all block and correction types */ 3286 #define SOC_SER_ERROR_STAT_ALL_BTYPE_CTYPE_SUM(unit, etype, value) \ 3287 do { \ 3288 int _i_, _j_; \ 3289 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3290 for (_j_ = SocSerCorrectTypeNoAction; _j_ < SocSerCorrectTypeCount; _j_++) { \ 3291 value += SOC_SER_ERROR_STAT(unit, _i_, etype, _j_); \ 3292 } \ 3293 } \ 3294 } while(0) 3295 3296 /* Sum TCAM error count of all block and correction types */ 3297 #define SOC_SER_TCAM_ERROR_STAT_ALL_BTYPE_CTYPE_SUM(unit, etype, value) \ 3298 do { \ 3299 int _i_, _j_; \ 3300 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3301 for (_j_ = SocSerCorrectTypeNoAction; _j_ < SocSerCorrectTypeCount; _j_++) { \ 3302 value += SOC_SER_TCAM_ERROR_STAT(unit, _i_, etype, _j_); \ 3303 } \ 3304 } \ 3305 } while(0) 3306 3307 /* Sum error count of all error and correction types */ 3308 #define SOC_SER_ERROR_STAT_ALL_ETYPE_CTYPE_SUM(unit, btype, value) \ 3309 do { \ 3310 int _i_, _j_; \ 3311 for (_i_ = SocSerErrorTypeUnknown; _i_ < SocSerErrorTypeCount; _i_++) { \ 3312 for (_j_ = SocSerCorrectTypeNoAction; _j_ < SocSerCorrectTypeCount; _j_++) { \ 3313 value += SOC_SER_ERROR_STAT(unit, btype, _i_, _j_); \ 3314 } \ 3315 } \ 3316 } while(0) 3317 3318 /* Sum TCAM error count of all error and correction types */ 3319 #define SOC_SER_TCAM_ERROR_STAT_ALL_ETYPE_CTYPE_SUM(unit, btype, value) \ 3320 do { \ 3321 int _i_, _j_; \ 3322 for (_i_ = SocSerErrorTypeUnknown; _i_ < SocSerErrorTypeCount; _i_++) { \ 3323 for (_j_ = SocSerCorrectTypeNoAction; _j_ < SocSerCorrectTypeCount; _j_++) { \ 3324 value += SOC_SER_TCAM_ERROR_STAT(unit, btype, _i_, _j_); \ 3325 } \ 3326 } \ 3327 } while(0) 3328 3329 /* Sum error count of all block, error and correction types */ 3330 #define SOC_SER_ERROR_STAT_ALL_BTYPE_ETYPE_CTYPE_SUM(unit, value) \ 3331 do { \ 3332 int _i_, _j_, _z_; \ 3333 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3334 for (_j_ = SocSerErrorTypeUnknown; _j_ < SocSerErrorTypeCount; _j_++) { \ 3335 for (_z_ = SocSerCorrectTypeNoAction; _z_ < SocSerCorrectTypeCount; _z_++) { \ 3336 value += SOC_SER_ERROR_STAT(unit, _i_, _j_, _z_); \ 3337 } \ 3338 } \ 3339 } \ 3340 } while(0) 3341 3342 /* Sum TCAM error count of all block, error and correction types */ 3343 #define SOC_SER_TCAM_ERROR_STAT_ALL_BTYPE_ETYPE_CTYPE_SUM(unit, value) \ 3344 do { \ 3345 int _i_, _j_, _z_; \ 3346 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3347 for (_j_ = SocSerErrorTypeUnknown; _j_ < SocSerErrorTypeCount; _j_++) { \ 3348 for (_z_ = SocSerCorrectTypeNoAction; _z_ < SocSerCorrectTypeCount; _z_++) { \ 3349 value += SOC_SER_TCAM_ERROR_STAT(unit, _i_, _j_, _z_); \ 3350 } \ 3351 } \ 3352 } \ 3353 } while(0) 3354 3355 #define SOC_SER_ERROR_STAT_CLEAR(unit, btype, etype, ctype) \ 3356 do { \ 3357 SOC_STAT(unit)->ser_err[btype][etype][ctype] = 0; \ 3358 SOC_STAT(unit)->ser_tcam_err[btype][etype][ctype] = 0; \ 3359 } while(0) 3360 #define SOC_SER_TCAM_ERROR_STAT_CLEAR(unit, btype, etype, ctype) \ 3361 do { \ 3362 SOC_STAT(unit)->ser_err[btype][etype][ctype] -= \ 3363 SOC_STAT(unit)->ser_tcam_err[btype][etype][ctype]; \ 3364 SOC_STAT(unit)->ser_tcam_err[btype][etype][ctype] = 0; \ 3365 } while(0) 3366 3367 /* Clear error count of all block types */ 3368 #define SOC_SER_ERROR_STAT_ALL_BTYPE_CLEAR(unit, etype, ctype) \ 3369 do { \ 3370 int _i_; \ 3371 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3372 SOC_STAT(unit)->ser_err[_i_][etype][ctype] = 0; \ 3373 SOC_STAT(unit)->ser_tcam_err[_i_][etype][ctype] = 0; \ 3374 } \ 3375 } while(0) 3376 3377 /* Clear TCAM error count of all block types */ 3378 #define SOC_SER_TCAM_ERROR_STAT_ALL_BTYPE_CLEAR(unit, etype, ctype) \ 3379 do { \ 3380 int _i_; \ 3381 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3382 SOC_STAT(unit)->ser_err[_i_][etype][ctype] -= \ 3383 SOC_STAT(unit)->ser_tcam_err[_i_][etype][ctype]; \ 3384 SOC_STAT(unit)->ser_tcam_err[_i_][etype][ctype] = 0; \ 3385 } \ 3386 } while(0) 3387 3388 /* Clear error count of all error types */ 3389 #define SOC_SER_ERROR_STAT_ALL_ETYPE_CLEAR(unit, btype, ctype) \ 3390 do { \ 3391 int _i_; \ 3392 for (_i_ = SocSerErrorTypeUnknown; _i_ < SocSerErrorTypeCount; _i_++) { \ 3393 SOC_STAT(unit)->ser_err[btype][_i_][ctype] = 0; \ 3394 SOC_STAT(unit)->ser_tcam_err[btype][_i_][ctype] = 0; \ 3395 } \ 3396 } while(0) 3397 3398 /* Clear TCAM error count of all error types */ 3399 #define SOC_SER_TCAM_ERROR_STAT_ALL_ETYPE_CLEAR(unit, btype, ctype) \ 3400 do { \ 3401 int _i_; \ 3402 for (_i_ = SocSerErrorTypeUnknown; _i_ < SocSerErrorTypeCount; _i_++) { \ 3403 SOC_STAT(unit)->ser_err[btype][_i_][ctype] -= \ 3404 SOC_STAT(unit)->ser_tcam_err[btype][_i_][ctype]; \ 3405 SOC_STAT(unit)->ser_tcam_err[btype][_i_][ctype] = 0; \ 3406 } \ 3407 } while(0) 3408 3409 /* Clear error count of all correction types */ 3410 #define SOC_SER_ERROR_STAT_ALL_CTYPE_CLEAR(unit, btype, etype) \ 3411 do { \ 3412 int _i_; \ 3413 for (_i_ = SocSerCorrectTypeNoAction; _i_ < SocSerCorrectTypeCount; _i_++) { \ 3414 SOC_STAT(unit)->ser_err[btype][etype][_i_] = 0; \ 3415 SOC_STAT(unit)->ser_tcam_err[btype][etype][_i_] = 0; \ 3416 } \ 3417 } while(0) 3418 3419 3420 /* Clear TCAM error count of all correction types */ 3421 #define SOC_SER_TCAM_ERROR_STAT_ALL_CTYPE_CLEAR(unit, btype, etype) \ 3422 do { \ 3423 int _i_; \ 3424 for (_i_ = SocSerCorrectTypeNoAction; _i_ < SocSerCorrectTypeCount; _i_++) { \ 3425 SOC_STAT(unit)->ser_err[btype][etype][_i_] -= \ 3426 SOC_STAT(unit)->ser_tcam_err[btype][etype][_i_]; \ 3427 SOC_STAT(unit)->ser_tcam_err[btype][etype][_i_] = 0; \ 3428 } \ 3429 } while(0) 3430 3431 3432 /* Clear error count of all block and error types */ 3433 #define SOC_SER_ERROR_STAT_ALL_BTYPE_ETYPE_CLEAR(unit, ctype) \ 3434 do { \ 3435 int _i_, _j_; \ 3436 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3437 for (_j_ = SocSerErrorTypeUnknown; _j_ < SocSerErrorTypeCount; _j_++) { \ 3438 SOC_STAT(unit)->ser_err[_i_][_j_][ctype] = 0; \ 3439 SOC_STAT(unit)->ser_tcam_err[_i_][_j_][ctype] = 0; \ 3440 } \ 3441 } \ 3442 } while(0) 3443 3444 /* Clear TCAM error count of all block and error types */ 3445 #define SOC_SER_TCAM_ERROR_STAT_ALL_BTYPE_ETYPE_CLEAR(unit, ctype) \ 3446 do { \ 3447 int _i_, _j_; \ 3448 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3449 for (_j_ = SocSerErrorTypeUnknown; _j_ < SocSerErrorTypeCount; _j_++) { \ 3450 SOC_STAT(unit)->ser_err[_i_][_j_][ctype] -= \ 3451 SOC_STAT(unit)->ser_tcam_err[_i_][_j_][ctype]; \ 3452 SOC_STAT(unit)->ser_tcam_err[_i_][_j_][ctype] = 0; \ 3453 } \ 3454 } \ 3455 } while(0) 3456 3457 /* Clear error count of all block and correction types */ 3458 #define SOC_SER_ERROR_STAT_ALL_BTYPE_CTYPE_CLEAR(unit, etype) \ 3459 do { \ 3460 int _i_, _j_; \ 3461 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3462 for (_j_ = SocSerCorrectTypeNoAction; _j_ < SocSerCorrectTypeCount; _j_++) { \ 3463 SOC_STAT(unit)->ser_err[_i_][etype][_j_] = 0; \ 3464 SOC_STAT(unit)->ser_tcam_err[_i_][etype][_j_] = 0; \ 3465 } \ 3466 } \ 3467 } while(0) 3468 3469 /* Clear TCAM error count of all block and correction types */ 3470 #define SOC_SER_TCAM_ERROR_STAT_ALL_BTYPE_CTYPE_CLEAR(unit, etype) \ 3471 do { \ 3472 int _i_, _j_; \ 3473 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3474 for (_j_ = SocSerCorrectTypeNoAction; _j_ < SocSerCorrectTypeCount; _j_++) { \ 3475 SOC_STAT(unit)->ser_err[_i_][etype][_j_] -= \ 3476 SOC_STAT(unit)->ser_tcam_err[_i_][etype][_j_]; \ 3477 SOC_STAT(unit)->ser_tcam_err[_i_][etype][_j_] = 0; \ 3478 } \ 3479 } \ 3480 } while(0) 3481 3482 /* Clear error count of all error and correction types */ 3483 #define SOC_SER_ERROR_STAT_ALL_ETYPE_CTYPE_CLEAR(unit, btype) \ 3484 do { \ 3485 int _i_, _j_; \ 3486 for (_i_ = SocSerErrorTypeUnknown; _i_ < SocSerErrorTypeCount; _i_++) { \ 3487 for (_j_ = SocSerCorrectTypeNoAction; _j_ < SocSerCorrectTypeCount; _j_++) { \ 3488 SOC_STAT(unit)->ser_err[btype][_i_][_j_] = 0; \ 3489 SOC_STAT(unit)->ser_tcam_err[btype][_i_][_j_] = 0; \ 3490 } \ 3491 } \ 3492 } while(0) 3493 3494 /* Clear TCAM error count of all error and correction types */ 3495 #define SOC_SER_TCAM_ERROR_STAT_ALL_ETYPE_CTYPE_CLEAR(unit, btype) \ 3496 do { \ 3497 int _i_, _j_; \ 3498 for (_i_ = SocSerErrorTypeUnknown; _i_ < SocSerErrorTypeCount; _i_++) { \ 3499 for (_j_ = SocSerCorrectTypeNoAction; _j_ < SocSerCorrectTypeCount; _j_++) { \ 3500 SOC_STAT(unit)->ser_err[btype][_i_][_j_] -= \ 3501 SOC_STAT(unit)->ser_tcam_err[btype][_i_][_j_]; \ 3502 SOC_STAT(unit)->ser_tcam_err[btype][_i_][_j_] = 0; \ 3503 } \ 3504 } \ 3505 } while(0) 3506 3507 /* Clear error count of all block, error and correction types */ 3508 #define SOC_SER_ERROR_STAT_ALL_BTYPE_ETYPE_CTYPE_CLEAR(unit) \ 3509 do { \ 3510 int _i_, _j_, _z_; \ 3511 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3512 for (_j_ = SocSerErrorTypeUnknown; _j_ < SocSerErrorTypeCount; _j_++) { \ 3513 for (_z_ = SocSerCorrectTypeNoAction; _z_ < SocSerCorrectTypeCount; _z_++) { \ 3514 SOC_STAT(unit)->ser_err[_i_][_j_][_z_] = 0; \ 3515 SOC_STAT(unit)->ser_tcam_err[_i_][_j_][_z_] = 0; \ 3516 } \ 3517 } \ 3518 } \ 3519 } while(0) 3520 3521 /* Clear TCAM error count of all block, error and correction types */ 3522 #define SOC_SER_TCAM_ERROR_STAT_ALL_BTYPE_ETYPE_CTYPE_CLEAR(unit) \ 3523 do { \ 3524 int _i_, _j_, _z_; \ 3525 for (_i_ = SocSerBlockTypeMMU; _i_ < SocSerBlockTypeCount; _i_++) {\ 3526 for (_j_ = SocSerErrorTypeUnknown; _j_ < SocSerErrorTypeCount; _j_++) { \ 3527 for (_z_ = SocSerCorrectTypeNoAction; _z_ < SocSerCorrectTypeCount; _z_++) { \ 3528 SOC_STAT(unit)->ser_err[_i_][_j_][_z_] -= \ 3529 SOC_STAT(unit)->ser_tcam_err[_i_][_j_][_z_]; \ 3530 SOC_STAT(unit)->ser_tcam_err[_i_][_j_][_z_] = 0; \ 3531 } \ 3532 } \ 3533 } \ 3534 } while(0) 3535 3536 /* 3537 * Typedef: soc_memstate_t 3538 * Purpose: Maintain per-memory information 3539 * Notes: To avoid deadlock, do not use MEM_LOCK while holding SCHAN_LOCK. 3540 * MEM_LOCK must be held while manipulating memory caches in any way. 3541 */ 3542 3543 #define SOC_MEM_STATE(unit, mem) SOC_CONTROL(unit)->memState[mem] 3544 3545 #define MEM_LOCK(unit, mem) \ 3546 sal_mutex_take(SOC_MEM_STATE(unit, mem).lock, sal_mutex_FOREVER) 3547 #define MEM_UNLOCK(unit, mem) \ 3548 sal_mutex_give(SOC_MEM_STATE(unit, mem).lock) 3549 3550 #define CACHE_VMAP_OP(vmap, index, BOOL_OP) \ 3551 ((vmap)[(index) / 8] BOOL_OP (1 << ((index) % 8))) 3552 3553 #define CACHE_VMAP_SET(vmap, index) CACHE_VMAP_OP(vmap, index, |=) 3554 #define CACHE_VMAP_CLR(vmap, index) CACHE_VMAP_OP(vmap, index, &= ~) 3555 #define CACHE_VMAP_TST(vmap, index) CACHE_VMAP_OP(vmap, index, &) 3556 3557 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_HELIX4_SUPPORT) || \ 3558 defined(BCM_KATANA2_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) || \ 3559 defined(BCM_GREYHOUND_SUPPORT) 3560 #define TCAM_CORRUPT_MAP_OP(corrupt, index, BOOL_OP) \ 3561 ((corrupt)[(index) / 8] BOOL_OP (1 << ((index) % 8))) 3562 3563 #define TCAM_CORRUPT_MAP_SET(corrupt, index) TCAM_CORRUPT_MAP_OP(corrupt, index, |=) 3564 #define TCAM_CORRUPT_MAP_CLR(corrupt, index) TCAM_CORRUPT_MAP_OP(corrupt, index, &= ~) 3565 #define TCAM_CORRUPT_MAP_TST(corrupt, index) TCAM_CORRUPT_MAP_OP(corrupt, index, &) 3566 #endif 3567 3568 typedef struct soc_memstate_s { 3569 sal_mutex_t lock; /* Table update lock */ 3570 /* (sorted tables only) */ 3571 uint32 *cache[SOC_MAX_NUM_BLKS];/* Write-through cache when non-NULL */ 3572 uint8 *vmap[SOC_MAX_NUM_BLKS]; /* Cache entry valid bitmap */ 3573 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_HELIX4_SUPPORT) || \ 3574 defined(BCM_KATANA2_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) || \ 3575 defined(BCM_GREYHOUND_SUPPORT) 3576 uint8 *corrupt[SOC_MAX_NUM_BLKS]; /* entry corrupted bitmap */ 3577 /* tcam tables only */ 3578 #endif 3579 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIDENT_SUPPORT) 3580 SHR_BITDCL *OverlayTcamMap[SOC_MAX_NUM_BLKS]; /* FP Overlay tcam bitmap*/ 3581 #endif 3582 } soc_memstate_t; 3583 3584 /* 3585 * Typedef: soc_driver_t 3586 * Purpose: Chip driver. All info about a particular device type. 3587 * Notes: These structures are automatically generated by mcm. 3588 * Used in soc/mcm/bcm*.c files. 3589 */ 3590 typedef struct soc_driver_s { 3591 soc_chip_types type; /* the chip type id */ 3592 char *chip_string; /* chip string for var defs */ 3593 char *origin; /* regsfile origin */ 3594 uint16 pci_vendor; /* nominal PCI vendor */ 3595 uint16 pci_device; /* nominal PCI device */ 3596 uint8 pci_revision; /* nominal PCI revision */ 3597 int num_cos; /* classes of service */ 3598 soc_reg_info_t **reg_info; /* register array */ 3599 soc_reg_t **reg_unique_acc; /* unique access type register array */ 3600 soc_reg_above_64_info_t **reg_above_64_info; /* large register array */ 3601 soc_reg_array_info_t **reg_array_info; /* register array array */ 3602 soc_mem_info_t **mem_info; /* memory array */ 3603 soc_mem_t **mem_unique_acc; /* unique access type memory array */ 3604 soc_mem_t **mem_aggr; /* memory aggregate */ 3605 soc_mem_array_info_t **mem_array_info; /* memory array array */ 3606 soc_block_info_t *block_info; /* block array */ 3607 soc_format_info_t **format_info; /* format array */ 3608 soc_dop_t *dop_info; /* dop format array */ 3609 soc_port_info_t *port_info; /* port array */ 3610 soc_cmap_t *counter_maps; /* counter map */ 3611 soc_feature_fun_t feature; /* boolean feature function */ 3612 soc_init_chip_fun_t init; /* chip init function */ 3613 void *reserved; /* compability */ 3614 int port_num_blktype; /* block types per port */ 3615 uint32 cmicd_base; /* Base address for CMICd Registers */ 3616 soc_ser_info_t *ser_info; /* soc ser info */ 3617 soc_ctr_tbl_info_t *ctr_tbl_info; /* counter tables */ 3618 } soc_driver_t; 3619 3620 typedef int (*soc_misc_init_f)(int); 3621 typedef int (*soc_mmu_init_f)(int); 3622 typedef int (*soc_age_timer_get_f)(int, int *, int *); 3623 typedef int (*soc_age_timer_max_get_f)(int, int *); 3624 typedef int (*soc_age_timer_set_f)(int, int, int); 3625 typedef int (*soc_phy_firmware_load_f)(int, int, uint8 *, int); 3626 typedef int (*soc_sbus_mdio_read_f)(int, uint32, uint32, uint32 *); 3627 typedef int (*soc_sbus_mdio_write_f)(int, uint32, uint32, uint32); 3628 typedef int (*soc_bond_options_init_f)(int); 3629 typedef int (*soc_misc_deinit_f)(int); 3630 3631 /* 3632 * Typedef: soc_functions_t 3633 * Purpose: Chip driver functions that are not automatically generated. 3634 */ 3635 typedef struct soc_functions_s { 3636 /* Get/set age timer value and enable in device, if supported */ 3637 soc_misc_init_f soc_misc_init; 3638 soc_mmu_init_f soc_mmu_init; 3639 soc_age_timer_get_f soc_age_timer_get; 3640 soc_age_timer_max_get_f soc_age_timer_max_get; 3641 soc_age_timer_set_f soc_age_timer_set; 3642 soc_phy_firmware_load_f soc_phy_firmware_load; 3643 soc_sbus_mdio_read_f soc_sbus_mdio_read; 3644 soc_sbus_mdio_write_f soc_sbus_mdio_write; 3645 soc_bond_options_init_f soc_bond_options_init; 3646 soc_misc_deinit_f soc_misc_deinit; 3647 } soc_functions_t; 3648 3649 typedef int (*soc_portctrl_pm_init_f)(int); 3650 typedef int (*soc_portctrl_pm_deinit_f)(int); 3651 typedef int (*soc_portctrl_pm_port_config_get_f)(int, soc_port_t, void*); 3652 typedef int (*soc_portctrl_pm_port_phyaddr_get_f)(int, soc_port_t); 3653 typedef int (*soc_portctrl_port_ability_update_f)(int, soc_port_t, soc_port_ability_t*); 3654 typedef int (*soc_portctrl_pm_type_get_f)(int, soc_port_t, int*); 3655 typedef int (*soc_portctrl_sbus_ring_info_get_f)(int, soc_port_t, int*, int*); 3656 typedef int (*soc_portctrl_sbus_bcast_id_get_f)(int, int, int*); 3657 typedef int (*soc_portctrl_pm_vco_store_clear_f)(int); 3658 typedef int (*soc_portctrl_pm_vco_store_f)(int, int, const void*); 3659 typedef int (*soc_portctrl_pm_vco_fetch_f)(int, int, void*); 3660 typedef int (*soc_portctrl_pm_vco_reconfigure_f)(int); 3661 3662 typedef struct soc_portctrl_functions_s { 3663 soc_portctrl_pm_init_f soc_portctrl_pm_init; 3664 soc_portctrl_pm_deinit_f soc_portctrl_pm_deinit; 3665 soc_portctrl_pm_port_config_get_f soc_portctrl_pm_port_config_get; 3666 soc_portctrl_pm_port_phyaddr_get_f soc_portctrl_pm_port_phyaddr_get; 3667 soc_portctrl_port_ability_update_f soc_portctrl_port_ability_update; 3668 soc_portctrl_pm_type_get_f soc_portctrl_pm_type_get; 3669 soc_portctrl_sbus_ring_info_get_f soc_portctrl_sbus_ring_info_get; 3670 soc_portctrl_sbus_bcast_id_get_f soc_portctrl_sbus_bcast_id_get; 3671 soc_portctrl_pm_vco_store_clear_f soc_portctrl_pm_vco_store_clear; 3672 soc_portctrl_pm_vco_store_f soc_portctrl_pm_vco_store; 3673 soc_portctrl_pm_vco_fetch_f soc_portctrl_pm_vco_fetch; 3674 soc_portctrl_pm_vco_reconfigure_f soc_portctrl_pm_vco_reconfigure; 3675 } soc_portctrl_functions_t; 3676 3677 #define GE_PORT 0x0001 3678 #define XE_PORT 0x0002 3679 #define HG_PORT 0x0004 3680 #define HGL_PORT 0x0008 3681 #define STK_PORT 0x0010 3682 #define CES_PORT 0x0020 3683 #define OLP_PORT 0x0040 3684 #define LPHY_PORT 0x0080 3685 #define ETH_PORT 0x0100 3686 #define INTLB_PORT 0x0200 3687 3688 /* soc_port_details_t is applicable to katana2 device only */ 3689 typedef struct soc_port_details_s { 3690 /* Range of port numbers */ 3691 uint8 start_port_no; 3692 uint8 end_port_no; 3693 uint8 port_incr; 3694 3695 /* Port Properties */ 3696 uint8 port_type;/*Combination of hash defines(GE,FE,XE,HG,HGL,STK,CE,LPH*/ 3697 3698 /* Port Speed */ 3699 uint32 port_speed; 3700 } soc_port_details_t; 3701 3702 /*Type used to define the distribution of 10G lanes for a 100G port using 3703 * a TSC-12 which provides up to 12 10G lanes*/ 3704 typedef enum soc_100g_lane_config_s { 3705 SOC_LANE_CONFIG_100G_4_4_2 = 0, 3706 SOC_LANE_CONFIG_100G_3_4_3 = 1, 3707 SOC_LANE_CONFIG_100G_2_4_4 = 2, 3708 SOC_INVALID_LANE_CONFIG = -1 3709 } soc_100g_lane_config_t; 3710 3711 #define SOC_LANE_CONFIG_100G_DEFAULT SOC_LANE_CONFIG_100G_4_4_2 3712 #define SOC_LANE_CONFIG_100G_AN_CORE_DEFAULT (1) 3713 3714 /* 3715 * This define tells whether a driver is active (not null). 3716 * The null driver is allocated, but is all zeros. We assume that 3717 * the block list (block_info) is non-null for non-null drivers. 3718 */ 3719 #define SOC_DRIVER_ACTIVE(i) (soc_base_driver_table[i]->block_info) 3720 3721 /* Find an active chip to get reg info from base driver table. */ 3722 #define SOC_FIRST_ACTIVE_DRIVER(chip) \ 3723 do { \ 3724 chip = 0; \ 3725 while (!SOC_DRIVER_ACTIVE(chip) && chip < SOC_NUM_SUPPORTED_CHIPS) { \ 3726 chip++; \ 3727 } \ 3728 assert(chip < SOC_NUM_SUPPORTED_CHIPS); \ 3729 } while (0) 3730 3731 3732 extern soc_driver_t *soc_chip_driver_find(uint16 dev_id, uint8 rev_id); 3733 extern void soc_chip_dump(int unit, soc_driver_t *d); 3734 3735 #define SOC_UNIT_NAME(unit) \ 3736 (SOC_CHIP_NAME(SOC_DRIVER(unit)->type)) 3737 3738 #define SOC_UNIT_GROUP(unit) \ 3739 (soc_chip_group_names[soc_chip_type_map[SOC_DRIVER(unit)->type]]) 3740 3741 #define SOC_UNIT_FAMILY(unit) \ 3742 (soc_chip_group_names[soc_chip_family_map[SOC_DRIVER(unit)->type]]) 3743 3744 /* 3745 * Typedef: soc_fm_t 3746 * Purpose: For each filter mask entry, cache the index of the first rule 3747 * using that mask, and the number of rules using that mask. 3748 * (All rules that use a given mask are necessarily contiguous.) 3749 * These values speed up searches in the FFP, and on 5690 they 3750 * are required by the hardware. 3751 */ 3752 3753 #define SOC_FFP_MASK_MAX 24 /* Max # masks of any chip */ 3754 3755 typedef struct soc_fm_s { 3756 uint16 start; 3757 uint16 count; 3758 } soc_fm_t; 3759 3760 /* 3761 * Typedef: soc_ipg_t 3762 * Purpose: IFG register setting for all speed/duplex combinations 3763 */ 3764 3765 typedef struct soc_ipg_s { 3766 uint32 hd_10; 3767 uint32 hd_100; 3768 uint32 hd_1000; 3769 uint32 hd_2500; 3770 uint32 fd_10; 3771 uint32 fd_100; 3772 uint32 fd_1000; 3773 uint32 fd_2500; 3774 uint32 fd_10000; 3775 uint32 fd_xe; 3776 uint32 fd_hg; 3777 uint32 fd_hg2; 3778 uint32 fe_hd_10; 3779 uint32 fe_hd_100; 3780 uint32 fe_fd_10; 3781 uint32 fe_fd_100; 3782 uint32 gth_hd_10; 3783 uint32 gth_hd_100; 3784 uint32 gth_fd_10; 3785 uint32 gth_fd_100; 3786 uint32 ge_hd_1000; 3787 uint32 ge_fd_1000; 3788 uint32 ge_hd_2500; 3789 uint32 ge_fd_2500; 3790 uint32 bm_fd_10000; 3791 } soc_ipg_t; 3792 3793 /* 3794 * soc_info_t is part of the per-unit soc_control_t. 3795 * It gets filled in at run time based on the port_info and block_info 3796 * from the driver structure. 3797 */ 3798 typedef struct { 3799 #if defined(BCM_ESW_SUPPORT) && (SOC_MAX_NUM_PP_PORTS > SOC_MAX_NUM_PORTS) 3800 int port[SOC_MAX_NUM_PP_PORTS]; 3801 #else 3802 int port[SOC_MAX_NUM_PORTS]; 3803 #endif 3804 int num; /* number of entries used in port[] */ 3805 int min; /* minimum bit on */ 3806 int max; /* maximum bit on */ 3807 pbmp_t bitmap; 3808 pbmp_t disabled_bitmap; /* ports that are forced to be disabled */ 3809 } soc_ptype_t; 3810 3811 typedef struct { 3812 int tvco; 3813 int ovco; 3814 int is_tvco_new; 3815 int is_ovco_new; 3816 } soc_pmvco_info_t; 3817 3818 3819 #define SOC_INFO_CHIP_ENDURO 0x00000001 /* 56334 */ 3820 #define SOC_INFO_CHIP_APOLLO 0x00000002 /* 56524 */ 3821 #define SOC_INFO_CHIP_TRIDENT2 0x00000004 /* 5685x */ 3822 #define SOC_INFO_CHIP_TITAN2 0x00000008 /* 5675x */ 3823 #define SOC_INFO_CHIP_KATANA2 0x00000010 /* 5645x */ 3824 #define SOC_INFO_CHIP_HURRICANE2 0x00000020 /* 5615x */ 3825 #define SOC_INFO_CHIP_HELIX4 0x00000040 /* 5634x */ 3826 #define SOC_INFO_CHIP_HERCULES15 0x00000080 /* 5675 */ 3827 #define SOC_INFO_CHIP_TOMAHAWK 0x00000100 /* 5696x */ 3828 #define SOC_INFO_CHIP_EASYRIDER 0x00000100 /* 5660x */ 3829 #define SOC_INFO_CHIP_FIREBOLT 0x00000200 /* 56504 */ 3830 #define SOC_INFO_CHIP_VALKYRIE2 0x00000400 /* 56685 */ 3831 #define SOC_INFO_CHIP_TRIDENT2PLUS 0x00000800 /* 5686x */ 3832 #define SOC_INFO_CHIP_FHX 0x00001000 /* 5610x, 5630x */ 3833 #define SOC_INFO_CHIP_SHADOW 0x00002000 /* 88732 */ 3834 #define SOC_INFO_CHIP_GOLDWING 0x00004000 /* 56580 */ 3835 #define SOC_INFO_CHIP_HUMV 0x00008000 /* 56700 */ 3836 #define SOC_INFO_CHIP_BRADLEY 0x00010000 /* 56800 */ 3837 #define SOC_INFO_CHIP_RAPTOR 0x00020000 /* 56218 */ 3838 #define SOC_INFO_CHIP_KATANA 0x00040000 /* 56440 */ 3839 #define SOC_INFO_CHIP_TRIUMPH3 0x00080000 /* 56640 */ 3840 #define SOC_INFO_CHIP_FIREBOLT2 0x00100000 /* 56514 */ 3841 #define SOC_INFO_CHIP_SCORPION 0x00200000 /* 56820 */ 3842 #define SOC_INFO_CHIP_TRIUMPH 0x00400000 /* 56624 */ 3843 #define SOC_INFO_CHIP_RAVEN 0x00800000 /* 56224 */ 3844 #define SOC_INFO_CHIP_HAWKEYE 0x01000000 /* 53314 */ 3845 #define SOC_INFO_CHIP_VALKYRIE 0x02000000 /* 56680 */ 3846 #define SOC_INFO_CHIP_CONQUEROR 0x04000000 /* 56725 */ 3847 #define SOC_INFO_CHIP_TRIUMPH2 0x08000000 /* 56634 */ 3848 #define SOC_INFO_CHIP_TRIDENT 0x10000000 /* 5684x */ 3849 #define SOC_INFO_CHIP_HURRICANE 0x20000000 /* 56142 */ 3850 #define SOC_INFO_CHIP_TITAN 0x40000000 /* 5674x */ 3851 #define SOC_INFO_CHIP_HERCULES (SOC_INFO_CHIP_HERCULES15) 3852 #define SOC_INFO_CHIP_FB (SOC_INFO_CHIP_FIREBOLT | SOC_INFO_CHIP_FIREBOLT2) 3853 #define SOC_INFO_CHIP_FX_HX (SOC_INFO_CHIP_FHX | \ 3854 SOC_INFO_CHIP_RAPTOR | \ 3855 SOC_INFO_CHIP_RAVEN | \ 3856 SOC_INFO_CHIP_HAWKEYE) 3857 #define SOC_INFO_CHIP_FB_FX_HX (SOC_INFO_CHIP_FB | SOC_INFO_CHIP_FX_HX) 3858 #define SOC_INFO_CHIP_HB_GW (SOC_INFO_CHIP_HUMV | \ 3859 SOC_INFO_CHIP_BRADLEY | \ 3860 SOC_INFO_CHIP_GOLDWING) 3861 #define SOC_INFO_CHIP_TD2_TT2 (SOC_INFO_CHIP_TRIDENT2 | \ 3862 SOC_INFO_CHIP_TITAN2 | \ 3863 SOC_INFO_CHIP_TOMAHAWK | \ 3864 SOC_INFO_CHIP_TRIDENT2PLUS) 3865 #define SOC_INFO_CHIP_TRIDENT2X (SOC_INFO_CHIP_TRIDENT2 | \ 3866 SOC_INFO_CHIP_TRIDENT2PLUS) 3867 #define SOC_INFO_CHIP_TD_TT (SOC_INFO_CHIP_TRIDENT | \ 3868 SOC_INFO_CHIP_TITAN | \ 3869 SOC_INFO_CHIP_TD2_TT2) 3870 #define SOC_INFO_CHIP_TR_VL (SOC_INFO_CHIP_TRIUMPH | \ 3871 SOC_INFO_CHIP_VALKYRIE | \ 3872 SOC_INFO_CHIP_TRIUMPH2 | \ 3873 SOC_INFO_CHIP_APOLLO | \ 3874 SOC_INFO_CHIP_VALKYRIE2 | \ 3875 SOC_INFO_CHIP_ENDURO | \ 3876 SOC_INFO_CHIP_TD_TT | \ 3877 SOC_INFO_CHIP_HURRICANE | \ 3878 SOC_INFO_CHIP_KATANA | \ 3879 SOC_INFO_CHIP_TRIUMPH3 | \ 3880 SOC_INFO_CHIP_HELIX4) 3881 #define SOC_INFO_CHIP_SC_CQ (SOC_INFO_CHIP_SCORPION | \ 3882 SOC_INFO_CHIP_CONQUEROR | \ 3883 SOC_INFO_CHIP_SHADOW) 3884 #define SOC_INFO_CHIP_HBX (SOC_INFO_CHIP_HB_GW | SOC_INFO_CHIP_SC_CQ) 3885 #define SOC_INFO_CHIP_TRX (SOC_INFO_CHIP_TR_VL | \ 3886 SOC_INFO_CHIP_SC_CQ | \ 3887 SOC_INFO_CHIP_KATANA2 | \ 3888 SOC_INFO_CHIP_HURRICANE2) 3889 #define SOC_INFO_CHIP_FBX (SOC_INFO_CHIP_FB_FX_HX | \ 3890 SOC_INFO_CHIP_HB_GW | \ 3891 SOC_INFO_CHIP_TRX) 3892 #define SOC_INFO_CHIP_XGS3_SWITCH (SOC_INFO_CHIP_FBX) 3893 #define SOC_INFO_CHIP_XGS3_FABRIC (SOC_INFO_CHIP_HUMV | \ 3894 SOC_INFO_CHIP_CONQUEROR | \ 3895 SOC_INFO_CHIP_TITAN | \ 3896 SOC_INFO_CHIP_TITAN2) 3897 #define SOC_INFO_CHIP_XGS_SWITCH (SOC_INFO_CHIP_XGS3_SWITCH) 3898 #define SOC_INFO_CHIP_XGS12_FABRIC (SOC_INFO_CHIP_HERCULES) 3899 #define SOC_INFO_CHIP_XGS_FABRIC (SOC_INFO_CHIP_XGS12_FABRIC | \ 3900 SOC_INFO_CHIP_XGS3_FABRIC) 3901 #define SOC_INFO_CHIP_XGS (SOC_INFO_CHIP_XGS_FABRIC | \ 3902 SOC_INFO_CHIP_XGS_SWITCH) 3903 3904 typedef struct { 3905 soc_chip_types driver_type; /* chip type (with rev) */ 3906 soc_chip_groups_t driver_group; /* chip type (no rev) */ 3907 3908 soc_chip_e chip_type; /* chip type enum - used instead of 'chip' 3909 for newer devices as the bitmap was exhausted */ 3910 uint32 spi_device; 3911 3912 uint32 chip; /* chip id bits */ 3913 3914 int port_num; /* count of entries in port_info */ 3915 int block_num; /* count of entries in block_info */ 3916 soc_ptype_t fe; 3917 soc_ptype_t ge; 3918 soc_ptype_t ce; /* 100g port */ 3919 soc_ptype_t cde; /* 200g and 400g port */ 3920 soc_ptype_t tpon; /* 10g PON port*/ 3921 soc_ptype_t pon; /* PON port*/ 3922 soc_ptype_t llid; /* LLID of epon*/ 3923 soc_ptype_t xe; 3924 soc_ptype_t le; /* 50g port */ 3925 soc_ptype_t cc; /* DNX 200g port */ 3926 soc_ptype_t hg; 3927 soc_ptype_t il; /* Interlaken */ 3928 soc_ptype_t sch; /* Stub Control Header */ 3929 soc_ptype_t hg_subport; /* Higig subport */ 3930 soc_ptype_t hl; /* Higig Lite */ 3931 soc_ptype_t st; /* hg | ge (Higig Lite) */ 3932 soc_ptype_t gx; /* gx (Unicore) */ 3933 soc_ptype_t xl; /* xl (Warpcore) */ 3934 soc_ptype_t xlb0; /* xlb0 (Apache PM 4x10) */ 3935 soc_ptype_t qsgmii; /* QSGMII ports */ 3936 soc_ptype_t mxq; /* MXQport (KA) */ 3937 soc_ptype_t xg; /* xg (Hyperlite + Octal Serdes) */ 3938 soc_ptype_t xq; /* xg (Unicore + Octal Serdes) */ 3939 soc_ptype_t xt; /* xport cores based port */ 3940 soc_ptype_t xw; /* clp-lite cores based port */ 3941 soc_ptype_t cl; /* cport and xport cores based port */ 3942 soc_ptype_t clg2; /* clport-gen2 based port */ 3943 soc_ptype_t cxx; /* cxxport - PM 12x10 */ 3944 soc_ptype_t cpri; /* CPRI ports */ 3945 soc_ptype_t rsvd4; /* RSVD4 ports */ 3946 soc_ptype_t c; /* cport cores based port */ 3947 soc_ptype_t lbport; /* loopback port */ 3948 soc_ptype_t rdbport; /* Re-direction port (EP Redir V2) */ 3949 soc_ptype_t faeport; /* Flow Analytics Engine Port */ 3950 soc_ptype_t macsecport; /* macsec port */ 3951 soc_ptype_t axp; /* Auxilliary port */ 3952 soc_ptype_t hyplite; /* Hyperlite ports */ 3953 soc_ptype_t mmu; /* Internal to the MMU only */ 3954 soc_ptype_t spi; /* spi interface port */ 3955 soc_ptype_t spi_subport; /* spi subport */ 3956 soc_ptype_t sci; /* fabric control */ 3957 soc_ptype_t sfi; /* fabric data */ 3958 soc_ptype_t req; /* requeue port */ 3959 soc_ptype_t tdm; /* TDM port */ 3960 soc_ptype_t rcy; /* RCY port */ 3961 soc_ptype_t cd; /* CD Port cores based port */ 3962 3963 soc_ptype_t port; /* fe|ge|xe|hg|spi|fl */ 3964 soc_ptype_t ether; /* fe|ge|xe */ 3965 soc_ptype_t all; /* fe|ge|xe|hg|cmic|fl */ 3966 soc_ptype_t pp; /* Packet Processing Port */ 3967 soc_ptype_t lp; /* Link PHY Port */ 3968 soc_ptype_t subtag; /* SubTag Port */ 3969 soc_ptype_t intp; /* Internal processor Port */ 3970 soc_ptype_t lbgport; /* Link bonding group port */ 3971 int num_coe_modules; /* Number of COE modules */ 3972 int max_subport_coe_groups; /* Max number of subpoort coe groups */ 3973 int max_subport_coe_ports; /* Max number of subport coe ports */ 3974 pbmp_t roe_compression; /* bitmap of ports where roe compression is enabled */ 3975 pbmp_t cmic_bitmap; /* cmic bitmap */ 3976 pbmp_t lmd_pbm; /* LMD port bitmap */ 3977 pbmp_t spi_bitmap; /* spi bitmap */ 3978 pbmp_t s_pbm; /* 2.5 Gpbs Comboserdes ports */ 3979 pbmp_t gmii_pbm; /* GMII port bitmap */ 3980 pbmp_t hg2_pbm; /* HiGig2 encap port bitmap */ 3981 pbmp_t lb_pbm; /* Internal loopback ports */ 3982 pbmp_t mmu_pbm; /* Ports internal to the MMU */ 3983 pbmp_t eq_pbm; /* Extended queuing ports */ 3984 pbmp_t management_pbm; /* Management ports */ 3985 pbmp_t oversub_pbm; /* Oversubscription ports */ 3986 pbmp_t pbm_ext_mem; /* Pors with buffer in exteral DRAM*/ 3987 pbmp_t xpipe_pbm; /* Ports in X-pipe */ 3988 pbmp_t ypipe_pbm; /* Ports in Y-pipe */ 3989 pbmp_t pipe_pbm[SOC_MAX_NUM_PIPES]; /* Ports in each pipe */ 3990 pbmp_t tdm_pbm; /* TDM port bitmap */ 3991 pbmp_t rcy_pbm; /* recycling port bitmap */ 3992 pbmp_t physical_pbm; /* physical port bitmap */ 3993 pbmp_t linkphy_pbm; /* LinkPHY enabled port bitmap */ 3994 pbmp_t subtag_pbm; /* 3rd Vlan SubTag enabled port bitmap */ 3995 pbmp_t subtag_allowed_pbm; /* port bitmap on which 3rd Vlan SubTag is allowed at runtime */ 3996 pbmp_t linkphy_allowed_pbm; /* port bitmap on which LinkPHY enable/disable is allowed at runtime */ 3997 pbmp_t linkphy_pp_port_pbm; /* pp_port bitmap reserved for LinkPHY*/ 3998 pbmp_t enabled_linkphy_pp_port_pbm; /* pp_port bitmap reserved for LinkPHY, which are also enabled */ 3999 pbmp_t subtag_pp_port_pbm; /* pp_port bitmap reserved for SubTag*/ 4000 pbmp_t enabled_subtag_pp_port_pbm; /* pp_port bitmap reserved for SubTag, which are also enabled */ 4001 pbmp_t general_pp_port_pbm; /* pp_port_bitmap to be used for general purpose */ 4002 pbmp_t enabled_general_pp_port_pbm; /* pp_port_bitmap reserved for general purpose, which are also enabled */ 4003 int linkphy_enabled; /* LinkPHY enabled status */ 4004 int subtag_enabled; /* SubTag enabled status */ 4005 int coe_stacking_mode; /* CoE stacking mode enabled */ 4006 int physical_port_offset; /* first physical port of direct mapping*/ 4007 int lb_port; /* loopback port */ 4008 int rdb_port; /* Redirection port (EP Redir v2) */ 4009 int fae_port; /* Flow Analytics Engine port */ 4010 int macsec_port; /* Redirection port (EP Redir v2) */ 4011 uint16 pcie_phy_addr; /* MDIO Address of the PCIE Phy*/ 4012 int management_port; /* 1G managment port */ 4013 int axp_port[SOC_AXP_NLF_NUM]; /* AXP NLF ports */ 4014 int ipic_port; /* ipic port or -1 */ 4015 int ipic_block; /* ipic block or -1 */ 4016 int olp_port[MAX_NUM_OF_CORES]; /* offload processor port */ 4017 int erp_port[MAX_NUM_OF_CORES]; /* egress replocation port */ 4018 int oamp_port[MAX_NUM_OF_CORES]; /* OAM processor port */ 4019 int rcpu_port; /* RCPU communication port */ 4020 int rcy_port_start; /* recycling port start */ 4021 int rcy_port_count; /* number of recycling ports */ 4022 int cmic_port; /* cmic port */ 4023 int cmic_block; /* cmic block */ 4024 int arl_block; /* arl block */ 4025 int mmu_block; /* mmu block */ 4026 int mmu_glb_block; /* mmu global block */ 4027 int mmu_xpe_block; /* mmu crosspoint element block */ 4028 int mmu_sc_block; /* mmu slice control block */ 4029 int mmu_sed_block; /* mmu slice control enqueue dequeue block */ 4030 int mmu_itm_block; /*TH3_MMU: mmu ingress tile block*/ 4031 int mmu_eb_block; /*TH3_MMU: mmu egress buffer block*/ 4032 int mcu_block; /* mcu block */ 4033 int ipipe_block; /* ipipe block (FB) */ 4034 int ipipe_hi_block; /* ipipe_hi block (FB) */ 4035 int epipe_block; /* epipe block (FB) */ 4036 int epipe_hi_block; /* epipe_hi block (FB) */ 4037 int igr_block; /* Ingress block (ER) */ 4038 int egr_block; /* Egress block (ER) */ 4039 int bse_block; /* bse block (ER) */ 4040 int cse_block; /* cse block (ER) */ 4041 int hse_block; /* hse block (ER) */ 4042 int bsafe_block; /* BSAFE block (FB/ER) */ 4043 int otpc_block[SOC_MAX_NUM_OTPC_BLKS]; /* OTPC block (Raven) */ 4044 int esm_block; /* External Search Machine block (TR) */ 4045 int pgw_cl_block[8]; /* PGW_CL blocks */ 4046 int pg4_block[2]; /* PORT_GROUP4 blocks (TD) */ 4047 int pg5_block[2]; /* PORT_GROUP5 blocks (TD) */ 4048 int exp_port; /* expansion port or -1 */ 4049 int exp_block; /* expansion block or -1 */ 4050 int spi_port; /* spi port */ /* Add for Robo */ 4051 int spi_block; /* spi block */ 4052 int inter_block; /* internal mii block*/ 4053 int exter_block; /* external mii block*/ 4054 int ms_isec_block[2]; /* MACSEC ISEC */ 4055 int ms_esec_block[2]; /* MACSEC ESEC */ 4056 int il_block[SOC_MAX_NUM_ILPORT_BLKS]; /* Interlaken blocks */ 4057 int top_block; 4058 int ser_block; 4059 int avs_block; 4060 int axp_block; 4061 int ism_block; 4062 int etu_block; 4063 int etu_wrap_block; 4064 int ibod_block; 4065 int lls_block; /* link list scheduler block */ 4066 int ces_block; /* Circuit Emulation Service Interface */ 4067 int cev_block; /* Counter Eviction block */ 4068 int cw; /* CW Block */ 4069 int iproc_block; 4070 int crypto_block; 4071 int pgw_ge_block[3]; /* PGW_GE blocks*/ 4072 /* Katana2 and Greyhound2 only blocks */ 4073 int ci_block[SOC_MAX_NUM_CI_BLKS]; /* ci blocks */ 4074 int clport_block[SOC_MAX_NUM_CLPORT_BLKS]; /* clport block */ 4075 int taf_block; 4076 int txlp_block[SOC_MAX_NUM_TXLP_BLKS]; 4077 int rxlp_block[SOC_MAX_NUM_RXLP_BLKS]; 4078 int pmq_block[SOC_MAX_NUM_PMQ_BLKS]; 4079 int nof_pmqs; 4080 4081 /* DPP & DFE blocks */ 4082 int cfc_block[SOC_MAX_NUM_CFC_BLKS]; 4083 int ocb_blocks[SOC_MAX_NUM_OCB_BLKS]; 4084 int crps_blocks[SOC_MAX_NUM_CRPS_BLKS]; 4085 int epre_blocks[SOC_MAX_NUM_EPRE_BLKS]; 4086 int ippf_blocks[SOC_MAX_NUM_IPPF_BLKS]; 4087 int mdb_arm_block; 4088 int cdport_block[SOC_MAX_NUM_CDPORT_BLKS]; 4089 int cdmac_block[SOC_MAX_NUM_CDMAC_BLKS]; 4090 int fdtl_block; 4091 int eci_block; 4092 int egq_blocks[SOC_MAX_NUM_EGQ_BLKS]; 4093 int fcr_block; 4094 int fct_block; 4095 int fdr_blocks[SOC_MAX_NUM_FDR_BLKS]; 4096 int fda_block; 4097 int fdt_block; 4098 int mesh_topology_block; 4099 int idr_block; 4100 int ihb_blocks[SOC_MAX_NUM_IHB_BLKS]; 4101 int ihp_blocks[SOC_MAX_NUM_IHP_BLKS]; 4102 int ips_blocks[SOC_MAX_NUM_IPS_BLKS]; 4103 int ipt_blocks[SOC_MAX_NUM_ILKN_PML_BLKS]; 4104 int iqm_blocks[SOC_MAX_NUM_IQM_BLKS]; 4105 int pqp_blocks[SOC_MAX_NUM_PQP_BLKS]; 4106 int ire_blocks[SOC_MAX_NUM_ILKN_PML_BLKS]; 4107 int irr_block; 4108 int fmac_block[SOC_MAX_NUM_FMAC_BLKS]; 4109 int xlp_block[SOC_MAX_NUM_XLP_BLKS]; 4110 int clp_block[SOC_MAX_NUM_CLP_BLKS]; 4111 int nbi_block; 4112 int nif_block; 4113 int cgm_blocks[SOC_MAX_NUM_CGM_BLKS]; 4114 int oamp_block; 4115 int olp_block; 4116 int sif_blocks[SOC_MAX_NUM_SIF_BLKS]; 4117 int mcp_blocks[SOC_MAX_NUM_MCP_BLKS]; 4118 int itpp_blocks[SOC_MAX_NUM_ITPP_BLKS]; 4119 int itppd_blocks[SOC_MAX_NUM_ITPPD_BLKS]; 4120 int pdm_blocks[SOC_MAX_NUM_PDM_BLKS]; 4121 int cdu_block[SOC_MAX_NUM_CDU_BLKS]; 4122 int cdum_blocks[SOC_MAX_NUM_CDUM_BLKS]; 4123 int eps_blocks[SOC_MAX_NUM_EPS_BLKS]; 4124 int hbmc_block[SOC_MAX_NUM_HBMC_BLKS]; 4125 int ilu_block[SOC_MAX_NUM_ILU_BLKS]; 4126 int nmg_blocks[SOC_MAX_NUM_NMG_BLKS]; 4127 4128 int ddha_block[SOC_MAX_NUM_DDHA_BLKS]; 4129 int ddhb_block[SOC_MAX_NUM_DDHB_BLKS]; 4130 int dhc_block[SOC_MAX_NUM_DHC_BLKS]; 4131 int dmu_block[SOC_MAX_NUM_DMU_BLKS]; 4132 int etppc_blocks[SOC_MAX_NUM_ETPPC_BLKS]; 4133 int evnt_block[SOC_MAX_NUM_EVNT_BLKS]; 4134 int hbc_block[SOC_MAX_NUM_HBC_BLKS]; 4135 int ile_blocks[SOC_MAX_NUM_ILE_BLKS]; 4136 int clu_blocks[SOC_MAX_NUM_CLU_BLKS]; 4137 int clup_blocks[SOC_MAX_NUM_CLUP_BLKS]; 4138 int clmac_blocks[SOC_MAX_NUM_CLMAC_BLKS]; 4139 int esb_block; 4140 int ippe_blocks[SOC_MAX_NUM_IPPE_BLKS]; 4141 int tcam_blocks[SOC_MAX_NUM_TCAM_BLKS]; 4142 int tdu_blocks[SOC_MAX_NUM_TDU_BLKS]; 4143 4144 int bdm_blocks[SOC_MAX_NUM_BDM_BLKS]; 4145 int mtm_block; 4146 int hbm_block[SOC_MAX_NUM_HBM_BLKS]; 4147 int rqp_blocks[SOC_MAX_NUM_RQP_BLKS]; 4148 int fqp_blocks[SOC_MAX_NUM_FQP_BLKS]; 4149 int mdb_block; 4150 int erpp_blocks[SOC_MAX_NUM_ERPP_BLKS]; 4151 int etppa_blocks[SOC_MAX_NUM_ETPPA_BLKS]; 4152 int etppb_blocks[SOC_MAX_NUM_ETPPB_BLKS]; 4153 int mact_block; 4154 int ippa_blocks[SOC_MAX_NUM_IPPA_BLKS]; 4155 int ippb_blocks[SOC_MAX_NUM_IPPB_BLKS]; 4156 int ippc_blocks[SOC_MAX_NUM_IPPC_BLKS]; 4157 int ippd_blocks[SOC_MAX_NUM_IPPD_BLKS]; 4158 int fsrd_block[SOC_MAX_NUM_FSRD_BLKS]; 4159 int rtp_block; 4160 int sch_blocks[SOC_MAX_NUM_SCH_BLKS]; 4161 int epni_blocks[SOC_MAX_NUM_EPNI_BLKS]; 4162 int mrps_blocks[SOC_MAX_NUM_MRPS_BLKS]; 4163 int mtrps_em_blocks[SOC_MAX_NUM_MTRPS_EM_BLKS]; 4164 int drca_block; 4165 int drcb_block; 4166 int drcc_block; 4167 int drcd_block; 4168 int drce_block; 4169 int drcf_block; 4170 int drcg_block; 4171 int drch_block; 4172 int drcbroadcast_block; 4173 int iecell_block[SOC_MAX_NUM_IECELL_BLKS]; 4174 int occg_block; 4175 int dch_block[SOC_MAX_NUM_DCH_BLKS]; 4176 int dcl_block[SOC_MAX_NUM_DCL_BLKS]; 4177 int dcma_block[SOC_MAX_NUM_DCMA_BLKS]; 4178 int dcmb_block[SOC_MAX_NUM_DCMB_BLKS]; 4179 int dcmc_block; 4180 int ccs_block[SOC_MAX_NUM_CCS_BLKS]; 4181 int edb_blocks[SOC_MAX_NUM_ILKN_PML_BLKS]; 4182 int ilkn_pmh_block; 4183 int ipst_block; 4184 int ilkn_pml_block[SOC_MAX_NUM_ILKN_PML_BLKS]; 4185 int iqmt_block; 4186 int kaps_blocks[SOC_MAX_NUM_ILKN_PML_BLKS]; 4187 int kaps_mi_block[SOC_MAX_NUM_KAPS_MI_BLKS]; 4188 int ilb_block; 4189 int iep_block; 4190 int imp_block; 4191 int spb_blocks[SOC_MAX_NUM_ILKN_PML_BLKS]; 4192 int ite_block; 4193 int ddp_blocks[SOC_MAX_NUM_DDP_BLKS]; 4194 int txq_block; 4195 int tar_block; 4196 int pts_block; 4197 int sqm_blocks[SOC_MAX_NUM_ILKN_PML_BLKS]; 4198 int ipsec_block; 4199 int ipsec_spu_wrapper_top_blocks[SOC_MAX_NUM_IPSEC_SPU_WRAPPER_TOP_BLKS]; 4200 int mxq_block[SOC_MAX_NUM_MXQ_BLKS]; 4201 int kaps_bbs_blocks[SOC_MAX_NUM_KAPS_BBS_BLKS]; 4202 int pll_block; 4203 int dqm_blocks[SOC_MAX_NUM_DQM_BLKS]; 4204 int ecgm_blocks[SOC_MAX_NUM_ECGM_BLKS]; 4205 int idb_block; 4206 int pem_blocks[SOC_MAX_NUM_PEM_BLKS]; 4207 4208 int ppdb_a_block; 4209 int ppdb_b_block; 4210 int nbil_block[SOC_MAX_NUM_NBIL_BLKS]; 4211 int nbih_block; 4212 int brdc_fmach_block; 4213 int brdc_fmacl_block; 4214 int brdc_fsrd_block; 4215 int brdc_kaps_bbs_block; 4216 int brdc_mrps_block; 4217 int brdc_mtrps_em_block; 4218 int brdc_ipsec_spu_wrapper_top_block; 4219 int gport_block[SOC_MAX_NUM_GPORT_BLKS]; 4220 /* fe 3200 blocks*/ 4221 int dcm_block[SOC_MAX_NUM_DCM_BLKS]; 4222 int brdc_dch_block; 4223 int brdc_dcm_block; 4224 int brdc_dcl_block; 4225 int brdc_ccs_block; 4226 int brdc_fmac_ac_block; 4227 int brdc_fmac_bd_block; 4228 int brdc_fmac_block; 4229 int brdc_hbc_block; 4230 int brdc_cgm_block; 4231 int brdc_egq_block; 4232 int brdc_epni_block; 4233 int brdc_ihb_block; 4234 int brdc_ihp_block; 4235 int brdc_ips_block; 4236 int brdc_iqm_block; 4237 int brdc_sch_block; 4238 int p3_cfg_block; 4239 int p3_em_block; 4240 int p3_table_block; 4241 int p3_tcam_block; 4242 int macsec_block; 4243 int prm_block; 4244 int blh_block[SOC_MAX_NUM_BLH_BLKS]; 4245 int am_top_block; 4246 /* Ramon blocks*/ 4247 int dcml_block[SOC_MAX_NUM_DCML_BLKS]; 4248 int mct_block; 4249 int qrh_block[SOC_MAX_NUM_QRH_BLKS]; 4250 int cch_block[SOC_MAX_NUM_CCH_BLKS]; 4251 int lcm_block[SOC_MAX_NUM_LCM_BLKS]; 4252 int brdc_cch_block; 4253 int brdc_dcml_block; 4254 int brdc_lcm_block; 4255 int brdc_qrh_block; 4256 4257 soc_block_t has_block[SOC_MAX_NUM_BLKS]; /* list of all blocks */ 4258 /* 4259 * The broadcast_blocks pointer will be null for blocks that are not broadcast blocks. 4260 * For broadcast block it points to an array of the block indexes of the blocks written to when writing to the broadcast block. 4261 * The size of the array (number of broadcast members) can be found using broadcast_blocks_size. 4262 */ 4263 int *broadcast_blocks[SOC_MAX_NUM_BLKS]; 4264 uint8 broadcast_blocks_size[SOC_MAX_NUM_BLKS]; 4265 int port_offset[SOC_MAX_NUM_PORTS]; /* 3 for ge3 */ 4266 int port_init_speed[SOC_MAX_NUM_PORTS]; /* ports initial speed */ 4267 int port_speed_max[SOC_MAX_NUM_PORTS]; /* max port speed */ 4268 int port_osg_bitmap[SOC_MAX_NUM_PORTS]; /* oversub speed group bitmap */ 4269 int port_pipe[SOC_MAX_NUM_PORTS]; /* pipe number */ 4270 int port_group[SOC_MAX_NUM_PORTS]; /* group number */ 4271 int port_serdes[SOC_MAX_NUM_PORTS]; /* serdes number */ 4272 int port_num_subport[SOC_MAX_NUM_PORTS]; /* number of subport */ 4273 int port_subport_base[SOC_MAX_NUM_PORTS];/* subport base */ 4274 int port_linkphy_s1_base[SOC_MAX_NUM_PORTS];/* s1 base for LinkPHY */ 4275 #if defined(BCM_ESW_SUPPORT) && (SOC_MAX_NUM_PP_PORTS > SOC_MAX_NUM_PORTS) 4276 char port_name[SOC_MAX_NUM_PP_PORTS][SOC_DRV_PORT_NAME_MAX]; 4277 char port_name_alter[SOC_MAX_NUM_PP_PORTS][SOC_DRV_PORT_NAME_MAX]; 4278 uint8 port_name_alter_valid[SOC_MAX_NUM_PP_PORTS]; 4279 int port_type[SOC_MAX_NUM_PP_PORTS]; 4280 int port_num_cosq[SOC_MAX_NUM_PP_PORTS]; /* cosq/mcast cosq */ 4281 int port_cosq_base[SOC_MAX_NUM_PP_PORTS]; /* cosq/mcast cosq base */ 4282 int port_num_uc_cosq[SOC_MAX_NUM_PP_PORTS]; /* ucast cosq */ 4283 int port_uc_cosq_base[SOC_MAX_NUM_PP_PORTS]; /* ucast cosq base */ 4284 int port_num_ext_cosq[SOC_MAX_NUM_PP_PORTS]; /* ext ucast cosq */ 4285 int port_ext_cosq_base[SOC_MAX_NUM_PP_PORTS]; /* ext ucast cosq base */ 4286 #else 4287 char port_name[SOC_MAX_NUM_PORTS][SOC_DRV_PORT_NAME_MAX]; 4288 char port_name_alter[SOC_MAX_NUM_PORTS][SOC_DRV_PORT_NAME_MAX]; 4289 uint8 port_name_alter_valid[SOC_MAX_NUM_PORTS]; 4290 int port_type[SOC_MAX_NUM_PORTS]; 4291 int port_num_cosq[SOC_MAX_NUM_PORTS]; /* cosq/mcast cosq */ 4292 int port_cosq_base[SOC_MAX_NUM_PORTS]; /* cosq/mcast cosq base */ 4293 int port_num_uc_cosq[SOC_MAX_NUM_PORTS]; /* ucast cosq */ 4294 int port_uc_cosq_base[SOC_MAX_NUM_PORTS]; /* ucast cosq base */ 4295 int port_num_ext_cosq[SOC_MAX_NUM_PORTS]; /* ext ucast cosq */ 4296 int port_ext_cosq_base[SOC_MAX_NUM_PORTS]; /* ext ucast cosq base */ 4297 #endif 4298 int port_p2l_mapping[SOC_MAX_NUM_PORTS]; /* phy to logic */ 4299 int flex_port_p2l_mapping[SOC_MAX_NUM_PORTS]; /* flex(current) phy to logic */ 4300 int port_l2p_mapping[SOC_MAX_NUM_PORTS]; /* logic to phy */ 4301 int port_l2pp_mapping[SOC_MAX_NUM_PORTS]; /* logic to primary port in external PHY */ 4302 int port_l2po_mapping[SOC_MAX_NUM_PORTS]; /* logic to port offset in external PHY */ 4303 int port_l2pa_mapping[SOC_MAX_NUM_PORTS]; /* logic to phy address in external PHY */ 4304 int port_l2i_mapping[SOC_MAX_NUM_PORTS]; /* logic to idb */ 4305 int port_p2m_mapping[SOC_MAX_NUM_PORTS]; /* phy to mmu */ 4306 int max_port_p2m_mapping[SOC_MAX_NUM_PORTS]; /* max(flex) phy to mmu */ 4307 int port_m2p_mapping[SOC_MAX_NUM_MMU_PORTS]; /* mmu to phy */ 4308 int port_num_lanes[SOC_MAX_NUM_PORTS]; /* number of lanes */ 4309 int port_refclk_int[SOC_MAX_NUM_PORTS]; /*internal phy refclk*/ 4310 soc_100g_lane_config_t port_100g_lane_config[SOC_MAX_NUM_PORTS]; /*Phy active lane assignment*/ 4311 int port_fallback_lane[SOC_MAX_NUM_PORTS]; /*lane used when 100G port Auto Negotiates down*/ 4312 int phy_port_base[2]; /* per pipe physical port base */ 4313 int mmu_port_base[2]; /* per pipe mmu port base */ 4314 uint32 ipipe_xpe_map[SOC_MAX_NUM_PIPES]; 4315 uint32 epipe_xpe_map[SOC_MAX_NUM_PIPES]; 4316 uint32 xpe_ipipe_map[4]; 4317 uint32 xpe_epipe_map[4]; 4318 uint32 ipipe_sc_map[SOC_MAX_NUM_PIPES]; 4319 uint32 epipe_sc_map[SOC_MAX_NUM_PIPES]; 4320 uint32 sc_ipipe_map[2]; 4321 uint32 sc_epipe_map[2]; 4322 uint32 ipipe_sed_map[SOC_MAX_NUM_PIPES]; 4323 uint32 epipe_sed_map[SOC_MAX_NUM_PIPES]; 4324 uint32 sed_ipipe_map[2]; 4325 uint32 sed_epipe_map[2]; 4326 char block_valid[SOC_MAX_NUM_BLKS]; /* is block used? */ 4327 pbmp_t block_bitmap[SOC_MAX_NUM_BLKS]; 4328 int block_port[SOC_MAX_NUM_BLKS]; 4329 char block_name[SOC_MAX_NUM_BLKS][16]; 4330 int mem_block_any[NUM_SOC_MEM]; 4331 int *blk_fpp; /* blk to first physical port mapping */ 4332 int bandwidth; /* max core bandwidth */ 4333 int io_bandwidth; /* max io bandwidth */ 4334 int frequency; /* core clock frequency */ 4335 int dpp_clk_ratio_x10; /* core_clk x 10 : dpp_clk ratio */ 4336 int modid_count; /* needed modids */ 4337 int modid_max; /* maximum modid supported */ 4338 int modport_max; /* max port id in each module */ 4339 int modport_max_first; /* max port id in first module 4340 * for asymmetric dual modid */ 4341 int port_class_max; /* Number of supported port classes */ 4342 int trunk_bit_pos; /* Bit-0 is 0 */ 4343 uint32 vlan_xlate_glp_wildcard; /* Value of GLP_WILDCARD per chip */ 4344 int port_addr_max; /* max addressable ports */ 4345 int hg_offset; /* offset of hg ports in pbmp */ 4346 int cpu_hg_index; /* table index for cpu port 4347 * higig packet where table indexed 4348 * by physical port*/ 4349 int cpu_hg_pp_port_index; /* table index for cpu port higig 4350 * packet where table indexed by 4351 * pp_port */ 4352 int num_pipe; /* number of pipeline */ 4353 int num_xpe; /* number of crosspoint element */ 4354 int num_itm; /* TH3_MMU:number of itm */ 4355 int num_eb; /* number of crosspoint element */ 4356 int num_slice; /* number of slice */ 4357 int num_sed; /* number of sed */ 4358 int num_layer; /* number of layer */ 4359 int num_cpu_cosq; /* number of cpu cosq */ 4360 int num_mmu_base_cosq; /* number of MMU base cosq */ 4361 int num_time_interface; /* number of time sync interfaces */ 4362 int num_ucs; /* number of uCs */ 4363 int internal_loopback; /* internal loopback non-zero BW */ 4364 char lock_info[128]; /* lock debug info */ 4365 int flex_eligible; /* config eligible for flex trans */ 4366 int fabric_port_enable; /* If set, HG port speeds are supported */ 4367 int num_flex_ingress_pools; /* number of ingress pools */ 4368 int size_flex_ingress_pool; /* size of ingress pools */ 4369 int num_flex_egress_pools; /* number of egress pools */ 4370 int size_flex_egress_pool; /* size of egress pools */ 4371 int global_meter_pools; /* number of global meter pools*/ 4372 int global_meter_size_of_pool; /* Size of each pool */ 4373 int global_meter_max_size_of_pool; /* Maximum size of each pool */ 4374 int global_meter_action_size; /* Size of global meter action */ 4375 int global_meter_tcam_size; /* Size of global meter tcam */ 4376 int global_meter_offset_mode_max; /* Max global meter offset_mode */ 4377 int fabric_logical_port_base; /* first fabric port */ 4378 4379 4380 /* MAX_SFLOW_RANGE is used for converting a sampling rate to a threshold 4381 * value used for comparison with the sFlow random number for a port. 4382 * If the random number is less than the threshold value, an sFlow 4383 * sample record is sent to the CPU. 4384 */ 4385 int sflow_range_max; 4386 int nat_id_max; /* Max NAT packet edit entries */ 4387 /* MMU Lossless mode. Applicable for chip which depends on soc property 4388 * spn_MMU_LOSSLESS. 4389 * Values: -1(un-initialized default value), 0(lossy), 1(lossless) 4390 */ 4391 int8 mmu_lossless; 4392 soc_reg_access_t reg_access; 4393 soc_custom_reg_access_t custom_reg_access; 4394 int max_mtu; /*max size of system mtu*/ 4395 #if defined(BCM_TRIUMPH3_SUPPORT) 4396 int port_credit[SOC_MAX_NUM_PORTS]; 4397 #endif 4398 4399 /* pm_ref_master_bitmap is the bitmap of port macros that will driven 4400 * directly from the system board and will act as the refclk master 4401 * to drive the other instances. 4402 */ 4403 SHR_BITDCL pm_ref_master_bitmap[_SHR_BITDCLSIZE(SOC_MAX_NUM_BLKS)]; 4404 int fp_hg_port_offset; /* FP table index offset of higig port */ 4405 #ifdef BCM_TOMAHAWK_SUPPORT 4406 int th_tflow_enabled; /* Tomahawk targeted flow */ 4407 int th_ctc_replace_enabled; /* Tomahawk CTC replace flag */ 4408 #endif /* BCM_TOMAHAWK_SUPPORT */ 4409 #if defined(BCM_KATANA2_SUPPORT) 4410 int subport_group_max; /* Max number of subport group */ 4411 int pp_port_index_max; /* Max number of pp port index */ 4412 int pp_port_index_min; /* Min number of pp port index */ 4413 int subport_index_min; /* Min subport index */ 4414 int subport_port_max; /* Max number of subports */ 4415 /* LinkPhy related variables */ 4416 int lp_tx_databuf_start_addr_max; /* Tx data buffer */ 4417 int lp_tx_databuf_end_addr_min; 4418 int lp_tx_databuf_end_addr_max; 4419 int lp_tx_stream_start_addr_offset; 4420 int lp_block_max; /* Max number of linkphy blocks */ 4421 int lp_ports_max; /* Max LP ports in all blocks */ 4422 int lp_streams_per_slice_max; /* Max streams per slice */ 4423 int lp_streams_per_port_max; /* Max streams per slice */ 4424 int lp_streams_per_subport; /* Max streams per subport */ 4425 #endif 4426 #if defined(BCM_METROLITE_SUPPORT) 4427 pbmp_t pp_port_bitmap[SOC_MAX_NUM_PORTS]; /* Free PP Port Bitmap for physical port */ 4428 #endif 4429 4430 /* flexible_pm_bitmap is the bitmap of port macros that support 4431 * flex port. 4432 */ 4433 SHR_BITDCL flexible_pm_bitmap[_SHR_BITDCLSIZE(SOC_MAX_NUM_BLKS)]; 4434 /* pm_max_ports is the max number of ports that the port macro could flex to. 4435 */ 4436 uint32 pm_max_ports[SOC_MAX_NUM_BLKS]; 4437 /* device oversubscription mode 4438 * 0 - linerate only; 1 - oversubscription only; 2 - mix 4439 */ 4440 int oversub_mode; 4441 4442 /* device oversubscribe mixed-sister 25/50G port config enable 4443 * 0 - disable; 1- enable 4444 */ 4445 int os_mixed_sister_25_50_enable; 4446 /* Bitmap of 25G port use 50G TDM calendar */ 4447 pbmp_t pbm_25g_use_50g_tdm; 4448 4449 /*Ipipe ITM maps required for tomahawk3*/ 4450 uint32 itm_ipipe_map[2]; /*Required for 2 ITMs. 4451 *Used constant value similar to XPE maps 4452 */ 4453 uint32 itm_map; 4454 uint32 ipipe_itm_map[SOC_MAX_NUM_PIPES]; 4455 4456 /* VCO information for each of the port macros. 4457 * Each PM may have different VCO settings depending on the speeds 4458 * required of that PM, so each bit represents a different VCO 4459 * 4460 * Tomahawk 3 has a total of 3 selectable VCOs (Voltage-controlled oscillator) 4461 * to determine the speed of the ports: PAM-4, 25G-NRZ, and 10G-NRZ. 4462 * 2 may be selected at a time. 4463 */ 4464 soc_pmvco_info_t pm_vco_info[SOC_MAX_NUM_BLKS]; 4465 4466 /* Additional speed configuration parameters required for 4467 * port macros that need them. */ 4468 /* Forward Error Correction type */ 4469 int port_fec_type[SOC_MAX_NUM_PORTS]; 4470 /* Serdes pmd lane config */ 4471 int port_phy_lane_config[SOC_MAX_NUM_PORTS]; 4472 /* Link Training on or off */ 4473 int port_link_training[SOC_MAX_NUM_PORTS]; 4474 int num_modules; /* Number of modules */ 4475 4476 #if defined(BCM_HELIX5_SUPPORT) 4477 uint8 hx5_chip_config_war_enable; 4478 uint32 hx5_chip_config_address; 4479 #endif /* BCM_HELIX5_SUPPORT */ 4480 4481 } soc_info_t; 4482 4483 4484 typedef int (*soc_rcpu_schan_op_cb)( 4485 int unit, 4486 schan_msg_t *msg, 4487 int dwc_write, 4488 int dwc_read); 4489 4490 extern int soc_rcpu_schan_op_register(int unit, soc_rcpu_schan_op_cb f); 4491 extern int soc_rcpu_schan_op_unregister(int unit); 4492 4493 4494 typedef void (*soc_event_cb_t)( 4495 int unit, 4496 soc_switch_event_t event, 4497 uint32 arg1, 4498 uint32 arg2, 4499 uint32 arg3, 4500 void *userdata); 4501 4502 typedef struct list_event_cb_s { 4503 soc_event_cb_t cb; 4504 void *userdata; 4505 struct list_event_cb_s *next; 4506 }soc_event_cb_list_t; 4507 4508 extern int soc_event_register(int unit, soc_event_cb_t cb, void *userdata); 4509 extern int soc_event_unregister(int unit, soc_event_cb_t cb, void *userdata); 4510 extern int soc_event_generate(int unit, soc_switch_event_t event, 4511 uint32 arg1, uint32 arg2, uint32 arg3); 4512 extern void soc_event_assert(const char *expr, const char *file, int line); 4513 4514 4515 4516 #ifdef BCM_WARM_BOOT_SUPPORT 4517 extern int soc_scache_esw_nh_mem_write(int unit, uint8 *buf, 4518 int offset, int nbytes); 4519 extern int soc_scache_esw_nh_mem_read(int unit, uint8 *buf, 4520 int offset, int nbytes); 4521 4522 #ifdef BROADCOM_DEBUG 4523 extern int soc_scache_file_close(void); 4524 extern int soc_scache_file_open(int unit, int warm_boot); 4525 #endif /* BROADCOM_DEBUG */ 4526 4527 extern int soc_switch_control_scache_init(int unit); 4528 extern int soc_switch_control_scache_sync(int unit); 4529 4530 #endif /* BCM_WARM_BOOT_SUPPORT */ 4531 4532 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 4533 /*Structures for UC message receive LL*/ 4534 /*LL Node*/ 4535 typedef struct ll_element_s { 4536 struct ll_element_s *p_next; 4537 struct ll_element_s *p_prev; 4538 }ll_element_t; 4539 4540 /* Doubly linked list ctrl structure*/ 4541 typedef struct ll_ctrl_s { 4542 ll_element_t *p_head; /* pointer to the first element */ 4543 ll_element_t *p_tail; /* pointer to the last element */ 4544 uint32 ll_count; /* the number of elements the list */ 4545 }ll_ctrl_t; 4546 4547 typedef struct mos_msg_ll_node_s { 4548 ll_element_t msg_q; /*LL linkage*/ 4549 mos_msg_data_t msg_data; /*Msg Data*/ 4550 }mos_msg_ll_node_t; 4551 #endif 4552 4553 /* SOC DMA mode definitions */ 4554 /* Continuous mode uses reload descriptors to chain DVs */ 4555 typedef enum soc_dma_mode_e { 4556 SOC_DMA_MODE_CHAINED = 0, /* Legacy CMIC devices */ 4557 SOC_DMA_MODE_CONTINUOUS = 1 /* CMICDV2 */ 4558 } soc_dma_mode_t; 4559 4560 typedef struct soc_latency_monitor_info_s { 4561 int32 time_step; 4562 int8 flex_pool_number; 4563 soc_pbmp_t src_pbmp; 4564 soc_pbmp_t dest_pbmp; 4565 } soc_latency_monitor_info_t; 4566 4567 4568 #if 0 4569 #ifdef SOC_L3_ECMP_PROTECTED_ACCESS_SUPPORT 4570 typedef struct soc_ecmp_group_info_s { 4571 int ecmp_grp; 4572 int ecmp_member_base; 4573 int max_paths; /* Maximum number of ECMP paths per group. */ 4574 uint32 flags; /* Ecmp group flags */ 4575 } soc_ecmp_group_info_t; 4576 4577 typedef struct soc_ecmp_group_state_s { 4578 int count; 4579 int base; 4580 int bank; 4581 } soc_ecmp_group_state_t; 4582 4583 typedef struct soc_ecmp_state_s { 4584 #define SOC_L3_ECMP_MAX_BANKS 0x8 4585 #define SOC_L3_ECMP_MAX_GROUPS 4095 4586 int ecmp_member_banks; 4587 int ecmp_members_per_banks; 4588 int ecmp_bank_to_level_mapping[SOC_L3_ECMP_MAX_BANKS]; 4589 int ecmp_members_in_bank[SOC_L3_ECMP_MAX_BANKS]; 4590 int ecmp_group_state[SOC_L3_ECMP_MAX_GROUPS]; 4591 int ecmp_spare_bank_idx; 4592 } soc_ecmp_state_t; 4593 #endif /* SOC_L3_ECMP_PROTECTED_ACCESS_SUPPORT */ 4594 #endif 4595 4596 /* 4597 * Typedef: soc_control_t 4598 * Purpose: SOC Control Structure. All info about a device instance. 4599 */ 4600 4601 typedef struct soc_control_s { 4602 uint32 soc_flags; /* Flags for this device */ 4603 #define SOC_F_ATTACHED 0x01 /* Device attached */ 4604 #define SOC_F_INITED 0x02 /* Device inited */ 4605 #define SOC_F_LSE 0x04 /* Link SCAN enabled in SW */ 4606 #define SOC_F_SL_MODE 0x08 /* Device is in SL stack mode */ 4607 #define SOC_F_POLLED 0x10 /* Polled IRQ mode */ 4608 #define SOC_F_URPF_ENABLED 0x20 /* Unicast rpf enabled on device */ 4609 #define SOC_F_IPMCREPLSHR 0x40 /* IPMC replication with lists */ 4610 #define SOC_F_BUSY 0x80 /* Device is not fully out of Reset */ 4611 #define SOC_F_MEM_CLEAR_USE_DMA 0x100 /* Device should use table dma 4612 for memory clear operations */ 4613 #define SOC_F_GPORT 0x200 /* Device should use GPORT for 4614 source/destination notation */ 4615 #define SOC_F_RCPU_SCHAN 0x400 /* Indicates that SCHAN operations will 4616 be sent over RCPU mechanism */ 4617 #define SOC_F_RCPU_ONLY 0x800 /* Indicates that all access to the device 4618 will be done through RCPU */ 4619 #define SOC_F_RE_INITED 0x1000 /* Device re-inited while running */ 4620 #define SOC_F_PORT_CLASS_BLOCKED 0x2000 /* Device is not allowed to change port classes */ 4621 #define SOC_F_XLATE_EGR_BLOCKED 0x4000 /* Device is not allowed to setup old 4622 style vlan egress translate */ 4623 #define SOC_F_KNET_MODE 0x8000 /* Device is in kernel networking mode */ 4624 #define SOC_F_REMOTE_ENCAP 0x10000 /* Device is uses remote multicast encapsulation */ 4625 #define SOC_F_MEM_CLEAR_HW_ACC 0x20000 /* Device should use h/w pipe clear 4626 for memory clear operations */ 4627 #define SOC_F_ALL_MODULES_INITED 0x40000 /* System Level Init Flag */ 4628 #define SOC_F_HW_RESETING 0x80000 /* System is processing cold boot */ 4629 4630 /* Mask of flags that are persistent across init */ 4631 #define SOC_F_RESET (SOC_F_ATTACHED|SOC_F_INITED|SOC_F_POLLED|SOC_F_HW_RESETING|SOC_F_KNET_MODE) 4632 4633 /* Port and block information filled in when attached or inited */ 4634 soc_info_t info; 4635 4636 /* Currently only used by DNX devices */ 4637 void *drv; 4638 4639 /* Disable subsets of registers and memories */ 4640 uint32 disabled_reg_flags; 4641 uint32 disabled_mem_flags; 4642 4643 /* Miscellaneous chip state */ 4644 uint32 gbpMemSize; /* GBP size in bytes */ 4645 int gbpBanks; /* Number of banks, 2 or 4 */ 4646 int gbpDDR; /* Boolean for DDR vs non-DDR */ 4647 int gbpWidth; /* 128 or 64 bits wide */ 4648 int gbpFullEnable; /* GBP Full interrupts (see soc/intr.c) */ 4649 int gbpFullTime; 4650 4651 int pciParityDPC; /* True if PCI Parity Error DPC queued */ 4652 int pciFatalDPC; /* True if PCI Fatal Error DPC queued */ 4653 4654 uint32 irq_mask; /* Cached copy of CMIC_IRQ_MASK */ 4655 uint32 irq1_mask; /* Cached copy of CMIC_IRQ_MASK_1 */ 4656 uint32 irq2_mask; /* Cached copy of CMIC_IRQ_MASK_2 */ 4657 4658 uint32 switch_event_nominal_storm; 4659 4660 #ifdef BCM_DDR3_SUPPORT 4661 int ddr3_num_columns; 4662 int ddr3_num_rows; 4663 int ddr3_num_banks; 4664 int ddr3_num_memories; 4665 int ddr3_clock_mhz; 4666 int ddr3_mem_grade; 4667 int ddr3_offset_wr_dq_ci02_wl0; 4668 int ddr3_offset_wr_dq_ci00_wl1; 4669 #endif /* BCM_DDR3_SUPPORT */ 4670 4671 uint32 board_type; /* From I2C */ 4672 uint32 remote_cpu; 4673 soc_rcpu_schan_op_cb soc_rcpu_schan_op; /* RCPU SCHAN function */ 4674 4675 /* Operation Management */ 4676 4677 int pci_cmc; 4678 int cmc_num; /* Number of CMCs on this unit. */ 4679 int pci_cmc_num; /* Number of CMCs used by the PCI host */ 4680 sal_mutex_t schanMutex; /* S-Channel mutual exclusion */ 4681 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 4682 sal_mutex_t fschanMutex; /* Fast S-Channel mutual exclusion */ 4683 /* CCM DMA register mutual exclusion */ 4684 sal_mutex_t ccmDmaMutex[SOC_CMCS_NUM_MAX]; 4685 int ccmDmaTimeout; /* Operation timeout in microseconds */ 4686 sal_sem_t ccmDmaIntr[SOC_CMCS_NUM_MAX]; /* CCM DMA interrupt */ 4687 int ccmDmaIntrEnb; /* Use interrupts instead of polling */ 4688 int arm_cmc[SOC_CMCS_NUM_MAX - 1]; 4689 uint32 cmc_irq0_mask[SOC_CMCS_NUM_MAX]; /* Cached copy of CMIC_CMCx_PCIE_IRQ_MASK0 */ 4690 uint32 cmc_irq1_mask[SOC_CMCS_NUM_MAX]; /* Cached copy of CMIC_CMCx_PCIE_IRQ_MASK1 */ 4691 uint32 cmc_irq2_mask[SOC_CMCS_NUM_MAX]; /* Cached copy of CMIC_CMCx_PCIE_IRQ_MASK2 */ 4692 uint32 cmc_irq3_mask[SOC_CMCS_NUM_MAX]; /* Cached copy of CMIC_CMCx_PCIE_IRQ_MASK3 */ 4693 uint32 cmc_irq4_mask[SOC_CMCS_NUM_MAX]; /* Cached copy of CMIC_CMCx_PCIE_IRQ_MASK4 */ 4694 uint32 cmc_irq5_mask[SOC_CMCS_NUM_MAX]; /* Cached copy of CMIC_CMCx_PCIE_IRQ_MASK5 */ 4695 uint32 cmc_irq6_mask[SOC_CMCS_NUM_MAX]; /* Cached copy of CMIC_CMCx_PCIE_IRQ_MASK6 */ 4696 #ifdef BCM_RCPU_SUPPORT 4697 uint32 rpe_irq0_mask; /* Cached copy of CMIC_RPE_RCPU_IRQ_MASK0 */ 4698 uint32 rpe_irq1_mask; /* Cached copy of CMIC_RPE_RCPU_IRQ_MASK1 */ 4699 uint32 rpe_irq2_mask; /* Cached copy of CMIC_RPE_RCPU_IRQ_MASK2 */ 4700 uint32 rpe_irq3_mask; /* Cached copy of CMIC_RPE_RCPU_IRQ_MASK3 */ 4701 uint32 rpe_irq4_mask; /* Cached copy of CMIC_RPE_RCPU_IRQ_MASK4 */ 4702 uint32 rpe_irq5_mask; /* Cached copy of CMIC_RPE_RCPU_IRQ_MASK5 */ 4703 uint32 rpe_pcie_irq0_mask; /* Cached copy of CMIC_RPE_PCIE_IRQ_MASK0 */ 4704 uint32 rpe_uc0_irq0_mask; /* Cached copy of CMIC_RPE_UC0_IRQ_MASK0 */ 4705 uint32 rpe_uc1_irq0_mask; /* Cached copy of CMIC_RPE_RCPU_IRQ_MASK2 */ 4706 #endif /* BCM_RCPU_SUPPORT */ 4707 /*SHR_BITDCLNAME(cpu_arm_queues[SOC_CMCS_NUM_MAX], NUM_CPU_COSQ_MAX);*/ 4708 SHR_BITDCL cpu_arm_queues[SOC_CMCS_NUM_MAX][_SHR_BITDCLSIZE(NUM_CPU_COSQ_MAX)]; 4709 /* Bitmap of CMIC queues allocated for ARM use */ 4710 /*SHR_BITDCLNAME(cpu_arm_reserved_queues[SOC_CMCS_NUM_MAX], NUM_CPU_COSQ_MAX);*/ 4711 SHR_BITDCL cpu_arm_reserved_queues[SOC_CMCS_NUM_MAX][_SHR_BITDCLSIZE(NUM_CPU_COSQ_MAX)]; 4712 /* Bitmap of CMIC queues reserved for special purpose*/ 4713 int num_cpu_arm_cosq[SOC_CMCS_NUM_MAX]; 4714 /* number of CPU/ARM cosq */ 4715 #ifdef BCM_KATANA_SUPPORT 4716 /* CES Service Control */ 4717 void *ces_ctrl; /* CES control, cast to bcm_ces_service_global_config_t */ 4718 void *tdm_ctrl; /* CES TDM control, cast to bcm_tdm_port_record_t */ 4719 uint32 tdm_count; /* Number of CES TDM ports */ 4720 #endif /* BCM_KATANA_SUPPORT */ 4721 4722 int swIntrActive; 4723 sal_sem_t swIntr[CMICM_SW_INTR_NUM_HOSTS]; /* For uc/host 4724 communications */ 4725 4726 uint32 *uc_hostram_buf[CMICM_NUM_UCS]; 4727 4728 /* uC message structures */ 4729 uint32 uc_msg_area; 4730 sal_mutex_t uc_msg_control; 4731 sal_sem_t uc_msg_active[CMICM_NUM_UCS]; 4732 4733 sal_sem_t uc_msg_rcv_sems[CMICM_NUM_UCS][MAX_MOS_MSG_CLASS + 1]; 4734 sal_sem_t uc_msg_ack_sems[CMICM_NUM_UCS][NUM_MOS_MSG_SLOTS]; 4735 4736 /* LL for Storing messages received per class */ 4737 ll_ctrl_t uc_msg_rcvd_ll[CMICM_NUM_UCS][MAX_MOS_MSG_CLASS + 1]; 4738 4739 uint8 *uc_msg_ack_data[CMICM_NUM_UCS][NUM_MOS_MSG_SLOTS]; 4740 4741 /* Semaphores for senders waiting for a free slot */ 4742 sal_sem_t uc_msg_send_queue_sems[CMICM_NUM_UCS]; 4743 4744 mos_msg_host_status_t uc_msg_prev_status_in[CMICM_NUM_UCS]; 4745 mos_msg_host_status_t uc_msg_prev_status_out[CMICM_NUM_UCS]; 4746 4747 /* Timeout properties */ 4748 sal_usecs_t uc_msg_queue_timeout; /* Free slot timeout */ 4749 sal_usecs_t uc_msg_ctl_timeout; /* Control seamphore timeout */ 4750 sal_usecs_t uc_msg_send_timeout; /* Ack/NAK wait timeout */ 4751 sal_usecs_t uc_msg_send_retry_delay; /* Delay btween send retries */ 4752 4753 /* System-type msg control */ 4754 sal_mutex_t uc_msg_system_control; 4755 uint8 uc_msg_system_count; /* Incremnted by thread */ 4756 4757 /* Callback for uC applications on shutdown */ 4758 soc_cmic_uc_appl_cb_t *uc_msg_appl_cb[CMICM_NUM_UCS][MAX_MOS_MSG_CLASS + 1]; 4759 void *uc_msg_appl_cb_data[CMICM_NUM_UCS][MAX_MOS_MSG_CLASS + 1]; 4760 4761 /* tx_beacon info */ 4762 int txbeacon_init; /* Set on init */ 4763 int txbeacon_uC; /* ARM responsible for txb */ 4764 sal_usecs_t txbeacon_msg_timeout; /* Timeout for msgs */ 4765 4766 #endif /* BCM_CMICM_SUPPORT or BCM_CMICX_SUPPORT */ 4767 #ifdef BCM_SBUSDMA_SUPPORT 4768 uint8 max_sbusdma_channels; 4769 int8 desc_ch; 4770 soc_sbusdma_desc_info_t *sbd_dm_inf; 4771 #endif /* BCM_SBUSDMA_SUPPORT */ 4772 4773 int8 tdma_ch; 4774 int8 tslam_ch; 4775 uint8 tdma_enb; 4776 uint8 tslam_enb; 4777 /* per CMC/CH sbusDMA register mutual exclusion */ 4778 sal_mutex_t sbusDmaMutexs[SOC_CMCS_NUM_MAX][SOC_SBUSDMA_CH_PER_CMC]; 4779 int sbusDmaTimeout; /* Operation timeout in microseconds */ 4780 /* per CMC/CH sbusDMA DONE interrupt */ 4781 sal_sem_t sbusDmaIntrs[SOC_CMCS_NUM_MAX][SOC_SBUSDMA_CH_PER_CMC]; 4782 int sbusDmaIntrEnb; /* Use interrupts instead of polling */ 4783 4784 int schanTimeout; /* Operation timeout in microseconds */ 4785 /* S-Channel DONE interrupt notification */ 4786 sal_sem_t schanIntr[SOC_CMCS_NUM_MAX+1]; 4787 int schanIntrEnb; /* Allow interrupts to be used */ 4788 sal_usecs_t schanIntrBlk; /* Length of time to block the S-channel 4789 error interrupt after one occurs */ 4790 /* CMIC_SCHAN_CTRL register after 4791 last S-channel operation */ 4792 uint32 schan_result[SOC_CMCS_NUM_MAX+1]; 4793 4794 sal_mutex_t miimMutex; /* MII registers mutual exclusion */ 4795 int miimTimeout; /* Operation timeout in microseconds */ 4796 sal_sem_t miimIntr; /* MII DONE interrupt notification */ 4797 int miimIntrEnb; /* Use interrupts instead of polling */ 4798 4799 int bistTimeout; /* Operation timeout in milliseconds */ 4800 int tableDmaTimeout;/* Operation timeout in microseconds */ 4801 int tableDmaIntrEnb;/* Use interrupts instead of polling */ 4802 int tslamDmaTimeout;/* Operation timeout in microseconds */ 4803 int tslamDmaIntrEnb;/* Use interrupts instead of polling */ 4804 4805 int schanFifoTimeout;/* SCHAN-FIFO Operation timeout in microseconds */ 4806 int schanFifoIntrEnb;/* Use interrupts instead of polling */ 4807 int memBulkSchanPioMode;/* If Schan PIO engine is used for Bulk memory operation */ 4808 4809 sal_mutex_t socControlMutex;/* SOC control structure mutual exclusion */ 4810 sal_mutex_t counterMutex; /* Counter activity mutual exclusion */ 4811 sal_mutex_t evictMutex; /* Evict activity mutual exclusion */ 4812 sal_thread_t schan_wb_thread_id; /*Thread ID use to evoide deadlock state while allowing warmboot write*/ 4813 sal_mutex_t schan_wb_mutex; /* mutex for toggling hw disable flag */ 4814 4815 int memCmdTimeout; /* Operation timeout in microseconds */ 4816 sal_sem_t memCmdIntr[3]; /* Memory command interrupt ER */ 4817 int memCmdIntrEnb; /* Use interrupts instead of polling */ 4818 4819 sal_sem_t ipfixIntr; /* IPFIX FIFO DMA interrupt */ 4820 int ipfixIntrEnb; /* Use interrupts instead of polling */ 4821 4822 sal_sem_t ftreportIntr; /* IPFIX FIFO DMA interrupt */ 4823 int ftreportIntrEnb; /* Use interrupts instead of polling */ 4824 4825 #ifdef BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT 4826 sal_sem_t ftExportIntr; /* Broadscan FT FIFO DMA interrupt */ 4827 int ftExportIntrEnb; /* Use interrupts instead of polling */ 4828 #endif /* BCM_FLOWTRACKER_EXPORT_FIFO_SUPPORT */ 4829 int l2modDmaIntrEnb; /* Use interrupts instead of polling */ 4830 4831 sal_sem_t ctrEvictIntr; /* Counter eviction FIFO DMA interrupt */ 4832 int ctrEvictDmaIntrEnb; /* Use interrupts instead of polling */ 4833 4834 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 4835 /* per CMC/CH FIFO DMA register mutual exclusion */ 4836 sal_mutex_t fifoDmaMutexs[SOC_CMCS_NUM_MAX][N_DMA_CHAN]; 4837 int fifoDmaTimeout; /* Operation timeout in microseconds */ 4838 /* per CMC/CH FIFO DMA DONE interrupt */ 4839 sal_sem_t fifoDmaIntrs[SOC_CMCS_NUM_MAX][N_DMA_CHAN]; 4840 int fifoDmaIntrEnb; /* Use interrupts instead of polling */ 4841 #endif /* BCM_CMICM_SUPPORT or BCM_CMICX_SUPPORT */ 4842 4843 int sbusCmdSpacing; /* Multiple outstanding sbus command spacing */ 4844 4845 sal_mutex_t overrideMutex; /* OVERRIDE registers mutual exclusion */ 4846 4847 int next_int0_cmc; /* Next CMC to service for interrupt 0 */ 4848 4849 /* MAC IPG Configuration */ 4850 4851 soc_ipg_t ipg; 4852 /* Statistics counts */ 4853 4854 soc_stat_t stat; 4855 sal_mutex_t ser_err_stat_lock; /* Lock for SER error statistics */ 4856 4857 /* On-chip memory management */ 4858 4859 soc_memstate_t 4860 memState[NUM_SOC_MEM]; 4861 uint8 tcam_protect_write; /* Duplicate existing entry before 4862 * overwrite */ 4863 uint8 tcam_protect_write_init;/* Duplicate existing entry before 4864 * overwrite */ 4865 uint8 *mem_scache_ptr; /* mem scache pointer */ 4866 uint8 skip_cache_use; /* Mem test mode to avoid cache use */ 4867 uint8 force_read_through; /* Read from h/w even if cached */ 4868 uint8 cache_coherency_chk; /* Check cache coherency */ 4869 uint8 dma_from_mem_cache; /* DMA from mem cache */ 4870 uint8 parity_enable; /* SER enabled */ 4871 uint8 parity_correction; /* SER correction enabled */ 4872 uint8 parity_counter_clear; /* 0:Clear or 1:Restore counter on SER event */ 4873 uint8 return_reg_error; /* Return error on SER error */ 4874 uint32 alpm_mem_ops; /* Bitmap for alpm mem ops executed */ 4875 #define _SOC_ALPM_LOOKUP 0 4876 #define _SOC_ALPM_INSERT 1 4877 #define _SOC_ALPM_DELETE 2 4878 sal_sem_t alpm_bulk_retry; /* ALPM bulk op retry handshake semaphore */ 4879 sal_sem_t alpm_lookup_retry; /* ALPM lookup op retry handshake semaphore */ 4880 sal_sem_t alpm_insert_retry; /* ALPM insert op retry handshake semaphore */ 4881 sal_sem_t alpm_delete_retry; /* ALPM delete op retry handshake semaphore */ 4882 sal_mutex_t l3x_lock; /* L3 module lock */ 4883 uint8 l3_defip_urpf; /* urpf_route_enabled */ 4884 int l3_defip_index_remap; /* l3_defip index remap offset */ 4885 int l3_defip_max_tcams; /* Number of defip tcams */ 4886 int l3_defip_tcam_size; /* size of each defip tcam */ 4887 _soc_l3_defip_index_table_t *defip_index_table; 4888 int l3_defip_max_128b_entries; /* Number of 128B V6 entries */ 4889 uint8 *l3_defip_scache_ptr; /* handle to save/resote l3_defip_max_128b_entries */ 4890 uint8 *fp_tcam_scache_ptr; /* handle to save/resote fp overlay_tcam_bitmap */ 4891 4892 #if 0 4893 #ifdef SOC_L3_ECMP_PROTECTED_ACCESS_SUPPORT 4894 sal_mutex_t ecmp_lock; /* SOC ECMP lock */ 4895 soc_ecmp_state_t *ecmp_state; /* SOC ECMP State */ 4896 #endif /* SOC_L3_ECMP_PROTECTED_ACCESS_SUPPORT */ 4897 #endif 4898 4899 #ifdef INCLUDE_MEM_SCAN 4900 VOL sal_thread_t 4901 mem_scan_pid; 4902 char mem_scan_name[16]; /* Memory scan task name */ 4903 VOL int mem_scan_rate; /* Max entries to scan per pass */ 4904 VOL sal_usecs_t 4905 mem_scan_interval; /* Task wake up interval */ 4906 sal_sem_t mem_scan_notify; 4907 sal_mutex_t mem_scan_lock; /* memscan lock */ 4908 #endif 4909 4910 #ifdef BCM_SRAM_SCAN_SUPPORT 4911 VOL sal_thread_t 4912 sram_scan_pid; 4913 char sram_scan_name[16]; /* SRAM scan task name */ 4914 VOL int sram_scan_rate; /* Max entries to scan per pass */ 4915 VOL sal_usecs_t 4916 sram_scan_interval; /* Task wake up interval */ 4917 sal_sem_t sram_scan_notify; 4918 #endif 4919 4920 #if defined(BCM_TRIUMPH3_SUPPORT) 4921 VOL sal_thread_t 4922 esm_recovery_pid; 4923 sal_sem_t esm_recovery_notify; /* ESM recovery handshake semaphore */ 4924 sal_mutex_t esm_lock; 4925 int esm_recovery_enable; 4926 #endif 4927 4928 #ifdef BCM_ISM_SUPPORT 4929 _soc_ism_t *ism; /* ISM info structure */ 4930 _soc_ism_hash_t *ism_hash; /* ISM hash info structure */ 4931 #endif /* BCM_ISM_SUPPORT */ 4932 4933 /* Hardware ARL Table */ 4934 4935 VOL sal_thread_t 4936 arl_pid; /* Software ARL message task */ 4937 char arl_name[16]; /* ARL message task name */ 4938 int arl_exit; /* Request for ARL thread to exit */ 4939 sal_sem_t arl_notify; 4940 VOL sal_usecs_t 4941 arl_interval; /* Interval between L2 table sync passes */ 4942 int arl_notified; /* TRUE if notify semaphore already given */ 4943 int arl_dma_cnt0; /* can only be set in intr; only cleared 4944 when done processing in arl thread. */ 4945 int arl_dma_xfer; /* can only be set in intr; only cleared 4946 when done processing in arl thread. */ 4947 int arl_mbuf_done; /* can only be set in intr; only cleared 4948 when done processing in arl thread. */ 4949 int arl_msg_drop; /* can only be set in intr; only cleared 4950 when processed in arl_mbuf_process. */ 4951 sal_time_t arlDropWarn; /* Timestamp of last warning msg printed */ 4952 uint32 arlResyncDelay; /* Time after drop before resync (0=never) */ 4953 int arlBufSize; /* Number of entries in arlBuf */ 4954 schan_msg_arlins_t 4955 *arlBuf; /* ARL DMA Message Buffer */ 4956 schan_msg_arlins_t 4957 *arlPtr; /* Consumer pointer */ 4958 shr_avl_t *arlShadow; /* Shadow copy of ARL or L2X table */ 4959 shr_avl_t *arlShadow_ext1;/* Shadow copy of EXT_L2_1 table */ 4960 shr_avl_t *arlShadow_ext2;/* Shadow copy of EXT_L2_2 table */ 4961 sal_mutex_t arlShadowMutex; 4962 int arlMode; /* Current ARL mode */ 4963 int arlNextBuf; /* Poll mode: next ARL Message Buffer (0-3) */ 4964 int arlRateLimit; /* Limit in msgs/sec */ 4965 4966 sal_mutex_t arl_table_Mutex; 4967 sal_mutex_t arl_mem_search_Mutex; 4968 sal_mutex_t mem_rwctrl_reg_Mutex; 4969 4970 4971 /* Hardware L2X Table */ 4972 4973 VOL sal_thread_t 4974 l2x_pid; /* Software L2 shadow task */ 4975 char l2x_name[16]; /* L2X shadow task name */ 4976 int l2x_mode; /* L2MODE_POLL or L2MODE_FIFO */ 4977 VOL sal_usecs_t 4978 l2x_interval; /* Interval between L2 table sync passes */ 4979 int l2x_age_timeout; /* Timeout for h/w l2x age to complete */ 4980 4981 #ifdef BCM_TRIUMPH3_SUPPORT 4982 VOL sal_usecs_t 4983 l2x_agetime_adjust_usec; /* usec waited on sem before 4984 age thread stops */ 4985 VOL sal_usecs_t 4986 l2x_agetime_curr_timeblk; /* Current timeout block index 4987 , each blk is 2147sec. */ 4988 VOL sal_usecs_t 4989 l2x_agetime_curr_timeblk_usec; /* amount of usec spent on sem 4990 of current 2147sec time blk */ 4991 VOL sal_usecs_t 4992 l2x_prev_age_timeout; /* stores prev age timeout between 4993 thread start and stop */ 4994 #endif 4995 VOL sal_thread_t 4996 l2x_age_pid; /* Software L2 age task */ 4997 char l2x_age_name[16]; /* L2X age task name */ 4998 #ifdef BCM_TOMAHAWK3_SUPPORT 4999 VOL sal_thread_t l2x_learn_pid; /* L2 Learn task */ 5000 char l2x_learn_name[16]; /* L2 Learn task name */ 5001 int l2x_lrn_mode; /* L2_MODE_POLL or L2_MODE_INTR */ 5002 VOL sal_usecs_t l2x_learn_interval; /* Interval to poll L2 learn cache */ 5003 shr_avl_t *l2x_lrn_shadow; /* Table used for h/w L2 updates (learn/age) 5004 and stn move */ 5005 sal_mutex_t l2x_lrn_shadow_mutex; /* Mutex for shadow table updates */ 5006 int lrn_cache_threshold; /* # entries in learn cache above which 5007 interrupt will be generated */ 5008 int lrn_cache_intr_ctl; /* H/w generates intr based on cache 5009 threshold (0/1) */ 5010 int lrn_cache_clr_on_rd; /* Clear-on-read settting (ena/dis) */ 5011 #endif /* BCM_TOMAHAWK3_SUPPORT */ 5012 #ifdef BCM_TRIUMPH3_SUPPORT 5013 int l2x_age_hitsa_only; 5014 #endif 5015 sal_sem_t l2x_age_notify; 5016 #ifdef BCM_TRIDENT2_SUPPORT 5017 sal_sem_t l2x_age_sync; 5018 int l2x_age_enable; 5019 int l2x_sw_aging; 5020 #endif 5021 VOL sal_usecs_t 5022 l2x_age_interval; /* Interval between L2 table age passes */ 5023 VOL uint32 l2x_flags; 5024 int l2x_ppa_in_progress; 5025 int l2x_ppa_bypass; 5026 sal_sem_t l2x_notify; 5027 sal_mutex_t l2x_del_sync; 5028 #define SOC_L2_DEL_SYNC_LOCK(s) sal_mutex_take((s)->l2x_del_sync, sal_mutex_FOREVER) 5029 5030 #define SOC_L2_DEL_SYNC_UNLOCK(s) sal_mutex_give((s)->l2x_del_sync) 5031 #ifdef BCM_TSN_SUPPORT 5032 sal_mutex_t l2x_sr_sync; 5033 #define SOC_L2_SR_LOCK(unit) \ 5034 do { \ 5035 if (soc_feature(unit, soc_feature_tsn)) { \ 5036 sal_mutex_take(SOC_CONTROL(unit)->l2x_sr_sync, sal_mutex_FOREVER);\ 5037 } \ 5038 } while (0) 5039 #define SOC_L2_SR_UNLOCK(unit) \ 5040 do { \ 5041 if (soc_feature(unit, soc_feature_tsn)) { \ 5042 sal_mutex_give(SOC_CONTROL(unit)->l2x_sr_sync); \ 5043 } \ 5044 } while (0) 5045 #else 5046 #define SOC_L2_SR_LOCK(unit) do {} while(0) 5047 #define SOC_L2_SR_UNLOCK(unit) do {} while(0) 5048 #endif /* BCM_TSN_SUPPORT */ 5049 5050 sal_sem_t l2x_lock; 5051 uint8 l2x_shadow_hit_bits; 5052 #define L2X_SHADOW_HIT_BITS 0x1 /* global hit bits control */ 5053 #define L2X_SHADOW_HIT_SRC 0x2 /* source hit bit control */ 5054 #define L2X_SHADOW_HIT_DST 0x4 /* destination hit bit control */ 5055 5056 int l2x_l2mc_in_l2entry; 5057 int l2x_external; 5058 int l2x_group_enable; 5059 int l2_overflow_active; /* L2 overflow mechanism active */ 5060 int l2_overflow_enable; /* L2 overflow mechanism enabled */ 5061 int l2_overflow_bucket_enable; /* L2 overflow bucket enabled */ 5062 /* Hash keys configuration */ 5063 uint32 hash_key_config; 5064 #define L3X_IPMC_ENABLE 0x0001 /* ipmc is enabled */ 5065 #define L3X_IPMC_SIP 0x0002 /* lookup includes src ip */ 5066 #define L3X_IPMC_SIP0 0x0004 /* lookup with src ip set to zero */ 5067 #define L3X_IPMC_VLAN 0x0008 /* lookup includes vlan */ 5068 5069 /* Hash mask cache */ 5070 5071 uint32 hash_mask_l2x; 5072 int hash_bits_l2x; 5073 uint32 hash_mask_l3x; 5074 int hash_bits_l3x; 5075 uint32 hash_mask_vlan_mac; 5076 int hash_bits_vlan_mac; 5077 uint32 hash_mask_egr_vlan_xlate; 5078 int hash_bits_egr_vlan_xlate; 5079 uint32 hash_mask_mpls; 5080 int hash_bits_mpls; 5081 uint32 hash_mask_l2x_ext; 5082 int hash_bits_l2x_ext; 5083 uint32 hash_mask_l3v6; 5084 int hash_bits_l3v6; 5085 uint32 hash_mask_my_station; 5086 int hash_bits_my_station; 5087 uint32 hash_mask_wlan_client; 5088 int hash_bits_wlan_client; 5089 uint32 hash_mask_wlan_port; 5090 int hash_bits_wlan_port; 5091 uint32 hash_mask_ing_vp_vlan_member; 5092 int hash_bits_ing_vp_vlan_member; 5093 uint32 hash_mask_egr_vp_vlan_member; 5094 int hash_bits_egr_vp_vlan_member; 5095 uint32 hash_mask_ing_dnat_address_type; 5096 int hash_bits_ing_dnat_address_type; 5097 uint32 hash_mask_l2_endpoint_id; 5098 int hash_bits_l2_endpoint_id; 5099 uint32 hash_mask_endpoint_queue_map; 5100 int hash_bits_endpoint_queue_map; 5101 uint32 hash_mask_ft_session_ipv4; 5102 int hash_bits_ft_session_ipv4; 5103 uint32 hash_mask_ft_session_ipv6; 5104 int hash_bits_ft_session_ipv6; 5105 uint32 hash_mask_tunnel; 5106 int hash_bits_tunnel; 5107 5108 /* Hash recurse depths */ 5109 uint32 dual_hash_recurse_depth; 5110 uint32 dual_hash_recurse_depth_l2x; 5111 uint32 dual_hash_recurse_depth_mpls; 5112 uint32 dual_hash_recurse_depth_vlan; 5113 uint32 dual_hash_recurse_depth_egress_vlan; 5114 #if defined(INCLUDE_L3) 5115 uint32 dual_hash_recurse_depth_l3x; 5116 uint32 dual_hash_recurse_depth_tunnel; 5117 #endif 5118 #if defined(BCM_TRIUMPH3_SUPPORT) 5119 uint32 dual_hash_recurse_depth_wlan_port; 5120 uint32 dual_hash_recurse_depth_wlan_client; 5121 uint32 dual_hash_recurse_depth_ft_session_ipv4; 5122 uint32 dual_hash_recurse_depth_ft_session_ipv6; 5123 #endif 5124 uint32 dual_hash_recurse_depth_ing_vp_vlan_member; 5125 uint32 dual_hash_recurse_depth_egr_vp_vlan_member; 5126 uint32 dual_hash_recurse_depth_ing_dnat_address_type; 5127 uint32 dual_hash_recurse_depth_l2_endpoint_id; 5128 uint32 dual_hash_recurse_depth_endpoint_queue_map; 5129 uint32 multi_hash_recurse_depth; 5130 uint32 multi_hash_recurse_depth_l2; 5131 uint32 multi_hash_recurse_depth_l3; 5132 uint32 multi_hash_recurse_depth_mpls; 5133 uint32 multi_hash_recurse_depth_vlan; 5134 uint32 multi_hash_recurse_depth_vlan_1; 5135 uint32 multi_hash_recurse_depth_vlan_2; 5136 uint32 multi_hash_recurse_depth_egress_vlan; 5137 uint32 multi_hash_recurse_depth_egress_vlan_1; 5138 uint32 multi_hash_recurse_depth_egress_vlan_2; 5139 uint32 multi_hash_recurse_depth_fpem; 5140 uint32 multi_hash_recurse_depth_l3_tunnel; 5141 5142 /* Multi-Hash move recurse algorithms */ 5143 #define MULTI_MOVE_MODE_LEGACY 0x0 5144 #define MULTI_MOVE_MODE_MIX 0x1 5145 #define MULTI_MOVE_MODE_DEPTH_FAST 0x2 5146 #define MULTI_MOVE_MODE_DEPTH 0x3 5147 #define MULTI_MOVE_MODE_BREADTH 0x4 5148 5149 uint32 multi_hash_move_algorithm; 5150 5151 #ifdef SOC_ROBUST_HASH 5152 /* Robust Hash */ 5153 soc_robust_hash_db_t *soc_robust_hash_config; 5154 #endif /* SOC_ROBUST_HASH */ 5155 5156 /* Multicast ranges */ 5157 5158 int mcast_size; 5159 int ipmc_size; 5160 int higig2_bcast_size; 5161 int higig2_mcast_size; 5162 int higig2_ipmc_size; 5163 5164 int mcast_add_all_router_ports; 5165 5166 #if defined(BCM_TRIUMPH3_SUPPORT) && defined(INCLUDE_L3) 5167 pbmp_t repl_eligible_pbmp; /* Ports eligible for packet replication */ 5168 #endif 5169 5170 /* Switching logic bypass mode */ 5171 int switch_bypass_mode; 5172 5173 /* Double tag mode when it is a device-wide property */ 5174 int dt_mode; 5175 5176 /* Link status */ 5177 5178 pbmp_t link_mask2; /* Override for LCC drain */ 5179 5180 int soc_link_pause; /* Link scan pause count */ 5181 pbmp_t hw_linkscan_pbmp; /* Cached HW linkscan port bitmap */ 5182 #ifdef BCM_RAVEN_SUPPORT 5183 int hw_linkscan_delay_ns; /* Delay required when stopping HW linkscan */ 5184 #endif 5185 void (*soc_link_callout)(int); 5186 5187 pbmp_t link_fwd; /* Forwarding ports current value */ 5188 5189 void (*soc_time_callout)(int); 5190 int time_call_ref_count; 5191 5192 #ifdef BCM_LINKSCAN_LOCK_PER_UNIT 5193 sal_mutex_t linkscan_mutex; 5194 #endif 5195 5196 /* DMA Management */ 5197 uint32 soc_robo_dma_lock; /* Lock for updating DMA operations etc. */ 5198 #define SOC_DMA_LOCK(l) (l = sal_splhi()) 5199 #define SOC_DMA_UNLOCK(l) (void)sal_spl(l) 5200 sdc_t soc_channels[SOC_CMCS_NUM_MAX * MAX_N_DMA_CHAN]; 5201 int soc_max_channels; /* maximum channel count */ 5202 int soc_dma_channels; /* dma channels available to the host CPU */ 5203 sdc_t *soc_dma_default_rx; /* Default RX channel */ 5204 sdc_t *soc_dma_default_tx; /* Default TX channel */ 5205 int dma_droptx; /* Any channels in drop tx mode */ 5206 dv_t *soc_dv_rx_free; /* Available RX DVs */ 5207 int soc_dv_rx_free_cnt; /* # on RX free list */ 5208 dv_t *soc_dv_tx_free; /* Available TX DVs */ 5209 int soc_dv_tx_free_cnt; /* # on TX free list */ 5210 int soc_dv_cnt; /* # allowed on free list */ 5211 int soc_dv_size; /* Number DCBs in free list entries */ 5212 uint32 *tx_purge_pkt; /* DMA able buffer for TX Purge */ 5213 5214 dcb_op_t *dcb_op; /* DCB operations */ 5215 5216 /* 5217 * Packet Counter Management 5218 * 5219 * The hardware counter buffer is allocated using I/O-safe 5220 * memory because counter values may be transferred to the buffer 5221 * via DMA. The software counter buffer uses regular memory. 5222 */ 5223 5224 int counter_portsize; /* Bytes per port for counters */ 5225 int counter_bufsize; /* Total memory allocated for dma */ 5226 int counter_ing_first; /* First index for ingress counter */ 5227 int counter_egr_first; /* First index for egress counter */ 5228 int counter_mac_first; /* First index for mac counter */ 5229 int counter_mib_tbl_first; /* First index for MIB table counter */ 5230 int counter_n32; /* Number of 32-bit counters */ 5231 int counter_n64; /* Number of 64-bit counters */ 5232 int counter_n64_non_dma; /* Number of non DMA 64-bit counters */ 5233 int counter_ports32; /* Number of 32-bit ports */ 5234 int counter_ports64; /* Number of 64-bit ports */ 5235 int counter_perport; /* Number of counter per port */ 5236 uint32 *counter_buf32; /* Hardware counter DMA buffer */ 5237 uint64 *counter_buf64; /* Hardware counter DMA buffer */ 5238 uint64 *counter_hw_val; /* Hardware counters */ 5239 uint64 *counter_sw_val; /* Software accumulated counters */ 5240 uint64 *counter_delta; /* Deltas over last two collections */ 5241 soc_cmap_t *counter_map[SOC_MAX_NUM_PORTS]; /* per port cmap */ 5242 5243 VOL sal_thread_t 5244 counter_pid; /* Counter DMA emulation task */ 5245 char counter_name[16]; /* Counter task name */ 5246 VOL int counter_interval; /* Update interval in usec */ 5247 /* (Zero when thread not running) */ 5248 sal_usecs_t counter_coll_prev; /* Timestamp of previous collection */ 5249 sal_usecs_t counter_coll_cur; /* Timestamp of current collection */ 5250 VOL pbmp_t counter_pbmp; /* Ports being scanned */ 5251 VOL uint32 counter_flags; /* SOC_COUNTER_F_XXX */ 5252 VOL sal_sem_t 5253 counter_trigger; /* Trigger counter thread attn */ 5254 VOL sal_sem_t 5255 counter_intr; /* Counter H/W interrupt notifier */ 5256 VOL sal_spinlock_t 5257 counter_lock; /* Counter value calculating protect lock */ 5258 VOL int counter_sync_req; /* soc_counter_sync() support */ 5259 VOL int counter_suspend; /* Skip update for another interval */ 5260 VOL int counter_updating; /* Processing update cycle */ 5261 VOL sal_sem_t 5262 counter_notify; /* Scan complete notification */ 5263 int counter_swap64; /* DMA buf 64-bit values must 5264 be word-swapped */ 5265 soc_counter_non_dma_t *counter_non_dma; /* non counter DMA support 5266 * entries */ 5267 soc_counter_evict_t *counter_evict; /* counter eviction support */ 5268 int counter_evict_max_mem_id; /* Max id of eviction counter pools */ 5269 uint32 counter_evict_inval_poolid_count; /* Count of invalid pool id in eviction */ 5270 soc_controlled_counter_t *controlled_counters; /* controlled counters support */ 5271 uint32 soc_controlled_counter_flags; /* controlled counters support */ 5272 uint32 soc_controlled_counter_num; /*number of collected counters*/ 5273 uint32 soc_controlled_counter_all_num; /*all controlled counters*/ 5274 shr_fifo_t *counter_timestamp_fifo[SOC_MAX_NUM_PORTS]; 5275 /* Timestamp FIFO data */ 5276 soc_blk_ctr_reg_desc_t *blk_ctr_desc; 5277 uint32 blk_ctr_desc_count; 5278 uint64 *blk_ctr_buf; 5279 uint64 *blk_counter_hw_val; 5280 uint64 *blk_counter_sw_val; 5281 uint32 blk_ctr_count; 5282 void *pstats_tbl_desc; 5283 uint32 pstats_tbl_desc_count; 5284 uint8 *pstats_tbl_buf; 5285 uint32 pstats_tbl_size; 5286 #define PSTATS_MODE_NULL 0 5287 #define PSTATS_MODE_PKT_BUFF 1 5288 #define PSTATS_MODE_PKT_SYNC 2 5289 #define PSTATS_MODE_OOB 3 5290 uint32 pstats_mode; 5291 int pstats_flags; 5292 sal_mutex_t pstatsMutex; 5293 #define SOC_PSTATS_LOCK(unit) \ 5294 do { \ 5295 if (SOC_CONTROL(unit)->pstatsMutex) { \ 5296 sal_mutex_take(SOC_CONTROL(unit)->pstatsMutex, sal_mutex_FOREVER); \ 5297 } \ 5298 } while (0) 5299 #define SOC_PSTATS_UNLOCK(unit) \ 5300 do { \ 5301 if (SOC_CONTROL(unit)->pstatsMutex) { \ 5302 sal_mutex_give(SOC_CONTROL(unit)->pstatsMutex); \ 5303 } \ 5304 } while (0) 5305 5306 VOL sal_thread_t 5307 ctr_evict_pid; /* Counter eviction fifo DMA task */ 5308 char ctr_evict_name[16]; /* Counter eviction task name */ 5309 VOL sal_usecs_t 5310 ctr_evict_interval; /* Task wake up interval in usec */ 5311 uint32 ctr_evict_flags; 5312 5313 /* Memory correction status */ 5314 5315 soc_mmu_error_t *mmu_errors; /* Statistics tracking for MMU */ 5316 uint32 *lla_cells_good; /* LLA/PP entries known good */ 5317 SHR_BITDCL **lla_map; /* LLA/PP analysis cache */ 5318 int *sbe_disable; /* PP has entries w/ SBE errors */ 5319 5320 SHR_BITDCL *port_lls_l0_bmap[SOC_MAX_NUM_PORTS]; /* LLS L0 usage map */ 5321 SHR_BITDCL *port_lls_l1_bmap[SOC_MAX_NUM_PORTS]; /* LLS l1 usage map */ 5322 SHR_BITDCL *port_lls_l2_bmap[SOC_MAX_NUM_PORTS]; /* LLS L2 usage map */ 5323 #if defined(BCM_KATANA2_SUPPORT) 5324 SHR_BITDCL *port_lls_s0_bmap[SOC_MAX_NUM_PORTS]; /* LLS S0 usage map */ 5325 #endif /*BCM_KATANA2_SUPPORT*/ 5326 #if defined(BCM_KATANA2_SUPPORT) || defined(BCM_APACHE_SUPPORT) 5327 SHR_BITDCL *port_lls_s1_bmap[SOC_MAX_NUM_PORTS]; /* LLS S1 usage map */ 5328 #endif /*BCM_KATANA2_SUPPORT || BCM_APACHE_SUPPORT */ 5329 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) 5330 soc_pbmp_t port_flush_pbmp; /* port flush pbmp */ 5331 #endif 5332 #if defined(BCM_KATANA_SUPPORT) || defined(BCM_KATANA2_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_APACHE_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 5333 sal_mutex_t llsMutex; /* LLS Mutex. */ 5334 #endif 5335 int mmu_error_block; /* Disable MMU errors */ 5336 /* Chip driver pointers */ 5337 5338 soc_driver_t 5339 *chip_driver; 5340 soc_functions_t 5341 *soc_functions; 5342 5343 soc_portctrl_functions_t 5344 *soc_portctrl_functions; 5345 5346 pbmp_t **reg_subset_mask; /* Reg mask subset arrays */ 5347 5348 void *i2c_bus; /* Cast to soc_i2c_bus_t */ 5349 void *bsc_bus; /* Cast to soc_bsc_bus_t */ 5350 uint16 max_vrf_id; /* Maximum vrf id on the device. */ 5351 uint16 max_address_class; /* Maximum src/dst class */ 5352 /* on the device. */ 5353 uint16 max_overlaid_address_class; /* Maximum overlaid src/dst class */ 5354 /* on the device. */ 5355 uint16 max_extended_address_class; /* Maximum extended src/dst class */ 5356 /* on the device. */ 5357 uint16 max_interface_class; /* Maximum interface class */ 5358 /* on the device. */ 5359 uint16 mem_clear_chunk_size; /* Memory clear chunk size. */ 5360 sal_mutex_t egressMeteringMutex; /* Egress metering access mutex. */ 5361 void *tcam_info; /* Ext memory control structure */ 5362 void *ext_l2_ppa_info; 5363 void *ext_l2_ppa_vlan; 5364 void *ext_l2_ppa_info_2; 5365 void *ext_l2_ppa_vlan_2; 5366 int ext_l2_ppa_threshold; /* Transition threshold */ 5367 int l2e_ppa; 5368 5369 int16 dport_map[SOC_DPORT_MAX];/* User to physical port map */ 5370 int16 dport_rmap[SOC_PBMP_PORT_MAX];/* Reverse user port map */ 5371 int dport_map_flags; /* See dport.h */ 5372 soc_event_cb_list_t *ev_cb_head; /* critical events cb handler */ 5373 5374 soc_module_t base_modid; /* Device base module id. */ 5375 5376 #ifdef BCM_WARM_BOOT_SUPPORT 5377 uint32 autosync; /* Autosync mode for warm boot */ 5378 uint32 scache_dirty; /* Warm boot cache is dirty */ 5379 #ifdef CRASH_RECOVERY_SUPPORT 5380 uint32 crash_recovery; /* Crash Recovery mode for warm boot */ 5381 uint32 journaling_mode; 5382 #endif 5383 uint32 downgrade_version; /* Warmboot downgrade version */ 5384 #endif 5385 5386 #if defined(BCM_ESW_SUPPORT) 5387 iarb_tdm_table_entry_t iarb_tdm; /* Cache of CPU slot (TR2/AP/EN) */ 5388 int iarb_tdm_idx; /* Cache of CPU slot (TR2/AP/EN) */ 5389 #endif 5390 void *tdm_info; /* TDM algorithm input/output data */ 5391 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) \ 5392 || defined(PORTMOD_SUPPORT) 5393 soc_interrupt_t *interrupts_info; /* interrupts array */ 5394 #endif 5395 /* WC firmware load configuration */ 5396 void *soc_wc_ucode_dma_buf; /* DMA buffer for WC firmware load */ 5397 void *soc_wc_ucode_dma_buf2; /* DMA buffer for 2nd type of WC firmware load */ 5398 int soc_wc_ucode_alloc_size; /* WC firmware DMA buffer size */ 5399 int soc_wc_ucode_alloc_size2; /* 2nd type of WC firmware DMA buffer size */ 5400 5401 /* MAC low power mode for Robo chips */ 5402 uint32 mac_low_power_enabled; /* currently low power mode */ 5403 uint32 auto_mac_low_power; /* Automatic enable low power mode */ 5404 sal_mutex_t mac_low_power_mutex; 5405 sal_time_t all_link_down_detected; /* Timestamp of event that all ports link down*/ 5406 5407 /* Mutex for internal CPU arbiter */ 5408 sal_mutex_t arbiter_mutex; 5409 uint8 int_cpu_enabled; 5410 uint32 arbiter_lock_count; 5411 /* Feature cache */ 5412 5413 /*SHR_BITDCLNAME(features, soc_feature_count);*/ 5414 SHR_BITDCL features[_SHR_BITDCLSIZE(soc_feature_count)]; 5415 5416 #ifdef BCM_TIMESYNC_SUPPORT 5417 /* Timesync clock period */ 5418 uint32 timesync_pll_clock_ns; 5419 #endif 5420 5421 #ifdef BCM_CB_ABORT_ON_ERR 5422 /* Callback return code handling */ 5423 uint8 cb_abort_on_err; 5424 #endif 5425 5426 sal_mutex_t ipArbiterMutex; 5427 5428 soc_dma_mode_t dma_mode; /* Continuous or Chained DMA mode */ 5429 5430 #ifdef BCM_TOMAHAWK_SUPPORT 5431 sal_mutex_t idb_lock; 5432 #endif 5433 int runtime_performance_optimize_enable_sched_allocation ; /* 0/1 ; Runtime optimization ; Memory for speed */ 5434 sal_mutex_t fp_lock; /* Field Module lock */ 5435 5436 /* Debug variables used for soc memwatch and regwatch */ 5437 soc_mem_t prev_mem; 5438 int soc_mem_watch; 5439 int soc_reg_watch; 5440 soc_reg_t prev_reg; 5441 5442 sal_mutex_t mem_ser_info_lock; 5443 sal_mutex_t udf_lock; /* UDF Module lock */ 5444 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) 5445 sal_mutex_t linkscan_modport_map_lock; 5446 #endif /* #(BCM_TRIUMPH3_SUPPORT) || defined(BCM_HELIX4_SUPPORT) */ 5447 5448 #ifdef BCM_PETRA_SUPPORT 5449 sal_sem_t pvt_mon_correction; /* PVT monitor correction semaphore */ 5450 int pvt_mon_correction_interval; /* PVT mon SW WA thread interval */ 5451 #endif 5452 #if defined(INCLUDE_FLOWTRACKER) 5453 int uc_flowtracker_enable; 5454 #endif /* INCLUDE_FLOWTRACKER */ 5455 5456 #ifdef BCM_CMICX_SUPPORT 5457 soc_iproc_m0ssq_control_t iproc_m0ssq_ctrl[MAX_UCORES]; 5458 int iproc_m0_init_done; 5459 int iproc_mbox_init_done; 5460 int iproc_m0ls_init_done; 5461 int iproc_m0led_init_done; 5462 int ls_mbox_id; 5463 int led_mbox_id; 5464 int led_fw_enabled; 5465 pbmp_t cmicx_link_stat; 5466 soc_iproc_mbox_info_t *ls_txmbox; 5467 soc_iproc_mbox_info_t *ls_rxmbox; 5468 soc_iproc_mbox_info_t *led_txmbox; 5469 soc_iproc_mbox_info_t *led_rxmbox; 5470 soc_iproc_mbox_config_t iproc_mbox_config; 5471 soc_iproc_mbox_info_t iproc_mbox_info[IPROC_MAX_MBOX][IPROC_MAX_TYPE]; 5472 #endif /* BCM_CMICX_SUPPORT */ 5473 5474 #ifdef BCM_TOMAHAWK3_SUPPORT 5475 soc_latency_monitor_info_t latency_monitor_info[SOC_MAX_LATENCY_MONITOR_COUNT]; 5476 #endif /* BCM_TOMAHAWK3_SUPPORT */ 5477 #ifdef INCLUDE_XFLOW_MACSEC 5478 sal_mutex_t xflow_macsec_lock; 5479 #endif 5480 #if defined(INCLUDE_TELEMETRY) 5481 int uc_telemetry_enable; 5482 #endif /* INCLUDE_TELEMETRY */ 5483 5484 #ifdef BCM_GREYHOUND_SUPPORT 5485 int l2x_learn_pause_on_table_write; /* Pause L2 hardware learning when 5486 tables are being written. */ 5487 #endif /* BCM_GREYHOUND_SUPPORT */ 5488 5489 #if defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 5490 int sw_timestamp_fifo_enable; /* 1588 timestamps SW FIFO. */ 5491 #endif /* BCM_TRIUMPH2_SUPPORT | BCM_TRIUMPH3_SUPPORT */ 5492 5493 int max_num_pipe; /* Maximum number of pipeline */ 5494 5495 #ifdef BCM_TOMAHAWK_SUPPORT 5496 int em_halfchip; 5497 #endif /* BCM_TOMAHAWK_SUPPORT */ 5498 } soc_control_t; 5499 5500 /* 5501 * Typedef: sop_memstate_t 5502 * Purpose: Maintain per-memory persistent information 5503 */ 5504 5505 #define SOP_MEM_STATE(unit, mem) SOC_PERSIST(unit)->memState[mem] 5506 5507 typedef struct sop_memstate_s { 5508 uint32 count[SOC_MAX_NUM_BLKS];/* Number of valid table entries */ 5509 /* (sorted tables only) */ 5510 int index_max; /* May be updated per unit */ 5511 } sop_memstate_t; 5512 5513 typedef struct sop_memcfg_er_s { 5514 uint32 ext_table_cfg; 5515 uint32 host_hash_table_cfg; 5516 uint32 l3v4_search_offset; 5517 uint32 l3v6_search_offset; 5518 uint32 mvl_hash_table_cfg; 5519 uint32 mystation_search_offset; 5520 int tcam_select; 5521 } sop_memcfg_er_t; 5522 5523 /* 5524 * Typedef: soc_persist_t 5525 * Purpose: SOC Persistent Structure. 5526 * All info about a device instance that must be saved across a reload. 5527 * Notes: 5528 * Modifications to this structure will prevent reload. A system running 5529 * a given version would not be able to be upgraded to a modified version. 5530 */ 5531 5532 typedef struct soc_persist_s { 5533 /* Miscellaneous chip state */ 5534 5535 int version; /* Persistent state version */ 5536 5537 int debugMode; /* True if MMU is in debug mode */ 5538 5539 /* DCB static configuration */ 5540 5541 uint32 dcb_srcmod; /* Source module and port for dcbs */ 5542 uint32 dcb_srcport; 5543 uint32 dcb_pfm; /* Port Forwarding Mode */ 5544 5545 /* IPG Configuration per port */ 5546 5547 soc_ipg_t ipg[SOC_MAX_NUM_PORTS]; 5548 5549 /* On-chip memory management */ 5550 5551 sop_memstate_t 5552 memState[NUM_SOC_MEM]; 5553 #ifdef SOC_MEM_L3_DEFIP_WAR 5554 uint32 l3_defip_map; /* Unused L3_DEFIP blocks */ 5555 #endif 5556 5557 sop_memcfg_er_t 5558 er_memcfg; 5559 5560 /* Link status */ 5561 5562 pbmp_t link_fwd; /* Forwarding ports current value */ 5563 5564 /* Linkscan status (private; may only accessed by link.c) */ 5565 5566 pbmp_t lc_pbm_link; /* Ports currently up */ 5567 pbmp_t lc_pbm_link_change; /* Ports needed to recognize down */ 5568 pbmp_t lc_pbm_override_ports; /* Force up/Down ports */ 5569 pbmp_t lc_pbm_override_link; /* Force up/Down status */ 5570 pbmp_t lc_pbm_linkdown_tx; /* Enable tx without link */ 5571 pbmp_t lc_pbm_remote_fault; /* Ports receiving remote fault */ 5572 pbmp_t lc_pbm_failover; /* Ports set for LAG failover */ 5573 pbmp_t lc_pbm_failed; /* Failed LAG failover ports */ 5574 pbmp_t lc_pbm_failed_clear; /* Failed ports ready to reset */ 5575 pbmp_t lc_pbm_fc; /* FC ports */ 5576 pbmp_t lc_pbm_eth_buffer_mode; /* Ethernet Buffer mode ports */ 5577 5578 /* 5579 * Stacking related: 5580 * stack_ports_current: Ports currently engaged in stacking 5581 * stack_ports_inactive: Ports stacked, but explicitly blocked 5582 * stack_ports_simplex: Ports stacked using simplex mode 5583 * stack_ports_previous: Last stack port; to detect changes 5584 */ 5585 soc_pbmp_t stack_ports_current; 5586 soc_pbmp_t stack_ports_inactive; 5587 soc_pbmp_t stack_ports_previous; 5588 } soc_persist_t; 5589 5590 #define SOC_AVERAGE_IPG_IEEE (96) 5591 #define SOC_AVERAGE_IPG_HG (64) 5592 5593 #define SOC_FLAGS_CLR(s, f) { \ 5594 int _s = sal_splhi(); \ 5595 (s)->soc_flags &= ~(f); \ 5596 sal_spl(_s); \ 5597 } 5598 5599 #define SOC_NDEV_IDX2DEV(_dev_idx) soc_ndev_idx2dev_map[_dev_idx] 5600 5601 /* 5602 * soc_control: Per-device non-persistent global driver state 5603 * soc_persist: Per-device persistent global driver state 5604 * soc_ndev: Number of devices found during probe 5605 */ 5606 5607 extern soc_control_t *soc_control[SOC_MAX_NUM_DEVICES]; 5608 extern soc_persist_t *soc_persist[SOC_MAX_NUM_DEVICES]; 5609 extern int soc_ndev_attached; 5610 extern int soc_ndev; 5611 extern int soc_ndev_idx2dev_map[SOC_MAX_NUM_DEVICES]; 5612 extern int soc_eth_ndev; 5613 extern int soc_all_ndev; 5614 extern int soc_eth_unit; 5615 extern int soc_mii_unit; 5616 extern char soc_reg_noinfo[]; 5617 5618 extern soc_block_name_t soc_block_port_names[]; 5619 extern soc_block_name_t soc_block_names[]; 5620 #if defined(BCM_SAND_SUPPORT) 5621 extern soc_block_name_t soc_dpp_block_port_names[]; 5622 extern soc_block_name_t soc_dpp_block_names[]; 5623 #endif /* defined(BCM_SAND_SUPPORT) */ 5624 extern sal_mutex_t spiMutex; 5625 5626 extern uint32 soc_state[SOC_MAX_NUM_DEVICES]; 5627 5628 #if defined(BCM_WARM_BOOT_SUPPORT) 5629 /* 5630 * BCM Warm Boot Support 5631 * 5632 * Purpose: Indicates whether the device is currently in reload 5633 * state (performing Warm boot) or not. 5634 * 5635 * If finer granularity is needed in the future, additional 5636 * flags can be defined to control specific hardware accesses. 5637 */ 5638 #define SOC_ST_F_FAST_REBOOTING 0x8 5639 #define SOC_FAST_REBOOT(unit) (soc_state[unit] & SOC_ST_F_FAST_REBOOTING) 5640 #define SOC_FAST_REBOOT_START(unit) (soc_state[unit] |= SOC_ST_F_FAST_REBOOTING) 5641 #define SOC_FAST_REBOOT_DONE(unit) (soc_state[unit] = soc_state[unit] & ~SOC_ST_F_FAST_REBOOTING) 5642 5643 #define SOC_ST_F_RELOADING 0x1 /* Warm boot in progress, device is reloading */ 5644 #define SOC_WARM_BOOT(unit) (soc_state[unit] & SOC_ST_F_RELOADING) 5645 #define SOC_WARM_BOOT_START(unit) (soc_state[unit] |= SOC_ST_F_RELOADING) 5646 #define SOC_WARM_BOOT_DONE(unit) (soc_state[unit] = soc_state[unit] & ~SOC_ST_F_RELOADING) 5647 #define SOC_IS_DONE_INIT(unit) ((SOC_CONTROL(unit)->soc_flags & SOC_F_ALL_MODULES_INITED) && \ 5648 (SOC_CONTROL(unit)->soc_flags & SOC_F_ATTACHED) && \ 5649 (SOC_CONTROL(unit)->soc_flags & SOC_F_INITED)) 5650 #define SOC_IS_INIT(unit) ((SOC_CONTROL(unit)->soc_flags & SOC_F_ATTACHED) && \ 5651 (SOC_CONTROL(unit)->soc_flags & SOC_F_INITED)) 5652 /*(((SOC_CONTROL(unit)->soc_flags & SOC_F_RESET) == SOC_F_RESET) ? TRUE : FALSE)*/ 5653 5654 extern int soc_wb_mim_state[SOC_MAX_NUM_DEVICES]; 5655 #define SOC_WARM_BOOT_MIM(unit) (soc_wb_mim_state[unit] = 1) 5656 #define SOC_WARM_BOOT_IS_MIM(unit) (soc_wb_mim_state[unit] == 1) 5657 extern int soc_shutdown(int unit); 5658 extern int soc_system_scrub(int unit); 5659 5660 /* Allow schan write during warmboot */ 5661 #define SOC_ALLOW_WB_WRITE(_unit, _operation, _rv)\ 5662 do {\ 5663 int _rv_tmp;\ 5664 _rv = soc_schan_override_enable(_unit);\ 5665 if (SOC_SUCCESS(_rv)) {\ 5666 _rv = _operation;\ 5667 _rv_tmp = soc_schan_override_disable(_unit);\ 5668 if (SOC_FAILURE(_rv_tmp)) {\ 5669 _rv = _rv_tmp;\ 5670 }\ 5671 }\ 5672 } while(0) 5673 5674 #define SOC_AUTOSYNC_IS_ENABLE(_unit) (SOC_CONTROL(_unit)->autosync) 5675 #else 5676 #define SOC_FAST_REBOOT(unit) (0) 5677 #define SOC_FAST_REBOOT_START(unit) \ 5678 do { \ 5679 } while(0) 5680 #define SOC_FAST_REBOOT_DONE(unit) \ 5681 do { \ 5682 } while(0) 5683 5684 #define SOC_WARM_BOOT(unit) (0) 5685 #define soc_shutdown(unit) (SOC_E_UNAVAIL) 5686 #define soc_system_scrub(unit) (SOC_E_UNAVAIL) 5687 #define SOC_WARM_BOOT_START(unit) \ 5688 do { \ 5689 } while(0) 5690 5691 #define SOC_WARM_BOOT_DONE(unit) \ 5692 do { \ 5693 } while(0) 5694 #define SOC_IS_DONE_INIT(unit) ((SOC_CONTROL(unit)->soc_flags & SOC_F_ALL_MODULES_INITED) && \ 5695 (SOC_CONTROL(unit)->soc_flags & SOC_F_ATTACHED) && \ 5696 (SOC_CONTROL(unit)->soc_flags & SOC_F_INITED)) 5697 #define SOC_IS_INIT(unit) ((SOC_CONTROL(unit)->soc_flags & SOC_F_ATTACHED) && \ 5698 (SOC_CONTROL(unit)->soc_flags & SOC_F_INITED)) 5699 #define SOC_WARM_BOOT_MIM(unit) (0) 5700 #define SOC_WARM_BOOT_IS_MIM(unit) (0) 5701 5702 #define SOC_ALLOW_WB_WRITE(_unit, _operation, _rv)\ 5703 do {\ 5704 _rv = _operation;\ 5705 } while(0) 5706 #define SOC_AUTOSYNC_IS_ENABLE(_unit) (0) 5707 #endif /* BCM_WARM_BOOT_SUPPORT */ 5708 5709 #define SOC_HW_RESET(unit) (SOC_CONTROL(unit)->soc_flags & SOC_F_HW_RESETING) 5710 #define SOC_HW_RESET_START(unit) (SOC_CONTROL(unit)->soc_flags |= SOC_F_HW_RESETING) 5711 #define SOC_HW_RESET_DONE(unit) (SOC_CONTROL(unit)->soc_flags &= ~SOC_F_HW_RESETING) 5712 5713 #if defined(BCM_EASY_RELOAD_SUPPORT) 5714 /* 5715 * BCM Easy Reload Support 5716 * 5717 * Purpose: Indicates whether the device is currently in reload 5718 * state (performing Easy Reload) or not. 5719 * 5720 * If finer granularity is needed in the future, additional 5721 * flags can be defined to control specific hardware accesses. 5722 */ 5723 5724 #define SOC_ST_F_EASY_RELOAD 0x2 /* Easy Reload is in progress */ 5725 /* Reload mode set/get macros */ 5726 #define SOC_IS_RELOADING(unit) (soc_state[unit] & SOC_ST_F_EASY_RELOAD) 5727 #define SOC_RELOAD_MODE_SET(unit, reload_mode) \ 5728 if (reload_mode) { \ 5729 soc_state[unit] |= SOC_ST_F_EASY_RELOAD; \ 5730 } else { \ 5731 soc_state[unit] = soc_state[unit] & ~SOC_ST_F_EASY_RELOAD; \ 5732 } 5733 #elif defined(BCM_EASY_RELOAD_WB_COMPAT_SUPPORT) 5734 /*Easy reload wb compat*/ 5735 #define SOC_ST_F_EASY_RELOAD 0x2 /* Easy Reload is in progress */ 5736 #define SOC_IS_RELOADING(unit) (soc_feature(unit, soc_feature_easy_reload_wb_compat) && \ 5737 soc_state[unit] & SOC_ST_F_EASY_RELOAD) 5738 #define SOC_RELOAD_MODE_SET(unit, reload_mode) \ 5739 if (soc_feature(unit, soc_feature_easy_reload_wb_compat)) { \ 5740 if (reload_mode) { \ 5741 soc_state[unit] |= SOC_ST_F_EASY_RELOAD; \ 5742 } else { \ 5743 soc_state[unit] = soc_state[unit] & ~SOC_ST_F_EASY_RELOAD; \ 5744 } \ 5745 } 5746 5747 #else 5748 /*No Easy reload support*/ 5749 #define SOC_IS_RELOADING(unit) (0) 5750 #define SOC_RELOAD_MODE_SET(unit, reload_mode) \ 5751 do { \ 5752 } while(0) 5753 #endif /* BCM_EASY_RELOAD_SUPPORT */ 5754 /* 5755 * BCM detach 5756 * 5757 * Purpose: Indicates whether the device is currently being detached from the 5758 * system state (performing detach) or not. 5759 */ 5760 5761 #define SOC_ST_F_DETACH 0x4 /* Detach is in progress */ 5762 /* Reload mode set/get macros */ 5763 #define SOC_IS_DETACHING(_unit_) (soc_state[_unit_] & SOC_ST_F_DETACH) 5764 #define SOC_DETACH(_unit_, _detach_) \ 5765 if (_detach_) { \ 5766 soc_state[_unit_] |= SOC_ST_F_DETACH; \ 5767 } else { \ 5768 soc_state[_unit_] = soc_state[_unit_] & ~SOC_ST_F_DETACH; \ 5769 } 5770 5771 #define SOC_HW_ACCESS_DISABLE(_unit_) \ 5772 ((SOC_WARM_BOOT(_unit_) && \ 5773 (SOC_CONTROL(unit)->schan_wb_thread_id != sal_thread_self())) ||\ 5774 SOC_IS_RELOADING(_unit_) || SOC_IS_DETACHING(_unit_)) 5775 5776 /* 5777 * Driver calls. 5778 */ 5779 extern int soc_attach(int unit); 5780 extern int soc_attached(int unit); 5781 extern int soc_reset(int unit); 5782 extern int soc_init(int unit); 5783 extern int soc_reset_init(int unit); 5784 extern int soc_device_reset(int unit, int mdoe, int action); 5785 extern int soc_detach(int unit); 5786 extern int soc_deinit(int unit); 5787 extern void soc_family_suffix_update(int unit); 5788 #if defined(BCM_ESW_SUPPORT) && defined(BCM_IPROC_SUPPORT) 5789 extern int soc_bond_info_init(int unit); 5790 extern int soc_bond_info_deinit(int unit); 5791 #endif 5792 5793 extern int soc_bist(int unit, soc_mem_t *mems, int num_mems, int timeout_msec); 5794 extern int soc_bist_all(int unit); 5795 5796 extern int soc_bpdu_addr_set(int unit, int index, sal_mac_addr_t addr); 5797 extern int soc_bpdu_addr_get(int unit, int index, sal_mac_addr_t *addr); 5798 5799 extern int soc_rcpu_schan_enable_set(int unit, int enable); 5800 5801 extern int soc_mmu_init(int unit); 5802 extern int soc_misc_init(int unit); 5803 extern const char *soc_dev_name(int unit); 5804 extern int soc_info_config(int unit, soc_control_t *soc); 5805 extern int soc_max_supported_vrf_get(int unit, uint16 *value); 5806 extern void soc_xgxs_lcpll_lock_check(int unit); 5807 extern void soc_xport_type_mode_update(int unit, soc_port_t port, int to_hg_port); 5808 extern void soc_xport_type_update(int unit, soc_port_t port, int to_hg_port); 5809 extern int soc_port_type_verify(int unit); 5810 extern int soc_port_name_verify(int unit); 5811 5812 #ifdef BCM_LEDPROC_SUPPORT 5813 extern int soc_ledproc_config(int unit, const uint8 *program, int bytes); 5814 #endif 5815 5816 extern int soc_warpcore_firmware_set(int unit, int port, uint8 *array, 5817 int datalen, int wc_instance, 5818 soc_mem_t wc_ucmem_data, 5819 soc_reg_t wc_ucmem_ctrl); 5820 5821 extern int 5822 soc_phy_firmware_load(int unit, int port, uint8 *fw_data, int fw_size); 5823 5824 extern int 5825 soc_sbus_mdio_reg_read(int unit, int port, int blk, int wc_instance, 5826 uint32 phy_addr, uint32 phy_reg, uint32 *phy_data, 5827 soc_mem_t wc_ucmem_data, soc_reg_t wc_ucmem_ctrl); 5828 extern int 5829 soc_sbus_mdio_reg_write(int unit, int port, int blk, int wc_instance, 5830 uint32 phy_addr, uint32 phy_reg, uint32 phy_data, 5831 soc_mem_t wc_ucmem_data, soc_reg_t wc_ucmem_ctrl); 5832 5833 extern int 5834 soc_sbus_tsc_reg_read(int unit, int port, int blk, uint32 phy_addr, 5835 uint32 phy_reg, uint32 *phy_data); 5836 extern int 5837 soc_sbus_tsc_reg_write(int unit, int port, int blk, uint32 phy_addr, 5838 uint32 phy_reg, uint32 phy_data); 5839 5840 #define SOC_PROPERTY_NAME_MAX 128 5841 #define SOC_PROPERTY_VALUE_MAX 64 5842 5843 extern char *soc_property_get_str(int unit, const char *name); 5844 extern uint32 soc_property_get(int unit, const char *name, uint32 defl); 5845 extern uint32 soc_property_obj_attr_get(int unit, const char *prefix, 5846 const char *obj, int index, 5847 const char *attr, int scale, 5848 char *suffix, uint32 defl); 5849 extern pbmp_t soc_property_get_pbmp(int unit, const char *name, 5850 int defneg); 5851 extern pbmp_t soc_property_get_pbmp_default(int unit, const char *name, 5852 pbmp_t def_pbmp); 5853 5854 extern pbmp_t soc_property_suffix_num_pbmp_get(int unit, int num, const char *name, 5855 const char *suffix, soc_pbmp_t pbmp_def); 5856 5857 extern void soc_property_get_bitmap_default(int unit, const char *name, 5858 uint32 *bitmap, int max_words, uint32 *def_bitmap); 5859 5860 extern int soc_property_get_csv(int unit, const char *name, 5861 int val_max, int *val_array); 5862 extern char *soc_property_port_get_str(int unit, soc_port_t port, 5863 const char *name); 5864 extern uint32 soc_property_port_get(int unit, soc_port_t port, 5865 const char *name, uint32 defl); 5866 extern char *soc_property_port_num_get_str(int unit, soc_port_t port, 5867 const char *name); 5868 extern uint32 soc_property_port_num_get(int unit, soc_port_t port, 5869 const char *name, uint32 defl); 5870 extern char *soc_property_phy_get_str(int unit, soc_port_t port, 5871 int phy_num, int phy_port, int lane, 5872 const char *name); 5873 extern uint32 soc_property_phy_get(int unit, soc_port_t port, 5874 int phy_num, int phy_port, int lane, 5875 const char *name, uint32 defl); 5876 extern uint32 soc_property_phys_port_get(int unit, soc_port_t port, 5877 const char *name, uint32 defl); 5878 extern uint32 soc_property_port_obj_attr_get(int unit, soc_port_t port, 5879 const char *prefix, 5880 const char *obj, int index, 5881 const char *attr, int scale, 5882 char *suffix, uint32 defl); 5883 extern int soc_property_port_get_csv(int unit, soc_port_t port, 5884 const char *name, int val_max, 5885 int *val_array); 5886 extern uint32 soc_property_suffix_num_get(int unit, int num, 5887 const char *name, 5888 const char *suffix, uint32 defl); 5889 5890 extern uint32 soc_property_suffix_num_get_only_suffix(int unit, int num, const char *name, 5891 const char *suffix, uint32 defl); 5892 5893 extern char* soc_property_suffix_num_str_get(int unit, int num, const char *name, 5894 const char *suffix); 5895 extern uint32 soc_property_port_suffix_num_get(int unit, soc_port_t port, 5896 int num, const char *name, 5897 const char *suffix, uint32 defl); 5898 extern uint32 soc_property_port_suffix_num_match_port_get(int unit, soc_port_t port, 5899 int num, const char *name, 5900 const char *suffix, uint32 defl); 5901 extern char *soc_property_port_suffix_num_get_str(int unit, soc_port_t port, 5902 int num, const char *name, 5903 const char *suffix); 5904 extern uint32 soc_property_cos_get(int unit, soc_cos_t cos, 5905 const char *name, uint32 defl); 5906 extern uint32 soc_property_uc_get(int unit, int uc, 5907 const char *name, uint32 defl); 5908 extern uint32 soc_property_ci_get(int unit, int ci, 5909 const char *name, uint32 defl); 5910 extern int soc_property_ci_get_csv(int unit, int ci, 5911 const char *name, int val_max, 5912 int *val_array); 5913 5914 extern char* soc_property_suffix_num_only_suffix_str_get(int unit, int num, const char *name, 5915 const char *suffix); 5916 5917 extern char *soc_block_port_name_lookup_ext(soc_block_t, int); 5918 extern char *soc_block_name_lookup_ext(soc_block_t, int); 5919 extern soc_block_t soc_block_port_name_match(char *); 5920 extern soc_block_t soc_block_name_match(int unit, char *); 5921 5922 5923 #define SOC_PCI_DEV_TYPE SAL_PCI_DEV_TYPE /* PCI device */ 5924 #define SOC_SPI_DEV_TYPE SAL_SPI_DEV_TYPE /* SPI device */ 5925 #define SOC_EB_DEV_TYPE SAL_EB_DEV_TYPE /* EB device */ 5926 #define SOC_ICS_DEV_TYPE SAL_ICS_DEV_TYPE /* ICS device */ 5927 #define SOC_MII_DEV_TYPE SAL_MII_DEV_TYPE /* MII device */ 5928 #define SOC_RCPU_DEV_TYPE SAL_RCPU_DEV_TYPE /* RCPU device */ 5929 #define SOC_I2C_DEV_TYPE SAL_I2C_DEV_TYPE /* I2C device */ 5930 #define SOC_AXI_DEV_TYPE SAL_AXI_DEV_TYPE /* AXI device */ 5931 #define SOC_EMMI_DEV_TYPE SAL_EMMI_DEV_TYPE /* EMMI device*/ 5932 #define SOC_DEV_BUS_ALT SAL_DEV_BUS_ALT /* Alternate Access */ 5933 #define SOC_DEV_BUS_MSI SAL_DEV_BUS_MSI /* Message-signaled interrupts */ 5934 5935 #define SOC_SWITCH_DEV_TYPE SAL_SWITCH_DEV_TYPE /* Switch device */ 5936 #define SOC_ETHER_DEV_TYPE SAL_ETHER_DEV_TYPE /* Ethernet device */ 5937 #define SOC_CPU_DEV_TYPE SAL_CPU_DEV_TYPE /* CPU device */ 5938 5939 /* Backward compatibility */ 5940 #define SOC_ET_DEV_TYPE SOC_MII_DEV_TYPE 5941 5942 #define SOC_TIMEOUT_VAL 100 /* Times for retrying */ 5943 /* soc/intr.c exported routines */ 5944 5945 /* Interrupt function type */ 5946 typedef void (*soc_interrupt_fn_t)(void *_unit); 5947 5948 5949 /******************************************* 5950 * @function soc_sbusdma_lock_init 5951 * purpose API to Initialize SBUSDMA 5952 * locks and Semaphores. This will also be used 5953 * for TSLAMDMA and TABLEDMA 5954 * 5955 * @param unit [in] unit 5956 * 5957 * @returns SOC_E_NONE 5958 * @returns SOC_E_XXX 5959 * 5960 * @end 5961 */ 5962 extern int 5963 soc_sbusdma_lock_init(int unit); 5964 5965 /******************************************* 5966 * @function soc_sbusdma_lock_deinit 5967 * purpose API to deinit SBUSDMA 5968 * locks and Semaphores 5969 * 5970 * @param unit [in] unit 5971 * 5972 * @returns SOC_E_NONE 5973 * 5974 * @end 5975 */ 5976 extern int 5977 soc_sbusdma_lock_deinit(int unit); 5978 5979 5980 5981 extern void soc_intr(void *unit); 5982 extern uint32 soc_intr_enable(int unit, uint32 mask); 5983 extern uint32 soc_intr_disable(int unit, uint32 mask); 5984 extern uint32 soc_intr_block_lo_enable(int unit, uint32 mask); 5985 extern uint32 soc_intr_block_lo_disable(int unit, uint32 mask); 5986 extern uint32 soc_intr_block_hi_enable(int unit, uint32 mask); 5987 extern uint32 soc_intr_block_hi_disable(int unit, uint32 mask); 5988 #ifdef BCM_CMICM_SUPPORT 5989 extern void soc_cmicm_intr(void *unit); 5990 #ifdef SEPARATE_PKTDMA_INTR_HANDLER 5991 extern void soc_cmicm_pktdma_intr(void *unit); 5992 #endif 5993 extern uint32 soc_cmicm_intr0_enable(int unit, uint32 mask); 5994 extern uint32 soc_cmicm_intr0_disable(int unit, uint32 mask); 5995 extern uint32 soc_cmicm_intr1_enable(int unit, uint32 mask); 5996 extern uint32 soc_cmicm_intr1_disable(int unit, uint32 mask); 5997 extern uint32 soc_cmicm_intr2_enable(int unit, uint32 mask); 5998 extern uint32 soc_cmicm_intr2_disable(int unit, uint32 mask); 5999 extern uint32 soc_cmicm_intr3_enable(int unit, uint32 mask); 6000 extern uint32 soc_cmicm_intr3_disable(int unit, uint32 mask); 6001 extern uint32 soc_cmicm_intr4_enable(int unit, uint32 mask); 6002 extern uint32 soc_cmicm_intr4_disable(int unit, uint32 mask); 6003 extern uint32 soc_cmicm_intr5_enable(int unit, uint32 mask); 6004 extern uint32 soc_cmicm_intr5_disable(int unit, uint32 mask); 6005 extern uint32 soc_cmicm_intr6_enable(int unit, uint32 mask); 6006 extern uint32 soc_cmicm_intr6_disable(int unit, uint32 mask); 6007 extern uint32 soc_cmicm_cmcx_intr0_enable(int unit, int cmc, uint32 mask); 6008 extern uint32 soc_cmicm_cmcx_intr0_disable(int unit, int cmc, uint32 mask); 6009 extern uint32 soc_cmicm_cmcx_intr1_enable(int unit, int cmc, uint32 mask); 6010 extern uint32 soc_cmicm_cmcx_intr1_disable(int unit, int cmc, uint32 mask); 6011 extern uint32 soc_cmicm_cmcx_intr2_enable(int unit, int cmc, uint32 mask); 6012 extern uint32 soc_cmicm_cmcx_intr2_disable(int unit, int cmc, uint32 mask); 6013 extern uint32 soc_cmicm_cmcx_intr3_enable(int unit, int cmc, uint32 mask); 6014 extern uint32 soc_cmicm_cmcx_intr3_disable(int unit, int cmc, uint32 mask); 6015 extern uint32 soc_cmicm_cmcx_intr4_enable(int unit, int cmc, uint32 mask); 6016 extern uint32 soc_cmicm_cmcx_intr4_disable(int unit, int cmc, uint32 mask); 6017 extern uint32 soc_cmicm_cmcx_intr5_enable(int unit, int cmc, uint32 mask); 6018 extern uint32 soc_cmicm_cmcx_intr5_disable(int unit, int cmc, uint32 mask); 6019 extern uint32 soc_cmicm_cmcx_intr6_enable(int unit, int cmc, uint32 mask); 6020 extern uint32 soc_cmicm_cmcx_intr6_disable(int unit, int cmc, uint32 mask); 6021 #ifdef BCM_RCPU_SUPPORT 6022 extern void soc_cmicm_rcpu_intr(int unit, soc_rcpu_intr_packet_t *intr_pkt); 6023 extern uint32 soc_cmicm_rcpu_intr0_enable(int unit, uint32 mask); 6024 extern uint32 soc_cmicm_rcpu_intr0_disable(int unit, uint32 mask); 6025 extern uint32 soc_cmicm_rcpu_intr1_enable(int unit, uint32 mask); 6026 extern uint32 soc_cmicm_rcpu_intr1_disable(int unit, uint32 mask); 6027 extern uint32 soc_cmicm_rcpu_intr2_enable(int unit, uint32 mask); 6028 extern uint32 soc_cmicm_rcpu_intr2_disable(int unit, uint32 mask); 6029 extern uint32 soc_cmicm_rcpu_intr3_enable(int unit, uint32 mask); 6030 extern uint32 soc_cmicm_rcpu_intr3_disable(int unit, uint32 mask); 6031 extern uint32 soc_cmicm_rcpu_intr4_enable(int unit, uint32 mask); 6032 extern uint32 soc_cmicm_rcpu_intr4_disable(int unit, uint32 mask); 6033 extern uint32 soc_cmicm_rcpu_cmc0_intr0_enable(int unit, uint32 mask); 6034 extern uint32 soc_cmicm_rcpu_cmc0_intr0_disable(int unit, uint32 mask); 6035 extern uint32 soc_cmicm_rcpu_cmc1_intr0_enable(int unit, uint32 mask); 6036 extern uint32 soc_cmicm_rcpu_cmc1_intr0_disable(int unit, uint32 mask); 6037 extern uint32 soc_cmicm_rcpu_cmc2_intr0_enable(int unit, uint32 mask); 6038 extern uint32 soc_cmicm_rcpu_cmc2_intr0_disable(int unit, uint32 mask); 6039 #endif /* BCM_RCPU_SUPPORT */ 6040 extern void soc_cmicm_ihost_irq_offset_set(int unit); 6041 extern void soc_cmicm_ihost_irq_offset_reset(int unit); 6042 #endif /* CMICM Support */ 6043 6044 extern void soc_endian_get(int unit, int *pio, int *packet, int *other); 6045 extern void soc_endian_config(int unit); 6046 extern void soc_pci_ep_config(int unit, int pcie); 6047 extern void soc_pci_burst_enable(int unit); 6048 6049 extern int soc_max_vrf_set(int unit, int value); 6050 6051 extern int soc_dump(int unit, const char *pfx); 6052 6053 /* MAC Core initialization */ 6054 extern int soc_xgxs_reset(int unit, soc_port_t port); 6055 extern int soc_wc_xgxs_reset(int unit, soc_port_t port, int reg_idx); 6056 extern int soc_wc_xgxs_pll_check(int unit, soc_port_t port, int reg_idx); 6057 extern int soc_wc_xgxs_power_down(int unit, soc_port_t port, int reg_idx); 6058 extern int soc_tsc_xgxs_reset(int unit, soc_port_t port, int reg_idx); 6059 extern int soc_tsc_xgxs_power_mode(int unit, soc_port_t port, int reg_idx, int mode); 6060 extern int soc_tsc_xgxs_pll_check(int unit, soc_port_t port, int reg_idx); 6061 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TRIDENT3_SUPPORT) 6062 extern int soc_xgxs_reset_master_tsc(int unit); 6063 #endif 6064 #ifdef BCM_XGS5_SWITCH_PORT_SUPPORT 6065 extern int soc_pm_power_mode_set(int unit, soc_port_t port, int reg_idx, 6066 int power_down); 6067 #endif /* BCM_XGS5_SWITCH_PORT_SUPPORT */ 6068 #if defined(BCM_GREYHOUND2_SUPPORT) 6069 extern int soc_sgmii4px2_reset(int unit, soc_port_t port, int reg_idx); 6070 #endif /* BCM_GREYHOUND2_SUPPORT */ 6071 6072 extern int soc_fusioncore_reset(int unit, soc_port_t port); 6073 #if defined(BCM_GXPORT_SUPPORT) 6074 extern int soc_unicore_reset(int unit, soc_port_t port); 6075 #endif /* BCM_GXPORT_SUPPORT */ 6076 6077 /* Cosq init */ 6078 #ifdef BCM_COSQ_HIGIG_MAP_DISABLE 6079 int soc_cosq_stack_port_map_disable(int unit); 6080 #endif 6081 6082 #ifdef BCM_XGS3_SWITCH_SUPPORT 6083 int soc_cpu_priority_mapping_init(int unit); 6084 #endif 6085 6086 #if defined(BCM_FIREBOLT_SUPPORT) 6087 #if defined(INCLUDE_L3) 6088 extern int soc_tunnel_term_block_size_set (int unit, int size); 6089 extern int soc_tunnel_term_block_size_get (int unit, int *size); 6090 #endif /* BCM_FIREBOLT_SUPPORT */ 6091 #endif /* INCLUDE_L3 */ 6092 6093 /* SER HW engine configuration and control structures */ 6094 6095 /* SER per-table control flags */ 6096 #define _SOC_SER_FLAG_ACC_TYPE_MASK 0x0001f /* Access type for multi-pipe */ 6097 #define _SOC_SER_FLAG_SW_COMPARE 0x00100 /* SW implemented SER check */ 6098 #define _SOC_SER_FLAG_DISCARD_READ 0x00200 /* Read DMA with HW discard */ 6099 #define _SOC_SER_FLAG_MULTI_PIPE 0x00400 /* HW multi-pipe table */ 6100 #define _SOC_SER_FLAG_XY_READ 0x00800 /* Read SER optimization */ 6101 #define _SOC_SER_FLAG_NO_DMA 0x01000 /* Use PIO iterations */ 6102 #define _SOC_SER_FLAG_REMAP_READ 0x02000 /* Read remapped indexes */ 6103 #define _SOC_SER_FLAG_OVERLAY 0x04000 /* Memories shared in HW */ 6104 #define _SOC_SER_FLAG_OVERLAY_CASE 0x08000 /* Polarity of overlay */ 6105 #define _SOC_SER_FLAG_SIZE_VERIFY 0x10000 /* Check table size */ 6106 #define _SOC_SER_FLAG_ACC_TYPE_CHK 0x20000 /* Used for unique pipe acc type mode */ 6107 #define _SOC_SER_FLAG_RANGE_DISABLE 0x40000 /* Use addr_mask as range disable bmap */ 6108 /* Create entry for this mem view but don't enable the engines range 6109 * Also, memscan will ignore such entry */ 6110 #define _SOC_SER_FLAG_VIEW_DISABLE 0x80000 6111 /* Don't create entry for this mem view in ser_engine. 6112 * This is only for memscan engine */ 6113 #define _SOC_SER_FLAG_CONFIG_SKIP 0x100000 6114 /*This flag is used to directly return when DMA read op occurs error 6115 *in soc_mem_ser_read_range.*/ 6116 #define _SOC_SER_FLAG_DMA_ERR_RETURN 0x200000 6117 6118 /* when pipe_mode_unique is set, memscan will remap mem to mem_PIPE0,1,2,3 */ 6119 #define _SOC_SER_STATE_PIPE_MODE_UNIQUE 0x0001 6120 6121 #define _SOC_SER_MEM_MODE_PIPE_UNIQUE 1 /* Memory accessed in per pipe (unique) mode */ 6122 #define _SOC_SER_MEM_MODE_GLOBAL 0 /* Memory accessed in global (duplicate) mode */ 6123 6124 /* 6125 * Multipipe entries for tables that should have the SER HW engine 6126 * configured to protect more than one pipeline must be 6127 * consecutive in the (generic) SER info structure for the same table. 6128 * 6129 * Overlay tables must also be consecutive by overlay type. 6130 * See trident[2].c for examples of the tables. 6131 */ 6132 6133 typedef enum { 6134 _SOC_SER_PARITY_MODE_1BIT, 6135 _SOC_SER_PARITY_MODE_2BITS, 6136 _SOC_SER_PARITY_MODE_4BITS, 6137 _SOC_SER_PARITY_MODE_8BITS, 6138 _SOC_SER_PARITY_MODE_NUM 6139 } _soc_ser_parity_mode_t; 6140 6141 typedef struct _soc_ser_parity_info_s { 6142 soc_mem_t mem; 6143 _soc_ser_parity_mode_t parity_mode; /* 0/1/2/3 => 1/2/4/8 bit parity */ 6144 soc_reg_t start_addr_reg; 6145 soc_reg_t end_addr_reg; 6146 soc_reg_t cmic_mem_addr_reg; 6147 soc_reg_t parity_mode_reg; 6148 soc_field_t parity_mode_field; 6149 int bit_offset; /* Ignored if -1 */ 6150 soc_reg_t entry_len_reg; /* Ignored if bit_offset is ignored */ 6151 uint8 cmic_ser_id; 6152 int ser_section_start; 6153 int ser_section_end; 6154 uint32 ser_flags; 6155 } _soc_ser_parity_info_t; 6156 6157 #define SOC_NUM_GENERIC_PROT_SECTIONS 4 6158 typedef enum { 6159 _SOC_SER_PARITY_1BIT, 6160 _SOC_SER_ECC_1FLD = _SOC_SER_PARITY_1BIT, 6161 _SOC_SER_PARITY_2BITS, 6162 _SOC_SER_ECC_2FLD = _SOC_SER_PARITY_2BITS, 6163 _SOC_SER_PARITY_4BITS, 6164 _SOC_SER_ECC_4FLD = _SOC_SER_PARITY_4BITS, 6165 _SOC_SER_PARITY_8BITS 6166 } _soc_ser_protection_mode_t; 6167 6168 typedef enum { 6169 _SOC_SER_TYPE_PARITY, 6170 _SOC_SER_TYPE_ECC 6171 } _soc_ser_protection_type_t; 6172 6173 typedef enum { 6174 _SOC_SER_INTERLEAVE_NONE, 6175 _SOC_SER_INTERLEAVE_MOD2, 6176 _SOC_SER_INTERLEAVE_MOD4 6177 } _soc_ser_interleave_type_t; 6178 6179 typedef struct __soc_ser_start_end_bits_s { 6180 int start_bit; 6181 int end_bit; 6182 } __soc_ser_start_end_bits_t; 6183 6184 typedef struct _soc_generic_ser_info_s { 6185 soc_mem_t mem; /* last if INVALIDm */ 6186 soc_mem_t alias_mem; /* share parity data with alias mem */ 6187 _soc_ser_protection_type_t prot_type; 6188 _soc_ser_protection_mode_t prot_mode; 6189 _soc_ser_interleave_type_t intrlv_mode; 6190 __soc_ser_start_end_bits_t start_end_bits[SOC_NUM_GENERIC_PROT_SECTIONS]; 6191 /* Following is also re-used for the new range disable bitmap to skip memory holes */ 6192 uint32 addr_mask; 6193 int ser_section_start; 6194 int ser_section_end; 6195 int ser_hw_index; 6196 uint32 ser_flags; /* these are read-only */ 6197 uint8 num_instances; /* Valid only for _SOC_SER_FLAG_ACC_TYPE_CHK */ 6198 uint8 addr_start_bit; /* Valid only for _SOC_SER_FLAG_RANGE_DISABLE */ 6199 uint32 ser_dynamic_state; /* can change during runtime */ 6200 } _soc_generic_ser_info_t; 6201 6202 extern int 6203 soc_ser_init(int unit, _soc_ser_parity_info_t *_soc_ser_parity_info, 6204 int max_mem); 6205 extern int 6206 soc_process_ser_parity_error(int unit, 6207 _soc_ser_parity_info_t *_soc_ser_parity_info, 6208 int parity_err_type); 6209 extern int 6210 soc_process_cmicm_ser_parity_error(int unit, 6211 _soc_ser_parity_info_t *_soc_ser_parity_info, 6212 int parity_err_type); 6213 6214 extern int 6215 soc_ser_mem_clear(int unit, 6216 _soc_ser_parity_info_t *_soc_ser_parity_info, 6217 soc_mem_t mem); 6218 extern int 6219 soc_cmicm_ser_mem_clear(int unit, 6220 _soc_ser_parity_info_t *_soc_ser_parity_info, 6221 soc_mem_t mem); 6222 extern int 6223 soc_generic_ser_mem_update(int unit, soc_mem_t mem, int stage, int mode); 6224 extern int 6225 soc_generic_ser_init(int unit, _soc_generic_ser_info_t *_ser_info); 6226 extern int 6227 soc_generic_ser_at_map_init(int unit, uint32 map[], int items); 6228 extern int 6229 soc_generic_ser_process_error(int unit, _soc_generic_ser_info_t *_ser_info, 6230 int err_type); 6231 6232 extern int 6233 soc_ser_mem_nack(void *unit_vp, void *addr_vp, void *d2, 6234 void *d3, void *d4); 6235 6236 extern void 6237 soc_ser_fail(void *unit_vp, void *addr_vp, void *d2, 6238 void *d3, void *d4); 6239 extern int 6240 soc_ser_parity_error_intr(int unit); 6241 6242 extern int 6243 soc_ser_parity_error_cmicm_intr(void *unit_vp, void *d1, void *d2, 6244 void *d3, void *d4); 6245 extern soc_error_t 6246 soc_ser_tcam_scan_engine_enable(int unit, int enable); 6247 6248 typedef struct soc_ser_functions_s { 6249 void (*_soc_ser_stat_nack_f)(int, int*); 6250 void (*_soc_ser_fail_f)(int); 6251 void (*_soc_ser_mem_nack_f)(void*, void*, void*, void*, void*); 6252 void (*_soc_ser_parity_error_intr_f)(void*, void*, void*, void*, void*); 6253 void (*_soc_ser_parity_error_cmicm_intr_f)(void*, void*, void*, void*, void*); 6254 void (*_soc_ser_parity_error_cmicx_intr_f)(void*, void*, void*, void*, void*); 6255 int (*_soc_ser_populate_tcam_log_f)(int, soc_mem_t, soc_acc_type_t, int); 6256 } soc_ser_functions_t; 6257 6258 typedef struct soc_oam_event_functions_s { 6259 void (*_soc_oam_event_intr_f)(void*, void*, void*, void*, void*); 6260 } soc_oam_event_functions_t; 6261 6262 #ifdef PORTMOD_SUPPORT 6263 6264 typedef struct soc_pm_intr_functions_s { 6265 void (*_soc_port_macro_intr_f)(void*, void*, void*, void*, void*); 6266 } soc_pm_intr_functions_t; 6267 6268 #endif /* PORTMOD_SUPPORT */ 6269 6270 #ifdef BCM_TSN_SUPPORT 6271 typedef struct soc_ser_tsn_stat_functions_s { 6272 int (*_soc_tsn_stat_counter_update_f) (int, soc_mem_t, int, uint64); 6273 } soc_ser_tsn_stat_functions_t; 6274 #endif /* BCM_TSN_SUPPORT */ 6275 6276 extern void 6277 soc_ser_function_register(int unit, soc_ser_functions_t *functions); 6278 extern void 6279 soc_oam_event_function_register(int unit, soc_oam_event_functions_t* functions); 6280 #ifdef BCM_TSN_SUPPORT 6281 extern int 6282 soc_ser_tsn_stat_function_register(int unit, soc_ser_tsn_stat_functions_t* functions); 6283 #endif /* BCM_TSN_SUPPORT */ 6284 extern int 6285 soc_ser_populate_tcam_log(int unit, soc_mem_t mem, int target_pipe, int index); 6286 extern int 6287 soc_ser_stat_error(int unit, int port); 6288 extern int 6289 soc_ser_reg_cache_init(int unit); 6290 extern int 6291 soc_ser_reg_cache_clear(int unit, soc_reg_t reg, int port); 6292 extern int 6293 soc_ser_reg_cache_set(int unit, soc_reg_t reg, int port, int index, uint64 data); 6294 extern int 6295 soc_ser_reg32_cache_set(int unit, soc_reg_t reg, int port, int index, uint32 data); 6296 extern int 6297 soc_ser_reg_cache_get(int unit, soc_reg_t reg, int port, int index, uint64 *data); 6298 extern int 6299 soc_ser_reg32_cache_get(int unit, soc_reg_t reg, int port, int index, uint32 *data); 6300 extern void 6301 soc_ser_reg_cache_info(int unit, int *count, int *size); 6302 extern int 6303 soc_ser_reg_load_scrub(int unit, int scrub_load); 6304 extern void 6305 soc_ser_alpm_cache_check(int unit); 6306 6307 6308 typedef struct _soc_ser_correct_info_s { 6309 uint32 flags; 6310 #define SOC_SER_SRC 0x1 /* Reg: 0, Mem: 1 */ 6311 #define SOC_SER_SRC_REG 0x0 6312 #define SOC_SER_SRC_MEM 0x1 6313 #define SOC_SER_REG_MEM_KNOWN 0x2 /* No decoding required */ 6314 #define SOC_SER_REG_MEM_UNKNOWN 0x0 /* Decoding required */ 6315 #define SOC_SER_ERR_HW 0x0 /* Error reported for hw lookup */ 6316 #define SOC_SER_ERR_CPU 0x4 /* Error reported for cpu access */ 6317 #define SOC_SER_ERR_MULTI 0x8 6318 #define SOC_SER_LOG_WRITE_CACHE 0x10 /* ser_correction logic will fill 'cached' entry portion of ser_log */ 6319 #define SOC_SER_LOG_MEM_REPORTED 0x20 /* ser_correction logic will set log_mem.memory to spci.mem_reported */ 6320 #define SOC_SER_ALSO_UPDATE_SW_COUNTER 0x40 /* ser_correction logic must update both hw and sw counters */ 6321 #define SOC_SER_SKIP_HARD_FALT_CHECK 0x80 /* ser_correction logic must skip hard falt check */ 6322 #define SOC_SER_REG_READ_AGAIN 0x100 /* ser_correction logic must read ICTRL_64 again */ 6323 soc_reg_t reg; 6324 soc_mem_t mem; 6325 soc_mem_t mem_reported; 6326 soc_mem_t counter_base_mem; 6327 int inst; 6328 soc_block_t blk_type; /* s/w block type */ 6329 uint32 sblk; /* schan blk */ 6330 int pipe_num; /* for multi pipe devices */ 6331 int acc_type; 6332 uint32 stage; 6333 uint32 addr; 6334 int port; 6335 int index; 6336 uint8 double_bit; 6337 uint32 log_id; 6338 sal_usecs_t detect_time; 6339 int parity_type; 6340 soc_ser_correction_type_t ctype; 6341 } _soc_ser_correct_info_t; 6342 6343 typedef struct _soc_ser_sram_info_s { 6344 #define _SOC_SER_MAX_SRAMS 16 6345 #define _SOC_SER_MAX_ENTRIES_PER_BKT 6 6346 #define _SOC_SER_SRAM_CORRECTION_MODE_0 0 /* So called "original" XOR scheme */ 6347 #define _SOC_SER_SRAM_CORRECTION_MODE_1 1 /* So called "modified" XOR scheme */ 6348 int ram_count; 6349 soc_mem_t view[_SOC_SER_MAX_SRAMS]; 6350 int index_count[_SOC_SER_MAX_SRAMS]; 6351 int mem_indexes[_SOC_SER_MAX_SRAMS][_SOC_SER_MAX_ENTRIES_PER_BKT]; 6352 soc_reg_t force_reg; 6353 soc_mem_t force_mem; 6354 soc_field_t force_field; /* Force XOR generation */ 6355 soc_field_t disable_xor_write_field; /* Disables XOR bank write */ 6356 soc_reg_t disable_reg; 6357 soc_field_t disable_field; /* Disable error generation on write */ 6358 soc_mem_t disable_mem; /* Control mem of MEMWR ECC checking */ 6359 soc_field_t disable_mem_field; /* Field of MEMWR ECC checking */ 6360 int disable_mem_index; 6361 } _soc_ser_sram_info_t; 6362 6363 extern void 6364 _soc_sram_info_init(int unit, _soc_ser_sram_info_t *sram_info); 6365 6366 extern int 6367 soc_ser_correction(int unit, _soc_ser_correct_info_t *si); 6368 extern int 6369 soc_ser_sram_correction(int unit, int pipe, int sblk, int addr, soc_mem_t mem, 6370 int copyno, int index, _soc_ser_correct_info_t *si); 6371 extern int 6372 soc_generic_ser_mem_scan_start(int unit); 6373 extern int 6374 soc_generic_ser_mem_scan_stop(int unit); 6375 extern int 6376 soc_generic_sram_mem_scan_start(int unit); 6377 extern int 6378 soc_generic_sram_mem_scan_stop(int unit); 6379 extern _soc_generic_ser_info_t * 6380 soc_mem_scan_ser_info_get(int unit); 6381 extern int 6382 soc_mem_alpm_aux_table_correction(int unit, int pipe, int index, soc_mem_t mem); 6383 extern int 6384 soc_ser_counter_info_set(int unit, soc_mem_t rst_mem, 6385 uint32 hw_idx, uint32 *entry_data); 6386 extern int 6387 soc_ser_counter_info_get(int unit, soc_mem_t rst_mem, 6388 int hw_idx, uint32 *entry_data); 6389 #ifdef BCM_CMICX_SUPPORT 6390 extern int soc_ser_top_intr_reg_enable(int unit, int num, int bit, int enable); 6391 extern void soc_ser_cmicx_intr_handler(int unit, void *data); 6392 extern int 6393 soc_ser_parity_error_cmicx_intr(void *unit_vp, void *d1, void *d2, 6394 void *d3, void *d4); 6395 #endif 6396 extern void soc_ser_stat_update(int unit, uint32 flags, int blk_type, 6397 int parity_type, uint8 db, 6398 soc_ser_correction_type_t ctype, 6399 soc_stat_t *stat); 6400 6401 #if defined(BCM_TRIDENT_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) 6402 /* FCOE Header Types */ 6403 #define SOC_FCOE_HDR_TYPE_STD 0x1 /* FC standard header */ 6404 #define SOC_FCOE_HDR_TYPE_VFT 0x2 /* Virtual Fabric Tag */ 6405 #define SOC_FCOE_HDR_TYPE_ENCAP 0x3 /* FC encapsulation hdr */ 6406 #define SOC_FCOE_HDR_TYPE_IFR 0x4 /* Inter fabric routing */ 6407 6408 /* FCOE header type configuration */ 6409 typedef struct _soc_fcoe_header_info_s { 6410 int fc_hdr_type; 6411 int r_ctl_min; 6412 int r_ctl_max; 6413 } _soc_fcoe_header_info_t; 6414 #endif /* (BCM_TRIDENT_SUPPORT) || (BCM_TRIUMPH3_SUPPORT) */ 6415 6416 typedef _shr_switch_temperature_monitor_t soc_switch_temperature_monitor_t; 6417 6418 extern int soc_do_init(int unit, int reset); 6419 6420 extern int soc_esw_div64(uint64 x, uint32 y, uint32 *result); 6421 extern int soc_esw_hw_qnum_get(int unit, int port, int cos, int *qnum); 6422 6423 extern int soc_is_valid_block_instance(int unit, soc_block_types_t block_types, int block_instance, int *is_valid); 6424 6425 extern int soc_port_pipe_get(int unit, int port, int *pipe); 6426 /* port_types currently supported: -1(all), ETH_PORT, STK_PORT, INTLB_PORT */ 6427 extern int soc_pipe_port_get(int unit, uint32 port_type, int pipe, 6428 soc_pbmp_t *pbmp); 6429 #if defined(BCM_SAND_SUPPORT) 6430 extern int soc_get_reg_first_block_id(int unit,soc_reg_t reg,uint32 *block); 6431 #endif /* defined(BCM_SAND_SUPPORT) */ 6432 6433 extern int soc_pcie_hot_swap_disable(int unit); 6434 6435 #ifdef INCLUDE_MACSEC 6436 #endif /* INCLUDE_MACSEC */ 6437 6438 /* Generic parameters to configure a PLL */ 6439 typedef struct soc_pp_pll_param_s { 6440 unsigned int ref_freq; 6441 unsigned int ndiv_int; 6442 unsigned int pdiv; 6443 unsigned int mdiv; 6444 unsigned int pp_clk; 6445 unsigned int vco; 6446 } soc_pp_pll_param_t; 6447 6448 /* Generic parameters to configure a PLL */ 6449 typedef struct soc_pll_param_s { 6450 unsigned int ref_freq; 6451 unsigned int ndiv_int; 6452 unsigned int ndiv_frac; 6453 unsigned int pdiv; 6454 unsigned int mdiv; 6455 unsigned int ka; 6456 unsigned int ki; 6457 unsigned int kp; 6458 unsigned int vco_div2; 6459 } soc_pll_param_t; 6460 6461 typedef struct soc_pll_16_param_s { 6462 unsigned int ref_freq; 6463 unsigned int ref_freq_info; 6464 unsigned int pwm_rate; 6465 unsigned int ka; 6466 unsigned int ki; 6467 unsigned int kp; 6468 unsigned int pdiv; 6469 unsigned int ndiv; 6470 unsigned int mdiv[6]; 6471 } soc_pll_16_param_t; 6472 6473 typedef enum { 6474 SOC_RCVR_CLK_SERDES_PLL, 6475 SOC_RCVR_CLK_MASTER_PLL, 6476 SOC_RCVR_CLK_XGPLL_0, 6477 SOC_RCVR_CLK_XGPLL_1, 6478 SOC_RCVR_CLK_XGPLL_2, 6479 SOC_RCVR_CLK_XGPLL_3, 6480 SOC_RCVR_CLK_EXT_PHY_0, 6481 SOC_RCVR_CLK_EXT_PHY_1 6482 } soc_recov_clk_src_t; 6483 6484 extern int soc_switch_sync_mux_from_port(int unit, int port, int *mux); 6485 extern int soc_switch_sync_mux_from_pbm(int unit, pbmp_t pbm, int *mux); 6486 extern int soc_switch_sync_mux_from_other(int unit, soc_recov_clk_src_t src, int *mux); 6487 6488 #ifdef CRASH_RECOVERY_SUPPORT 6489 #define SOC_CR_ENABALED(unit) (SOC_UNIT_VALID(unit) && SOC_IS_JERICHO(unit) && (SOC_CONTROL(unit))->crash_recovery && SOC_IS_DONE_INIT(unit)) 6490 #define SOC_CR_ENABLE(unit) (SOC_CONTROL(unit)->crash_recovery = TRUE) 6491 #define SOC_CR_DISABLE(unit) (SOC_CONTROL(unit)->crash_recovery = FALSE) 6492 #else 6493 #define SOC_CR_ENABALED(unit) FALSE 6494 #endif 6495 6496 typedef struct soc_chip_info_vectors_s { 6497 int (*icid_get)(int unit, uint8 *data, int len); 6498 } soc_chip_info_vectors_t; 6499 6500 extern int 6501 soc_chip_info_vect_config(soc_chip_info_vectors_t *vect); 6502 extern int 6503 soc_icid_default_get(int unit, uint8 *data, int size); 6504 extern int 6505 soc_cpu_flow_ctrl(int unit, int enable); 6506 #endif /* !_SOC_DRV_H */