ddrc28.h (132272B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 10 * 11 * File: ddrc28.h 12 * Purpose: PHY info for ddrc28 13 */ 14 15 16 #ifndef _SOC_PHY_DDRC28_H 17 #define _SOC_PHY_DDRC28_H 18 19 #include <soc/register.h> 20 #include <soc/types.h> 21 22 extern int soc_phy_ddrc28_reg32_read(int unit, soc_reg_t reg, int instance, uint32 *data); 23 extern int soc_phy_ddrc28_reg32_write(int unit, soc_reg_t reg, int instance, uint32 data); 24 extern int soc_phy_ddrc28_reg_field_set(int unit, soc_reg_t reg, uint32 *regval, soc_field_t field, uint32 value); 25 extern int soc_phy_ddrc28_reg_field_get(int unit, soc_reg_t reg, uint32 regval, soc_field_t field, uint32* field_val); 26 27 extern soc_reg_info_t soc_phy_ddrc28_reg_list[]; 28 29 30 extern soc_field_info_t soc_phy_ddrc28_AQ_IO_CONFIGr_fields[]; 31 extern soc_field_info_t soc_phy_ddrc28_AQ_LDO_CONFIGr_fields[]; 32 extern soc_field_info_t soc_phy_ddrc28_AQ_LOOPBACK_CONFIGr_fields[]; 33 extern soc_field_info_t soc_phy_ddrc28_AQ_L_MACRO_RESERVED_REGr_fields[]; 34 extern soc_field_info_t soc_phy_ddrc28_AQ_L_MAX_VDL_ADDRr_fields[]; 35 extern soc_field_info_t soc_phy_ddrc28_AQ_L_MAX_VDL_CTRLr_fields[]; 36 extern soc_field_info_t soc_phy_ddrc28_AQ_L_STATUS_MACRO_RESERVEDr_fields[]; 37 extern soc_field_info_t soc_phy_ddrc28_AQ_U_MACRO_RESERVED_REGr_fields[]; 38 extern soc_field_info_t soc_phy_ddrc28_AQ_U_MAX_VDL_ADDRr_fields[]; 39 extern soc_field_info_t soc_phy_ddrc28_AQ_U_MAX_VDL_CTRLr_fields[]; 40 extern soc_field_info_t soc_phy_ddrc28_AQ_U_STATUS_MACRO_RESERVEDr_fields[]; 41 extern soc_field_info_t soc_phy_ddrc28_COMMON_CK_CONFIGr_fields[]; 42 extern soc_field_info_t soc_phy_ddrc28_COMMON_IO_CONFIGr_fields[]; 43 extern soc_field_info_t soc_phy_ddrc28_COMMON_LDO_CONFIGr_fields[]; 44 extern soc_field_info_t soc_phy_ddrc28_COMMON_MACRO_RESERVED_REGr_fields[]; 45 extern soc_field_info_t soc_phy_ddrc28_COMMON_MAX_VDL_CKr_fields[]; 46 extern soc_field_info_t soc_phy_ddrc28_COMMON_RESCAL_INIT_CONFIGr_fields[]; 47 extern soc_field_info_t soc_phy_ddrc28_COMMON_RESCAL_OPERATION_CONFIGr_fields[]; 48 extern soc_field_info_t soc_phy_ddrc28_COMMON_STATUS_MACRO_RESERVEDr_fields[]; 49 extern soc_field_info_t soc_phy_ddrc28_COMMON_STATUS_RESCALr_fields[]; 50 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr_fields[]; 51 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr_fields[]; 52 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_FREQ_CNTR_CONFIGr_fields[]; 53 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_INPUT_SHIFT_CTRLr_fields[]; 54 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_READ_CLOCK_CONFIGr_fields[]; 55 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_READ_FIFO_CTRLr_fields[]; 56 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr_fields[]; 57 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr_fields[]; 58 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_RESERVED_REGr_fields[]; 59 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_RESET_CTRLr_fields[]; 60 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_REVISIONr_fields[]; 61 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr_fields[]; 62 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr_fields[]; 63 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr_fields[]; 64 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_STATUS_MACRO_RESERVEDr_fields[]; 65 extern soc_field_info_t soc_phy_ddrc28_CONTROL_REGS_WRITE_FIFO_CTRLr_fields[]; 66 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_CDR_IQ_VDL_CONFIGr_fields[]; 67 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_CDR_OPERATION_CONFIGr_fields[]; 68 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_CDR_PN_VDL_CONFIGr_fields[]; 69 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr_fields[]; 70 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_DATA_IO_CONFIGr_fields[]; 71 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_DQS_IO_CONFIGr_fields[]; 72 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_EDCEN_FIFO_CONFIGr_fields[]; 73 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_LDO_R_CONFIGr_fields[]; 74 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_LDO_W_CONFIGr_fields[]; 75 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_MACRO_RESERVED_REGr_fields[]; 76 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MAX_VDL_DQSNr_fields[]; 77 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MAX_VDL_DQSPr_fields[]; 78 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MAX_VDL_FSMr_fields[]; 79 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT0r_fields[]; 80 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT1r_fields[]; 81 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT2r_fields[]; 82 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT3r_fields[]; 83 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT4r_fields[]; 84 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT5r_fields[]; 85 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT6r_fields[]; 86 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_BIT7r_fields[]; 87 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_DBIr_fields[]; 88 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_READ_MIN_VDL_EDCr_fields[]; 89 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_REN_FIFO_CONFIGr_fields[]; 90 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_REN_GEN_ERR_CTRLr_fields[]; 91 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_REN_STRETCH_CONFIGr_fields[]; 92 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_CDR_IQ_VDLr_fields[]; 93 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_CDR_OPERATIONr_fields[]; 94 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_CDR_PN_VDLr_fields[]; 95 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_EDCEN_FIFOr_fields[]; 96 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_EDCRDATA_FIFOr_fields[]; 97 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_MACRO_RESERVEDr_fields[]; 98 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr_fields[]; 99 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr_fields[]; 100 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACHr_fields[]; 101 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r_fields[]; 102 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r_fields[]; 103 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r_fields[]; 104 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr_fields[]; 105 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_RDATA_FIFOr_fields[]; 106 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_REN_FIFOr_fields[]; 107 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_REN_GEN_ERR1r_fields[]; 108 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_REN_GEN_ERR2r_fields[]; 109 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr_fields[]; 110 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_STATUS_WRITE_LEVELINGr_fields[]; 111 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_VREF_DAC_CONFIGr_fields[]; 112 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_LEVELING_CONFIGr_fields[]; 113 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MAX_VDL_DATAr_fields[]; 114 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MAX_VDL_DQSr_fields[]; 115 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT0r_fields[]; 116 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT1r_fields[]; 117 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT2r_fields[]; 118 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT3r_fields[]; 119 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT4r_fields[]; 120 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT5r_fields[]; 121 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT6r_fields[]; 122 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_BIT7r_fields[]; 123 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_DBIr_fields[]; 124 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE0_WRITE_MIN_VDL_EDCr_fields[]; 125 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_CDR_IQ_VDL_CONFIGr_fields[]; 126 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_CDR_OPERATION_CONFIGr_fields[]; 127 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_CDR_PN_VDL_CONFIGr_fields[]; 128 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr_fields[]; 129 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_DATA_IO_CONFIGr_fields[]; 130 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_DQS_IO_CONFIGr_fields[]; 131 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_EDCEN_FIFO_CONFIGr_fields[]; 132 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_LDO_R_CONFIGr_fields[]; 133 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_LDO_W_CONFIGr_fields[]; 134 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_MACRO_RESERVED_REGr_fields[]; 135 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MAX_VDL_DQSNr_fields[]; 136 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MAX_VDL_DQSPr_fields[]; 137 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MAX_VDL_FSMr_fields[]; 138 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT0r_fields[]; 139 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT1r_fields[]; 140 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT2r_fields[]; 141 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT3r_fields[]; 142 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT4r_fields[]; 143 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT5r_fields[]; 144 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT6r_fields[]; 145 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_BIT7r_fields[]; 146 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_DBIr_fields[]; 147 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_READ_MIN_VDL_EDCr_fields[]; 148 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_REN_FIFO_CONFIGr_fields[]; 149 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_REN_GEN_ERR_CTRLr_fields[]; 150 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_REN_STRETCH_CONFIGr_fields[]; 151 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_CDR_IQ_VDLr_fields[]; 152 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_CDR_OPERATIONr_fields[]; 153 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_CDR_PN_VDLr_fields[]; 154 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_EDCEN_FIFOr_fields[]; 155 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_EDCRDATA_FIFOr_fields[]; 156 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_MACRO_RESERVEDr_fields[]; 157 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr_fields[]; 158 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr_fields[]; 159 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACHr_fields[]; 160 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r_fields[]; 161 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r_fields[]; 162 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r_fields[]; 163 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr_fields[]; 164 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_RDATA_FIFOr_fields[]; 165 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_REN_FIFOr_fields[]; 166 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_REN_GEN_ERR1r_fields[]; 167 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_REN_GEN_ERR2r_fields[]; 168 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr_fields[]; 169 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_STATUS_WRITE_LEVELINGr_fields[]; 170 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_VREF_DAC_CONFIGr_fields[]; 171 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_LEVELING_CONFIGr_fields[]; 172 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MAX_VDL_DATAr_fields[]; 173 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MAX_VDL_DQSr_fields[]; 174 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT0r_fields[]; 175 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT1r_fields[]; 176 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT2r_fields[]; 177 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT3r_fields[]; 178 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT4r_fields[]; 179 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT5r_fields[]; 180 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT6r_fields[]; 181 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_BIT7r_fields[]; 182 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_DBIr_fields[]; 183 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE1_WRITE_MIN_VDL_EDCr_fields[]; 184 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_CDR_IQ_VDL_CONFIGr_fields[]; 185 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_CDR_OPERATION_CONFIGr_fields[]; 186 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_CDR_PN_VDL_CONFIGr_fields[]; 187 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr_fields[]; 188 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_DATA_IO_CONFIGr_fields[]; 189 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_DQS_IO_CONFIGr_fields[]; 190 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_EDCEN_FIFO_CONFIGr_fields[]; 191 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_LDO_R_CONFIGr_fields[]; 192 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_LDO_W_CONFIGr_fields[]; 193 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_MACRO_RESERVED_REGr_fields[]; 194 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MAX_VDL_DQSNr_fields[]; 195 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MAX_VDL_DQSPr_fields[]; 196 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MAX_VDL_FSMr_fields[]; 197 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT0r_fields[]; 198 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT1r_fields[]; 199 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT2r_fields[]; 200 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT3r_fields[]; 201 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT4r_fields[]; 202 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT5r_fields[]; 203 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT6r_fields[]; 204 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_BIT7r_fields[]; 205 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_DBIr_fields[]; 206 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_READ_MIN_VDL_EDCr_fields[]; 207 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_REN_FIFO_CONFIGr_fields[]; 208 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_REN_GEN_ERR_CTRLr_fields[]; 209 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_REN_STRETCH_CONFIGr_fields[]; 210 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_CDR_IQ_VDLr_fields[]; 211 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_CDR_OPERATIONr_fields[]; 212 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_CDR_PN_VDLr_fields[]; 213 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_EDCEN_FIFOr_fields[]; 214 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_EDCRDATA_FIFOr_fields[]; 215 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_MACRO_RESERVEDr_fields[]; 216 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr_fields[]; 217 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr_fields[]; 218 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACHr_fields[]; 219 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r_fields[]; 220 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r_fields[]; 221 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r_fields[]; 222 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr_fields[]; 223 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_RDATA_FIFOr_fields[]; 224 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_REN_FIFOr_fields[]; 225 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_REN_GEN_ERR1r_fields[]; 226 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_REN_GEN_ERR2r_fields[]; 227 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr_fields[]; 228 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_STATUS_WRITE_LEVELINGr_fields[]; 229 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_VREF_DAC_CONFIGr_fields[]; 230 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_LEVELING_CONFIGr_fields[]; 231 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MAX_VDL_DATAr_fields[]; 232 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MAX_VDL_DQSr_fields[]; 233 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT0r_fields[]; 234 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT1r_fields[]; 235 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT2r_fields[]; 236 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT3r_fields[]; 237 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT4r_fields[]; 238 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT5r_fields[]; 239 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT6r_fields[]; 240 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_BIT7r_fields[]; 241 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_DBIr_fields[]; 242 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE2_WRITE_MIN_VDL_EDCr_fields[]; 243 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_CDR_IQ_VDL_CONFIGr_fields[]; 244 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_CDR_OPERATION_CONFIGr_fields[]; 245 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_CDR_PN_VDL_CONFIGr_fields[]; 246 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr_fields[]; 247 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_DATA_IO_CONFIGr_fields[]; 248 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_DQS_IO_CONFIGr_fields[]; 249 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_EDCEN_FIFO_CONFIGr_fields[]; 250 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_LDO_R_CONFIGr_fields[]; 251 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_LDO_W_CONFIGr_fields[]; 252 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_MACRO_RESERVED_REGr_fields[]; 253 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MAX_VDL_DQSNr_fields[]; 254 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MAX_VDL_DQSPr_fields[]; 255 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MAX_VDL_FSMr_fields[]; 256 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT0r_fields[]; 257 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT1r_fields[]; 258 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT2r_fields[]; 259 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT3r_fields[]; 260 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT4r_fields[]; 261 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT5r_fields[]; 262 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT6r_fields[]; 263 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_BIT7r_fields[]; 264 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_DBIr_fields[]; 265 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_READ_MIN_VDL_EDCr_fields[]; 266 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_REN_FIFO_CONFIGr_fields[]; 267 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_REN_GEN_ERR_CTRLr_fields[]; 268 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_REN_STRETCH_CONFIGr_fields[]; 269 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_CDR_IQ_VDLr_fields[]; 270 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_CDR_OPERATIONr_fields[]; 271 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_CDR_PN_VDLr_fields[]; 272 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_EDCEN_FIFOr_fields[]; 273 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_EDCRDATA_FIFOr_fields[]; 274 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_MACRO_RESERVEDr_fields[]; 275 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr_fields[]; 276 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr_fields[]; 277 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACHr_fields[]; 278 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r_fields[]; 279 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r_fields[]; 280 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r_fields[]; 281 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr_fields[]; 282 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_RDATA_FIFOr_fields[]; 283 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_REN_FIFOr_fields[]; 284 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_REN_GEN_ERR1r_fields[]; 285 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_REN_GEN_ERR2r_fields[]; 286 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr_fields[]; 287 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_STATUS_WRITE_LEVELINGr_fields[]; 288 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_VREF_DAC_CONFIGr_fields[]; 289 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_LEVELING_CONFIGr_fields[]; 290 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MAX_VDL_DATAr_fields[]; 291 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MAX_VDL_DQSr_fields[]; 292 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT0r_fields[]; 293 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT1r_fields[]; 294 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT2r_fields[]; 295 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT3r_fields[]; 296 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT4r_fields[]; 297 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT5r_fields[]; 298 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT6r_fields[]; 299 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_BIT7r_fields[]; 300 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_DBIr_fields[]; 301 extern soc_field_info_t soc_phy_ddrc28_DQ_BYTE3_WRITE_MIN_VDL_EDCr_fields[]; 302 303 typedef enum soc_phy_ddrc28_fields_e { 304 SOC_PHY_FLD_ACCU_LOADf, 305 SOC_PHY_FLD_ACCU_LOAD_VALUEf, 306 SOC_PHY_FLD_ACCU_POS_THRESHOLDf, 307 SOC_PHY_FLD_ACCU_VALUEf, 308 SOC_PHY_FLD_AQ_L_FLIP_RDATA_UIf, 309 SOC_PHY_FLD_AQ_L_LOOPBACK_WR_RESET_Nf, 310 SOC_PHY_FLD_AQ_L_TEST_UPPER_HALFf, 311 SOC_PHY_FLD_AQ_U_FLIP_RDATA_UIf, 312 SOC_PHY_FLD_AQ_U_LOOPBACK_WR_RESET_Nf, 313 SOC_PHY_FLD_AQ_U_TEST_UPPER_HALFf, 314 SOC_PHY_FLD_A_0f, 315 SOC_PHY_FLD_A_MINUS_1f, 316 SOC_PHY_FLD_A_MINUS_2f, 317 SOC_PHY_FLD_A_MINUS_3f, 318 SOC_PHY_FLD_A_PLUS_1f, 319 SOC_PHY_FLD_A_PLUS_2f, 320 SOC_PHY_FLD_BIAS_CTRLf, 321 SOC_PHY_FLD_BYPASSf, 322 SOC_PHY_FLD_CDR_RESET_Nf, 323 SOC_PHY_FLD_CK_ENABLEf, 324 SOC_PHY_FLD_CLK_DIV_RATIOf, 325 SOC_PHY_FLD_COMP_ACKf, 326 SOC_PHY_FLD_COMP_DONEf, 327 SOC_PHY_FLD_COMP_ENf, 328 SOC_PHY_FLD_COMP_ERRORf, 329 SOC_PHY_FLD_COMP_INIT_FDEPTHf, 330 SOC_PHY_FLD_COMP_INIT_OFFSETf, 331 SOC_PHY_FLD_COMP_OFFSET_ENf, 332 SOC_PHY_FLD_COMP_OFFSET_OPf, 333 SOC_PHY_FLD_CTRLf, 334 SOC_PHY_FLD_CUR_STATEf, 335 SOC_PHY_FLD_CUR_WCOUNTf, 336 SOC_PHY_FLD_DATAf, 337 SOC_PHY_FLD_DATAPATH_ADDITIONAL_LATENCYf, 338 SOC_PHY_FLD_DATAPATH_SHIFT_ENABLEf, 339 SOC_PHY_FLD_DATA_SOURCEf, 340 SOC_PHY_FLD_DCOUNTf, 341 SOC_PHY_FLD_DDR4_CK_PATTERNf, 342 SOC_PHY_FLD_DDR4_GLUE_RESET_Nf, 343 SOC_PHY_FLD_DQ_BYTE0_RD2_2G_DELAY_DECf, 344 SOC_PHY_FLD_DQ_BYTE0_RD2_2G_DELAY_INCf, 345 SOC_PHY_FLD_DQ_BYTE0_RD2_2G_DELAY_IN_USEf, 346 SOC_PHY_FLD_DQ_BYTE0_RD2_2G_SELECTf, 347 SOC_PHY_FLD_DQ_BYTE0_WRITE_ENABLEf, 348 SOC_PHY_FLD_DQ_BYTE1_RD2_2G_DELAY_DECf, 349 SOC_PHY_FLD_DQ_BYTE1_RD2_2G_DELAY_INCf, 350 SOC_PHY_FLD_DQ_BYTE1_RD2_2G_DELAY_IN_USEf, 351 SOC_PHY_FLD_DQ_BYTE1_RD2_2G_SELECTf, 352 SOC_PHY_FLD_DQ_BYTE1_WRITE_ENABLEf, 353 SOC_PHY_FLD_DQ_BYTE2_RD2_2G_DELAY_DECf, 354 SOC_PHY_FLD_DQ_BYTE2_RD2_2G_DELAY_INCf, 355 SOC_PHY_FLD_DQ_BYTE2_RD2_2G_DELAY_IN_USEf, 356 SOC_PHY_FLD_DQ_BYTE2_RD2_2G_SELECTf, 357 SOC_PHY_FLD_DQ_BYTE2_WRITE_ENABLEf, 358 SOC_PHY_FLD_DQ_BYTE3_RD2_2G_DELAY_DECf, 359 SOC_PHY_FLD_DQ_BYTE3_RD2_2G_DELAY_INCf, 360 SOC_PHY_FLD_DQ_BYTE3_RD2_2G_DELAY_IN_USEf, 361 SOC_PHY_FLD_DQ_BYTE3_RD2_2G_SELECTf, 362 SOC_PHY_FLD_DQ_BYTE3_WRITE_ENABLEf, 363 SOC_PHY_FLD_DRC_1G_RESET_Nf, 364 SOC_PHY_FLD_ENABLEf, 365 SOC_PHY_FLD_EN_NLDL_CLKOUT_BARf, 366 SOC_PHY_FLD_ERR1_CLEARf, 367 SOC_PHY_FLD_ERR2_CLEARf, 368 SOC_PHY_FLD_ERRORf, 369 SOC_PHY_FLD_EXP_RCMD_IDf, 370 SOC_PHY_FLD_FREE_RUNNING_MODEf, 371 SOC_PHY_FLD_FREQ_CNTR_FC_RESET_Nf, 372 SOC_PHY_FLD_FREQ_CNTR_RO_RESET_Nf, 373 SOC_PHY_FLD_GDDR5_CK_PATTERNf, 374 SOC_PHY_FLD_GDDR5_MODEf, 375 SOC_PHY_FLD_IB_VDL_LOAD_VALUEf, 376 SOC_PHY_FLD_IB_VDL_VALUEf, 377 SOC_PHY_FLD_ID4f, 378 SOC_PHY_FLD_ID8f, 379 SOC_PHY_FLD_INIT_LOCK_OPTIONSf, 380 SOC_PHY_FLD_INIT_LOCK_STATUSf, 381 SOC_PHY_FLD_INIT_LOCK_TRANSITIONf, 382 SOC_PHY_FLD_I_VDL_LOAD_VALUEf, 383 SOC_PHY_FLD_I_VDL_VALUEf, 384 SOC_PHY_FLD_LOCK_STATUSf, 385 SOC_PHY_FLD_MAJORf, 386 SOC_PHY_FLD_MANUAL_OVERRIDE_ENf, 387 SOC_PHY_FLD_MAX_VDL_STEPf, 388 SOC_PHY_FLD_MAX_WCOUNTf, 389 SOC_PHY_FLD_MINORf, 390 SOC_PHY_FLD_MIN_VDL_STEPf, 391 SOC_PHY_FLD_NCOMP_CODE_2COREf, 392 SOC_PHY_FLD_NCOMP_DINf, 393 SOC_PHY_FLD_NCOMP_ENB_2COREf, 394 SOC_PHY_FLD_NCOMP_INIT_CODEf, 395 SOC_PHY_FLD_NDf, 396 SOC_PHY_FLD_NDONE_2COREf, 397 SOC_PHY_FLD_NTERMf, 398 SOC_PHY_FLD_NXT_RCMD_FIFO_WDATA0f, 399 SOC_PHY_FLD_NXT_RCMD_FIFO_WDATA1f, 400 SOC_PHY_FLD_NXT_RCMD_FIFO_WR0f, 401 SOC_PHY_FLD_NXT_RCMD_FIFO_WR1f, 402 SOC_PHY_FLD_NXT_RD_EN_UI01f, 403 SOC_PHY_FLD_NXT_RD_EN_UI23f, 404 SOC_PHY_FLD_NXT_STATEf, 405 SOC_PHY_FLD_N_VDL_LOAD_VALUEf, 406 SOC_PHY_FLD_N_VDL_VALUEf, 407 SOC_PHY_FLD_OBS_INTERVALf, 408 SOC_PHY_FLD_OBS_RCMD_IDf, 409 SOC_PHY_FLD_OVERRIDE_ENf, 410 SOC_PHY_FLD_OVERRIDE_MODEf, 411 SOC_PHY_FLD_OVERRIDE_VALUEf, 412 SOC_PHY_FLD_PAST_STATE0f, 413 SOC_PHY_FLD_PAST_STATE1f, 414 SOC_PHY_FLD_PAST_STATE2f, 415 SOC_PHY_FLD_PAST_STATE3f, 416 SOC_PHY_FLD_PAST_STATE4f, 417 SOC_PHY_FLD_PAST_STATE5f, 418 SOC_PHY_FLD_PAST_STATE6f, 419 SOC_PHY_FLD_PAST_STATE7f, 420 SOC_PHY_FLD_PCOMP_CODE_2COREf, 421 SOC_PHY_FLD_PCOMP_DINf, 422 SOC_PHY_FLD_PCOMP_ENB_2COREf, 423 SOC_PHY_FLD_PCOMP_INIT_CODEf, 424 SOC_PHY_FLD_PDf, 425 SOC_PHY_FLD_PDONE_2COREf, 426 SOC_PHY_FLD_PHY_1G_RESET_Nf, 427 SOC_PHY_FLD_PHY_2G_RESET_Nf, 428 SOC_PHY_FLD_PNCOMP_INIT_DIFFf, 429 SOC_PHY_FLD_POWERSAVE_ENf, 430 SOC_PHY_FLD_PTERMf, 431 SOC_PHY_FLD_PWRDNf, 432 SOC_PHY_FLD_P_VDL_LOAD_VALUEf, 433 SOC_PHY_FLD_P_VDL_VALUEf, 434 SOC_PHY_FLD_Q_VDL_LOAD_VALUEf, 435 SOC_PHY_FLD_Q_VDL_VALUEf, 436 SOC_PHY_FLD_RCMD_ADDITIONAL_LATENCYf, 437 SOC_PHY_FLD_RCMD_FIFO_RDf, 438 SOC_PHY_FLD_RCMD_FIFO_RDATAf, 439 SOC_PHY_FLD_RCMD_FIFO_RESET_Nf, 440 SOC_PHY_FLD_RCMD_PAIRf, 441 SOC_PHY_FLD_RCMD_SHIFT_ENABLEf, 442 SOC_PHY_FLD_RD2_2G_DELAYf, 443 SOC_PHY_FLD_RD_2G_DELAYf, 444 SOC_PHY_FLD_RD_2G_DELAY_DECf, 445 SOC_PHY_FLD_RD_2G_DELAY_INCf, 446 SOC_PHY_FLD_RD_DELAYf, 447 SOC_PHY_FLD_RD_EN_UI01f, 448 SOC_PHY_FLD_RD_EN_UI23f, 449 SOC_PHY_FLD_RD_SELf, 450 SOC_PHY_FLD_READ_FIFO_RESET_Nf, 451 SOC_PHY_FLD_READ_FSM_CLOCK_SOURCEf, 452 SOC_PHY_FLD_REF_CTRLf, 453 SOC_PHY_FLD_REF_EXTf, 454 SOC_PHY_FLD_REF_SEL_EXTf, 455 SOC_PHY_FLD_RESCAL_RESET_Nf, 456 SOC_PHY_FLD_RESERVEDf, 457 SOC_PHY_FLD_RO_OVERFLOWf, 458 SOC_PHY_FLD_RO_UCOUNTf, 459 SOC_PHY_FLD_RO_VDL_STEPf, 460 SOC_PHY_FLD_RPf, 461 SOC_PHY_FLD_RP0f, 462 SOC_PHY_FLD_RP0_XMSBf, 463 SOC_PHY_FLD_RP1f, 464 SOC_PHY_FLD_RP1_XMSBf, 465 SOC_PHY_FLD_RP_1Gf, 466 SOC_PHY_FLD_RP_1G_XMSBf, 467 SOC_PHY_FLD_RP_2Gf, 468 SOC_PHY_FLD_RP_2G_XMSBf, 469 SOC_PHY_FLD_RP_XMSBf, 470 SOC_PHY_FLD_RXENBf, 471 SOC_PHY_FLD_RXENB_ALERT_Nf, 472 SOC_PHY_FLD_RX_MODEf, 473 SOC_PHY_FLD_SEL_FC_REFCLKf, 474 SOC_PHY_FLD_SLEWf, 475 SOC_PHY_FLD_START_OBSf, 476 SOC_PHY_FLD_STATEf, 477 SOC_PHY_FLD_TEST_PIN_DIV_SELf, 478 SOC_PHY_FLD_TX_MODEf, 479 SOC_PHY_FLD_UI_SHIFTf, 480 SOC_PHY_FLD_UPDATE_GAPf, 481 SOC_PHY_FLD_UPDATE_MODEf, 482 SOC_PHY_FLD_VDL_LOADf, 483 SOC_PHY_FLD_VDL_SWITCHf, 484 SOC_PHY_FLD_VDL_VALUE_CAPf, 485 SOC_PHY_FLD_W2R_MIN_DELAY_2f, 486 SOC_PHY_FLD_WCLK_SELf, 487 SOC_PHY_FLD_WFULLf, 488 SOC_PHY_FLD_WPf, 489 SOC_PHY_FLD_WP0f, 490 SOC_PHY_FLD_WP0_XMSBf, 491 SOC_PHY_FLD_WP1f, 492 SOC_PHY_FLD_WP1_XMSBf, 493 SOC_PHY_FLD_WP_XMSBf, 494 SOC_PHY_FLD_WRITE_ERRORf, 495 SOC_PHY_FLD_WRITE_LEVELING_MODEf, 496 SOC_PHY_DDRC28_NUM_FIELDS 497 } soc_phy_ddrc28_fields_t; 498 499 #include <soc/types.h> 500 501 #ifndef SOC_RESET_VAL_DEC 502 # if !defined(SOC_NO_RESET_VALS) 503 # define SOC_RESET_VAL_DEC(_lo, _hi) _lo, _hi, 504 # define SOC_RESET_MASK_DEC(_lo, _hi) _lo, _hi, 505 # else 506 # define SOC_RESET_VAL_DEC(_lo, _hi) 507 # define SOC_RESET_MASK_DEC(_lo, _hi) 508 # endif 509 #endif 510 511 typedef enum soc_phy_ddrc28_reg_e { 512 SOC_PHY_REG_AQ_IO_CONFIGr, 513 SOC_PHY_REG_AQ_LDO_CONFIGr, 514 SOC_PHY_REG_AQ_LOOPBACK_CONFIGr, 515 SOC_PHY_REG_AQ_L_MACRO_RESERVED_REGr, 516 SOC_PHY_REG_AQ_L_MAX_VDL_ADDRr, 517 SOC_PHY_REG_AQ_L_MAX_VDL_CTRLr, 518 SOC_PHY_REG_AQ_L_STATUS_MACRO_RESERVEDr, 519 SOC_PHY_REG_AQ_U_MACRO_RESERVED_REGr, 520 SOC_PHY_REG_AQ_U_MAX_VDL_ADDRr, 521 SOC_PHY_REG_AQ_U_MAX_VDL_CTRLr, 522 SOC_PHY_REG_AQ_U_STATUS_MACRO_RESERVEDr, 523 SOC_PHY_REG_COMMON_CK_CONFIGr, 524 SOC_PHY_REG_COMMON_IO_CONFIGr, 525 SOC_PHY_REG_COMMON_LDO_CONFIGr, 526 SOC_PHY_REG_COMMON_MACRO_RESERVED_REGr, 527 SOC_PHY_REG_COMMON_MAX_VDL_CKr, 528 SOC_PHY_REG_COMMON_RESCAL_INIT_CONFIGr, 529 SOC_PHY_REG_COMMON_RESCAL_OPERATION_CONFIGr, 530 SOC_PHY_REG_COMMON_STATUS_MACRO_RESERVEDr, 531 SOC_PHY_REG_COMMON_STATUS_RESCALr, 532 SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr, 533 SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr, 534 SOC_PHY_REG_CONTROL_REGS_FREQ_CNTR_CONFIGr, 535 SOC_PHY_REG_CONTROL_REGS_INPUT_SHIFT_CTRLr, 536 SOC_PHY_REG_CONTROL_REGS_READ_CLOCK_CONFIGr, 537 SOC_PHY_REG_CONTROL_REGS_READ_FIFO_CTRLr, 538 SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr, 539 SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr, 540 SOC_PHY_REG_CONTROL_REGS_RESERVED_REGr, 541 SOC_PHY_REG_CONTROL_REGS_RESET_CTRLr, 542 SOC_PHY_REG_CONTROL_REGS_REVISIONr, 543 SOC_PHY_REG_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr, 544 SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr, 545 SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr, 546 SOC_PHY_REG_CONTROL_REGS_STATUS_MACRO_RESERVEDr, 547 SOC_PHY_REG_CONTROL_REGS_WRITE_FIFO_CTRLr, 548 SOC_PHY_REG_DQ_BYTE0_CDR_IQ_VDL_CONFIGr, 549 SOC_PHY_REG_DQ_BYTE0_CDR_OPERATION_CONFIGr, 550 SOC_PHY_REG_DQ_BYTE0_CDR_PN_VDL_CONFIGr, 551 SOC_PHY_REG_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr, 552 SOC_PHY_REG_DQ_BYTE0_DATA_IO_CONFIGr, 553 SOC_PHY_REG_DQ_BYTE0_DQS_IO_CONFIGr, 554 SOC_PHY_REG_DQ_BYTE0_EDCEN_FIFO_CONFIGr, 555 SOC_PHY_REG_DQ_BYTE0_LDO_R_CONFIGr, 556 SOC_PHY_REG_DQ_BYTE0_LDO_W_CONFIGr, 557 SOC_PHY_REG_DQ_BYTE0_MACRO_RESERVED_REGr, 558 SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSNr, 559 SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSPr, 560 SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_FSMr, 561 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT0r, 562 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT1r, 563 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT2r, 564 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT3r, 565 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT4r, 566 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT5r, 567 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT6r, 568 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT7r, 569 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_DBIr, 570 SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_EDCr, 571 SOC_PHY_REG_DQ_BYTE0_REN_FIFO_CONFIGr, 572 SOC_PHY_REG_DQ_BYTE0_REN_GEN_ERR_CTRLr, 573 SOC_PHY_REG_DQ_BYTE0_REN_STRETCH_CONFIGr, 574 SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_IQ_VDLr, 575 SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_OPERATIONr, 576 SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_PN_VDLr, 577 SOC_PHY_REG_DQ_BYTE0_STATUS_EDCEN_FIFOr, 578 SOC_PHY_REG_DQ_BYTE0_STATUS_EDCRDATA_FIFOr, 579 SOC_PHY_REG_DQ_BYTE0_STATUS_MACRO_RESERVEDr, 580 SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr, 581 SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr, 582 SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACHr, 583 SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r, 584 SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r, 585 SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r, 586 SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr, 587 SOC_PHY_REG_DQ_BYTE0_STATUS_RDATA_FIFOr, 588 SOC_PHY_REG_DQ_BYTE0_STATUS_REN_FIFOr, 589 SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR1r, 590 SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR2r, 591 SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr, 592 SOC_PHY_REG_DQ_BYTE0_STATUS_WRITE_LEVELINGr, 593 SOC_PHY_REG_DQ_BYTE0_VREF_DAC_CONFIGr, 594 SOC_PHY_REG_DQ_BYTE0_WRITE_LEVELING_CONFIGr, 595 SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DATAr, 596 SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DQSr, 597 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT0r, 598 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT1r, 599 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT2r, 600 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT3r, 601 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT4r, 602 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT5r, 603 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT6r, 604 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT7r, 605 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_DBIr, 606 SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_EDCr, 607 SOC_PHY_REG_DQ_BYTE1_CDR_IQ_VDL_CONFIGr, 608 SOC_PHY_REG_DQ_BYTE1_CDR_OPERATION_CONFIGr, 609 SOC_PHY_REG_DQ_BYTE1_CDR_PN_VDL_CONFIGr, 610 SOC_PHY_REG_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr, 611 SOC_PHY_REG_DQ_BYTE1_DATA_IO_CONFIGr, 612 SOC_PHY_REG_DQ_BYTE1_DQS_IO_CONFIGr, 613 SOC_PHY_REG_DQ_BYTE1_EDCEN_FIFO_CONFIGr, 614 SOC_PHY_REG_DQ_BYTE1_LDO_R_CONFIGr, 615 SOC_PHY_REG_DQ_BYTE1_LDO_W_CONFIGr, 616 SOC_PHY_REG_DQ_BYTE1_MACRO_RESERVED_REGr, 617 SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSNr, 618 SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSPr, 619 SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_FSMr, 620 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT0r, 621 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT1r, 622 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT2r, 623 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT3r, 624 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT4r, 625 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT5r, 626 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT6r, 627 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT7r, 628 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_DBIr, 629 SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_EDCr, 630 SOC_PHY_REG_DQ_BYTE1_REN_FIFO_CONFIGr, 631 SOC_PHY_REG_DQ_BYTE1_REN_GEN_ERR_CTRLr, 632 SOC_PHY_REG_DQ_BYTE1_REN_STRETCH_CONFIGr, 633 SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_IQ_VDLr, 634 SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_OPERATIONr, 635 SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_PN_VDLr, 636 SOC_PHY_REG_DQ_BYTE1_STATUS_EDCEN_FIFOr, 637 SOC_PHY_REG_DQ_BYTE1_STATUS_EDCRDATA_FIFOr, 638 SOC_PHY_REG_DQ_BYTE1_STATUS_MACRO_RESERVEDr, 639 SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr, 640 SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr, 641 SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACHr, 642 SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r, 643 SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r, 644 SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r, 645 SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr, 646 SOC_PHY_REG_DQ_BYTE1_STATUS_RDATA_FIFOr, 647 SOC_PHY_REG_DQ_BYTE1_STATUS_REN_FIFOr, 648 SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR1r, 649 SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR2r, 650 SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr, 651 SOC_PHY_REG_DQ_BYTE1_STATUS_WRITE_LEVELINGr, 652 SOC_PHY_REG_DQ_BYTE1_VREF_DAC_CONFIGr, 653 SOC_PHY_REG_DQ_BYTE1_WRITE_LEVELING_CONFIGr, 654 SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DATAr, 655 SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DQSr, 656 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT0r, 657 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT1r, 658 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT2r, 659 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT3r, 660 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT4r, 661 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT5r, 662 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT6r, 663 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT7r, 664 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_DBIr, 665 SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_EDCr, 666 SOC_PHY_REG_DQ_BYTE2_CDR_IQ_VDL_CONFIGr, 667 SOC_PHY_REG_DQ_BYTE2_CDR_OPERATION_CONFIGr, 668 SOC_PHY_REG_DQ_BYTE2_CDR_PN_VDL_CONFIGr, 669 SOC_PHY_REG_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr, 670 SOC_PHY_REG_DQ_BYTE2_DATA_IO_CONFIGr, 671 SOC_PHY_REG_DQ_BYTE2_DQS_IO_CONFIGr, 672 SOC_PHY_REG_DQ_BYTE2_EDCEN_FIFO_CONFIGr, 673 SOC_PHY_REG_DQ_BYTE2_LDO_R_CONFIGr, 674 SOC_PHY_REG_DQ_BYTE2_LDO_W_CONFIGr, 675 SOC_PHY_REG_DQ_BYTE2_MACRO_RESERVED_REGr, 676 SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSNr, 677 SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSPr, 678 SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_FSMr, 679 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT0r, 680 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT1r, 681 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT2r, 682 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT3r, 683 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT4r, 684 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT5r, 685 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT6r, 686 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT7r, 687 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_DBIr, 688 SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_EDCr, 689 SOC_PHY_REG_DQ_BYTE2_REN_FIFO_CONFIGr, 690 SOC_PHY_REG_DQ_BYTE2_REN_GEN_ERR_CTRLr, 691 SOC_PHY_REG_DQ_BYTE2_REN_STRETCH_CONFIGr, 692 SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_IQ_VDLr, 693 SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_OPERATIONr, 694 SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_PN_VDLr, 695 SOC_PHY_REG_DQ_BYTE2_STATUS_EDCEN_FIFOr, 696 SOC_PHY_REG_DQ_BYTE2_STATUS_EDCRDATA_FIFOr, 697 SOC_PHY_REG_DQ_BYTE2_STATUS_MACRO_RESERVEDr, 698 SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr, 699 SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr, 700 SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACHr, 701 SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r, 702 SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r, 703 SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r, 704 SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr, 705 SOC_PHY_REG_DQ_BYTE2_STATUS_RDATA_FIFOr, 706 SOC_PHY_REG_DQ_BYTE2_STATUS_REN_FIFOr, 707 SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR1r, 708 SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR2r, 709 SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr, 710 SOC_PHY_REG_DQ_BYTE2_STATUS_WRITE_LEVELINGr, 711 SOC_PHY_REG_DQ_BYTE2_VREF_DAC_CONFIGr, 712 SOC_PHY_REG_DQ_BYTE2_WRITE_LEVELING_CONFIGr, 713 SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DATAr, 714 SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DQSr, 715 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT0r, 716 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT1r, 717 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT2r, 718 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT3r, 719 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT4r, 720 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT5r, 721 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT6r, 722 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT7r, 723 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_DBIr, 724 SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_EDCr, 725 SOC_PHY_REG_DQ_BYTE3_CDR_IQ_VDL_CONFIGr, 726 SOC_PHY_REG_DQ_BYTE3_CDR_OPERATION_CONFIGr, 727 SOC_PHY_REG_DQ_BYTE3_CDR_PN_VDL_CONFIGr, 728 SOC_PHY_REG_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr, 729 SOC_PHY_REG_DQ_BYTE3_DATA_IO_CONFIGr, 730 SOC_PHY_REG_DQ_BYTE3_DQS_IO_CONFIGr, 731 SOC_PHY_REG_DQ_BYTE3_EDCEN_FIFO_CONFIGr, 732 SOC_PHY_REG_DQ_BYTE3_LDO_R_CONFIGr, 733 SOC_PHY_REG_DQ_BYTE3_LDO_W_CONFIGr, 734 SOC_PHY_REG_DQ_BYTE3_MACRO_RESERVED_REGr, 735 SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSNr, 736 SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSPr, 737 SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_FSMr, 738 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT0r, 739 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT1r, 740 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT2r, 741 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT3r, 742 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT4r, 743 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT5r, 744 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT6r, 745 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT7r, 746 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_DBIr, 747 SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_EDCr, 748 SOC_PHY_REG_DQ_BYTE3_REN_FIFO_CONFIGr, 749 SOC_PHY_REG_DQ_BYTE3_REN_GEN_ERR_CTRLr, 750 SOC_PHY_REG_DQ_BYTE3_REN_STRETCH_CONFIGr, 751 SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_IQ_VDLr, 752 SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_OPERATIONr, 753 SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_PN_VDLr, 754 SOC_PHY_REG_DQ_BYTE3_STATUS_EDCEN_FIFOr, 755 SOC_PHY_REG_DQ_BYTE3_STATUS_EDCRDATA_FIFOr, 756 SOC_PHY_REG_DQ_BYTE3_STATUS_MACRO_RESERVEDr, 757 SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr, 758 SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr, 759 SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACHr, 760 SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r, 761 SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r, 762 SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r, 763 SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr, 764 SOC_PHY_REG_DQ_BYTE3_STATUS_RDATA_FIFOr, 765 SOC_PHY_REG_DQ_BYTE3_STATUS_REN_FIFOr, 766 SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR1r, 767 SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR2r, 768 SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr, 769 SOC_PHY_REG_DQ_BYTE3_STATUS_WRITE_LEVELINGr, 770 SOC_PHY_REG_DQ_BYTE3_VREF_DAC_CONFIGr, 771 SOC_PHY_REG_DQ_BYTE3_WRITE_LEVELING_CONFIGr, 772 SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DATAr, 773 SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DQSr, 774 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT0r, 775 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT1r, 776 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT2r, 777 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT3r, 778 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT4r, 779 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT5r, 780 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT6r, 781 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT7r, 782 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_DBIr, 783 SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_EDCr, 784 SOC_PHY_DDRC28_NUM_REGS 785 } soc_phy_ddrc28_reg_t; 786 787 #define READ_DDRC28_AQ_IO_CONFIGr(unit, instance, data) \ 788 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_IO_CONFIGr, instance, data) 789 #define WRITE_DDRC28_AQ_IO_CONFIGr(unit, instance, data) \ 790 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_IO_CONFIGr, instance, data) 791 792 #define READ_DDRC28_AQ_LDO_CONFIGr(unit, instance, data) \ 793 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_LDO_CONFIGr, instance, data) 794 #define WRITE_DDRC28_AQ_LDO_CONFIGr(unit, instance, data) \ 795 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_LDO_CONFIGr, instance, data) 796 797 #define READ_DDRC28_AQ_LOOPBACK_CONFIGr(unit, instance, data) \ 798 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_LOOPBACK_CONFIGr, instance, data) 799 #define WRITE_DDRC28_AQ_LOOPBACK_CONFIGr(unit, instance, data) \ 800 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_LOOPBACK_CONFIGr, instance, data) 801 802 #define READ_DDRC28_AQ_L_MACRO_RESERVED_REGr(unit, instance, data) \ 803 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_L_MACRO_RESERVED_REGr, instance, data) 804 #define WRITE_DDRC28_AQ_L_MACRO_RESERVED_REGr(unit, instance, data) \ 805 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_L_MACRO_RESERVED_REGr, instance, data) 806 807 #define READ_DDRC28_AQ_L_MAX_VDL_ADDRr(unit, instance, data) \ 808 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_L_MAX_VDL_ADDRr, instance, data) 809 #define WRITE_DDRC28_AQ_L_MAX_VDL_ADDRr(unit, instance, data) \ 810 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_L_MAX_VDL_ADDRr, instance, data) 811 812 #define READ_DDRC28_AQ_L_MAX_VDL_CTRLr(unit, instance, data) \ 813 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_L_MAX_VDL_CTRLr, instance, data) 814 #define WRITE_DDRC28_AQ_L_MAX_VDL_CTRLr(unit, instance, data) \ 815 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_L_MAX_VDL_CTRLr, instance, data) 816 817 #define READ_DDRC28_AQ_L_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 818 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_L_STATUS_MACRO_RESERVEDr, instance, data) 819 #define WRITE_DDRC28_AQ_L_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 820 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_L_STATUS_MACRO_RESERVEDr, instance, data) 821 822 #define READ_DDRC28_AQ_U_MACRO_RESERVED_REGr(unit, instance, data) \ 823 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_U_MACRO_RESERVED_REGr, instance, data) 824 #define WRITE_DDRC28_AQ_U_MACRO_RESERVED_REGr(unit, instance, data) \ 825 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_U_MACRO_RESERVED_REGr, instance, data) 826 827 #define READ_DDRC28_AQ_U_MAX_VDL_ADDRr(unit, instance, data) \ 828 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_U_MAX_VDL_ADDRr, instance, data) 829 #define WRITE_DDRC28_AQ_U_MAX_VDL_ADDRr(unit, instance, data) \ 830 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_U_MAX_VDL_ADDRr, instance, data) 831 832 #define READ_DDRC28_AQ_U_MAX_VDL_CTRLr(unit, instance, data) \ 833 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_U_MAX_VDL_CTRLr, instance, data) 834 #define WRITE_DDRC28_AQ_U_MAX_VDL_CTRLr(unit, instance, data) \ 835 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_U_MAX_VDL_CTRLr, instance, data) 836 837 #define READ_DDRC28_AQ_U_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 838 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_AQ_U_STATUS_MACRO_RESERVEDr, instance, data) 839 #define WRITE_DDRC28_AQ_U_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 840 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_AQ_U_STATUS_MACRO_RESERVEDr, instance, data) 841 842 #define READ_DDRC28_COMMON_CK_CONFIGr(unit, instance, data) \ 843 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_CK_CONFIGr, instance, data) 844 #define WRITE_DDRC28_COMMON_CK_CONFIGr(unit, instance, data) \ 845 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_CK_CONFIGr, instance, data) 846 847 #define READ_DDRC28_COMMON_IO_CONFIGr(unit, instance, data) \ 848 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_IO_CONFIGr, instance, data) 849 #define WRITE_DDRC28_COMMON_IO_CONFIGr(unit, instance, data) \ 850 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_IO_CONFIGr, instance, data) 851 852 #define READ_DDRC28_COMMON_LDO_CONFIGr(unit, instance, data) \ 853 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_LDO_CONFIGr, instance, data) 854 #define WRITE_DDRC28_COMMON_LDO_CONFIGr(unit, instance, data) \ 855 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_LDO_CONFIGr, instance, data) 856 857 #define READ_DDRC28_COMMON_MACRO_RESERVED_REGr(unit, instance, data) \ 858 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_MACRO_RESERVED_REGr, instance, data) 859 #define WRITE_DDRC28_COMMON_MACRO_RESERVED_REGr(unit, instance, data) \ 860 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_MACRO_RESERVED_REGr, instance, data) 861 862 #define READ_DDRC28_COMMON_MAX_VDL_CKr(unit, instance, data) \ 863 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_MAX_VDL_CKr, instance, data) 864 #define WRITE_DDRC28_COMMON_MAX_VDL_CKr(unit, instance, data) \ 865 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_MAX_VDL_CKr, instance, data) 866 867 #define READ_DDRC28_COMMON_RESCAL_INIT_CONFIGr(unit, instance, data) \ 868 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_RESCAL_INIT_CONFIGr, instance, data) 869 #define WRITE_DDRC28_COMMON_RESCAL_INIT_CONFIGr(unit, instance, data) \ 870 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_RESCAL_INIT_CONFIGr, instance, data) 871 872 #define READ_DDRC28_COMMON_RESCAL_OPERATION_CONFIGr(unit, instance, data) \ 873 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_RESCAL_OPERATION_CONFIGr, instance, data) 874 #define WRITE_DDRC28_COMMON_RESCAL_OPERATION_CONFIGr(unit, instance, data) \ 875 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_RESCAL_OPERATION_CONFIGr, instance, data) 876 877 #define READ_DDRC28_COMMON_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 878 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_STATUS_MACRO_RESERVEDr, instance, data) 879 #define WRITE_DDRC28_COMMON_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 880 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_STATUS_MACRO_RESERVEDr, instance, data) 881 882 #define READ_DDRC28_COMMON_STATUS_RESCALr(unit, instance, data) \ 883 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_COMMON_STATUS_RESCALr, instance, data) 884 #define WRITE_DDRC28_COMMON_STATUS_RESCALr(unit, instance, data) \ 885 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_COMMON_STATUS_RESCALr, instance, data) 886 887 #define READ_DDRC28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr(unit, instance, data) \ 888 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr, instance, data) 889 #define WRITE_DDRC28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr(unit, instance, data) \ 890 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_INITIALIZERr, instance, data) 891 892 #define READ_DDRC28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr(unit, instance, data) \ 893 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr, instance, data) 894 #define WRITE_DDRC28_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr(unit, instance, data) \ 895 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_EDCEN_FIFO_CENTRAL_MODIFIERr, instance, data) 896 897 #define READ_DDRC28_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, instance, data) \ 898 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_FREQ_CNTR_CONFIGr, instance, data) 899 #define WRITE_DDRC28_CONTROL_REGS_FREQ_CNTR_CONFIGr(unit, instance, data) \ 900 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_FREQ_CNTR_CONFIGr, instance, data) 901 902 #define READ_DDRC28_CONTROL_REGS_INPUT_SHIFT_CTRLr(unit, instance, data) \ 903 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_INPUT_SHIFT_CTRLr, instance, data) 904 #define WRITE_DDRC28_CONTROL_REGS_INPUT_SHIFT_CTRLr(unit, instance, data) \ 905 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_INPUT_SHIFT_CTRLr, instance, data) 906 907 #define READ_DDRC28_CONTROL_REGS_READ_CLOCK_CONFIGr(unit, instance, data) \ 908 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_READ_CLOCK_CONFIGr, instance, data) 909 #define WRITE_DDRC28_CONTROL_REGS_READ_CLOCK_CONFIGr(unit, instance, data) \ 910 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_READ_CLOCK_CONFIGr, instance, data) 911 912 #define READ_DDRC28_CONTROL_REGS_READ_FIFO_CTRLr(unit, instance, data) \ 913 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_READ_FIFO_CTRLr, instance, data) 914 #define WRITE_DDRC28_CONTROL_REGS_READ_FIFO_CTRLr(unit, instance, data) \ 915 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_READ_FIFO_CTRLr, instance, data) 916 917 #define READ_DDRC28_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr(unit, instance, data) \ 918 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr, instance, data) 919 #define WRITE_DDRC28_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr(unit, instance, data) \ 920 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_INITIALIZERr, instance, data) 921 922 #define READ_DDRC28_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr(unit, instance, data) \ 923 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr, instance, data) 924 #define WRITE_DDRC28_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr(unit, instance, data) \ 925 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_REN_FIFO_CENTRAL_MODIFIERr, instance, data) 926 927 #define READ_DDRC28_CONTROL_REGS_RESERVED_REGr(unit, instance, data) \ 928 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_RESERVED_REGr, instance, data) 929 #define WRITE_DDRC28_CONTROL_REGS_RESERVED_REGr(unit, instance, data) \ 930 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_RESERVED_REGr, instance, data) 931 932 #define READ_DDRC28_CONTROL_REGS_RESET_CTRLr(unit, instance, data) \ 933 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_RESET_CTRLr, instance, data) 934 #define WRITE_DDRC28_CONTROL_REGS_RESET_CTRLr(unit, instance, data) \ 935 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_RESET_CTRLr, instance, data) 936 937 #define READ_DDRC28_CONTROL_REGS_REVISIONr(unit, instance, data) \ 938 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_REVISIONr, instance, data) 939 #define WRITE_DDRC28_CONTROL_REGS_REVISIONr(unit, instance, data) \ 940 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_REVISIONr, instance, data) 941 942 #define READ_DDRC28_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, instance, data) \ 943 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr, instance, data) 944 #define WRITE_DDRC28_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr(unit, instance, data) \ 945 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_SHARED_VREF_DAC_CONFIGr, instance, data) 946 947 #define READ_DDRC28_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr(unit, instance, data) \ 948 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr, instance, data) 949 #define WRITE_DDRC28_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr(unit, instance, data) \ 950 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNTr, instance, data) 951 952 #define READ_DDRC28_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr(unit, instance, data) \ 953 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr, instance, data) 954 #define WRITE_DDRC28_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr(unit, instance, data) \ 955 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNTr, instance, data) 956 957 #define READ_DDRC28_CONTROL_REGS_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 958 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_MACRO_RESERVEDr, instance, data) 959 #define WRITE_DDRC28_CONTROL_REGS_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 960 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_STATUS_MACRO_RESERVEDr, instance, data) 961 962 #define READ_DDRC28_CONTROL_REGS_WRITE_FIFO_CTRLr(unit, instance, data) \ 963 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_CONTROL_REGS_WRITE_FIFO_CTRLr, instance, data) 964 #define WRITE_DDRC28_CONTROL_REGS_WRITE_FIFO_CTRLr(unit, instance, data) \ 965 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_CONTROL_REGS_WRITE_FIFO_CTRLr, instance, data) 966 967 #define READ_DDRC28_DQ_BYTE0_CDR_IQ_VDL_CONFIGr(unit, instance, data) \ 968 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_CDR_IQ_VDL_CONFIGr, instance, data) 969 #define WRITE_DDRC28_DQ_BYTE0_CDR_IQ_VDL_CONFIGr(unit, instance, data) \ 970 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_CDR_IQ_VDL_CONFIGr, instance, data) 971 972 #define READ_DDRC28_DQ_BYTE0_CDR_OPERATION_CONFIGr(unit, instance, data) \ 973 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_CDR_OPERATION_CONFIGr, instance, data) 974 #define WRITE_DDRC28_DQ_BYTE0_CDR_OPERATION_CONFIGr(unit, instance, data) \ 975 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_CDR_OPERATION_CONFIGr, instance, data) 976 977 #define READ_DDRC28_DQ_BYTE0_CDR_PN_VDL_CONFIGr(unit, instance, data) \ 978 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_CDR_PN_VDL_CONFIGr, instance, data) 979 #define WRITE_DDRC28_DQ_BYTE0_CDR_PN_VDL_CONFIGr(unit, instance, data) \ 980 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_CDR_PN_VDL_CONFIGr, instance, data) 981 982 #define READ_DDRC28_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \ 983 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr, instance, data) 984 #define WRITE_DDRC28_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \ 985 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_CDR_VDL_COMMON_CONFIGr, instance, data) 986 987 #define READ_DDRC28_DQ_BYTE0_DATA_IO_CONFIGr(unit, instance, data) \ 988 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_DATA_IO_CONFIGr, instance, data) 989 #define WRITE_DDRC28_DQ_BYTE0_DATA_IO_CONFIGr(unit, instance, data) \ 990 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_DATA_IO_CONFIGr, instance, data) 991 992 #define READ_DDRC28_DQ_BYTE0_DQS_IO_CONFIGr(unit, instance, data) \ 993 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_DQS_IO_CONFIGr, instance, data) 994 #define WRITE_DDRC28_DQ_BYTE0_DQS_IO_CONFIGr(unit, instance, data) \ 995 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_DQS_IO_CONFIGr, instance, data) 996 997 #define READ_DDRC28_DQ_BYTE0_EDCEN_FIFO_CONFIGr(unit, instance, data) \ 998 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_EDCEN_FIFO_CONFIGr, instance, data) 999 #define WRITE_DDRC28_DQ_BYTE0_EDCEN_FIFO_CONFIGr(unit, instance, data) \ 1000 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_EDCEN_FIFO_CONFIGr, instance, data) 1001 1002 #define READ_DDRC28_DQ_BYTE0_LDO_R_CONFIGr(unit, instance, data) \ 1003 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_LDO_R_CONFIGr, instance, data) 1004 #define WRITE_DDRC28_DQ_BYTE0_LDO_R_CONFIGr(unit, instance, data) \ 1005 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_LDO_R_CONFIGr, instance, data) 1006 1007 #define READ_DDRC28_DQ_BYTE0_LDO_W_CONFIGr(unit, instance, data) \ 1008 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_LDO_W_CONFIGr, instance, data) 1009 #define WRITE_DDRC28_DQ_BYTE0_LDO_W_CONFIGr(unit, instance, data) \ 1010 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_LDO_W_CONFIGr, instance, data) 1011 1012 #define READ_DDRC28_DQ_BYTE0_MACRO_RESERVED_REGr(unit, instance, data) \ 1013 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_MACRO_RESERVED_REGr, instance, data) 1014 #define WRITE_DDRC28_DQ_BYTE0_MACRO_RESERVED_REGr(unit, instance, data) \ 1015 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_MACRO_RESERVED_REGr, instance, data) 1016 1017 #define READ_DDRC28_DQ_BYTE0_READ_MAX_VDL_DQSNr(unit, instance, data) \ 1018 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSNr, instance, data) 1019 #define WRITE_DDRC28_DQ_BYTE0_READ_MAX_VDL_DQSNr(unit, instance, data) \ 1020 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSNr, instance, data) 1021 1022 #define READ_DDRC28_DQ_BYTE0_READ_MAX_VDL_DQSPr(unit, instance, data) \ 1023 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSPr, instance, data) 1024 #define WRITE_DDRC28_DQ_BYTE0_READ_MAX_VDL_DQSPr(unit, instance, data) \ 1025 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_DQSPr, instance, data) 1026 1027 #define READ_DDRC28_DQ_BYTE0_READ_MAX_VDL_FSMr(unit, instance, data) \ 1028 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_FSMr, instance, data) 1029 #define WRITE_DDRC28_DQ_BYTE0_READ_MAX_VDL_FSMr(unit, instance, data) \ 1030 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MAX_VDL_FSMr, instance, data) 1031 1032 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT0r(unit, instance, data) \ 1033 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT0r, instance, data) 1034 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT0r(unit, instance, data) \ 1035 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT0r, instance, data) 1036 1037 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT1r(unit, instance, data) \ 1038 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT1r, instance, data) 1039 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT1r(unit, instance, data) \ 1040 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT1r, instance, data) 1041 1042 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT2r(unit, instance, data) \ 1043 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT2r, instance, data) 1044 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT2r(unit, instance, data) \ 1045 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT2r, instance, data) 1046 1047 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT3r(unit, instance, data) \ 1048 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT3r, instance, data) 1049 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT3r(unit, instance, data) \ 1050 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT3r, instance, data) 1051 1052 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT4r(unit, instance, data) \ 1053 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT4r, instance, data) 1054 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT4r(unit, instance, data) \ 1055 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT4r, instance, data) 1056 1057 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT5r(unit, instance, data) \ 1058 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT5r, instance, data) 1059 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT5r(unit, instance, data) \ 1060 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT5r, instance, data) 1061 1062 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT6r(unit, instance, data) \ 1063 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT6r, instance, data) 1064 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT6r(unit, instance, data) \ 1065 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT6r, instance, data) 1066 1067 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT7r(unit, instance, data) \ 1068 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT7r, instance, data) 1069 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_BIT7r(unit, instance, data) \ 1070 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_BIT7r, instance, data) 1071 1072 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_DBIr(unit, instance, data) \ 1073 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_DBIr, instance, data) 1074 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_DBIr(unit, instance, data) \ 1075 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_DBIr, instance, data) 1076 1077 #define READ_DDRC28_DQ_BYTE0_READ_MIN_VDL_EDCr(unit, instance, data) \ 1078 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_EDCr, instance, data) 1079 #define WRITE_DDRC28_DQ_BYTE0_READ_MIN_VDL_EDCr(unit, instance, data) \ 1080 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_READ_MIN_VDL_EDCr, instance, data) 1081 1082 #define READ_DDRC28_DQ_BYTE0_REN_FIFO_CONFIGr(unit, instance, data) \ 1083 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_REN_FIFO_CONFIGr, instance, data) 1084 #define WRITE_DDRC28_DQ_BYTE0_REN_FIFO_CONFIGr(unit, instance, data) \ 1085 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_REN_FIFO_CONFIGr, instance, data) 1086 1087 #define READ_DDRC28_DQ_BYTE0_REN_GEN_ERR_CTRLr(unit, instance, data) \ 1088 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_REN_GEN_ERR_CTRLr, instance, data) 1089 #define WRITE_DDRC28_DQ_BYTE0_REN_GEN_ERR_CTRLr(unit, instance, data) \ 1090 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_REN_GEN_ERR_CTRLr, instance, data) 1091 1092 #define READ_DDRC28_DQ_BYTE0_REN_STRETCH_CONFIGr(unit, instance, data) \ 1093 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_REN_STRETCH_CONFIGr, instance, data) 1094 #define WRITE_DDRC28_DQ_BYTE0_REN_STRETCH_CONFIGr(unit, instance, data) \ 1095 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_REN_STRETCH_CONFIGr, instance, data) 1096 1097 #define READ_DDRC28_DQ_BYTE0_STATUS_CDR_IQ_VDLr(unit, instance, data) \ 1098 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_IQ_VDLr, instance, data) 1099 #define WRITE_DDRC28_DQ_BYTE0_STATUS_CDR_IQ_VDLr(unit, instance, data) \ 1100 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_IQ_VDLr, instance, data) 1101 1102 #define READ_DDRC28_DQ_BYTE0_STATUS_CDR_OPERATIONr(unit, instance, data) \ 1103 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_OPERATIONr, instance, data) 1104 #define WRITE_DDRC28_DQ_BYTE0_STATUS_CDR_OPERATIONr(unit, instance, data) \ 1105 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_OPERATIONr, instance, data) 1106 1107 #define READ_DDRC28_DQ_BYTE0_STATUS_CDR_PN_VDLr(unit, instance, data) \ 1108 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_PN_VDLr, instance, data) 1109 #define WRITE_DDRC28_DQ_BYTE0_STATUS_CDR_PN_VDLr(unit, instance, data) \ 1110 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_CDR_PN_VDLr, instance, data) 1111 1112 #define READ_DDRC28_DQ_BYTE0_STATUS_EDCEN_FIFOr(unit, instance, data) \ 1113 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_EDCEN_FIFOr, instance, data) 1114 #define WRITE_DDRC28_DQ_BYTE0_STATUS_EDCEN_FIFOr(unit, instance, data) \ 1115 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_EDCEN_FIFOr, instance, data) 1116 1117 #define READ_DDRC28_DQ_BYTE0_STATUS_EDCRDATA_FIFOr(unit, instance, data) \ 1118 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_EDCRDATA_FIFOr, instance, data) 1119 #define WRITE_DDRC28_DQ_BYTE0_STATUS_EDCRDATA_FIFOr(unit, instance, data) \ 1120 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_EDCRDATA_FIFOr, instance, data) 1121 1122 #define READ_DDRC28_DQ_BYTE0_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 1123 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_MACRO_RESERVEDr, instance, data) 1124 #define WRITE_DDRC28_DQ_BYTE0_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 1125 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_MACRO_RESERVEDr, instance, data) 1126 1127 #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \ 1128 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr, instance, data) 1129 #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \ 1130 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_CTRr, instance, data) 1131 1132 #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \ 1133 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr, instance, data) 1134 #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \ 1135 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_FIFO_PTRr, instance, data) 1136 1137 #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACHr(unit, instance, data) \ 1138 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACHr, instance, data) 1139 #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACHr(unit, instance, data) \ 1140 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACHr, instance, data) 1141 1142 #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \ 1143 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r, instance, data) 1144 #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \ 1145 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR1r, instance, data) 1146 1147 #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \ 1148 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r, instance, data) 1149 #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \ 1150 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR2r, instance, data) 1151 1152 #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \ 1153 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r, instance, data) 1154 #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \ 1155 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_ERR3r, instance, data) 1156 1157 #define READ_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \ 1158 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr, instance, data) 1159 #define WRITE_DDRC28_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \ 1160 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RCMD_MACH_RCMD_IDr, instance, data) 1161 1162 #define READ_DDRC28_DQ_BYTE0_STATUS_RDATA_FIFOr(unit, instance, data) \ 1163 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RDATA_FIFOr, instance, data) 1164 #define WRITE_DDRC28_DQ_BYTE0_STATUS_RDATA_FIFOr(unit, instance, data) \ 1165 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_RDATA_FIFOr, instance, data) 1166 1167 #define READ_DDRC28_DQ_BYTE0_STATUS_REN_FIFOr(unit, instance, data) \ 1168 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_FIFOr, instance, data) 1169 #define WRITE_DDRC28_DQ_BYTE0_STATUS_REN_FIFOr(unit, instance, data) \ 1170 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_FIFOr, instance, data) 1171 1172 #define READ_DDRC28_DQ_BYTE0_STATUS_REN_GEN_ERR1r(unit, instance, data) \ 1173 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR1r, instance, data) 1174 #define WRITE_DDRC28_DQ_BYTE0_STATUS_REN_GEN_ERR1r(unit, instance, data) \ 1175 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR1r, instance, data) 1176 1177 #define READ_DDRC28_DQ_BYTE0_STATUS_REN_GEN_ERR2r(unit, instance, data) \ 1178 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR2r, instance, data) 1179 #define WRITE_DDRC28_DQ_BYTE0_STATUS_REN_GEN_ERR2r(unit, instance, data) \ 1180 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_ERR2r, instance, data) 1181 1182 #define READ_DDRC28_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \ 1183 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr, instance, data) 1184 #define WRITE_DDRC28_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \ 1185 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_REN_GEN_RCMD_IDr, instance, data) 1186 1187 #define READ_DDRC28_DQ_BYTE0_STATUS_WRITE_LEVELINGr(unit, instance, data) \ 1188 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_WRITE_LEVELINGr, instance, data) 1189 #define WRITE_DDRC28_DQ_BYTE0_STATUS_WRITE_LEVELINGr(unit, instance, data) \ 1190 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_STATUS_WRITE_LEVELINGr, instance, data) 1191 1192 #define READ_DDRC28_DQ_BYTE0_VREF_DAC_CONFIGr(unit, instance, data) \ 1193 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_VREF_DAC_CONFIGr, instance, data) 1194 #define WRITE_DDRC28_DQ_BYTE0_VREF_DAC_CONFIGr(unit, instance, data) \ 1195 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_VREF_DAC_CONFIGr, instance, data) 1196 1197 #define READ_DDRC28_DQ_BYTE0_WRITE_LEVELING_CONFIGr(unit, instance, data) \ 1198 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_LEVELING_CONFIGr, instance, data) 1199 #define WRITE_DDRC28_DQ_BYTE0_WRITE_LEVELING_CONFIGr(unit, instance, data) \ 1200 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_LEVELING_CONFIGr, instance, data) 1201 1202 #define READ_DDRC28_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, instance, data) \ 1203 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DATAr, instance, data) 1204 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MAX_VDL_DATAr(unit, instance, data) \ 1205 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DATAr, instance, data) 1206 1207 #define READ_DDRC28_DQ_BYTE0_WRITE_MAX_VDL_DQSr(unit, instance, data) \ 1208 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DQSr, instance, data) 1209 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MAX_VDL_DQSr(unit, instance, data) \ 1210 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MAX_VDL_DQSr, instance, data) 1211 1212 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT0r(unit, instance, data) \ 1213 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT0r, instance, data) 1214 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT0r(unit, instance, data) \ 1215 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT0r, instance, data) 1216 1217 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT1r(unit, instance, data) \ 1218 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT1r, instance, data) 1219 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT1r(unit, instance, data) \ 1220 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT1r, instance, data) 1221 1222 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT2r(unit, instance, data) \ 1223 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT2r, instance, data) 1224 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT2r(unit, instance, data) \ 1225 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT2r, instance, data) 1226 1227 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT3r(unit, instance, data) \ 1228 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT3r, instance, data) 1229 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT3r(unit, instance, data) \ 1230 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT3r, instance, data) 1231 1232 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT4r(unit, instance, data) \ 1233 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT4r, instance, data) 1234 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT4r(unit, instance, data) \ 1235 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT4r, instance, data) 1236 1237 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT5r(unit, instance, data) \ 1238 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT5r, instance, data) 1239 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT5r(unit, instance, data) \ 1240 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT5r, instance, data) 1241 1242 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT6r(unit, instance, data) \ 1243 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT6r, instance, data) 1244 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT6r(unit, instance, data) \ 1245 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT6r, instance, data) 1246 1247 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT7r(unit, instance, data) \ 1248 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT7r, instance, data) 1249 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_BIT7r(unit, instance, data) \ 1250 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_BIT7r, instance, data) 1251 1252 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_DBIr(unit, instance, data) \ 1253 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_DBIr, instance, data) 1254 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_DBIr(unit, instance, data) \ 1255 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_DBIr, instance, data) 1256 1257 #define READ_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_EDCr(unit, instance, data) \ 1258 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_EDCr, instance, data) 1259 #define WRITE_DDRC28_DQ_BYTE0_WRITE_MIN_VDL_EDCr(unit, instance, data) \ 1260 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE0_WRITE_MIN_VDL_EDCr, instance, data) 1261 1262 #define READ_DDRC28_DQ_BYTE1_CDR_IQ_VDL_CONFIGr(unit, instance, data) \ 1263 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_CDR_IQ_VDL_CONFIGr, instance, data) 1264 #define WRITE_DDRC28_DQ_BYTE1_CDR_IQ_VDL_CONFIGr(unit, instance, data) \ 1265 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_CDR_IQ_VDL_CONFIGr, instance, data) 1266 1267 #define READ_DDRC28_DQ_BYTE1_CDR_OPERATION_CONFIGr(unit, instance, data) \ 1268 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_CDR_OPERATION_CONFIGr, instance, data) 1269 #define WRITE_DDRC28_DQ_BYTE1_CDR_OPERATION_CONFIGr(unit, instance, data) \ 1270 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_CDR_OPERATION_CONFIGr, instance, data) 1271 1272 #define READ_DDRC28_DQ_BYTE1_CDR_PN_VDL_CONFIGr(unit, instance, data) \ 1273 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_CDR_PN_VDL_CONFIGr, instance, data) 1274 #define WRITE_DDRC28_DQ_BYTE1_CDR_PN_VDL_CONFIGr(unit, instance, data) \ 1275 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_CDR_PN_VDL_CONFIGr, instance, data) 1276 1277 #define READ_DDRC28_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \ 1278 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr, instance, data) 1279 #define WRITE_DDRC28_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \ 1280 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_CDR_VDL_COMMON_CONFIGr, instance, data) 1281 1282 #define READ_DDRC28_DQ_BYTE1_DATA_IO_CONFIGr(unit, instance, data) \ 1283 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_DATA_IO_CONFIGr, instance, data) 1284 #define WRITE_DDRC28_DQ_BYTE1_DATA_IO_CONFIGr(unit, instance, data) \ 1285 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_DATA_IO_CONFIGr, instance, data) 1286 1287 #define READ_DDRC28_DQ_BYTE1_DQS_IO_CONFIGr(unit, instance, data) \ 1288 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_DQS_IO_CONFIGr, instance, data) 1289 #define WRITE_DDRC28_DQ_BYTE1_DQS_IO_CONFIGr(unit, instance, data) \ 1290 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_DQS_IO_CONFIGr, instance, data) 1291 1292 #define READ_DDRC28_DQ_BYTE1_EDCEN_FIFO_CONFIGr(unit, instance, data) \ 1293 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_EDCEN_FIFO_CONFIGr, instance, data) 1294 #define WRITE_DDRC28_DQ_BYTE1_EDCEN_FIFO_CONFIGr(unit, instance, data) \ 1295 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_EDCEN_FIFO_CONFIGr, instance, data) 1296 1297 #define READ_DDRC28_DQ_BYTE1_LDO_R_CONFIGr(unit, instance, data) \ 1298 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_LDO_R_CONFIGr, instance, data) 1299 #define WRITE_DDRC28_DQ_BYTE1_LDO_R_CONFIGr(unit, instance, data) \ 1300 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_LDO_R_CONFIGr, instance, data) 1301 1302 #define READ_DDRC28_DQ_BYTE1_LDO_W_CONFIGr(unit, instance, data) \ 1303 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_LDO_W_CONFIGr, instance, data) 1304 #define WRITE_DDRC28_DQ_BYTE1_LDO_W_CONFIGr(unit, instance, data) \ 1305 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_LDO_W_CONFIGr, instance, data) 1306 1307 #define READ_DDRC28_DQ_BYTE1_MACRO_RESERVED_REGr(unit, instance, data) \ 1308 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_MACRO_RESERVED_REGr, instance, data) 1309 #define WRITE_DDRC28_DQ_BYTE1_MACRO_RESERVED_REGr(unit, instance, data) \ 1310 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_MACRO_RESERVED_REGr, instance, data) 1311 1312 #define READ_DDRC28_DQ_BYTE1_READ_MAX_VDL_DQSNr(unit, instance, data) \ 1313 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSNr, instance, data) 1314 #define WRITE_DDRC28_DQ_BYTE1_READ_MAX_VDL_DQSNr(unit, instance, data) \ 1315 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSNr, instance, data) 1316 1317 #define READ_DDRC28_DQ_BYTE1_READ_MAX_VDL_DQSPr(unit, instance, data) \ 1318 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSPr, instance, data) 1319 #define WRITE_DDRC28_DQ_BYTE1_READ_MAX_VDL_DQSPr(unit, instance, data) \ 1320 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_DQSPr, instance, data) 1321 1322 #define READ_DDRC28_DQ_BYTE1_READ_MAX_VDL_FSMr(unit, instance, data) \ 1323 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_FSMr, instance, data) 1324 #define WRITE_DDRC28_DQ_BYTE1_READ_MAX_VDL_FSMr(unit, instance, data) \ 1325 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MAX_VDL_FSMr, instance, data) 1326 1327 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT0r(unit, instance, data) \ 1328 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT0r, instance, data) 1329 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT0r(unit, instance, data) \ 1330 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT0r, instance, data) 1331 1332 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT1r(unit, instance, data) \ 1333 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT1r, instance, data) 1334 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT1r(unit, instance, data) \ 1335 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT1r, instance, data) 1336 1337 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT2r(unit, instance, data) \ 1338 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT2r, instance, data) 1339 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT2r(unit, instance, data) \ 1340 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT2r, instance, data) 1341 1342 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT3r(unit, instance, data) \ 1343 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT3r, instance, data) 1344 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT3r(unit, instance, data) \ 1345 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT3r, instance, data) 1346 1347 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT4r(unit, instance, data) \ 1348 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT4r, instance, data) 1349 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT4r(unit, instance, data) \ 1350 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT4r, instance, data) 1351 1352 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT5r(unit, instance, data) \ 1353 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT5r, instance, data) 1354 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT5r(unit, instance, data) \ 1355 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT5r, instance, data) 1356 1357 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT6r(unit, instance, data) \ 1358 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT6r, instance, data) 1359 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT6r(unit, instance, data) \ 1360 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT6r, instance, data) 1361 1362 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT7r(unit, instance, data) \ 1363 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT7r, instance, data) 1364 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_BIT7r(unit, instance, data) \ 1365 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_BIT7r, instance, data) 1366 1367 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_DBIr(unit, instance, data) \ 1368 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_DBIr, instance, data) 1369 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_DBIr(unit, instance, data) \ 1370 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_DBIr, instance, data) 1371 1372 #define READ_DDRC28_DQ_BYTE1_READ_MIN_VDL_EDCr(unit, instance, data) \ 1373 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_EDCr, instance, data) 1374 #define WRITE_DDRC28_DQ_BYTE1_READ_MIN_VDL_EDCr(unit, instance, data) \ 1375 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_READ_MIN_VDL_EDCr, instance, data) 1376 1377 #define READ_DDRC28_DQ_BYTE1_REN_FIFO_CONFIGr(unit, instance, data) \ 1378 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_REN_FIFO_CONFIGr, instance, data) 1379 #define WRITE_DDRC28_DQ_BYTE1_REN_FIFO_CONFIGr(unit, instance, data) \ 1380 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_REN_FIFO_CONFIGr, instance, data) 1381 1382 #define READ_DDRC28_DQ_BYTE1_REN_GEN_ERR_CTRLr(unit, instance, data) \ 1383 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_REN_GEN_ERR_CTRLr, instance, data) 1384 #define WRITE_DDRC28_DQ_BYTE1_REN_GEN_ERR_CTRLr(unit, instance, data) \ 1385 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_REN_GEN_ERR_CTRLr, instance, data) 1386 1387 #define READ_DDRC28_DQ_BYTE1_REN_STRETCH_CONFIGr(unit, instance, data) \ 1388 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_REN_STRETCH_CONFIGr, instance, data) 1389 #define WRITE_DDRC28_DQ_BYTE1_REN_STRETCH_CONFIGr(unit, instance, data) \ 1390 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_REN_STRETCH_CONFIGr, instance, data) 1391 1392 #define READ_DDRC28_DQ_BYTE1_STATUS_CDR_IQ_VDLr(unit, instance, data) \ 1393 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_IQ_VDLr, instance, data) 1394 #define WRITE_DDRC28_DQ_BYTE1_STATUS_CDR_IQ_VDLr(unit, instance, data) \ 1395 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_IQ_VDLr, instance, data) 1396 1397 #define READ_DDRC28_DQ_BYTE1_STATUS_CDR_OPERATIONr(unit, instance, data) \ 1398 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_OPERATIONr, instance, data) 1399 #define WRITE_DDRC28_DQ_BYTE1_STATUS_CDR_OPERATIONr(unit, instance, data) \ 1400 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_OPERATIONr, instance, data) 1401 1402 #define READ_DDRC28_DQ_BYTE1_STATUS_CDR_PN_VDLr(unit, instance, data) \ 1403 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_PN_VDLr, instance, data) 1404 #define WRITE_DDRC28_DQ_BYTE1_STATUS_CDR_PN_VDLr(unit, instance, data) \ 1405 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_CDR_PN_VDLr, instance, data) 1406 1407 #define READ_DDRC28_DQ_BYTE1_STATUS_EDCEN_FIFOr(unit, instance, data) \ 1408 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_EDCEN_FIFOr, instance, data) 1409 #define WRITE_DDRC28_DQ_BYTE1_STATUS_EDCEN_FIFOr(unit, instance, data) \ 1410 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_EDCEN_FIFOr, instance, data) 1411 1412 #define READ_DDRC28_DQ_BYTE1_STATUS_EDCRDATA_FIFOr(unit, instance, data) \ 1413 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_EDCRDATA_FIFOr, instance, data) 1414 #define WRITE_DDRC28_DQ_BYTE1_STATUS_EDCRDATA_FIFOr(unit, instance, data) \ 1415 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_EDCRDATA_FIFOr, instance, data) 1416 1417 #define READ_DDRC28_DQ_BYTE1_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 1418 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_MACRO_RESERVEDr, instance, data) 1419 #define WRITE_DDRC28_DQ_BYTE1_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 1420 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_MACRO_RESERVEDr, instance, data) 1421 1422 #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \ 1423 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr, instance, data) 1424 #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \ 1425 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_CTRr, instance, data) 1426 1427 #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \ 1428 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr, instance, data) 1429 #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \ 1430 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_FIFO_PTRr, instance, data) 1431 1432 #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACHr(unit, instance, data) \ 1433 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACHr, instance, data) 1434 #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACHr(unit, instance, data) \ 1435 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACHr, instance, data) 1436 1437 #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \ 1438 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r, instance, data) 1439 #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \ 1440 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR1r, instance, data) 1441 1442 #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \ 1443 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r, instance, data) 1444 #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \ 1445 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR2r, instance, data) 1446 1447 #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \ 1448 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r, instance, data) 1449 #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \ 1450 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_ERR3r, instance, data) 1451 1452 #define READ_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \ 1453 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr, instance, data) 1454 #define WRITE_DDRC28_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \ 1455 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RCMD_MACH_RCMD_IDr, instance, data) 1456 1457 #define READ_DDRC28_DQ_BYTE1_STATUS_RDATA_FIFOr(unit, instance, data) \ 1458 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RDATA_FIFOr, instance, data) 1459 #define WRITE_DDRC28_DQ_BYTE1_STATUS_RDATA_FIFOr(unit, instance, data) \ 1460 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_RDATA_FIFOr, instance, data) 1461 1462 #define READ_DDRC28_DQ_BYTE1_STATUS_REN_FIFOr(unit, instance, data) \ 1463 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_FIFOr, instance, data) 1464 #define WRITE_DDRC28_DQ_BYTE1_STATUS_REN_FIFOr(unit, instance, data) \ 1465 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_FIFOr, instance, data) 1466 1467 #define READ_DDRC28_DQ_BYTE1_STATUS_REN_GEN_ERR1r(unit, instance, data) \ 1468 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR1r, instance, data) 1469 #define WRITE_DDRC28_DQ_BYTE1_STATUS_REN_GEN_ERR1r(unit, instance, data) \ 1470 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR1r, instance, data) 1471 1472 #define READ_DDRC28_DQ_BYTE1_STATUS_REN_GEN_ERR2r(unit, instance, data) \ 1473 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR2r, instance, data) 1474 #define WRITE_DDRC28_DQ_BYTE1_STATUS_REN_GEN_ERR2r(unit, instance, data) \ 1475 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_ERR2r, instance, data) 1476 1477 #define READ_DDRC28_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \ 1478 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr, instance, data) 1479 #define WRITE_DDRC28_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \ 1480 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_REN_GEN_RCMD_IDr, instance, data) 1481 1482 #define READ_DDRC28_DQ_BYTE1_STATUS_WRITE_LEVELINGr(unit, instance, data) \ 1483 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_WRITE_LEVELINGr, instance, data) 1484 #define WRITE_DDRC28_DQ_BYTE1_STATUS_WRITE_LEVELINGr(unit, instance, data) \ 1485 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_STATUS_WRITE_LEVELINGr, instance, data) 1486 1487 #define READ_DDRC28_DQ_BYTE1_VREF_DAC_CONFIGr(unit, instance, data) \ 1488 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_VREF_DAC_CONFIGr, instance, data) 1489 #define WRITE_DDRC28_DQ_BYTE1_VREF_DAC_CONFIGr(unit, instance, data) \ 1490 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_VREF_DAC_CONFIGr, instance, data) 1491 1492 #define READ_DDRC28_DQ_BYTE1_WRITE_LEVELING_CONFIGr(unit, instance, data) \ 1493 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_LEVELING_CONFIGr, instance, data) 1494 #define WRITE_DDRC28_DQ_BYTE1_WRITE_LEVELING_CONFIGr(unit, instance, data) \ 1495 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_LEVELING_CONFIGr, instance, data) 1496 1497 #define READ_DDRC28_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, instance, data) \ 1498 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DATAr, instance, data) 1499 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MAX_VDL_DATAr(unit, instance, data) \ 1500 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DATAr, instance, data) 1501 1502 #define READ_DDRC28_DQ_BYTE1_WRITE_MAX_VDL_DQSr(unit, instance, data) \ 1503 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DQSr, instance, data) 1504 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MAX_VDL_DQSr(unit, instance, data) \ 1505 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MAX_VDL_DQSr, instance, data) 1506 1507 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT0r(unit, instance, data) \ 1508 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT0r, instance, data) 1509 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT0r(unit, instance, data) \ 1510 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT0r, instance, data) 1511 1512 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT1r(unit, instance, data) \ 1513 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT1r, instance, data) 1514 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT1r(unit, instance, data) \ 1515 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT1r, instance, data) 1516 1517 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT2r(unit, instance, data) \ 1518 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT2r, instance, data) 1519 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT2r(unit, instance, data) \ 1520 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT2r, instance, data) 1521 1522 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT3r(unit, instance, data) \ 1523 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT3r, instance, data) 1524 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT3r(unit, instance, data) \ 1525 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT3r, instance, data) 1526 1527 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT4r(unit, instance, data) \ 1528 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT4r, instance, data) 1529 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT4r(unit, instance, data) \ 1530 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT4r, instance, data) 1531 1532 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT5r(unit, instance, data) \ 1533 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT5r, instance, data) 1534 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT5r(unit, instance, data) \ 1535 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT5r, instance, data) 1536 1537 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT6r(unit, instance, data) \ 1538 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT6r, instance, data) 1539 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT6r(unit, instance, data) \ 1540 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT6r, instance, data) 1541 1542 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT7r(unit, instance, data) \ 1543 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT7r, instance, data) 1544 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_BIT7r(unit, instance, data) \ 1545 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_BIT7r, instance, data) 1546 1547 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_DBIr(unit, instance, data) \ 1548 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_DBIr, instance, data) 1549 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_DBIr(unit, instance, data) \ 1550 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_DBIr, instance, data) 1551 1552 #define READ_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_EDCr(unit, instance, data) \ 1553 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_EDCr, instance, data) 1554 #define WRITE_DDRC28_DQ_BYTE1_WRITE_MIN_VDL_EDCr(unit, instance, data) \ 1555 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE1_WRITE_MIN_VDL_EDCr, instance, data) 1556 1557 #define READ_DDRC28_DQ_BYTE2_CDR_IQ_VDL_CONFIGr(unit, instance, data) \ 1558 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_CDR_IQ_VDL_CONFIGr, instance, data) 1559 #define WRITE_DDRC28_DQ_BYTE2_CDR_IQ_VDL_CONFIGr(unit, instance, data) \ 1560 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_CDR_IQ_VDL_CONFIGr, instance, data) 1561 1562 #define READ_DDRC28_DQ_BYTE2_CDR_OPERATION_CONFIGr(unit, instance, data) \ 1563 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_CDR_OPERATION_CONFIGr, instance, data) 1564 #define WRITE_DDRC28_DQ_BYTE2_CDR_OPERATION_CONFIGr(unit, instance, data) \ 1565 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_CDR_OPERATION_CONFIGr, instance, data) 1566 1567 #define READ_DDRC28_DQ_BYTE2_CDR_PN_VDL_CONFIGr(unit, instance, data) \ 1568 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_CDR_PN_VDL_CONFIGr, instance, data) 1569 #define WRITE_DDRC28_DQ_BYTE2_CDR_PN_VDL_CONFIGr(unit, instance, data) \ 1570 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_CDR_PN_VDL_CONFIGr, instance, data) 1571 1572 #define READ_DDRC28_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \ 1573 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr, instance, data) 1574 #define WRITE_DDRC28_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \ 1575 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_CDR_VDL_COMMON_CONFIGr, instance, data) 1576 1577 #define READ_DDRC28_DQ_BYTE2_DATA_IO_CONFIGr(unit, instance, data) \ 1578 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_DATA_IO_CONFIGr, instance, data) 1579 #define WRITE_DDRC28_DQ_BYTE2_DATA_IO_CONFIGr(unit, instance, data) \ 1580 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_DATA_IO_CONFIGr, instance, data) 1581 1582 #define READ_DDRC28_DQ_BYTE2_DQS_IO_CONFIGr(unit, instance, data) \ 1583 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_DQS_IO_CONFIGr, instance, data) 1584 #define WRITE_DDRC28_DQ_BYTE2_DQS_IO_CONFIGr(unit, instance, data) \ 1585 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_DQS_IO_CONFIGr, instance, data) 1586 1587 #define READ_DDRC28_DQ_BYTE2_EDCEN_FIFO_CONFIGr(unit, instance, data) \ 1588 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_EDCEN_FIFO_CONFIGr, instance, data) 1589 #define WRITE_DDRC28_DQ_BYTE2_EDCEN_FIFO_CONFIGr(unit, instance, data) \ 1590 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_EDCEN_FIFO_CONFIGr, instance, data) 1591 1592 #define READ_DDRC28_DQ_BYTE2_LDO_R_CONFIGr(unit, instance, data) \ 1593 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_LDO_R_CONFIGr, instance, data) 1594 #define WRITE_DDRC28_DQ_BYTE2_LDO_R_CONFIGr(unit, instance, data) \ 1595 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_LDO_R_CONFIGr, instance, data) 1596 1597 #define READ_DDRC28_DQ_BYTE2_LDO_W_CONFIGr(unit, instance, data) \ 1598 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_LDO_W_CONFIGr, instance, data) 1599 #define WRITE_DDRC28_DQ_BYTE2_LDO_W_CONFIGr(unit, instance, data) \ 1600 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_LDO_W_CONFIGr, instance, data) 1601 1602 #define READ_DDRC28_DQ_BYTE2_MACRO_RESERVED_REGr(unit, instance, data) \ 1603 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_MACRO_RESERVED_REGr, instance, data) 1604 #define WRITE_DDRC28_DQ_BYTE2_MACRO_RESERVED_REGr(unit, instance, data) \ 1605 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_MACRO_RESERVED_REGr, instance, data) 1606 1607 #define READ_DDRC28_DQ_BYTE2_READ_MAX_VDL_DQSNr(unit, instance, data) \ 1608 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSNr, instance, data) 1609 #define WRITE_DDRC28_DQ_BYTE2_READ_MAX_VDL_DQSNr(unit, instance, data) \ 1610 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSNr, instance, data) 1611 1612 #define READ_DDRC28_DQ_BYTE2_READ_MAX_VDL_DQSPr(unit, instance, data) \ 1613 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSPr, instance, data) 1614 #define WRITE_DDRC28_DQ_BYTE2_READ_MAX_VDL_DQSPr(unit, instance, data) \ 1615 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_DQSPr, instance, data) 1616 1617 #define READ_DDRC28_DQ_BYTE2_READ_MAX_VDL_FSMr(unit, instance, data) \ 1618 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_FSMr, instance, data) 1619 #define WRITE_DDRC28_DQ_BYTE2_READ_MAX_VDL_FSMr(unit, instance, data) \ 1620 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MAX_VDL_FSMr, instance, data) 1621 1622 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT0r(unit, instance, data) \ 1623 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT0r, instance, data) 1624 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT0r(unit, instance, data) \ 1625 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT0r, instance, data) 1626 1627 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT1r(unit, instance, data) \ 1628 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT1r, instance, data) 1629 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT1r(unit, instance, data) \ 1630 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT1r, instance, data) 1631 1632 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT2r(unit, instance, data) \ 1633 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT2r, instance, data) 1634 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT2r(unit, instance, data) \ 1635 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT2r, instance, data) 1636 1637 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT3r(unit, instance, data) \ 1638 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT3r, instance, data) 1639 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT3r(unit, instance, data) \ 1640 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT3r, instance, data) 1641 1642 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT4r(unit, instance, data) \ 1643 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT4r, instance, data) 1644 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT4r(unit, instance, data) \ 1645 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT4r, instance, data) 1646 1647 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT5r(unit, instance, data) \ 1648 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT5r, instance, data) 1649 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT5r(unit, instance, data) \ 1650 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT5r, instance, data) 1651 1652 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT6r(unit, instance, data) \ 1653 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT6r, instance, data) 1654 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT6r(unit, instance, data) \ 1655 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT6r, instance, data) 1656 1657 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT7r(unit, instance, data) \ 1658 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT7r, instance, data) 1659 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_BIT7r(unit, instance, data) \ 1660 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_BIT7r, instance, data) 1661 1662 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_DBIr(unit, instance, data) \ 1663 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_DBIr, instance, data) 1664 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_DBIr(unit, instance, data) \ 1665 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_DBIr, instance, data) 1666 1667 #define READ_DDRC28_DQ_BYTE2_READ_MIN_VDL_EDCr(unit, instance, data) \ 1668 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_EDCr, instance, data) 1669 #define WRITE_DDRC28_DQ_BYTE2_READ_MIN_VDL_EDCr(unit, instance, data) \ 1670 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_READ_MIN_VDL_EDCr, instance, data) 1671 1672 #define READ_DDRC28_DQ_BYTE2_REN_FIFO_CONFIGr(unit, instance, data) \ 1673 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_REN_FIFO_CONFIGr, instance, data) 1674 #define WRITE_DDRC28_DQ_BYTE2_REN_FIFO_CONFIGr(unit, instance, data) \ 1675 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_REN_FIFO_CONFIGr, instance, data) 1676 1677 #define READ_DDRC28_DQ_BYTE2_REN_GEN_ERR_CTRLr(unit, instance, data) \ 1678 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_REN_GEN_ERR_CTRLr, instance, data) 1679 #define WRITE_DDRC28_DQ_BYTE2_REN_GEN_ERR_CTRLr(unit, instance, data) \ 1680 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_REN_GEN_ERR_CTRLr, instance, data) 1681 1682 #define READ_DDRC28_DQ_BYTE2_REN_STRETCH_CONFIGr(unit, instance, data) \ 1683 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_REN_STRETCH_CONFIGr, instance, data) 1684 #define WRITE_DDRC28_DQ_BYTE2_REN_STRETCH_CONFIGr(unit, instance, data) \ 1685 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_REN_STRETCH_CONFIGr, instance, data) 1686 1687 #define READ_DDRC28_DQ_BYTE2_STATUS_CDR_IQ_VDLr(unit, instance, data) \ 1688 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_IQ_VDLr, instance, data) 1689 #define WRITE_DDRC28_DQ_BYTE2_STATUS_CDR_IQ_VDLr(unit, instance, data) \ 1690 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_IQ_VDLr, instance, data) 1691 1692 #define READ_DDRC28_DQ_BYTE2_STATUS_CDR_OPERATIONr(unit, instance, data) \ 1693 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_OPERATIONr, instance, data) 1694 #define WRITE_DDRC28_DQ_BYTE2_STATUS_CDR_OPERATIONr(unit, instance, data) \ 1695 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_OPERATIONr, instance, data) 1696 1697 #define READ_DDRC28_DQ_BYTE2_STATUS_CDR_PN_VDLr(unit, instance, data) \ 1698 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_PN_VDLr, instance, data) 1699 #define WRITE_DDRC28_DQ_BYTE2_STATUS_CDR_PN_VDLr(unit, instance, data) \ 1700 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_CDR_PN_VDLr, instance, data) 1701 1702 #define READ_DDRC28_DQ_BYTE2_STATUS_EDCEN_FIFOr(unit, instance, data) \ 1703 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_EDCEN_FIFOr, instance, data) 1704 #define WRITE_DDRC28_DQ_BYTE2_STATUS_EDCEN_FIFOr(unit, instance, data) \ 1705 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_EDCEN_FIFOr, instance, data) 1706 1707 #define READ_DDRC28_DQ_BYTE2_STATUS_EDCRDATA_FIFOr(unit, instance, data) \ 1708 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_EDCRDATA_FIFOr, instance, data) 1709 #define WRITE_DDRC28_DQ_BYTE2_STATUS_EDCRDATA_FIFOr(unit, instance, data) \ 1710 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_EDCRDATA_FIFOr, instance, data) 1711 1712 #define READ_DDRC28_DQ_BYTE2_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 1713 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_MACRO_RESERVEDr, instance, data) 1714 #define WRITE_DDRC28_DQ_BYTE2_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 1715 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_MACRO_RESERVEDr, instance, data) 1716 1717 #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \ 1718 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr, instance, data) 1719 #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \ 1720 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_CTRr, instance, data) 1721 1722 #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \ 1723 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr, instance, data) 1724 #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \ 1725 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_FIFO_PTRr, instance, data) 1726 1727 #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACHr(unit, instance, data) \ 1728 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACHr, instance, data) 1729 #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACHr(unit, instance, data) \ 1730 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACHr, instance, data) 1731 1732 #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \ 1733 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r, instance, data) 1734 #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \ 1735 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR1r, instance, data) 1736 1737 #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \ 1738 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r, instance, data) 1739 #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \ 1740 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR2r, instance, data) 1741 1742 #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \ 1743 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r, instance, data) 1744 #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \ 1745 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_ERR3r, instance, data) 1746 1747 #define READ_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \ 1748 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr, instance, data) 1749 #define WRITE_DDRC28_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \ 1750 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RCMD_MACH_RCMD_IDr, instance, data) 1751 1752 #define READ_DDRC28_DQ_BYTE2_STATUS_RDATA_FIFOr(unit, instance, data) \ 1753 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RDATA_FIFOr, instance, data) 1754 #define WRITE_DDRC28_DQ_BYTE2_STATUS_RDATA_FIFOr(unit, instance, data) \ 1755 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_RDATA_FIFOr, instance, data) 1756 1757 #define READ_DDRC28_DQ_BYTE2_STATUS_REN_FIFOr(unit, instance, data) \ 1758 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_FIFOr, instance, data) 1759 #define WRITE_DDRC28_DQ_BYTE2_STATUS_REN_FIFOr(unit, instance, data) \ 1760 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_FIFOr, instance, data) 1761 1762 #define READ_DDRC28_DQ_BYTE2_STATUS_REN_GEN_ERR1r(unit, instance, data) \ 1763 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR1r, instance, data) 1764 #define WRITE_DDRC28_DQ_BYTE2_STATUS_REN_GEN_ERR1r(unit, instance, data) \ 1765 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR1r, instance, data) 1766 1767 #define READ_DDRC28_DQ_BYTE2_STATUS_REN_GEN_ERR2r(unit, instance, data) \ 1768 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR2r, instance, data) 1769 #define WRITE_DDRC28_DQ_BYTE2_STATUS_REN_GEN_ERR2r(unit, instance, data) \ 1770 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_ERR2r, instance, data) 1771 1772 #define READ_DDRC28_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \ 1773 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr, instance, data) 1774 #define WRITE_DDRC28_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \ 1775 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_REN_GEN_RCMD_IDr, instance, data) 1776 1777 #define READ_DDRC28_DQ_BYTE2_STATUS_WRITE_LEVELINGr(unit, instance, data) \ 1778 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_WRITE_LEVELINGr, instance, data) 1779 #define WRITE_DDRC28_DQ_BYTE2_STATUS_WRITE_LEVELINGr(unit, instance, data) \ 1780 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_STATUS_WRITE_LEVELINGr, instance, data) 1781 1782 #define READ_DDRC28_DQ_BYTE2_VREF_DAC_CONFIGr(unit, instance, data) \ 1783 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_VREF_DAC_CONFIGr, instance, data) 1784 #define WRITE_DDRC28_DQ_BYTE2_VREF_DAC_CONFIGr(unit, instance, data) \ 1785 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_VREF_DAC_CONFIGr, instance, data) 1786 1787 #define READ_DDRC28_DQ_BYTE2_WRITE_LEVELING_CONFIGr(unit, instance, data) \ 1788 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_LEVELING_CONFIGr, instance, data) 1789 #define WRITE_DDRC28_DQ_BYTE2_WRITE_LEVELING_CONFIGr(unit, instance, data) \ 1790 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_LEVELING_CONFIGr, instance, data) 1791 1792 #define READ_DDRC28_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, instance, data) \ 1793 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DATAr, instance, data) 1794 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MAX_VDL_DATAr(unit, instance, data) \ 1795 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DATAr, instance, data) 1796 1797 #define READ_DDRC28_DQ_BYTE2_WRITE_MAX_VDL_DQSr(unit, instance, data) \ 1798 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DQSr, instance, data) 1799 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MAX_VDL_DQSr(unit, instance, data) \ 1800 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MAX_VDL_DQSr, instance, data) 1801 1802 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT0r(unit, instance, data) \ 1803 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT0r, instance, data) 1804 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT0r(unit, instance, data) \ 1805 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT0r, instance, data) 1806 1807 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT1r(unit, instance, data) \ 1808 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT1r, instance, data) 1809 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT1r(unit, instance, data) \ 1810 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT1r, instance, data) 1811 1812 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT2r(unit, instance, data) \ 1813 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT2r, instance, data) 1814 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT2r(unit, instance, data) \ 1815 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT2r, instance, data) 1816 1817 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT3r(unit, instance, data) \ 1818 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT3r, instance, data) 1819 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT3r(unit, instance, data) \ 1820 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT3r, instance, data) 1821 1822 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT4r(unit, instance, data) \ 1823 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT4r, instance, data) 1824 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT4r(unit, instance, data) \ 1825 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT4r, instance, data) 1826 1827 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT5r(unit, instance, data) \ 1828 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT5r, instance, data) 1829 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT5r(unit, instance, data) \ 1830 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT5r, instance, data) 1831 1832 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT6r(unit, instance, data) \ 1833 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT6r, instance, data) 1834 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT6r(unit, instance, data) \ 1835 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT6r, instance, data) 1836 1837 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT7r(unit, instance, data) \ 1838 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT7r, instance, data) 1839 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_BIT7r(unit, instance, data) \ 1840 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_BIT7r, instance, data) 1841 1842 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_DBIr(unit, instance, data) \ 1843 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_DBIr, instance, data) 1844 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_DBIr(unit, instance, data) \ 1845 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_DBIr, instance, data) 1846 1847 #define READ_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_EDCr(unit, instance, data) \ 1848 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_EDCr, instance, data) 1849 #define WRITE_DDRC28_DQ_BYTE2_WRITE_MIN_VDL_EDCr(unit, instance, data) \ 1850 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE2_WRITE_MIN_VDL_EDCr, instance, data) 1851 1852 #define READ_DDRC28_DQ_BYTE3_CDR_IQ_VDL_CONFIGr(unit, instance, data) \ 1853 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_CDR_IQ_VDL_CONFIGr, instance, data) 1854 #define WRITE_DDRC28_DQ_BYTE3_CDR_IQ_VDL_CONFIGr(unit, instance, data) \ 1855 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_CDR_IQ_VDL_CONFIGr, instance, data) 1856 1857 #define READ_DDRC28_DQ_BYTE3_CDR_OPERATION_CONFIGr(unit, instance, data) \ 1858 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_CDR_OPERATION_CONFIGr, instance, data) 1859 #define WRITE_DDRC28_DQ_BYTE3_CDR_OPERATION_CONFIGr(unit, instance, data) \ 1860 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_CDR_OPERATION_CONFIGr, instance, data) 1861 1862 #define READ_DDRC28_DQ_BYTE3_CDR_PN_VDL_CONFIGr(unit, instance, data) \ 1863 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_CDR_PN_VDL_CONFIGr, instance, data) 1864 #define WRITE_DDRC28_DQ_BYTE3_CDR_PN_VDL_CONFIGr(unit, instance, data) \ 1865 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_CDR_PN_VDL_CONFIGr, instance, data) 1866 1867 #define READ_DDRC28_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \ 1868 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr, instance, data) 1869 #define WRITE_DDRC28_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr(unit, instance, data) \ 1870 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_CDR_VDL_COMMON_CONFIGr, instance, data) 1871 1872 #define READ_DDRC28_DQ_BYTE3_DATA_IO_CONFIGr(unit, instance, data) \ 1873 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_DATA_IO_CONFIGr, instance, data) 1874 #define WRITE_DDRC28_DQ_BYTE3_DATA_IO_CONFIGr(unit, instance, data) \ 1875 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_DATA_IO_CONFIGr, instance, data) 1876 1877 #define READ_DDRC28_DQ_BYTE3_DQS_IO_CONFIGr(unit, instance, data) \ 1878 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_DQS_IO_CONFIGr, instance, data) 1879 #define WRITE_DDRC28_DQ_BYTE3_DQS_IO_CONFIGr(unit, instance, data) \ 1880 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_DQS_IO_CONFIGr, instance, data) 1881 1882 #define READ_DDRC28_DQ_BYTE3_EDCEN_FIFO_CONFIGr(unit, instance, data) \ 1883 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_EDCEN_FIFO_CONFIGr, instance, data) 1884 #define WRITE_DDRC28_DQ_BYTE3_EDCEN_FIFO_CONFIGr(unit, instance, data) \ 1885 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_EDCEN_FIFO_CONFIGr, instance, data) 1886 1887 #define READ_DDRC28_DQ_BYTE3_LDO_R_CONFIGr(unit, instance, data) \ 1888 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_LDO_R_CONFIGr, instance, data) 1889 #define WRITE_DDRC28_DQ_BYTE3_LDO_R_CONFIGr(unit, instance, data) \ 1890 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_LDO_R_CONFIGr, instance, data) 1891 1892 #define READ_DDRC28_DQ_BYTE3_LDO_W_CONFIGr(unit, instance, data) \ 1893 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_LDO_W_CONFIGr, instance, data) 1894 #define WRITE_DDRC28_DQ_BYTE3_LDO_W_CONFIGr(unit, instance, data) \ 1895 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_LDO_W_CONFIGr, instance, data) 1896 1897 #define READ_DDRC28_DQ_BYTE3_MACRO_RESERVED_REGr(unit, instance, data) \ 1898 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_MACRO_RESERVED_REGr, instance, data) 1899 #define WRITE_DDRC28_DQ_BYTE3_MACRO_RESERVED_REGr(unit, instance, data) \ 1900 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_MACRO_RESERVED_REGr, instance, data) 1901 1902 #define READ_DDRC28_DQ_BYTE3_READ_MAX_VDL_DQSNr(unit, instance, data) \ 1903 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSNr, instance, data) 1904 #define WRITE_DDRC28_DQ_BYTE3_READ_MAX_VDL_DQSNr(unit, instance, data) \ 1905 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSNr, instance, data) 1906 1907 #define READ_DDRC28_DQ_BYTE3_READ_MAX_VDL_DQSPr(unit, instance, data) \ 1908 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSPr, instance, data) 1909 #define WRITE_DDRC28_DQ_BYTE3_READ_MAX_VDL_DQSPr(unit, instance, data) \ 1910 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_DQSPr, instance, data) 1911 1912 #define READ_DDRC28_DQ_BYTE3_READ_MAX_VDL_FSMr(unit, instance, data) \ 1913 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_FSMr, instance, data) 1914 #define WRITE_DDRC28_DQ_BYTE3_READ_MAX_VDL_FSMr(unit, instance, data) \ 1915 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MAX_VDL_FSMr, instance, data) 1916 1917 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT0r(unit, instance, data) \ 1918 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT0r, instance, data) 1919 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT0r(unit, instance, data) \ 1920 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT0r, instance, data) 1921 1922 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT1r(unit, instance, data) \ 1923 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT1r, instance, data) 1924 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT1r(unit, instance, data) \ 1925 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT1r, instance, data) 1926 1927 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT2r(unit, instance, data) \ 1928 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT2r, instance, data) 1929 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT2r(unit, instance, data) \ 1930 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT2r, instance, data) 1931 1932 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT3r(unit, instance, data) \ 1933 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT3r, instance, data) 1934 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT3r(unit, instance, data) \ 1935 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT3r, instance, data) 1936 1937 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT4r(unit, instance, data) \ 1938 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT4r, instance, data) 1939 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT4r(unit, instance, data) \ 1940 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT4r, instance, data) 1941 1942 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT5r(unit, instance, data) \ 1943 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT5r, instance, data) 1944 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT5r(unit, instance, data) \ 1945 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT5r, instance, data) 1946 1947 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT6r(unit, instance, data) \ 1948 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT6r, instance, data) 1949 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT6r(unit, instance, data) \ 1950 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT6r, instance, data) 1951 1952 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT7r(unit, instance, data) \ 1953 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT7r, instance, data) 1954 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_BIT7r(unit, instance, data) \ 1955 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_BIT7r, instance, data) 1956 1957 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_DBIr(unit, instance, data) \ 1958 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_DBIr, instance, data) 1959 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_DBIr(unit, instance, data) \ 1960 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_DBIr, instance, data) 1961 1962 #define READ_DDRC28_DQ_BYTE3_READ_MIN_VDL_EDCr(unit, instance, data) \ 1963 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_EDCr, instance, data) 1964 #define WRITE_DDRC28_DQ_BYTE3_READ_MIN_VDL_EDCr(unit, instance, data) \ 1965 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_READ_MIN_VDL_EDCr, instance, data) 1966 1967 #define READ_DDRC28_DQ_BYTE3_REN_FIFO_CONFIGr(unit, instance, data) \ 1968 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_REN_FIFO_CONFIGr, instance, data) 1969 #define WRITE_DDRC28_DQ_BYTE3_REN_FIFO_CONFIGr(unit, instance, data) \ 1970 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_REN_FIFO_CONFIGr, instance, data) 1971 1972 #define READ_DDRC28_DQ_BYTE3_REN_GEN_ERR_CTRLr(unit, instance, data) \ 1973 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_REN_GEN_ERR_CTRLr, instance, data) 1974 #define WRITE_DDRC28_DQ_BYTE3_REN_GEN_ERR_CTRLr(unit, instance, data) \ 1975 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_REN_GEN_ERR_CTRLr, instance, data) 1976 1977 #define READ_DDRC28_DQ_BYTE3_REN_STRETCH_CONFIGr(unit, instance, data) \ 1978 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_REN_STRETCH_CONFIGr, instance, data) 1979 #define WRITE_DDRC28_DQ_BYTE3_REN_STRETCH_CONFIGr(unit, instance, data) \ 1980 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_REN_STRETCH_CONFIGr, instance, data) 1981 1982 #define READ_DDRC28_DQ_BYTE3_STATUS_CDR_IQ_VDLr(unit, instance, data) \ 1983 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_IQ_VDLr, instance, data) 1984 #define WRITE_DDRC28_DQ_BYTE3_STATUS_CDR_IQ_VDLr(unit, instance, data) \ 1985 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_IQ_VDLr, instance, data) 1986 1987 #define READ_DDRC28_DQ_BYTE3_STATUS_CDR_OPERATIONr(unit, instance, data) \ 1988 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_OPERATIONr, instance, data) 1989 #define WRITE_DDRC28_DQ_BYTE3_STATUS_CDR_OPERATIONr(unit, instance, data) \ 1990 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_OPERATIONr, instance, data) 1991 1992 #define READ_DDRC28_DQ_BYTE3_STATUS_CDR_PN_VDLr(unit, instance, data) \ 1993 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_PN_VDLr, instance, data) 1994 #define WRITE_DDRC28_DQ_BYTE3_STATUS_CDR_PN_VDLr(unit, instance, data) \ 1995 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_CDR_PN_VDLr, instance, data) 1996 1997 #define READ_DDRC28_DQ_BYTE3_STATUS_EDCEN_FIFOr(unit, instance, data) \ 1998 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_EDCEN_FIFOr, instance, data) 1999 #define WRITE_DDRC28_DQ_BYTE3_STATUS_EDCEN_FIFOr(unit, instance, data) \ 2000 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_EDCEN_FIFOr, instance, data) 2001 2002 #define READ_DDRC28_DQ_BYTE3_STATUS_EDCRDATA_FIFOr(unit, instance, data) \ 2003 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_EDCRDATA_FIFOr, instance, data) 2004 #define WRITE_DDRC28_DQ_BYTE3_STATUS_EDCRDATA_FIFOr(unit, instance, data) \ 2005 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_EDCRDATA_FIFOr, instance, data) 2006 2007 #define READ_DDRC28_DQ_BYTE3_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 2008 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_MACRO_RESERVEDr, instance, data) 2009 #define WRITE_DDRC28_DQ_BYTE3_STATUS_MACRO_RESERVEDr(unit, instance, data) \ 2010 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_MACRO_RESERVEDr, instance, data) 2011 2012 #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \ 2013 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr, instance, data) 2014 #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr(unit, instance, data) \ 2015 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_CTRr, instance, data) 2016 2017 #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \ 2018 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr, instance, data) 2019 #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr(unit, instance, data) \ 2020 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_FIFO_PTRr, instance, data) 2021 2022 #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACHr(unit, instance, data) \ 2023 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACHr, instance, data) 2024 #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACHr(unit, instance, data) \ 2025 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACHr, instance, data) 2026 2027 #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \ 2028 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r, instance, data) 2029 #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r(unit, instance, data) \ 2030 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR1r, instance, data) 2031 2032 #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \ 2033 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r, instance, data) 2034 #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r(unit, instance, data) \ 2035 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR2r, instance, data) 2036 2037 #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \ 2038 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r, instance, data) 2039 #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r(unit, instance, data) \ 2040 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_ERR3r, instance, data) 2041 2042 #define READ_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \ 2043 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr, instance, data) 2044 #define WRITE_DDRC28_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr(unit, instance, data) \ 2045 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RCMD_MACH_RCMD_IDr, instance, data) 2046 2047 #define READ_DDRC28_DQ_BYTE3_STATUS_RDATA_FIFOr(unit, instance, data) \ 2048 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RDATA_FIFOr, instance, data) 2049 #define WRITE_DDRC28_DQ_BYTE3_STATUS_RDATA_FIFOr(unit, instance, data) \ 2050 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_RDATA_FIFOr, instance, data) 2051 2052 #define READ_DDRC28_DQ_BYTE3_STATUS_REN_FIFOr(unit, instance, data) \ 2053 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_FIFOr, instance, data) 2054 #define WRITE_DDRC28_DQ_BYTE3_STATUS_REN_FIFOr(unit, instance, data) \ 2055 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_FIFOr, instance, data) 2056 2057 #define READ_DDRC28_DQ_BYTE3_STATUS_REN_GEN_ERR1r(unit, instance, data) \ 2058 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR1r, instance, data) 2059 #define WRITE_DDRC28_DQ_BYTE3_STATUS_REN_GEN_ERR1r(unit, instance, data) \ 2060 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR1r, instance, data) 2061 2062 #define READ_DDRC28_DQ_BYTE3_STATUS_REN_GEN_ERR2r(unit, instance, data) \ 2063 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR2r, instance, data) 2064 #define WRITE_DDRC28_DQ_BYTE3_STATUS_REN_GEN_ERR2r(unit, instance, data) \ 2065 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_ERR2r, instance, data) 2066 2067 #define READ_DDRC28_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \ 2068 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr, instance, data) 2069 #define WRITE_DDRC28_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr(unit, instance, data) \ 2070 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_REN_GEN_RCMD_IDr, instance, data) 2071 2072 #define READ_DDRC28_DQ_BYTE3_STATUS_WRITE_LEVELINGr(unit, instance, data) \ 2073 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_WRITE_LEVELINGr, instance, data) 2074 #define WRITE_DDRC28_DQ_BYTE3_STATUS_WRITE_LEVELINGr(unit, instance, data) \ 2075 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_STATUS_WRITE_LEVELINGr, instance, data) 2076 2077 #define READ_DDRC28_DQ_BYTE3_VREF_DAC_CONFIGr(unit, instance, data) \ 2078 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_VREF_DAC_CONFIGr, instance, data) 2079 #define WRITE_DDRC28_DQ_BYTE3_VREF_DAC_CONFIGr(unit, instance, data) \ 2080 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_VREF_DAC_CONFIGr, instance, data) 2081 2082 #define READ_DDRC28_DQ_BYTE3_WRITE_LEVELING_CONFIGr(unit, instance, data) \ 2083 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_LEVELING_CONFIGr, instance, data) 2084 #define WRITE_DDRC28_DQ_BYTE3_WRITE_LEVELING_CONFIGr(unit, instance, data) \ 2085 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_LEVELING_CONFIGr, instance, data) 2086 2087 #define READ_DDRC28_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, instance, data) \ 2088 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DATAr, instance, data) 2089 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MAX_VDL_DATAr(unit, instance, data) \ 2090 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DATAr, instance, data) 2091 2092 #define READ_DDRC28_DQ_BYTE3_WRITE_MAX_VDL_DQSr(unit, instance, data) \ 2093 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DQSr, instance, data) 2094 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MAX_VDL_DQSr(unit, instance, data) \ 2095 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MAX_VDL_DQSr, instance, data) 2096 2097 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT0r(unit, instance, data) \ 2098 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT0r, instance, data) 2099 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT0r(unit, instance, data) \ 2100 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT0r, instance, data) 2101 2102 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT1r(unit, instance, data) \ 2103 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT1r, instance, data) 2104 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT1r(unit, instance, data) \ 2105 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT1r, instance, data) 2106 2107 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT2r(unit, instance, data) \ 2108 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT2r, instance, data) 2109 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT2r(unit, instance, data) \ 2110 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT2r, instance, data) 2111 2112 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT3r(unit, instance, data) \ 2113 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT3r, instance, data) 2114 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT3r(unit, instance, data) \ 2115 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT3r, instance, data) 2116 2117 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT4r(unit, instance, data) \ 2118 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT4r, instance, data) 2119 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT4r(unit, instance, data) \ 2120 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT4r, instance, data) 2121 2122 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT5r(unit, instance, data) \ 2123 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT5r, instance, data) 2124 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT5r(unit, instance, data) \ 2125 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT5r, instance, data) 2126 2127 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT6r(unit, instance, data) \ 2128 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT6r, instance, data) 2129 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT6r(unit, instance, data) \ 2130 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT6r, instance, data) 2131 2132 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT7r(unit, instance, data) \ 2133 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT7r, instance, data) 2134 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_BIT7r(unit, instance, data) \ 2135 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_BIT7r, instance, data) 2136 2137 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_DBIr(unit, instance, data) \ 2138 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_DBIr, instance, data) 2139 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_DBIr(unit, instance, data) \ 2140 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_DBIr, instance, data) 2141 2142 #define READ_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_EDCr(unit, instance, data) \ 2143 soc_phy_ddrc28_reg32_read(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_EDCr, instance, data) 2144 #define WRITE_DDRC28_DQ_BYTE3_WRITE_MIN_VDL_EDCr(unit, instance, data) \ 2145 soc_phy_ddrc28_reg32_write(unit, SOC_PHY_REG_DQ_BYTE3_WRITE_MIN_VDL_EDCr, instance, data) 2146 2147 2148 #endif /* _SOC_PHY_DDRC28_H */