dcbformats.h (144593B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: soc/dcbformats.h 8 * Purpose: Define dma control block (DCB) formats for various chips. 9 * This information is only needed in soc/dcb.c, which 10 * provides a uniform interface to the reset of software 11 * for controlling DCBs. 12 * 13 * There are currently 32 DMA Control block formats 14 * (also known as DMA descriptors): 15 * 16 * Type 2 5670/75 (TX) 17 * Type 3 5690 aka DRACO1 18 * Type 4 5670/75 (RX) aka HERCULES 19 * Type 5 5673 aka LYNX 20 * Type 6 5665 aka TUCANA 21 * Type 7 5695 aka DRACO15 22 * Type 9 56504 aka XGS3 (Firebolt) 23 * Type 10 56601 aka XGS3 (Easyrider) 24 * Type 11 56800 aka XGS3 (HUMV) 25 * Type 12 56218 aka XGS3 (Raptor) (Derived from DCB 9) 26 * Type 13 56514 aka XGS3 (Firebolt2) (Derived from DCB 9) 27 * Type 14 56624 & 56680 aka XGS3 (Triumph & Valkyrie) 28 * Type 15 56224 aka XGS3 (Raven A0) (Derived from DCB 12) 29 * Type 16 56820 aka XGS3 (Scorpion) 30 * Type 17 53314 aka XGS3 (Hawkeye) (Derived from DCB 15) 31 * Type 18 56224 aka XGS3 (Raven B0) (Derived from DCB 15) 32 * Type 19 56634/56524/56685 aka XGS3 (Triumph2/Apollo/Valkyrie2) 33 * Type 20 56334 aka XGS3 (Enduro) (Derived from DCB 19) 34 * Type 21 56840 aka XGS3 (Trident) 35 * Type 22 88732 (SHADOW) 36 * Type 23 56640 aka XGS3 (Triumph3) 37 * Type 24 56440 aka XGS3 (Katana) 38 * Type 25 Obsolete: 88030 aka Caladan3 39 * Type 26 56850 aka XGS3 (Trident2) (Derived from DCB 23) 40 * Type 27 Obsolete: 88230 aka Sirius 41 * Type 29 56450 aka XGX3 (Katana2) 42 * Type 31 53400 aka XGX3 (Greyhound) 43 * Type 32 56960 aka XGX3 (Tomahawk) (Derived from DCB 26) 44 * Type 33 56860 aka XGS3 (Trident2+) (Derived from DCB 26) 45 * Type 34 56160 aka XGX3 (Hurricane3) 46 * Type 35 56560 APACHE 47 * Type 36 56870 (Trident 3)88690 (Jericho 2) 48 * Type 37 53570 aka XGX3 (Greyhound2) 49 * Type 38 56980 (Tomahawk 3) 50 * 51 * The 5670/75 uses two different formats depending on whether the DCB is 52 * for transmit or receive. 53 * 54 * The 5695 can be configured to use type 3 or type 7 depending on whether 55 * CMIC_CONFIG.EXTENDED_DCB_ENABLE is set or not. 56 */ 57 58 #ifndef _SOC_DCBFORMATS_H 59 #define _SOC_DCBFORMATS_H 60 61 #include <soc/types.h> 62 #include <soc/defs.h> 63 64 #define DCB_STRATA_OPTIM_PURGE 3 65 #define DCB_STRATA_CRC_LEAVE 0 66 #define DCB_STRATA_CRC_REGEN 2 67 #define DCB_XGS_CRC_LEAVE 0 68 #define DCB_XGS_CRC_REGEN 1 69 70 #define DCB_MAX_REQCOUNT 0x7fff /* 32KB */ 71 #define DCB_MAX_SIZE (16*4) /* type 14 */ 72 73 #if defined(BCM_HERCULES_SUPPORT) 74 /* 75 * DMA Control Block - Type 2 76 * Used on STRATA2 devices and on 5670/75 for transmission 77 * 8 words 78 */ 79 typedef struct { 80 uint32 addr; /* T2.0: physical address */ 81 /* T2.1: Control 0 (same as T1) */ 82 #ifdef LE_HOST 83 uint32 c_count:16, /* Requested byte count */ 84 :1, 85 c_reload:1, /* Reload */ 86 c_sg:1, /* Scatter Gather */ 87 :2, 88 :1, /* Unused (L3/IPX data) */ 89 c_ip:1, /* L3/IP switched packet */ 90 c_optim:2, /* DMAR: optimization bits (below) */ 91 c_crc:2, /* DMAW: send pkt asis or regen crc */ 92 c_jumbo:1, /* DMAR: jumbo packet */ 93 c_cos:3, /* DMAR: Class of service */ 94 c_chain:1; /* Chaining */ 95 #else 96 uint32 c_chain:1, 97 c_cos:3, 98 c_jumbo:1, 99 c_crc:2, 100 c_optim:2, 101 c_ip:1, 102 :1, 103 :2, 104 c_sg:1, 105 c_reload:1, 106 :1, 107 c_count:16; 108 #endif /* LE_HOST */ 109 uint32 l2ports; /* T2.2: L2 transmit to ports */ 110 uint32 utports; /* T2.3: L2 untagged ports */ 111 uint32 l3ports; /* T2.4: L3 transmit to ports */ 112 /* T2.5: Status 0 (same as T1) */ 113 #ifdef LE_HOST 114 uint32 count:16, /* Transferred byte count */ 115 :4, 116 start:1, /* Start of packet transferred */ 117 optim:2, /* Optimization: 0:unused; 1:C bit set; 118 * 2:frame mismatch; 3:RSVP */ 119 crc:2, /* CRC_LEAVE: valid CRC */ 120 /* CRC_REGEN: invalid CRC */ 121 :1, 122 cos:3, /* COS value for packet */ 123 untagged:1, /* cmic/egr removed tag */ 124 end:1, /* Last packet or end of packet */ 125 s0valid:1; /* Status word valid */ 126 #else 127 uint32 s0valid:1, 128 end:1, 129 untagged:1, 130 cos:3, 131 :1, 132 crc:2, 133 optim:2, 134 start:1, 135 :4, 136 count:16; 137 #endif 138 /* T2.6: Status 1 (same as T1) */ 139 #ifdef LE_HOST 140 uint32 srcport:6, /* Source port for this packet */ 141 :2, 142 s1valid:1, /* status word valid */ 143 :5, 144 reason:18; /* CPU opcode */ 145 #else 146 uint32 reason:18, 147 :5, 148 s1valid:1, 149 :2, 150 srcport:6; 151 #endif 152 /* T2.7: Status 2 */ 153 #ifdef LE_HOST 154 uint32 remote_port:6, /* Remote port */ 155 match_rule:8, /* Match rule */ 156 :17, 157 s2valid:1; /* status word valid */ 158 #else 159 uint32 s2valid:1, 160 :17, 161 match_rule:8, 162 remote_port:6; 163 #endif 164 } dcb2_t; 165 #endif /* BCM_HERCULES_SUPPORT */ 166 167 #ifdef BCM_DRACO1_SUPPORT 168 /* 169 * DMA Control Block - Type 3 170 * Used on 5690 devices 171 * 8 words 172 */ 173 typedef struct { 174 uint32 addr; /* T3.0: physical address */ 175 /* T3.1: Control 0 */ 176 #ifdef LE_HOST 177 uint32 c_count:15, /* Requested byte count */ 178 c_crc:1, /* send pkt asis or regen crc */ 179 c_destport_hi:1, /* Destination port [4] */ 180 c_reload:1, /* Reload */ 181 c_sg:1, /* Scatter Gather */ 182 c_destport_lo:4, /* Destination port [3:0] */ 183 c_destmod:5, /* Destination module */ 184 c_cos:3, /* class of service */ 185 c_chain:1; /* Chaining */ 186 #else 187 uint32 c_chain:1, 188 c_cos:3, 189 c_destmod:5, 190 c_destport_lo:4, 191 c_sg:1, 192 c_reload:1, 193 c_destport_hi:1, 194 c_crc:1, 195 c_count:15; 196 #endif /* LE_HOST */ 197 /* T3.2: L2 transmit to ports */ 198 #ifdef LE_HOST 199 uint32 l2ports:31, 200 c_opcode0:1; /* hdr opcode [0] */ 201 #else 202 uint32 c_opcode0:1, 203 l2ports:31; 204 #endif 205 /* T3.3: L2 untagged ports */ 206 #ifdef LE_HOST 207 uint32 utports:31, 208 c_opcode1:1; /* hdr opcode [1] */ 209 #else 210 uint32 c_opcode1:1, 211 utports:31; 212 #endif 213 /* T3.4: L3 transmit to ports */ 214 #ifdef LE_HOST 215 uint32 l3ports:31, 216 c_opcode2:1; /* hdr opcode [2] */ 217 #else 218 uint32 c_opcode2:1, 219 l3ports:31; 220 #endif 221 /* T3.5: Status 0 */ 222 #ifdef LE_HOST 223 uint32 count:16, /* Transferred byte count */ 224 crc:1, /* Pkt had invalid CRC */ 225 tagged:1, /* Pkt was tagged */ 226 srcport_hi:1, /* Source port [4] */ 227 l3:1, /* Pkt was l3 switched */ 228 start:1, /* Start of pkt */ 229 cos:3, /* cpu class of service */ 230 srcport_lo:5, /* Source Port [3:0] */ 231 error:1, /* Error occurred */ 232 end:1, /* End of pkt */ 233 s0valid:1; /* Status word valid */ 234 #else 235 uint32 s0valid:1, 236 end:1, 237 error:1, 238 srcport_lo:5, 239 cos:3, 240 start:1, 241 l3:1, 242 srcport_hi:1, 243 tagged:1, 244 crc:1, 245 count:16; 246 #endif 247 /* T3.6: Status 1 */ 248 #ifdef LE_HOST 249 uint32 ingport:4, /* local source (ingress) port */ 250 opcode:3, /* hdr opcode */ 251 prio_lo:1, /* hdr priority [0] */ 252 s1valid:1, /* status word valid */ 253 prio_hi:2, /* hdr priority [2:1] */ 254 srcmod:5, /* source module */ 255 reason:16; /* cpu opcode */ 256 #else 257 uint32 reason:16, 258 srcmod:5, 259 prio_hi:2, 260 s1valid:1, 261 prio_lo:1, 262 opcode:3, 263 ingport:4; 264 #endif 265 /* T3.7: Status 2 */ 266 #ifdef LE_HOST 267 uint32 class_tag:16, /* classification tag */ 268 match_rule:7, /* match rule */ 269 destport:5, /* destination port */ 270 destmod_lo:3, /* destination module [2:0] */ 271 s2valid:1; /* status word valid */ 272 #else 273 uint32 s2valid:1, 274 destmod_lo:3, 275 destport:5, 276 match_rule:7, 277 class_tag:16; 278 #endif 279 } dcb3_t; 280 #endif /* BCM_DRACO1_SUPPORT */ 281 282 #ifdef BCM_HERCULES_SUPPORT 283 /* 284 * DMA Control Block - Type 4 285 * Used on 5670/75 devices for RX 286 * 8 words 287 */ 288 typedef struct { 289 uint32 addr; /* T4.0: physical address */ 290 /* T4.1: Control 0 (same as T1) */ 291 #ifdef LE_HOST 292 uint32 c_count:16, /* Requested byte count */ 293 :1, 294 c_reload:1, /* Reload */ 295 c_sg:1, /* Scatter Gather */ 296 :2, 297 :1, /* Unused (L3/IPX data) */ 298 c_ip:1, /* L3/IP switched packet */ 299 c_optim:2, /* DMAR: optimization bits (below) */ 300 c_crc:2, /* DMAW: send pkt asis or regen crc */ 301 c_jumbo:1, /* DMAR: jumbo packet */ 302 c_cos:3, /* DMAR: Class of service */ 303 c_chain:1; /* Chaining */ 304 #else 305 uint32 c_chain:1, 306 c_cos:3, 307 c_jumbo:1, 308 c_crc:2, 309 c_optim:2, 310 c_ip:1, 311 :1, 312 :2, 313 c_sg:1, 314 c_reload:1, 315 :1, 316 c_count:16; 317 #endif /* LE_HOST */ 318 uint32 l2ports; /* T4.2: L2 transmit to ports */ 319 uint32 utports; /* T4.3: L2 untagged ports */ 320 uint32 l3ports; /* T4.4: L3 transmit to ports */ 321 /* T4.5: Status 0 */ 322 #ifdef LE_HOST 323 uint32 count:16, /* Transferred byte count */ 324 ip:2, /* L3/IP switched packet (always 0) */ 325 utvalid:1, /* Untag bitmap received (always 0) */ 326 l3:1, /* Pkt was l3 switched (always 0) */ 327 start:1, /* Start of pkt */ 328 optim:2, /* Optimization bits (always 0) */ 329 crc:2, /* Pkt had invalid CRC (always 0) */ 330 jumbo:1, /* Jumbo packet (always 0) */ 331 cos:3, /* cpu class of service */ 332 error:1, /* Error occurred */ 333 end:1, /* End of pkt */ 334 s0valid:1; /* Status word valid */ 335 #else 336 uint32 s0valid:1, 337 end:1, 338 error:1, 339 cos:3, 340 jumbo:1, 341 crc:2, 342 optim:2, 343 start:1, 344 l3:1, 345 utvalid:1, 346 ip:2, 347 count:16; 348 #endif 349 /* T4.6: Status 1 (same as T3) */ 350 #ifdef LE_HOST 351 uint32 ingport:4, /* local source (ingress) port */ 352 opcode:3, /* hdr opcode */ 353 prio_lo:1, /* hdr priority [0] */ 354 s1valid:1, /* status word valid */ 355 prio_hi:2, /* hdr priority [2:1] */ 356 srcmod:5, /* source module */ 357 reason:16; /* cpu opcode */ 358 #else 359 uint32 reason:16, 360 srcmod:5, 361 prio_hi:2, 362 s1valid:1, 363 prio_lo:1, 364 opcode:3, 365 ingport:4; 366 #endif 367 /* T4.7: Status 2 (same as T3) */ 368 #ifdef LE_HOST 369 uint32 class_tag:16, /* classification tag */ 370 match_rule:7, /* match rule */ 371 destport:5, /* destination port */ 372 destmod_lo:3, /* destination module [2:0] */ 373 s2valid:1; /* status word valid */ 374 #else 375 uint32 s2valid:1, 376 destmod_lo:3, 377 destport:5, 378 match_rule:7, 379 class_tag:16; 380 #endif 381 } dcb4_t; 382 #endif /* BCM_HERCULES_SUPPORT */ 383 384 #ifdef BCM_LYNX_SUPPORT 385 /* 386 * DMA Control Block - Type 5 387 * Used on 5673 devices 388 * 9 words 389 */ 390 typedef struct { 391 uint32 addr; /* T5.0: physical address */ 392 /* T5.1: Control 0 (same as T3) */ 393 #ifdef LE_HOST 394 uint32 c_count:15, /* Requested byte count */ 395 c_crc:1, /* send pkt asis or regen crc */ 396 c_destport_hi:1, /* Destination port [4] */ 397 c_reload:1, /* Reload */ 398 c_sg:1, /* Scatter Gather */ 399 c_destport_lo:4, /* Destination port [3:0] */ 400 c_destmod:5, /* Destination module */ 401 c_cos:3, /* class of service */ 402 c_chain:1; /* Chaining */ 403 #else 404 uint32 c_chain:1, 405 c_cos:3, 406 c_destmod:5, 407 c_destport_lo:4, 408 c_sg:1, 409 c_reload:1, 410 c_destport_hi:1, 411 c_crc:1, 412 c_count:15; 413 #endif /* LE_HOST */ 414 /* T5.2: L2 transmit to ports */ 415 #ifdef LE_HOST 416 uint32 l2ports:31, 417 c_opcode0:1; /* hdr opcode [0] */ 418 #else 419 uint32 c_opcode0:1, 420 l2ports:31; 421 #endif 422 /* T5.3: L2 untagged ports */ 423 #ifdef LE_HOST 424 uint32 utports:31, 425 c_opcode1:1; /* hdr opcode [1] */ 426 #else 427 uint32 c_opcode1:1, 428 utports:31; 429 #endif 430 /* T5.4: L3 transmit to ports */ 431 #ifdef LE_HOST 432 uint32 l3ports:31, 433 c_opcode2:1; /* hdr opcode [2] */ 434 #else 435 uint32 c_opcode2:1, 436 l3ports:31; 437 #endif 438 /* T5.5: Status 0 (same as T3) */ 439 #ifdef LE_HOST 440 uint32 count:16, /* Transferred byte count */ 441 crc:1, /* Pkt had invalid CRC */ 442 tagged:1, /* Pkt was tagged */ 443 srcport_hi:1, /* Source port [4] */ 444 l3:1, /* Pkt was l3 switched */ 445 start:1, /* Start of pkt */ 446 cos:3, /* cpu class of service */ 447 srcport_lo:5, /* Source Port [3:0] */ 448 error:1, /* Error occurred */ 449 end:1, /* End of pkt */ 450 s0valid:1; /* Status word valid */ 451 #else 452 uint32 s0valid:1, 453 end:1, 454 error:1, 455 srcport_lo:5, 456 cos:3, 457 start:1, 458 l3:1, 459 srcport_hi:1, 460 tagged:1, 461 crc:1, 462 count:16; 463 #endif 464 /* T5.6: Status 1 (same as T3) */ 465 #ifdef LE_HOST 466 uint32 ingport:4, /* local source (ingress) port */ 467 opcode:3, /* hdr opcode */ 468 prio_lo:1, /* hdr priority [0] */ 469 s1valid:1, /* status word valid */ 470 prio_hi:2, /* hdr priority [2:1] */ 471 srcmod:5, /* source module */ 472 reason:16; /* cpu opcode */ 473 #else 474 uint32 reason:16, 475 srcmod:5, 476 prio_hi:2, 477 s1valid:1, 478 prio_lo:1, 479 opcode:3, 480 ingport:4; 481 #endif 482 /* T5.7: Status 2 (same as T3) */ 483 #ifdef LE_HOST 484 uint32 class_tag:16, /* classification tag */ 485 match_rule_lo:7, /* match rule (renamed from type 3) */ 486 destport:5, /* destination port */ 487 destmod_lo:3, /* destination module [2:0] */ 488 s2valid:1; /* status word valid */ 489 #else 490 uint32 s2valid:1, 491 destmod_lo:3, 492 destport:5, 493 match_rule_lo:7, 494 class_tag:16; 495 #endif 496 /* T5.8: Status 3 */ 497 #ifdef LE_HOST 498 uint32 match_rule:10, /* match rule */ 499 :21, 500 s3valid:1; /* status word valid */ 501 #else 502 uint32 s3valid:1, 503 :21, 504 match_rule:10; 505 #endif 506 } dcb5_t; 507 #endif /* BCM_LYNX_SUPPORT */ 508 509 #ifdef BCM_TUCANA_SUPPORT 510 /* 511 * DMA Control Block - Type 6 512 * Used on 5665 devices 513 * 15 words 514 */ 515 typedef struct { 516 uint32 addr; /* T6.0: physical address */ 517 /* T6.1: Control 0 (same as T3) */ 518 #ifdef LE_HOST 519 uint32 c_count:15, /* Requested byte count */ 520 c_crc:1, /* send pkt asis or regen crc */ 521 c_destport_hi:1, /* Destination port [4] */ 522 c_reload:1, /* Reload */ 523 c_sg:1, /* Scatter Gather */ 524 c_destport_lo:4, /* Destination port [3:0] */ 525 c_destmod:5, /* Destination module */ 526 c_cos:3, /* class of service */ 527 c_chain:1; /* Chaining */ 528 #else 529 uint32 c_chain:1, 530 c_cos:3, 531 c_destmod:5, 532 c_destport_lo:4, 533 c_sg:1, 534 c_reload:1, 535 c_destport_hi:1, 536 c_crc:1, 537 c_count:15; 538 #endif /* LE_HOST */ 539 uint32 l2ports_mod0; /* T6.2: L2 transmit to ports */ 540 uint32 l2ports_mod1; /* T6.3: L2 transmit to ports */ 541 uint32 utports_mod0; /* T6.4: L2 untagged ports */ 542 uint32 utports_mod1; /* T6.5: L2 untagged ports */ 543 uint32 l3ports_mod0; /* T6.6: L3 transmit to ports */ 544 uint32 l3ports_mod1; /* T6.7: L3 transmit to ports */ 545 /* T6.8: Control 1 */ 546 #ifdef LE_HOST 547 uint32 c_vclabel:20, /* HTLS VC Label / c_class_tag:16 */ 548 :12; 549 #else 550 uint32 :12, 551 c_vclabel:20; 552 #endif 553 /* T6.9: Control 2 */ 554 #ifdef LE_HOST 555 uint32 :6, 556 c_opcode:3, /* hdr opcode */ 557 c_dest_tgid:3, /* dest trunk bit (if no classtag) */ 558 c_dest_trunk:1, /* dest trunk (if no classtag) */ 559 c_mirror:1, /* packet is mirrored */ 560 c_mirror_done:1, /* mirroring done for packet */ 561 c_mirror_only:1, /* mirror only */ 562 :16; 563 #else 564 uint32 :16, 565 c_mirror_only:1, 566 c_mirror_done:1, 567 c_mirror:1, 568 c_dest_trunk:1, 569 c_dest_tgid:3, 570 c_opcode:3, 571 :6; 572 #endif 573 /* T6.10: Status 0 (same as T3) */ 574 #ifdef LE_HOST 575 uint32 count:16, /* Transferred byte count */ 576 crc:1, /* Pkt had invalid CRC */ 577 tagged:1, /* Pkt was tagged */ 578 srcport_hi:1, /* Source port [4] */ 579 l3:1, /* Pkt was l3 switched */ 580 start:1, /* Start of pkt */ 581 cos:3, /* cpu class of service */ 582 srcport_lo:5, /* Source Port [3:0] */ 583 error:1, /* Error occurred */ 584 end:1, /* End of pkt */ 585 s0valid:1; /* Status word valid */ 586 #else 587 uint32 s0valid:1, 588 end:1, 589 error:1, 590 srcport_lo:5, 591 cos:3, 592 start:1, 593 l3:1, 594 srcport_hi:1, 595 tagged:1, 596 crc:1, 597 count:16; 598 #endif 599 /* T6.11: Status 1 (same as T3) */ 600 #ifdef LE_HOST 601 uint32 ingport_lo:4, /* local source (ingress) port [3:0] */ 602 opcode:3, /* hdr opcode */ 603 prio_lo:1, /* hdr priority [0] */ 604 s1valid:1, /* status word valid */ 605 prio_hi:2, /* hdr priority [2:1] */ 606 srcmod:5, /* source module */ 607 reason:16; /* cpu opcode */ 608 #else 609 uint32 reason:16, 610 srcmod:5, 611 prio_hi:2, 612 s1valid:1, 613 prio_lo:1, 614 opcode:3, 615 ingport_lo:4; 616 #endif 617 /* T6.12: Status 2 (same as T3) */ 618 #ifdef LE_HOST 619 uint32 class_tag:16, /* classification / vc label [15:0] */ 620 match_rule:7, /* match rule */ 621 destport:5, /* destination port */ 622 destmod_lo:3, /* destination module [2:0] */ 623 s2valid:1; /* status word valid */ 624 #else 625 uint32 s2valid:1, 626 destmod_lo:3, 627 destport:5, 628 match_rule:7, 629 class_tag:16; 630 #endif 631 /* T6.13: Status 3 */ 632 #ifdef LE_HOST 633 uint32 ingport_hi:1, /* local source (ingress) port [4] */ 634 match_rule_hi:1, /* match rule [7] */ 635 destmod_hi:2, /* dest module [4:3] */ 636 vclabel_hi:4, /* vc label [19:16] */ 637 :23, 638 s3valid:1; /* status word valid */ 639 #else 640 uint32 s3valid:1, 641 :23, 642 vclabel_hi:4, 643 destmod_hi:2, 644 match_rule_hi:1, 645 ingport_hi:1; 646 #endif 647 /* T6.14: Status 4 */ 648 #ifdef LE_HOST 649 uint32 s4purge:1, /* purge */ 650 s4destmod1:1, /* destination module is high */ 651 s4aged:1, /* packet aged in mmu */ 652 s4untagged:1, /* untagged packet */ 653 s4ipmc_repl:1, /* ipmc replication start */ 654 s4destport:5, /* destination port */ 655 s4smp:1, /* switch on mirror port */ 656 s4l3_stats:1, /* received for l3 stats */ 657 s4srcmod1:1, /* source module is high */ 658 s4cos:3, /* class of service */ 659 :1, 660 s4hdr_type:2, /* higig header type */ 661 s4cng:1, /* congestion */ 662 :1, 663 s4dest_tgid:3, /* destination trunk group */ 664 s4dest_trunk:1, /* destination is a trunk */ 665 s4mirror:1, /* packet is mirrored */ 666 s4mirror_done:1, /* mirroring done */ 667 s4mirror_only:1, /* mirror only */ 668 s4pfm:2, /* port filtering mode */ 669 :1, 670 s4valid:1; /* status word valid */ 671 #else 672 uint32 s4valid:1, 673 :1, 674 s4pfm:2, 675 s4mirror_only:1, 676 s4mirror_done:1, 677 s4mirror:1, 678 s4dest_trunk:1, 679 s4dest_tgid:3, 680 :1, 681 s4cng:1, 682 s4hdr_type:2, 683 :1, 684 s4cos:3, 685 s4srcmod1:1, 686 s4l3_stats:1, 687 s4smp:1, 688 s4destport:5, 689 s4ipmc_repl:1, 690 s4untagged:1, 691 s4aged:1, 692 s4destmod1:1, 693 s4purge:1; 694 #endif 695 } dcb6_t; 696 #endif /* BCM_TUCANA_SUPPORT */ 697 698 #ifdef BCM_DRACO15_SUPPORT 699 /* 700 * DMA Control Block - Type 7 701 * Used on 5695 devices 702 * 10 words 703 */ 704 typedef struct { 705 uint32 addr; /* T7.0: physical address */ 706 /* T7.1: Control 0 */ 707 #ifdef LE_HOST 708 uint32 c_count:15, /* Requested byte count */ 709 c_crc:1, /* send pkt asis or regen crc */ 710 c_l3:1, /* l3 switch packet in egress */ 711 c_reload:1, /* Reload */ 712 c_sg:1, /* Scatter Gather */ 713 c_l3stat:1, /* update l3 stats in egress */ 714 c_opcode:4, /* hdr opcode */ 715 c_tagged:1, /* tagged packet */ 716 c_prio:3, /* hdr priority */ 717 c_cos:3, /* class of service */ 718 c_chain:1; /* Chaining */ 719 #else 720 uint32 c_chain:1, 721 c_cos:3, 722 c_prio:3, 723 c_tagged:1, 724 c_opcode:4, 725 c_l3stat:1, 726 c_sg:1, 727 c_reload:1, 728 c_l3:1, 729 c_crc:1, 730 c_count:15; 731 #endif /* LE_HOST */ 732 uint32 l2ports; /* T7.2: L2 transmit to ports */ 733 uint32 utports; /* T7.3: L2 untagged ports */ 734 uint32 l3ports; /* T7.4: L3 transmit to ports */ 735 /* T7.5: Control 1 */ 736 #ifdef LE_HOST 737 uint32 c_destmod:7, /* Destination module */ 738 c_destport:6, /* Destination port */ 739 c_srcmod:7, /* Source module */ 740 c_srcport:6, /* Source port/trunk */ 741 c_pfm:2, /* Port filtering mode */ 742 c_smp:1, /* Switch on mirror port */ 743 :3; 744 #else 745 uint32 :3, 746 c_smp:1, 747 c_pfm:2, 748 c_srcport:6, 749 c_srcmod:7, 750 c_destport:6, 751 c_destmod:7; 752 #endif 753 /* T7.6: Status 0 */ 754 #ifdef LE_HOST 755 uint32 count:16, /* Transferred byte count */ 756 crc:1, /* CRC Regen */ 757 /* DMA_GARBAGE_COLLECT set, pkt_aged */ 758 tagged:1, /* Ingress tagged */ 759 l3:1, /* L3 switch info received */ 760 start:1, /* S bit when DMA started */ 761 cos:3, /* CPU COS */ 762 error:1, /* Packet error */ 763 end:1, /* Last/End packet */ 764 ingport:6, /* packet ingress source port */ 765 cng:1; /* Packet marked for congestion */ 766 #else 767 uint32 cng:1, 768 ingport:6, 769 end:1, 770 error:1, 771 cos:3, 772 start:1, 773 l3:1, 774 tagged:1, 775 crc:1, 776 count:16; 777 #endif 778 /* T7.7: Status 1 */ 779 #ifdef LE_HOST 780 uint32 srcport:6, /* Source port/trunk */ 781 srcmod:7, /* Source modid */ 782 destport:6, /* Destination port / mcindex */ 783 destmod:7, /* Destination module / mcindex */ 784 opcode:4, /* hdr opcode */ 785 pfm:2; /* Port Filtering Mode */ 786 #else 787 uint32 pfm:2, 788 opcode:4, 789 destmod:7, 790 destport:6, 791 srcmod:7, 792 srcport:6; 793 #endif 794 /* T7.8: Status 2 */ 795 #ifdef LE_HOST 796 uint32 class_tag:16, /* classification tag */ 797 match_rule:16; /* match rule */ 798 #else 799 uint32 match_rule:16, 800 class_tag:16; 801 #endif 802 /* T7.9: Status 3 */ 803 #ifdef LE_HOST 804 uint32 reason:24, /* CPU opcode */ 805 :2, 806 hdr_type:2, /* higig hdr type */ 807 prio:3, /* hdr priority */ 808 s3valid:1; /* status word valid */ 809 #else 810 uint32 s3valid:1, 811 prio:3, 812 hdr_type:2, 813 :2, 814 reason:24; 815 #endif 816 } dcb7_t; 817 #endif /* BCM_DRACO15_SUPPORT */ 818 819 820 #if defined(BCM_XGS3_SWITCH_SUPPORT) || defined(BCM_PETRA_SUPPORT) 821 /* 822 * DMA Control Block - Type 9 823 * Used on 56504 devices 824 * 11 words 825 */ 826 typedef struct { 827 uint32 addr; /* T9.0: physical address */ 828 /* T9.1: Control 0 */ 829 #ifdef LE_HOST 830 uint32 c_count:16, /* Requested byte count */ 831 c_chain:1, /* Chaining */ 832 c_sg:1, /* Scatter Gather */ 833 c_reload:1, /* Reload */ 834 c_hg:1, /* Higig (TX) */ 835 c_stat:1, /* update stats (TX) */ 836 c_pause:1, /* Pause packet (TX) */ 837 c_purge:1, /* Purge packet (TX) */ 838 :9; /* Don't care */ 839 #else 840 uint32 :9, /* Don't care */ 841 c_purge:1, /* Purge packet (TX) */ 842 c_pause:1, 843 c_stat:1, 844 c_hg:1, 845 c_reload:1, 846 c_sg:1, 847 c_chain:1, 848 c_count:16; 849 #endif /* LE_HOST */ 850 uint32 mh0; /* T9.2: Module Header word 0 */ 851 uint32 mh1; /* T9.3: Module Header word 1 */ 852 uint32 mh2; /* T9.4: Module Header word 2 */ 853 #ifdef LE_HOST 854 /* T9.5: RX Status 0 */ 855 uint32 mtp_index_hi:5, /* Mirror-to-Port Index */ 856 l3uc:1, /* L3 UC */ 857 l3only:1, /* L3 only */ 858 l3ipmc:1, /* L3 IPMC */ 859 l3_intf:12, /* L3 Intf number */ 860 imirror:1, /* Ingress Mirroring */ 861 emirror:1, /* Egress Mirroring */ 862 cos:3, /* Packet Priority */ 863 cpu_cos:3, /* CPU COS */ 864 chg_tos:1, /* DSCP Changed */ 865 cell_error:1, /* Cell CRC Checksum Error Detected */ 866 bpdu:1, /* BPDU Packet */ 867 add_vid:1; /* VLAN ID Added */ 868 /* T9.6: RX Status 1 */ 869 uint32 reason:25, /* CPU opcode */ 870 regen_crc:1, /* Regenerate CRC */ 871 switch_pkt:1, /* Switched packet */ 872 src_hg:1, /* Source is Higig */ 873 purge_cell:1, /* Packet is marked Purged */ 874 pkt_aged:1, /* Pkt is Aged */ 875 mtp_index_lo:2; /* Mirror-to-Port Index */ 876 /* T9.7: RX Status 2 */ 877 uint32 dscp_hi:2, /* New DSCP */ 878 srcport:5, /* Source port */ 879 nh_index:13, /* Next hop index */ 880 match_rule:10, /* Matched Rule */ 881 match_rule_valid:1, /* Matched Rule valid */ 882 decap_iptunnel:1; /* Decap IP Tunneling Packet */ 883 884 /* T9.8: RX Status 3 */ 885 uint32 :11, 886 ingress_untagged:1, /* Pkt came in untagged */ 887 outer_vid:12, /* VID */ 888 outer_cfi:1, /* CFI */ 889 outer_pri:3, /* Priority */ 890 dscp_lo:4; /* New DSCP */ 891 #else 892 /* T9.5: RX Status 0 */ 893 uint32 add_vid:1, /* VLAN ID Added */ 894 bpdu:1, /* BPDU Packet */ 895 cell_error:1, /* Cell CRC Checksum Error Detected */ 896 chg_tos:1, /* DSCP Changed */ 897 cpu_cos:3, /* CPU COS */ 898 cos:3, /* Packet Priority */ 899 emirror:1, /* Egress Mirroring */ 900 imirror:1, /* Ingress Mirroring */ 901 l3_intf:12, /* L3 Intf number */ 902 l3ipmc:1, /* L3 IPMC */ 903 l3only:1, /* L3 only */ 904 l3uc:1, /* L3 UC */ 905 mtp_index_hi:5; /* Mirror-to-Port Index */ 906 /* T9.6: RX Status 1 */ 907 uint32 mtp_index_lo:2, /* Mirror-to-Port Index */ 908 pkt_aged:1, /* Pkt is Aged */ 909 purge_cell:1, /* Packet is marked Purged */ 910 src_hg:1, /* Source is Higig */ 911 switch_pkt:1, /* Switched packet */ 912 regen_crc:1, /* Regenerate CRC */ 913 reason:25; /* CPU opcode */ 914 /* T9.7: RX Status 2 */ 915 uint32 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 916 match_rule_valid:1, /* Matched Rule valid */ 917 match_rule:10, /* Matched Rule */ 918 nh_index:13, /* Next hop index */ 919 srcport:5, /* Source port */ 920 dscp_hi:2; /* New DSCP */ 921 /* T9.8: RX Status 3 */ 922 uint32 dscp_lo:4, /* New DSCP */ 923 outer_pri:3, /* Priority (D)*/ 924 outer_cfi:1, /* CFI (D)*/ 925 outer_vid:12, /* VID (D)*/ 926 ingress_untagged:1, /* Pkt came in untagged (D)*/ 927 :11; 928 #endif 929 930 uint32 s_4; /* T9.9: RX Status 4 */ 931 /* T9.10: DMA Status 0 */ 932 #ifdef LE_HOST 933 uint32 count:16, /* Transferred byte count */ 934 end:1, /* End bit (RX) */ 935 start:1, /* Start bit (RX) */ 936 error:1, /* Cell Error (RX) */ 937 dc:12, /* Don't Care */ 938 done:1; /* Descriptor Done */ 939 #else 940 uint32 done:1, 941 dc:12, 942 error:1, 943 start:1, 944 end:1, 945 count:16; 946 #endif 947 } dcb9_t; 948 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 949 950 #ifdef BCM_EASYRIDER_SUPPORT 951 /* 952 * DMA Control Block - Type 10 953 * Used on 56601 devices 954 * 11 words 955 */ 956 typedef struct { 957 uint32 addr; /* T10.0: physical address */ 958 /* T10.1: Control 0 */ 959 #ifdef LE_HOST 960 uint32 c_count:16, /* Requested byte count */ 961 c_chain:1, /* Chaining */ 962 c_sg:1, /* Scatter Gather */ 963 c_reload:1, /* Reload */ 964 c_hg:1, /* Higig (TX) */ 965 c_stat:1, /* update stats (TX) */ 966 c_pause:1, /* Pause packet (TX) */ 967 c_purge:1, /* Purge packet (TX) */ 968 :9; /* Don't care */ 969 #else 970 uint32 :9, /* Don't care */ 971 c_purge:1, /* Purge packet (TX) */ 972 c_pause:1, 973 c_stat:1, 974 c_hg:1, 975 c_reload:1, 976 c_sg:1, 977 c_chain:1, 978 c_count:16; 979 #endif /* LE_HOST */ 980 uint32 mh0; /* T10.2: Module Header word 0 */ 981 uint32 mh1; /* T10.3: Module Header word 1 */ 982 uint32 mh2; /* T10.4: Module Header word 2 */ 983 #ifdef LE_HOST 984 /* T10.5: RX Status 0 */ 985 uint32 mtp_index:5, /* Mirror-to-Port Index (D)*/ 986 l3uc:1, /* L3 UC */ 987 l3only:1, /* L3 only */ 988 l3ipmc:1, /* L3 IPMC */ 989 l3_intf:12, /* L3 Intf number */ 990 imirror:1, /* Ingress Mirroring */ 991 emirror:1, /* Egress Mirroring */ 992 cos:3, /* Packet Priority */ 993 cpu_cos:3, /* CPU COS */ 994 chg_tos:1, /* DSCP Changed */ 995 cell_error:1, /* Cell CRC Checksum Error Detected */ 996 bpdu:1, /* BPDU Packet */ 997 add_vid:1; /* VLAN ID Added */ 998 /* T10.6: RX Status 1 */ 999 uint32 reason_hi:26, /* CPU opcode (D)*/ 1000 pkt_not_changed:1, /* L2 pkt unmodified for L2 MPLS (D)*/ 1001 regen_crc:1, /* Regenerate CRC */ 1002 switch_pkt:1, /* Switched packet */ 1003 src_hg:1, /* Source is Higig */ 1004 purge_cell:1, /* Packet is marked Purged */ 1005 pkt_aged:1; /* Pkt is Aged */ 1006 /* T10.8: RX Status 2 */ 1007 uint32 nh_index_hi:14, /* Next hop index (D)*/ 1008 match_rule:9, /* Matched Rule (D)*/ 1009 decap_iptunnel:3, /* Decap IP Tunneling Packet (D)*/ 1010 reason_lo:6; /* CPU opcode (D)*/ 1011 /* T10.8: RX Status 3 */ 1012 uint32 :18, 1013 ingress_untagged:1, /* Pkt came in untagged (D)*/ 1014 ecn:2, /* New ECN */ 1015 dscp:6, /* New DSCP */ 1016 srcport:4, /* Source port (D)*/ 1017 nh_index_lo:1; /* Next hop index (D)*/ 1018 #else 1019 /* T10.5: RX Status 0 */ 1020 uint32 add_vid:1, /* VLAN ID Added */ 1021 bpdu:1, /* BPDU Packet */ 1022 cell_error:1, /* Cell CRC Checksum Error Detected */ 1023 chg_tos:1, /* DSCP Changed */ 1024 cpu_cos:3, /* CPU COS */ 1025 cos:3, /* Packet Priority */ 1026 emirror:1, /* Egress Mirroring */ 1027 imirror:1, /* Ingress Mirroring */ 1028 l3_intf:12, /* L3 Intf number */ 1029 l3ipmc:1, /* L3 IPMC */ 1030 l3only:1, /* L3 only */ 1031 l3uc:1, /* L3 UC */ 1032 mtp_index:5; /* Mirror-to-Port Index (D)*/ 1033 /* T10.6: RX Status 1 */ 1034 uint32 pkt_aged:1, /* Pkt is Aged */ 1035 purge_cell:1, /* Packet is marked Purged */ 1036 src_hg:1, /* Source is Higig */ 1037 switch_pkt:1, /* Switched packet */ 1038 regen_crc:1, /* Regenerate CRC */ 1039 pkt_not_changed:1, /* L2 pkt unmodified for L2 MPLS (D)*/ 1040 reason_hi:26; /* CPU opcode (D)*/ 1041 /* T10.8: RX Status 2 */ 1042 uint32 reason_lo:6, /* CPU opcode (D)*/ 1043 decap_iptunnel:3, /* Decap IP Tunneling Packet (D)*/ 1044 match_rule:9, /* Matched Rule (D)*/ 1045 nh_index_hi:14; /* Next hop index (D)*/ 1046 /* T10.8: RX Status 3 */ 1047 uint32 nh_index_lo:1, /* Next hop index (D)*/ 1048 srcport:4, /* Source port (D)*/ 1049 dscp:6, /* New DSCP */ 1050 ecn:2, /* New ECN */ 1051 ingress_untagged:1, /* Pkt came in untagged (D)*/ 1052 :18; 1053 #endif 1054 1055 uint32 s_4; /* T10.9: RX Status 4 */ 1056 /* T10.10: DMA Status 0 */ 1057 #ifdef LE_HOST 1058 uint32 count:16, /* Transferred byte count */ 1059 end:1, /* End bit (RX) */ 1060 start:1, /* Start bit (RX) */ 1061 error:1, /* Cell Error (RX) */ 1062 dc:12, /* Don't Care */ 1063 done:1; /* Descriptor Done */ 1064 #else 1065 uint32 done:1, 1066 dc:12, 1067 error:1, 1068 start:1, 1069 end:1, 1070 count:16; 1071 #endif 1072 } dcb10_t; 1073 #endif /* BCM_EASYRIDER_SUPPORT */ 1074 1075 #ifdef BCM_BRADLEY_SUPPORT 1076 /* 1077 * DMA Control Block - Type 11 1078 * Used on 5680x, 5670x and 56580 devices 1079 * 11 words 1080 */ 1081 typedef struct { 1082 uint32 addr; /* T11.0: physical address */ 1083 /* T11.1: Control 0 */ 1084 #ifdef LE_HOST 1085 uint32 c_count:16, /* Requested byte count */ 1086 c_chain:1, /* Chaining */ 1087 c_sg:1, /* Scatter Gather */ 1088 c_reload:1, /* Reload */ 1089 c_hg:1, /* Higig (TX) */ 1090 :12; /* Don't care */ 1091 #else 1092 uint32 :12, /* Don't care */ 1093 c_hg:1, /* Higig (TX) */ 1094 c_reload:1, /* Reload */ 1095 c_sg:1, /* Scatter Gather */ 1096 c_chain:1, /* Chaining */ 1097 c_count:16; /* Requested byte count */ 1098 #endif /* LE_HOST */ 1099 uint32 mh0; /* T11.2: Module Header word 0 */ 1100 uint32 mh1; /* T11.3: Module Header word 1 */ 1101 uint32 mh2; /* T11.4: Module Header word 2 */ 1102 uint32 mh3; /* T11.5: Module Header word 3 */ 1103 #ifdef LE_HOST 1104 /* T11.6: RX Status 0 */ 1105 uint32 cos:4, /* COS queue for non-CPU packets */ 1106 cpu_cos:4, /* COS queue for CPU packets */ 1107 l3_intf:12, /* Interface from IPMC replication */ 1108 l3ipmc:1, /* L3 IPMC replicated copy */ 1109 imirror:1, /* Ingress Mirroring */ 1110 emirror:1, /* Egress Mirroring */ 1111 chg_tos:1, /* DSCP has been changed by HW */ 1112 cell_error:1, /* CRC error in buffer memory cell */ 1113 bpdu:1, /* BPDU packet */ 1114 add_vid:1, /* Add VLAN ID */ 1115 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 1116 hgi:2, /* Higig Interface Format Indicator */ 1117 :1, /* Reserved */ 1118 hg_type:1; /* 0: Higig+, 1: Higig2 */ 1119 1120 uint32 reason:25, /* CPU opcode */ 1121 mtp_index:7; /* Mirror-to port */ 1122 1123 uint32 outer_vid:12, /* Outer VLAN ID */ 1124 outer_cfi:1, /* Outer Canoncial Format Indicator */ 1125 outer_pri:3, /* Outer priority */ 1126 dscp:8, /* New DSCP */ 1127 decap_iptunnel:1, /* IP tunnel was decapsulated */ 1128 srcport:5, /* Source port number */ 1129 ecn:2; /* New ECN */ 1130 1131 uint32 nh_index:13, /* Next hop index */ 1132 ingress_untagged:1, /* Packet came in untagged */ 1133 regen_crc:1, /* Packet modified and needs new CRC */ 1134 switch_pkt:1, /* Switched packet */ 1135 src_hg:1, /* Source port was Higig */ 1136 purge_cell:1, /* Packet contains purged cells */ 1137 pkt_aged:1, /* Packet aged while in MMU buffer */ 1138 l3uc:1, /* L3 unicast packet */ 1139 l3only:1, /* L3 only IPMC packet */ 1140 match_rule:10, /* Matched FP rule */ 1141 match_rule_valid:1; /* Matched Rule valid */ 1142 1143 /* T11.10: DMA Status 0 */ 1144 uint32 count:16, /* Transferred byte count */ 1145 end:1, /* End bit (RX) */ 1146 start:1, /* Start bit (RX) */ 1147 error:1, /* Cell Error (RX) */ 1148 dc:12, /* Don't Care */ 1149 done:1; /* Descriptor Done */ 1150 #else 1151 /* T11.6: RX Status 0 */ 1152 uint32 hg_type:1, /* 0: Higig+, 1: Higig2 */ 1153 :1, /* Reserved */ 1154 hgi:2, /* Higig Interface Format Indicator */ 1155 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 1156 add_vid:1, /* Add VLAN ID */ 1157 bpdu:1, /* BPDU packet */ 1158 cell_error:1, /* CRC error in buffer memory cell */ 1159 chg_tos:1, /* DSCP has been changed by HW */ 1160 emirror:1, /* Egress Mirroring */ 1161 imirror:1, /* Ingress Mirroring */ 1162 l3ipmc:1, /* L3 IPMC replicated copy */ 1163 l3_intf:12, /* Interface from IPMC replication */ 1164 cpu_cos:4, /* COS queue for CPU packets */ 1165 cos:4; /* COS queue for non-CPU packets */ 1166 1167 uint32 mtp_index:7, /* Mirror-to port */ 1168 reason:25; /* CPU opcode */ 1169 1170 uint32 ecn:2, /* New ECN */ 1171 srcport:5, /* Source port number */ 1172 decap_iptunnel:1, /* IP tunnel was decapsulated */ 1173 dscp:8, /* New DSCP */ 1174 outer_pri:3, /* Outer priority */ 1175 outer_cfi:1, /* Outer Canoncial Format Indicator */ 1176 outer_vid:12; /* Outer VLAN ID */ 1177 1178 uint32 match_rule_valid:1, /* Matched Rule valid */ 1179 match_rule:10, /* Matched FP rule */ 1180 l3only:1, /* L3 only IPMC packet */ 1181 l3uc:1, /* L3 unicast packet */ 1182 pkt_aged:1, /* Packet aged while in MMU buffer */ 1183 purge_cell:1, /* Packet contains purged cells */ 1184 src_hg:1, /* Source port was Higig */ 1185 switch_pkt:1, /* Switched packet */ 1186 regen_crc:1, /* Packet modified and needs new CRC */ 1187 ingress_untagged:1, /* Packet came in untagged */ 1188 nh_index:13; /* Next hop index */ 1189 1190 /* T11.10: DMA Status 0 */ 1191 uint32 done:1, /* Descriptor Done */ 1192 dc:12, /* Don't Care */ 1193 error:1, /* Cell Error (RX) */ 1194 start:1, /* Start bit (RX) */ 1195 end:1, /* End bit (RX) */ 1196 count:16; /* Transferred byte count */ 1197 #endif 1198 } dcb11_t; 1199 #endif /* BCM_BRADLEY_SUPPORT */ 1200 1201 #ifdef BCM_RAPTOR_SUPPORT 1202 /* 1203 * DMA Control Block - Type 12 1204 * Used on 56218 devices 1205 * 11 words 1206 */ 1207 typedef struct { 1208 uint32 addr; /* T12.0: physical address */ 1209 /* T12.1: Control 0 */ 1210 #ifdef LE_HOST 1211 uint32 c_count:16, /* Requested byte count */ 1212 c_chain:1, /* Chaining */ 1213 c_sg:1, /* Scatter Gather */ 1214 c_reload:1, /* Reload */ 1215 c_hg:1, /* Higig (TX) */ 1216 c_stat:1, /* Reserved (TX) */ 1217 c_pause:1, /* Reserved (TX) */ 1218 c_purge:1, /* Purge packet (TX) */ 1219 :9; /* Don't care */ 1220 #else 1221 uint32 :9, /* Don't care */ 1222 c_purge:1, /* Purge packet (TX) */ 1223 c_pause:1, 1224 c_stat:1, 1225 c_hg:1, 1226 c_reload:1, 1227 c_sg:1, 1228 c_chain:1, 1229 c_count:16; 1230 #endif /* LE_HOST */ 1231 uint32 mh0; /* T12.2: Module Header word 0 */ 1232 uint32 mh1; /* T12.3: Module Header word 1 */ 1233 uint32 mh2; /* T12.4: Module Header word 2 */ 1234 uint32 mh3; /* T12.5: Module Header word 3 */ 1235 #ifdef LE_HOST 1236 /* T12.6: RX Status 0 */ 1237 uint32 :6, /* Reserved */ 1238 regen_crc:1, /* Regenerate CRC */ 1239 switch_pkt:1, /* Switched packet */ 1240 src_hg:1, /* Source is Higig */ 1241 purge_cell:1, /* Packet is marked Purged */ 1242 pkt_aged:1, /* Pkt is Aged */ 1243 mtp_index:7, /* Mirror-to-Port Index */ 1244 l3uc:1, /* L3 UC */ 1245 imirror:1, /* Ingress Mirroring */ 1246 emirror:1, /* Egress Mirroring */ 1247 cos:3, /* Packet Priority */ 1248 cpu_cos:3, /* CPU COS */ 1249 chg_tos:1, /* DSCP Changed */ 1250 cell_error:1, /* Cell CRC Checksum Error Detected */ 1251 bpdu:1, /* BPDU Packet */ 1252 add_vid:1, /* VLAN ID Added */ 1253 do_not_change_ttl:1; /* FP indicator for L3 unicast */ 1254 1255 /* T12.7: RX Status 0 */ 1256 uint32 reason:26, /* CPU opcode */ 1257 :6; /* Padding */ 1258 1259 /* T12.8: RX Status 2 */ 1260 uint32 dscp:8, /* New DSCP */ 1261 srcport:6, /* Source port */ 1262 nh_index:8, /* Next hop index */ 1263 match_rule:10; /* Matched Rule */ 1264 1265 /* T12.9: RX Status 3 */ 1266 uint32 :14, 1267 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 1268 ingress_untagged:1, /* Pkt came in untagged */ 1269 outer_vid:12, /* VID */ 1270 outer_cfi:1, /* CFI */ 1271 outer_pri:3; /* Priority */ 1272 #else 1273 /* T12.6: RX Status 0 */ 1274 uint32 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 1275 add_vid:1, /* VLAN ID Added */ 1276 bpdu:1, /* BPDU Packet */ 1277 cell_error:1, /* Cell CRC Checksum Error Detected */ 1278 chg_tos:1, /* DSCP Changed */ 1279 cpu_cos:3, /* CPU COS */ 1280 cos:3, /* Packet Priority */ 1281 emirror:1, /* Egress Mirroring */ 1282 imirror:1, /* Ingress Mirroring */ 1283 l3uc:1, /* L3 UC */ 1284 mtp_index:7, /* Mirror-to-Port Index */ 1285 pkt_aged:1, /* Pkt is Aged */ 1286 purge_cell:1, /* Packet is marked Purged */ 1287 src_hg:1, /* Source is Higig */ 1288 switch_pkt:1, /* Switched packet */ 1289 regen_crc:1, /* Regenerate CRC */ 1290 :6; 1291 /* T12.7: RX Status 1 */ 1292 uint32 :6, 1293 reason:26; /* CPU opcode */ 1294 /* T12.8: RX Status 2 */ 1295 uint32 match_rule:10, /* Matched Rule */ 1296 nh_index:8, /* Next hop index */ 1297 srcport:6, /* Source port */ 1298 dscp:8; /* New DSCP */ 1299 /* T12.9: RX Status 3 */ 1300 uint32 outer_pri:3, /* Priority (D)*/ 1301 outer_cfi:1, /* CFI (D)*/ 1302 outer_vid:12, /* VID (D)*/ 1303 ingress_untagged:1, /* Pkt came in untagged (D)*/ 1304 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 1305 :14; 1306 #endif 1307 1308 /* T12.10: DMA Status 0 */ 1309 #ifdef LE_HOST 1310 uint32 count:16, /* Transferred byte count */ 1311 end:1, /* End bit (RX) */ 1312 start:1, /* Start bit (RX) */ 1313 error:1, /* Cell Error (RX) */ 1314 dc:12, /* Don't Care */ 1315 done:1; /* Descriptor Done */ 1316 #else 1317 uint32 done:1, 1318 dc:12, 1319 error:1, 1320 start:1, 1321 end:1, 1322 count:16; 1323 #endif 1324 } dcb12_t; 1325 #endif /* BCM_RAPTOR_SUPPORT */ 1326 1327 #if defined(BCM_FIREBOLT2_SUPPORT) || defined(BCM_FIREBOLT_SUPPORT) 1328 /* 1329 * DMA Control Block - Type 13 1330 * Used on 56514 devices 1331 * 11 words 1332 */ 1333 typedef struct { 1334 uint32 addr; /* T13.0: physical address */ 1335 /* T13.1: Control 0 */ 1336 #ifdef LE_HOST 1337 uint32 c_count:16, /* Requested byte count */ 1338 c_chain:1, /* Chaining */ 1339 c_sg:1, /* Scatter Gather */ 1340 c_reload:1, /* Reload */ 1341 c_hg:1, /* Higig (TX) */ 1342 c_stat:1, /* update stats (TX) */ 1343 c_pause:1, /* Pause packet (TX) */ 1344 c_purge:1, /* Purge packet (TX) */ 1345 :9; /* Don't care */ 1346 #else 1347 uint32 :9, /* Don't care */ 1348 c_purge:1, /* Purge packet (TX) */ 1349 c_pause:1, 1350 c_stat:1, 1351 c_hg:1, 1352 c_reload:1, 1353 c_sg:1, 1354 c_chain:1, 1355 c_count:16; 1356 #endif /* LE_HOST */ 1357 uint32 mh0; /* T13.2: Module Header word 0 */ 1358 uint32 mh1; /* T13.3: Module Header word 1 */ 1359 uint32 mh2; /* T13.4: Module Header word 2 */ 1360 #ifdef LE_HOST 1361 /* T13.5: RX Status 0 */ 1362 uint32 mtp_index_hi:5, /* Mirror-to-Port Index */ 1363 l3uc:1, /* L3 UC */ 1364 l3only:1, /* L3 only */ 1365 l3ipmc:1, /* L3 IPMC */ 1366 l3_intf:12, /* L3 Intf number */ 1367 imirror:1, /* Ingress Mirroring */ 1368 emirror:1, /* Egress Mirroring */ 1369 cos:3, /* Packet Priority */ 1370 cpu_cos:3, /* CPU COS */ 1371 chg_tos:1, /* DSCP Changed */ 1372 cell_error:1, /* Cell CRC Checksum Error Detected */ 1373 bpdu:1, /* BPDU Packet */ 1374 add_vid:1; /* VLAN ID Added */ 1375 /* T13.6: RX Status 1 */ 1376 uint32 reason:25, /* CPU opcode */ 1377 regen_crc:1, /* Regenerate CRC */ 1378 switch_pkt:1, /* Switched packet */ 1379 src_hg:1, /* Source is Higig */ 1380 purge_cell:1, /* Packet is marked Purged */ 1381 pkt_aged:1, /* Pkt is Aged */ 1382 mtp_index_lo:2; /* Mirror-to-Port Index */ 1383 /* T13.7: RX Status 2 */ 1384 uint32 dscp_hi:2, /* New DSCP */ 1385 srcport:5, /* Source port */ 1386 nh_index:13, /* Next hop index */ 1387 match_rule:10, /* Matched Rule */ 1388 match_rule_valid:1, /* Matched Rule valid */ 1389 decap_iptunnel:1; /* Decap IP Tunneling Packet */ 1390 1391 /* T13.8: RX Status 3 */ 1392 uint32 :8, 1393 inner_vlan_add:1, /* Inner VLAN tag, only for Firebolt_2 */ 1394 ingress_untagged:1, /* Pkt came in untagged */ 1395 outer_vid:12, /* VID */ 1396 outer_cfi:1, /* CFI */ 1397 outer_pri:3, /* Priority */ 1398 dscp_lo:6; /* New DSCP */ 1399 #else 1400 /* T13.5: RX Status 0 */ 1401 uint32 add_vid:1, /* VLAN ID Added */ 1402 bpdu:1, /* BPDU Packet */ 1403 cell_error:1, /* Cell CRC Checksum Error Detected */ 1404 chg_tos:1, /* DSCP Changed */ 1405 cpu_cos:3, /* CPU COS */ 1406 cos:3, /* Packet Priority */ 1407 emirror:1, /* Egress Mirroring */ 1408 imirror:1, /* Ingress Mirroring */ 1409 l3_intf:12, /* L3 Intf number */ 1410 l3ipmc:1, /* L3 IPMC */ 1411 l3only:1, /* L3 only */ 1412 l3uc:1, /* L3 UC */ 1413 mtp_index_hi:5; /* Mirror-to-Port Index */ 1414 /* T13.6: RX Status 1 */ 1415 uint32 mtp_index_lo:2, /* Mirror-to-Port Index */ 1416 pkt_aged:1, /* Pkt is Aged */ 1417 purge_cell:1, /* Packet is marked Purged */ 1418 src_hg:1, /* Source is Higig */ 1419 switch_pkt:1, /* Switched packet */ 1420 regen_crc:1, /* Regenerate CRC */ 1421 reason:25; /* CPU opcode */ 1422 /* T13.7: RX Status 2 */ 1423 uint32 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 1424 match_rule_valid:1, /* Matched Rule valid */ 1425 match_rule:10, /* Matched Rule */ 1426 nh_index:13, /* Next hop index */ 1427 srcport:5, /* Source port */ 1428 dscp_hi:2; /* New DSCP */ 1429 /* T13.8: RX Status 3 */ 1430 uint32 dscp_lo:6, /* New DSCP */ 1431 outer_pri:3, /* Priority (D)*/ 1432 outer_cfi:1, /* CFI (D)*/ 1433 outer_vid:12, /* VID (D)*/ 1434 ingress_untagged:1, /* Pkt came in untagged (D)*/ 1435 inner_vlan_add:1, /* Inner VLAN tag, only for Firebolt_2 */ 1436 :8; 1437 #endif 1438 1439 uint32 s_4; /* T13.9: RX Status 4 */ 1440 /* T13.10: DMA Status 0 */ 1441 #ifdef LE_HOST 1442 uint32 count:16, /* Transferred byte count */ 1443 end:1, /* End bit (RX) */ 1444 start:1, /* Start bit (RX) */ 1445 error:1, /* Cell Error (RX) */ 1446 dc:12, /* Don't Care */ 1447 done:1; /* Descriptor Done */ 1448 #else 1449 uint32 done:1, 1450 dc:12, 1451 error:1, 1452 start:1, 1453 end:1, 1454 count:16; 1455 #endif 1456 } dcb13_t; 1457 #endif /* BCM_FIREBOLT2_SUPPORT || BCM_FIREBOLT_SUPPORT */ 1458 1459 #if defined(BCM_TRIUMPH_SUPPORT) || defined(BCM_SCORPION_SUPPORT) 1460 /* 1461 * DMA Control Block - Type 14 1462 * Used on 5661x devices 1463 * 16 words 1464 */ 1465 typedef struct { 1466 uint32 addr; /* T14.0: physical address */ 1467 /* T14.1: Control 0 */ 1468 #ifdef LE_HOST 1469 uint32 c_count:16, /* Requested byte count */ 1470 c_chain:1, /* Chaining */ 1471 c_sg:1, /* Scatter Gather */ 1472 c_reload:1, /* Reload */ 1473 c_hg:1, /* Higig (TX) */ 1474 c_stat:1, /* update stats (TX) */ 1475 c_pause:1, /* Pause packet (TX) */ 1476 c_purge:1, /* Purge packet (TX) */ 1477 :9; /* Don't care */ 1478 #else 1479 uint32 :9, /* Don't care */ 1480 c_purge:1, /* Purge packet (TX) */ 1481 c_pause:1, 1482 c_stat:1, 1483 c_hg:1, 1484 c_reload:1, 1485 c_sg:1, 1486 c_chain:1, 1487 c_count:16; 1488 #endif /* LE_HOST */ 1489 uint32 mh0; /* T14.2: Module Header word 0 */ 1490 uint32 mh1; /* T14.3: Module Header word 1 */ 1491 uint32 mh2; /* T14.4: Module Header word 2 */ 1492 uint32 mh3; /* T14.5: Module Header word 3 */ 1493 #ifdef LE_HOST 1494 /* T14.6: RX Status 0 */ 1495 uint32 :8, /* Reserved */ 1496 cpu_cos:6, /* COS queue for CPU packets */ 1497 :2, /* Reserved */ 1498 pkt_len:14, /* Packet Length After Modification */ 1499 :2; /* Reserved */ 1500 1501 /* T14.7 */ 1502 uint32 reason_hi:16, /* CPU opcode (high bits) */ 1503 :16; /* Reserved */ 1504 1505 /* T14.8 */ 1506 uint32 reason; /* CPU opcode */ 1507 1508 /* T14.9 */ 1509 uint32 dscp:8, /* New DSCP */ 1510 decap_iptunnel:1, /* IP tunnel was decapsulated */ 1511 chg_tos:1, /* DSCP has been changed by HW */ 1512 regen_crc:1, /* Packet modified and needs new CRC */ 1513 ingress_untagged:1, /* Packet came in untagged */ 1514 :4, /* Reserved */ 1515 outer_vid:12, /* Outer VLAN ID */ 1516 outer_cfi:1, /* Outer Canoncial Format Indicator */ 1517 outer_pri:3; /* Outer priority */ 1518 1519 /* T14.10 */ 1520 uint32 reserved_w10; /* Reserved */ 1521 1522 /* T14.11 */ 1523 uint32 cos:3, /* COS */ 1524 :5, /* Reserved */ 1525 higig_cos:5, /* Higig COS */ 1526 :3, /* Reserved */ 1527 vlan_cos:5, /* VLAN COS */ 1528 :3, /* Reserved */ 1529 shaping_cos_sel:2, /* Shaping COS Select */ 1530 :6; /* Reserved */ 1531 1532 /* T14.12 */ 1533 uint32 srcport:8, /* Source port number */ 1534 hgi:2, /* Higig Interface Format Indicator */ 1535 itag_status:2, /* Ingress incoming tag status */ 1536 otag_action:2, /* Ingress Outer tag action */ 1537 itag_action:2, /* Ingress Inner tag action */ 1538 switch_pkt:1, /* Switched packet */ 1539 hg_type:1, /* 0: Higig+, 1: Higig2 */ 1540 src_hg:1, /* Source is Higig */ 1541 purge_cell:1, /* Packet is marked Purged */ 1542 pkt_aged:1, /* Pkt is Aged */ 1543 l3uc:1, /* L3 UC */ 1544 l3only:1, /* L3 only IPMC packet */ 1545 l3ipmc:1, /* L3 IPMC replicated copy */ 1546 imirror:1, /* Ingress Mirroring */ 1547 emirror:1, /* Egress Mirroring */ 1548 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 1549 cell_error:1, /* Cell CRC Checksum Error Detected */ 1550 bpdu:1, /* BPDU Packet */ 1551 :3; /* Reserved */ 1552 1553 /* T14.13 */ 1554 uint32 nh_index:13, /* Next hop index */ 1555 :3, /* Reserved */ 1556 em_mtp_index:5, /* Egress Mirror-to port */ 1557 :3, /* Reserved */ 1558 mtp_index:6, /* Ingress Mirror-to port */ 1559 :2; /* Reserved */ 1560 1561 /* T14.14 */ 1562 uint32 l3_intf:12, /* L3 Intf number */ 1563 :4, /* Reserved */ 1564 match_rule:11, /* Matched FP rule */ 1565 :5; /* Reserved */ 1566 1567 /* T14.15: DMA Status 0 */ 1568 uint32 count:16, /* Transferred byte count */ 1569 end:1, /* End bit (RX) */ 1570 start:1, /* Start bit (RX) */ 1571 error:1, /* Cell Error (RX) */ 1572 dc:12, /* Don't Care */ 1573 done:1; /* Descriptor Done */ 1574 #else 1575 /* T14.6: RX Status 0 */ 1576 uint32 :2, /* Reserved */ 1577 pkt_len:14, /* Packet Length After Modification */ 1578 :2, /* Reserved */ 1579 cpu_cos:6, /* COS queue for CPU packets */ 1580 :8; /* Reserved */ 1581 1582 /* T14.7 */ 1583 uint32 :16, /* CPU opcode (high bits) */ 1584 reason_hi:16; /* Reserved */ 1585 1586 /* T14.8 */ 1587 uint32 reason; /* CPU opcode */ 1588 1589 /* T14.9 */ 1590 uint32 outer_pri:3, /* Outer priority */ 1591 outer_cfi:1, /* Outer Canoncial Format Indicator */ 1592 outer_vid:12, /* Outer VLAN ID */ 1593 :4, /* Reserved */ 1594 ingress_untagged:1, /* Packet came in untagged */ 1595 regen_crc:1, /* Packet modified and needs new CRC */ 1596 chg_tos:1, /* DSCP has been changed by HW */ 1597 decap_iptunnel:1, /* IP tunnel was decapsulated */ 1598 dscp:8; /* New DSCP */ 1599 1600 /* T14.10 */ 1601 uint32 reserved_w10; /* Reserved */ 1602 1603 /* T14.11 */ 1604 uint32 :6, /* Reserved */ 1605 shaping_cos_sel:2, /* Shaping COS Select */ 1606 :3, /* Reserved */ 1607 vlan_cos:5, /* VLAN COS */ 1608 :3, /* Reserved */ 1609 higig_cos:5, /* Higig COS */ 1610 :5, /* Reserved */ 1611 cos:3; /* COS */ 1612 1613 /* T14.12 */ 1614 uint32 :3, /* Reserved */ 1615 bpdu:1, /* BPDU Packet */ 1616 cell_error:1, /* Cell CRC Checksum Error Detected */ 1617 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 1618 emirror:1, /* Egress Mirroring */ 1619 imirror:1, /* Ingress Mirroring */ 1620 l3ipmc:1, /* L3 IPMC replicated copy */ 1621 l3only:1, /* L3 only IPMC packet */ 1622 l3uc:1, /* L3 UC */ 1623 pkt_aged:1, /* Pkt is Aged */ 1624 purge_cell:1, /* Packet is marked Purged */ 1625 src_hg:1, /* Source is Higig */ 1626 hg_type:1, /* 0: Higig+, 1: Higig2 */ 1627 switch_pkt:1, /* Switched packet */ 1628 itag_action:2, /* Ingress Inner tag action */ 1629 otag_action:2, /* Ingress Outer tag action */ 1630 itag_status:2, /* Incoming tag status */ 1631 hgi:2, /* Higig Interface Format Indicator */ 1632 srcport:8; /* Source port number */ 1633 1634 /* T14.13 */ 1635 uint32 :2, /* Reserved */ 1636 mtp_index:6, /* Ingress Mirror-to port */ 1637 :3, /* Reserved */ 1638 em_mtp_index:5, /* Egress Mirror-to port */ 1639 :3, /* Reserved */ 1640 nh_index:13; /* Next hop index */ 1641 1642 /* T14.14 */ 1643 uint32 :5, /* Reserved */ 1644 match_rule:11, /* Matched FP rule */ 1645 :4, /* Reserved */ 1646 l3_intf:12; /* L3 Intf number */ 1647 1648 /* T14.15: DMA Status 0 */ 1649 uint32 done:1, /* Descriptor Done */ 1650 dc:12, /* Don't Care */ 1651 error:1, /* Cell Error (RX) */ 1652 start:1, /* Start bit (RX) */ 1653 end:1, /* End bit (RX) */ 1654 count:16; /* Transferred byte count */ 1655 #endif 1656 } dcb14_t; 1657 #endif /* BCM_TRIUMPH_SUPPORT */ 1658 1659 #ifdef BCM_RAPTOR_SUPPORT 1660 /* 1661 * DMA Control Block - Type 15 1662 * Used on 56224_A0 devices 1663 * 11 words 1664 */ 1665 typedef struct { 1666 uint32 addr; /* T15.0: physical address */ 1667 /* T15.1: Control 0 */ 1668 #ifdef LE_HOST 1669 uint32 c_count:16, /* Requested byte count */ 1670 c_chain:1, /* Chaining */ 1671 c_sg:1, /* Scatter Gather */ 1672 c_reload:1, /* Reload */ 1673 c_hg:1, /* Higig (TX) */ 1674 c_stat:1, /* Reserved (TX) */ 1675 c_pause:1, /* Reserved (TX) */ 1676 c_purge:1, /* Purge packet (TX) */ 1677 :9; /* Don't care */ 1678 #else 1679 uint32 :9, /* Don't care */ 1680 c_purge:1, /* Purge packet (TX) */ 1681 c_pause:1, 1682 c_stat:1, 1683 c_hg:1, 1684 c_reload:1, 1685 c_sg:1, 1686 c_chain:1, 1687 c_count:16; 1688 #endif /* LE_HOST */ 1689 uint32 mh0; /* T15.2: Module Header word 0 */ 1690 uint32 mh1; /* T15.3: Module Header word 1 */ 1691 uint32 mh2; /* T15.4: Module Header word 2 */ 1692 uint32 mh3; /* T15.5: Module Header word 3 */ 1693 #ifdef LE_HOST 1694 /* T15.6: RX Status 0 */ 1695 uint32 l3_intf:12, /* Interface from IPMC replication */ 1696 regen_crc:1, /* Regenerate CRC */ 1697 switch_pkt:1, /* Switched packet */ 1698 src_hg:1, /* Source is Higig */ 1699 purge_cell:1, /* Packet is marked Purged */ 1700 pkt_aged:1, /* Pkt is Aged */ 1701 mtp_index:7, /* Mirror-to-Port Index */ 1702 l3uc:1, /* L3 UC */ 1703 l3only:1, /* L3 only IPMC packet */ 1704 l3ipmc:1, /* L3 IPMC replicated copy */ 1705 imirror:1, /* Ingress Mirroring */ 1706 emirror:1, /* Egress Mirroring */ 1707 bpdu:1, /* BPDU Packet */ 1708 add_vid:1, /* VLAN ID Added */ 1709 do_not_change_ttl:1; /* FP indicator for L3 unicast */ 1710 1711 /* T15.7: RX Status 0 */ 1712 uint32 reason:26, /* CPU opcode */ 1713 cos:3, /* Interface from IPMC replication */ 1714 cpu_cos:3; /* CPU COS */ 1715 1716 /* T15.8: RX Status 2 */ 1717 uint32 dscp:8, /* New DSCP */ 1718 nh_index:11, /* Next hop index */ 1719 match_rule:10, /* Matched Rule */ 1720 match_rule_valid:1, /* Matched Rule valid */ 1721 chg_tos:1, /* DSCP changed */ 1722 cell_error:1; /* Cell CRC Checksum Error Detected */ 1723 1724 /* T15.9: RX Status 3 */ 1725 uint32 :8, 1726 inner_vlan_add:1, /* Inner VLAN tag added to packet */ 1727 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 1728 ingress_untagged:1, /* Pkt came in untagged */ 1729 outer_vid:12, /* VID */ 1730 outer_cfi:1, /* CFI */ 1731 outer_pri:3, /* Priority */ 1732 srcport:5; /* Source port */ 1733 #else 1734 /* T15.6: RX Status 0 */ 1735 uint32 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 1736 add_vid:1, /* VLAN ID Added */ 1737 bpdu:1, /* BPDU Packet */ 1738 emirror:1, /* Egress Mirroring */ 1739 imirror:1, /* Ingress Mirroring */ 1740 l3ipmc:1, /* L3 IPMC replicated copy */ 1741 l3only:1, /* L3 only IPMC packet */ 1742 l3uc:1, /* L3 UC */ 1743 mtp_index:7, /* Mirror-to-Port Index */ 1744 pkt_aged:1, /* Pkt is Aged */ 1745 purge_cell:1, /* Packet is marked Purged */ 1746 src_hg:1, /* Source is Higig */ 1747 switch_pkt:1, /* Switched packet */ 1748 regen_crc:1, /* Regenerate CRC */ 1749 l3_intf:12; /* Interface from IPMC replication */ 1750 /* T15.7: RX Status 1 */ 1751 uint32 cpu_cos:3, /* CPU COS */ 1752 cos:3, /* Interface from IPMC replication */ 1753 reason:26; /* CPU opcode */ 1754 /* T15.8: RX Status 2 */ 1755 uint32 cell_error:1, /* Cell CRC Checksum Error Detected */ 1756 chg_tos:1, /* DSCP changed */ 1757 match_rule_valid:1, /* Matched Rule valid */ 1758 match_rule:10, /* Matched Rule */ 1759 nh_index:11, /* Next hop index */ 1760 dscp:8; /* New DSCP */ 1761 /* T15.9: RX Status 3 */ 1762 uint32 srcport:5, /* Source port */ 1763 outer_pri:3, /* Priority (D)*/ 1764 outer_cfi:1, /* CFI (D)*/ 1765 outer_vid:12, /* VID (D)*/ 1766 ingress_untagged:1, /* Pkt came in untagged (D)*/ 1767 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 1768 inner_vlan_add:1, /* Inner VLAN tag added to packet */ 1769 :8; 1770 #endif 1771 1772 /* T15.10: DMA Status 0 */ 1773 #ifdef LE_HOST 1774 uint32 count:16, /* Transferred byte count */ 1775 end:1, /* End bit (RX) */ 1776 start:1, /* Start bit (RX) */ 1777 error:1, /* Cell Error (RX) */ 1778 dc:12, /* Don't Care */ 1779 done:1; /* Descriptor Done */ 1780 #else 1781 uint32 done:1, 1782 dc:12, 1783 error:1, 1784 start:1, 1785 end:1, 1786 count:16; 1787 #endif 1788 } dcb15_t; 1789 #endif /* BCM_RAPTOR_SUPPORT */ 1790 1791 #ifdef BCM_SCORPION_SUPPORT 1792 /* 1793 * DMA Control Block - Type 16 1794 * Used on 5661x devices 1795 * 11 words 1796 */ 1797 typedef struct { 1798 uint32 addr; /* T16.0: physical address */ 1799 /* T16.1: Control 0 */ 1800 #ifdef LE_HOST 1801 uint32 c_count:16, /* Requested byte count */ 1802 c_chain:1, /* Chaining */ 1803 c_sg:1, /* Scatter Gather */ 1804 c_reload:1, /* Reload */ 1805 c_hg:1, /* Higig (TX) */ 1806 c_stat:1, /* update stats (TX) */ 1807 c_pause:1, /* Pause packet (TX) */ 1808 c_purge:1, /* Purge packet (TX) */ 1809 :9; /* Don't care */ 1810 #else 1811 uint32 :9, /* Don't care */ 1812 c_purge:1, /* Purge packet (TX) */ 1813 c_pause:1, 1814 c_stat:1, 1815 c_hg:1, 1816 c_reload:1, 1817 c_sg:1, 1818 c_chain:1, 1819 c_count:16; 1820 #endif /* LE_HOST */ 1821 uint32 mh0; /* T16.2: Module Header word 0 */ 1822 uint32 mh1; /* T16.3: Module Header word 1 */ 1823 uint32 mh2; /* T16.4: Module Header word 2 */ 1824 uint32 mh3; /* T16.5: Module Header word 3 */ 1825 #ifdef LE_HOST 1826 /* T16.6: RX Status 0 */ 1827 uint32 cos:4, /* COS queue for non-CPU packets */ 1828 :4, /* Reserved */ 1829 cpu_cos:5, /* COS queue for CPU packets */ 1830 :3, /* Reserved */ 1831 pkt_len:14, /* Packet Length After Modification */ 1832 :2; /* Reserved */ 1833 1834 /* T16.7 */ 1835 uint32 reserved_w7; /* Reserved */ 1836 1837 /* T16.8 */ 1838 uint32 reason:32; /* CPU opcode */ 1839 1840 /* T16.9 */ 1841 uint32 dscp:8, /* New DSCP */ 1842 decap_iptunnel:1, /* IP tunnel was decapsulated */ 1843 chg_tos:1, /* DSCP has been changed by HW */ 1844 regen_crc:1, /* Packet modified and needs new CRC */ 1845 ingress_untagged:1, /* Packet came in untagged */ 1846 :4, /* Reserved */ 1847 outer_vid:12, /* Outer VLAN ID */ 1848 outer_cfi:1, /* Outer Canoncial Format Indicator */ 1849 outer_pri:3; /* Outer priority */ 1850 1851 /* T16.10 */ 1852 uint32 reserved_w10; /* Reserved */ 1853 1854 /* T16.11 */ 1855 uint32 reserved_w11; /* Reserved */ 1856 1857 /* T16.12 */ 1858 uint32 srcport:8, /* Source port number */ 1859 hgi:2, /* Higig Interface Format Indicator */ 1860 itag_status:2, /* Ingress incoming tag status */ 1861 otag_action:2, /* Ingress Outer tag action */ 1862 itag_action:2, /* Ingress Inner tag action */ 1863 switch_pkt:1, /* Switched packet */ 1864 hg_type:1, /* 0: Higig+, 1: Higig2 */ 1865 src_hg:1, /* Source is Higig */ 1866 purge_cell:1, /* Packet is marked Purged */ 1867 pkt_aged:1, /* Pkt is Aged */ 1868 l3uc:1, /* L3 UC */ 1869 l3only:1, /* L3 only IPMC packet */ 1870 l3ipmc:1, /* L3 IPMC replicated copy */ 1871 imirror:1, /* Ingress Mirroring */ 1872 emirror:1, /* Egress Mirroring */ 1873 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 1874 cell_error:1, /* Cell CRC Checksum Error Detected */ 1875 bpdu:1, /* BPDU Packet */ 1876 :3; /* Reserved */ 1877 /* T16.13 */ 1878 uint32 nh_index:13, /* Next hop index */ 1879 :3, /* Reserved */ 1880 em_mtp_index:5, /* Egress Mirror-to port */ 1881 :3, /* Reserved */ 1882 mtp_index:6, /* Ingress Mirror-to port */ 1883 :2; /* Reserved */ 1884 1885 /* T16.14 */ 1886 uint32 l3_intf:12, /* L3 Intf number */ 1887 :4, /* Reserved */ 1888 match_rule:8, /* Matched FP rule */ 1889 :8; /* Reserved */ 1890 1891 /* T16.15: DMA Status 0 */ 1892 uint32 count:16, /* Transferred byte count */ 1893 end:1, /* End bit (RX) */ 1894 start:1, /* Start bit (RX) */ 1895 error:1, /* Cell Error (RX) */ 1896 dc:12, /* Don't Care */ 1897 done:1; /* Descriptor Done */ 1898 #else 1899 /* T16.6: RX Status 0 */ 1900 uint32 :2, /* Reserved */ 1901 pkt_len:14, /* Packet Length After Modification */ 1902 :3, /* Reserved */ 1903 cpu_cos:5, /* COS queue for CPU packets */ 1904 :4, /* Reserved */ 1905 cos:4; /* COS queue for non-CPU packets */ 1906 1907 /* T16.7 */ 1908 uint32 reserved_w7; /* Reserved */ 1909 1910 /* T16.8 */ 1911 uint32 reason:32; /* CPU opcode */ 1912 1913 /* T16.9 */ 1914 uint32 outer_pri:3, /* Outer priority */ 1915 outer_cfi:1, /* Outer Canoncial Format Indicator */ 1916 outer_vid:12, /* Outer VLAN ID */ 1917 :4, /* Reserved */ 1918 ingress_untagged:1, /* Packet came in untagged */ 1919 regen_crc:1, /* Packet modified and needs new CRC */ 1920 chg_tos:1, /* DSCP has been changed by HW */ 1921 decap_iptunnel:1, /* IP tunnel was decapsulated */ 1922 dscp:8; /* New DSCP */ 1923 1924 /* T16.10 */ 1925 uint32 reserved_w10; /* Reserved */ 1926 1927 /* T16.11 */ 1928 uint32 reserved_w11; /* Reserved */ 1929 1930 /* T16.12 */ 1931 uint32 :3, /* Reserved */ 1932 bpdu:1, /* BPDU Packet */ 1933 cell_error:1, /* Cell CRC Checksum Error Detected */ 1934 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 1935 emirror:1, /* Egress Mirroring */ 1936 imirror:1, /* Ingress Mirroring */ 1937 l3ipmc:1, /* L3 IPMC replicated copy */ 1938 l3only:1, /* L3 only IPMC packet */ 1939 l3uc:1, /* L3 UC */ 1940 pkt_aged:1, /* Pkt is Aged */ 1941 purge_cell:1, /* Packet is marked Purged */ 1942 src_hg:1, /* Source is Higig */ 1943 hg_type:1, /* 0: Higig+, 1: Higig2 */ 1944 switch_pkt:1, /* Switched packet */ 1945 itag_action:2, /* Ingress Inner tag action */ 1946 otag_action:2, /* Ingress Outer tag action */ 1947 itag_status:2, /* Ingress incoming tag status */ 1948 hgi:2, /* Higig Interface Format Indicator */ 1949 srcport:8; /* Source port number */ 1950 1951 /* T16.13 */ 1952 uint32 :2, /* Reserved */ 1953 mtp_index:6, /* Ingress Mirror-to port */ 1954 :3, /* Reserved */ 1955 em_mtp_index:5, /* Egress Mirror-to port */ 1956 :3, /* Reserved */ 1957 nh_index:13; /* Next hop index */ 1958 1959 /* T16.14 */ 1960 uint32 :8, /* Reserved */ 1961 match_rule:8, /* Matched FP rule */ 1962 :4, /* Reserved */ 1963 l3_intf:12; /* L3 Intf number */ 1964 1965 /* T16.15: DMA Status 0 */ 1966 uint32 done:1, /* Descriptor Done */ 1967 dc:12, /* Don't Care */ 1968 error:1, /* Cell Error (RX) */ 1969 start:1, /* Start bit (RX) */ 1970 end:1, /* End bit (RX) */ 1971 count:16; /* Transferred byte count */ 1972 #endif 1973 } dcb16_t; 1974 #endif /* BCM_SCORPION_SUPPORT */ 1975 1976 #ifdef BCM_HAWKEYE_SUPPORT 1977 /* 1978 * DMA Control Block - Type 17 1979 * Used on 53314 devices 1980 * 11 words 1981 */ 1982 typedef struct { 1983 uint32 addr; /* T17.0: physical address */ 1984 /* T17.1: Control 0 */ 1985 #ifdef LE_HOST 1986 uint32 c_count:16, /* Requested byte count */ 1987 c_chain:1, /* Chaining */ 1988 c_sg:1, /* Scatter Gather */ 1989 c_reload:1, /* Reload */ 1990 c_hg:1, /* Higig (TX) */ 1991 c_stat:1, /* Reserved (TX) */ 1992 c_pause:1, /* Reserved (TX) */ 1993 c_purge:1, /* Purge packet (TX) */ 1994 :9; /* Don't care */ 1995 #else 1996 uint32 :9, /* Don't care */ 1997 c_purge:1, /* Purge packet (TX) */ 1998 c_pause:1, 1999 c_stat:1, 2000 c_hg:1, 2001 c_reload:1, 2002 c_sg:1, 2003 c_chain:1, 2004 c_count:16; 2005 #endif /* LE_HOST */ 2006 uint32 mh0; /* Only for PBSMH word 0 */ 2007 uint32 mh1; /* Only for PBSMH word 1 */ 2008 uint32 mh2; /* Only for PBSMH word 2 */ 2009 uint32 mh3; /* Used for PBSMH word 3 and Timestamp for EAV packets in rx */ 2010 #ifdef LE_HOST 2011 /* T17.6: RX Status 0 */ 2012 uint32 l3_intf:12, /* Interface from IPMC replication */ 2013 regen_crc:1, /* Regenerate CRC */ 2014 switch_pkt:1, /* Switched packet */ 2015 src_hg:1, /* Source is Higig */ 2016 purge_cell:1, /* Packet is marked Purged */ 2017 pkt_aged:1, /* Pkt is Aged */ 2018 mtp_index:7, /* Mirror-to-Port Index */ 2019 l3uc:1, /* L3 UC */ 2020 l3only:1, /* L3 only IPMC packet */ 2021 l3ipmc:1, /* L3 IPMC replicated copy */ 2022 imirror:1, /* Ingress Mirroring */ 2023 emirror:1, /* Egress Mirroring */ 2024 bpdu:1, /* BPDU Packet */ 2025 add_vid:1, /* VLAN ID Added */ 2026 do_not_change_ttl:1; /* FP indicator for L3 unicast */ 2027 2028 /* T17.7: RX Status 0 */ 2029 uint32 reason:28, /* CPU opcode */ 2030 reserved_0:1, /* Reserved */ 2031 cpu_cos:3; /* CPU COS */ 2032 2033 /* T17.8: RX Status 2 */ 2034 uint32 dscp:8, /* New DSCP */ 2035 nh_index:11, /* Next hop index */ 2036 match_rule:10, /* Matched Rule */ 2037 match_rule_valid:1, /* Matched Rule valid */ 2038 chg_tos:1, /* DSCP changed */ 2039 cell_error:1; /* Cell CRC Checksum Error Detected */ 2040 2041 /* T17.9: RX Status 3 */ 2042 uint32 :8, 2043 inner_vlan_add:1, /* Inner VLAN tag added to packet */ 2044 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 2045 ingress_untagged:1, /* Pkt came in untagged */ 2046 outer_vid:12, /* VID */ 2047 outer_cfi:1, /* CFI */ 2048 outer_pri:3, /* Priority */ 2049 srcport:5; /* Source port */ 2050 #else 2051 /* T17.6: RX Status 0 */ 2052 uint32 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 2053 add_vid:1, /* VLAN ID Added */ 2054 bpdu:1, /* BPDU Packet */ 2055 emirror:1, /* Egress Mirroring */ 2056 imirror:1, /* Ingress Mirroring */ 2057 l3ipmc:1, /* L3 IPMC replicated copy */ 2058 l3only:1, /* L3 only IPMC packet */ 2059 l3uc:1, /* L3 UC */ 2060 mtp_index:7, /* Mirror-to-Port Index */ 2061 pkt_aged:1, /* Pkt is Aged */ 2062 purge_cell:1, /* Packet is marked Purged */ 2063 src_hg:1, /* Source is Higig */ 2064 switch_pkt:1, /* Switched packet */ 2065 regen_crc:1, /* Regenerate CRC */ 2066 l3_intf:12; /* Interface from IPMC replication */ 2067 /* T17.7: RX Status 1 */ 2068 uint32 cpu_cos:3, /* CPU COS */ 2069 reserved_0:1, /* Reserved */ 2070 reason:28; /* CPU opcode */ 2071 /* T17.8: RX Status 2 */ 2072 uint32 cell_error:1, /* Cell CRC Checksum Error Detected */ 2073 chg_tos:1, /* DSCP changed */ 2074 match_rule_valid:1, /* Matched Rule valid */ 2075 match_rule:10, /* Matched Rule */ 2076 nh_index:11, /* Next hop index */ 2077 dscp:8; /* New DSCP */ 2078 /* T17.9: RX Status 3 */ 2079 uint32 srcport:5, /* Source port */ 2080 outer_pri:3, /* Priority (D)*/ 2081 outer_cfi:1, /* CFI (D)*/ 2082 outer_vid:12, /* VID (D)*/ 2083 ingress_untagged:1, /* Pkt came in untagged (D)*/ 2084 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 2085 inner_vlan_add:1, /* Inner VLAN tag added to packet */ 2086 :8; 2087 #endif 2088 2089 /* T17.10: DMA Status 0 */ 2090 #ifdef LE_HOST 2091 uint32 count:16, /* Transferred byte count */ 2092 end:1, /* End bit (RX) */ 2093 start:1, /* Start bit (RX) */ 2094 error:1, /* Cell Error (RX) */ 2095 dc:12, /* Don't Care */ 2096 done:1; /* Descriptor Done */ 2097 #else 2098 uint32 done:1, 2099 dc:12, 2100 error:1, 2101 start:1, 2102 end:1, 2103 count:16; 2104 #endif 2105 } dcb17_t; 2106 #endif /* BCM_HAWKEYE_SUPPORT */ 2107 2108 #ifdef BCM_RAPTOR_SUPPORT 2109 /* 2110 * DMA Control Block - Type 18 2111 * Used on 56224_B0 devices 2112 * 11 words 2113 */ 2114 typedef struct { 2115 uint32 addr; /* T18.0: physical address */ 2116 /* T18.1: Control 0 */ 2117 #ifdef LE_HOST 2118 uint32 c_count:16, /* Requested byte count */ 2119 c_chain:1, /* Chaining */ 2120 c_sg:1, /* Scatter Gather */ 2121 c_reload:1, /* Reload */ 2122 c_hg:1, /* Higig (TX) */ 2123 c_stat:1, /* Reserved (TX) */ 2124 c_pause:1, /* Reserved (TX) */ 2125 c_purge:1, /* Purge packet (TX) */ 2126 :9; /* Don't care */ 2127 #else 2128 uint32 :9, /* Don't care */ 2129 c_purge:1, /* Purge packet (TX) */ 2130 c_pause:1, 2131 c_stat:1, 2132 c_hg:1, 2133 c_reload:1, 2134 c_sg:1, 2135 c_chain:1, 2136 c_count:16; 2137 #endif /* LE_HOST */ 2138 uint32 mh0; /* T18.2: Module Header word 0 */ 2139 uint32 mh1; /* T18.3: Module Header word 1 */ 2140 uint32 mh2; /* T18.4: Module Header word 2 */ 2141 uint32 mh3; /* T18.5: Module Header word 3 */ 2142 #ifdef LE_HOST 2143 /* T18.6: RX Status 0 */ 2144 uint32 l3_intf:12, /* Interface from IPMC replication */ 2145 regen_crc:1, /* Regenerate CRC */ 2146 switch_pkt:1, /* Switched packet */ 2147 src_hg:1, /* Source is Higig */ 2148 purge_cell:1, /* Packet is marked Purged */ 2149 pkt_aged:1, /* Pkt is Aged */ 2150 mtp_index:7, /* Mirror-to-Port Index */ 2151 l3uc:1, /* L3 UC */ 2152 l3only:1, /* L3 only IPMC packet */ 2153 l3ipmc:1, /* L3 IPMC replicated copy */ 2154 imirror:1, /* Ingress Mirroring */ 2155 emirror:1, /* Egress Mirroring */ 2156 bpdu:1, /* BPDU Packet */ 2157 add_vid:1, /* VLAN ID Added */ 2158 do_not_change_ttl:1; /* FP indicator for L3 unicast */ 2159 2160 /* T18.7: RX Status 0 */ 2161 uint32 reason:26, /* CPU opcode */ 2162 cos:3, /* Interface from IPMC replication */ 2163 cpu_cos:3; /* CPU COS */ 2164 2165 /* T18.8: RX Status 2 */ 2166 uint32 dscp:8, /* New DSCP */ 2167 nh_index:12, /* Next hop index */ 2168 match_rule:10, /* Matched Rule */ 2169 match_rule_valid:1, /* Matched Rule valid */ 2170 cell_error:1; /* Cell CRC Checksum Error Detected */ 2171 2172 /* T18.9: RX Status 3 */ 2173 uint32 :7, 2174 chg_tos:1, /* DSCP changed */ 2175 inner_vlan_add:1, /* Inner VLAN tag added to packet */ 2176 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 2177 ingress_untagged:1, /* Pkt came in untagged */ 2178 outer_vid:12, /* VID */ 2179 outer_cfi:1, /* CFI */ 2180 outer_pri:3, /* Priority */ 2181 srcport:5; /* Source port */ 2182 #else 2183 /* T18.6: RX Status 0 */ 2184 uint32 do_not_change_ttl:1, /* FP indicator for L3 unicast */ 2185 add_vid:1, /* VLAN ID Added */ 2186 bpdu:1, /* BPDU Packet */ 2187 emirror:1, /* Egress Mirroring */ 2188 imirror:1, /* Ingress Mirroring */ 2189 l3ipmc:1, /* L3 IPMC replicated copy */ 2190 l3only:1, /* L3 only IPMC packet */ 2191 l3uc:1, /* L3 UC */ 2192 mtp_index:7, /* Mirror-to-Port Index */ 2193 pkt_aged:1, /* Pkt is Aged */ 2194 purge_cell:1, /* Packet is marked Purged */ 2195 src_hg:1, /* Source is Higig */ 2196 switch_pkt:1, /* Switched packet */ 2197 regen_crc:1, /* Regenerate CRC */ 2198 l3_intf:12; /* Interface from IPMC replication */ 2199 /* T18.7: RX Status 1 */ 2200 uint32 cpu_cos:3, /* CPU COS */ 2201 cos:3, /* Interface from IPMC replication */ 2202 reason:26; /* CPU opcode */ 2203 /* T18.8: RX Status 2 */ 2204 uint32 cell_error:1, /* Cell CRC Checksum Error Detected */ 2205 match_rule_valid:1, /* Matched Rule valid */ 2206 match_rule:10, /* Matched Rule */ 2207 nh_index:12, /* Next hop index */ 2208 dscp:8; /* New DSCP */ 2209 /* T18.9: RX Status 3 */ 2210 uint32 srcport:5, /* Source port */ 2211 outer_pri:3, /* Priority (D)*/ 2212 outer_cfi:1, /* CFI (D)*/ 2213 outer_vid:12, /* VID (D)*/ 2214 ingress_untagged:1, /* Pkt came in untagged (D)*/ 2215 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 2216 inner_vlan_add:1, /* Inner VLAN tag added to packet */ 2217 chg_tos:1, /* DSCP changed */ 2218 :7; 2219 #endif 2220 2221 /* T18.10: DMA Status 0 */ 2222 #ifdef LE_HOST 2223 uint32 count:16, /* Transferred byte count */ 2224 end:1, /* End bit (RX) */ 2225 start:1, /* Start bit (RX) */ 2226 error:1, /* Cell Error (RX) */ 2227 dc:12, /* Don't Care */ 2228 done:1; /* Descriptor Done */ 2229 #else 2230 uint32 done:1, 2231 dc:12, 2232 error:1, 2233 start:1, 2234 end:1, 2235 count:16; 2236 #endif 2237 } dcb18_t; 2238 #endif /* BCM_RAPTOR_SUPPORT */ 2239 2240 #if defined(BCM_TRIUMPH2_SUPPORT) || defined(BCM_SHADOW_SUPPORT) 2241 /* 2242 * DMA Control Block - Type 19 2243 * Used on 5663x devices 2244 * 16 words 2245 */ 2246 #include <soc/shared/dcbformats/type19.h> 2247 #endif /* BCM_TRIUMPH2_SUPPORT */ 2248 2249 #if defined(BCM_ENDURO_SUPPORT) 2250 /* 2251 * DMA Control Block - Type 20 2252 * Used on 5623x devices 2253 * 16 words 2254 */ 2255 typedef struct { 2256 uint32 addr; /* T20.0: physical address */ 2257 /* T20.1: Control 0 */ 2258 #ifdef LE_HOST 2259 uint32 c_count:16, /* Requested byte count */ 2260 c_chain:1, /* Chaining */ 2261 c_sg:1, /* Scatter Gather */ 2262 c_reload:1, /* Reload */ 2263 c_hg:1, /* Higig (TX) */ 2264 c_stat:1, /* update stats (TX) */ 2265 c_pause:1, /* Pause packet (TX) */ 2266 c_purge:1, /* Purge packet (TX) */ 2267 :9; /* Don't care */ 2268 #else 2269 uint32 :9, /* Don't care */ 2270 c_purge:1, /* Purge packet (TX) */ 2271 c_pause:1, 2272 c_stat:1, 2273 c_hg:1, 2274 c_reload:1, 2275 c_sg:1, 2276 c_chain:1, 2277 c_count:16; 2278 #endif /* LE_HOST */ 2279 uint32 mh0; /* T20.2: Module Header word 0 */ 2280 uint32 mh1; /* T20.3: Module Header word 1 */ 2281 uint32 mh2; /* T20.4: Module Header word 2 */ 2282 uint32 mh3; /* T20.5: Module Header word 3 */ 2283 #ifdef LE_HOST 2284 /* T20.6: RX Status 0 */ 2285 uint32 timestamp_type:2, /* TIMESTAMP field type indicator */ 2286 em_mtp_index:5, /* EM Mirror-to-Port Index */ 2287 :1, /* Reserved */ 2288 cpu_cos:6, /* COS queue for CPU packets */ 2289 :2, /* Reserved */ 2290 inner_vid:12, /* Inner VLAN ID */ 2291 inner_cfi:1, /* Inner Canoncial Format Indicator */ 2292 inner_pri:3; /* Inner priority */ 2293 2294 /* T20.7 */ 2295 uint32 reason_hi:16, /* CPU opcode (high bits) */ 2296 pkt_len:14, /* Packet Length After Modification */ 2297 :2; /* Reserved */ 2298 2299 /* T20.8 */ 2300 uint32 reason; /* CPU opcode */ 2301 2302 /* T20.9 */ 2303 uint32 dscp:8, /* New DSCP */ 2304 chg_tos:1, /* DSCP has been changed by HW */ 2305 decap_tunnel_type:4, /* Tunnel type that was decapsulated */ 2306 regen_crc:1, /* Packet modified and needs new CRC */ 2307 :2, /* Reserved */ 2308 outer_vid:12, /* Outer VLAN ID */ 2309 outer_cfi:1, /* Outer Canoncial Format Indicator */ 2310 outer_pri:3; /* Outer priority */ 2311 2312 /* T20.10 */ 2313 uint32 timestamp; /* Timestamp */ 2314 2315 /* T20.11 */ 2316 uint32 cos:4, /* COS */ 2317 higig_cos:5, /* Higig COS */ 2318 vlan_cos:5, /* VLAN COS */ 2319 shaping_cos_sel:2, /* Shaping COS Select */ 2320 vfi:12, /* Internal VFI or FID value */ 2321 vfi_valid:1, /* VFI or FID */ 2322 :3; /* Reserved */ 2323 2324 /* T20.12 */ 2325 uint32 srcport:8, /* Source port number */ 2326 hgi:2, /* Higig Interface Format Indicator */ 2327 itag_status:2, /* Ingress incoming tag status */ 2328 otag_action:2, /* Ingress Outer tag action */ 2329 itag_action:2, /* Ingress Inner tag action */ 2330 service_tag:1, /* SD tag present */ 2331 switch_pkt:1, /* Switched packet */ 2332 hg_type:1, /* 0: Higig+, 1: Higig2 */ 2333 src_hg:1, /* Source is Higig */ 2334 l3routed:1, /* Any IP routed packet */ 2335 l3only:1, /* L3 only IPMC packet */ 2336 replicated:1, /* Replicated copy */ 2337 imirror:1, /* Ingress Mirroring */ 2338 emirror:1, /* Egress Mirroring */ 2339 do_not_change_ttl:1, /* Do not change TTL */ 2340 bpdu:1, /* BPDU Packet */ 2341 hg_lookup:1, /* Reserved for future use */ 2342 :4; /* Reserved */ 2343 2344 /* T20.13 */ 2345 uint32 nhop_index:15, /* L3 IP Multicast Interface Number or Next HOP Index */ 2346 :1, /* Reserved */ 2347 match_rule:8, /* Matched FP rule */ 2348 im_mtp_index:5, /* IM Mirror-to-Port Index */ 2349 ecn:2, /* Reserved */ 2350 change_ecn:1; /* Reserved */ 2351 2352 /* T20.14 */ 2353 uint32 timestamp_upper; /* OAM delay measurement: Upper 32-bit of 64-bit timestamp */ 2354 2355 /* T20.15: DMA Status 0 */ 2356 uint32 count:16, /* Transferred byte count */ 2357 end:1, /* End bit (RX) */ 2358 start:1, /* Start bit (RX) */ 2359 error:1, /* Cell Error (RX) */ 2360 dc:12, /* Don't Care */ 2361 done:1; /* Descriptor Done */ 2362 #else 2363 /* T20.6: RX Status 0 */ 2364 uint32 inner_pri:3, /* Inner priority */ 2365 inner_cfi:1, /* Inner Canoncial Format Indicator */ 2366 inner_vid:12, /* Inner VLAN ID */ 2367 :2, /* Reserved */ 2368 cpu_cos:6, /* COS queue for CPU packets */ 2369 :1, /* Reserved */ 2370 em_mtp_index:5, /* EM Mirror-to-Port Index */ 2371 timestamp_type:2; /* TIMESTAMP field type indicator */ 2372 2373 /* T20.7 */ 2374 uint32 :2, /* Reserved */ 2375 pkt_len:14, /* Packet Length After Modification */ 2376 reason_hi:16; /* CPU opcode (high bits) */ 2377 2378 /* T20.8 */ 2379 uint32 reason; /* CPU opcode */ 2380 2381 /* T20.9 */ 2382 uint32 outer_pri:3, /* Outer priority */ 2383 outer_cfi:1, /* Outer Canoncial Format Indicator */ 2384 outer_vid:12, /* Outer VLAN ID */ 2385 :2, /* Reserved */ 2386 regen_crc:1, /* Packet modified and needs new CRC */ 2387 decap_tunnel_type:4, /* Tunnel type that was decapsulated */ 2388 chg_tos:1, /* DSCP has been changed by HW */ 2389 dscp:8; /* New DSCP */ 2390 2391 /* T20.10 */ 2392 uint32 timestamp; /* Timestamp */ 2393 2394 /* T20.11 */ 2395 uint32 :3, /* Reserved */ 2396 vfi_valid:1, /* VFI or FID */ 2397 vfi:12, /* Internal VFI or FID value */ 2398 shaping_cos_sel:2, /* Shaping COS Select */ 2399 vlan_cos:5, /* VLAN COS */ 2400 higig_cos:5, /* Higig COS */ 2401 cos:4; /* COS */ 2402 2403 /* T20.12 */ 2404 uint32 :4, /* Reserved */ 2405 hg_lookup:1, /* Reserved for future use */ 2406 bpdu:1, /* BPDU Packet */ 2407 do_not_change_ttl:1, /* Do not change TTL */ 2408 emirror:1, /* Egress Mirroring */ 2409 imirror:1, /* Ingress Mirroring */ 2410 replicated:1, /* Replicated copy */ 2411 l3only:1, /* L3 only IPMC packet */ 2412 l3routed:1, /* Any IP routed packet */ 2413 src_hg:1, /* Source is Higig */ 2414 hg_type:1, /* 0: Higig+, 1: Higig2 */ 2415 switch_pkt:1, /* Switched packet */ 2416 service_tag:1, /* SD tag present */ 2417 itag_action:2, /* Ingress Inner tag action */ 2418 otag_action:2, /* Ingress Outer tag action */ 2419 itag_status:2, /* Ingress incoming tag status */ 2420 hgi:2, /* Higig Interface Format Indicator */ 2421 srcport:8; /* Source port number */ 2422 2423 /* T20.13 */ 2424 uint32 change_ecn:1, /* Reserved */ 2425 ecn:2, /* Reserved */ 2426 im_mtp_index:5, /* IM Mirror-to-Port Index */ 2427 match_rule:8, /* Matched FP rule */ 2428 :1, /* Reserved */ 2429 nhop_index:15; /* L3 IP Multicast Interface Number or Next HOP Index */ 2430 2431 /* T20.14 */ 2432 uint32 timestamp_upper; /* OAM delay measurement: Upper 32-bit of 64-bit timestamp */ 2433 2434 /* T20.15: DMA Status 0 */ 2435 uint32 done:1, /* Descriptor Done */ 2436 dc:12, /* Don't Care */ 2437 error:1, /* Cell Error (RX) */ 2438 start:1, /* Start bit (RX) */ 2439 end:1, /* End bit (RX) */ 2440 count:16; /* Transferred byte count */ 2441 #endif 2442 } dcb20_t; 2443 #endif /* BCM_ENDURO_SUPPORT */ 2444 2445 #if defined(BCM_TRIDENT_SUPPORT) 2446 /* 2447 * DMA Control Block - Type 21 2448 * Used on 56840 devices 2449 * 16 words 2450 */ 2451 typedef struct { 2452 uint32 addr; /* T21.0: physical address */ 2453 /* T21.1: Control 0 */ 2454 #ifdef LE_HOST 2455 uint32 c_count:16, /* Requested byte count */ 2456 c_chain:1, /* Chaining */ 2457 c_sg:1, /* Scatter Gather */ 2458 c_reload:1, /* Reload */ 2459 c_hg:1, /* Higig (TX) */ 2460 c_stat:1, /* Update stats (TX) */ 2461 c_pause:1, /* Pause packet (TX) */ 2462 c_purge:1, /* Purge packet (TX) */ 2463 :9; /* Don't care */ 2464 #else 2465 uint32 :9, /* Don't care */ 2466 c_purge:1, /* Purge packet (TX) */ 2467 c_pause:1, /* Pause packet (TX) */ 2468 c_stat:1, /* Update stats (TX) */ 2469 c_hg:1, /* Higig (TX) */ 2470 c_reload:1, /* Reload */ 2471 c_sg:1, /* Scatter Gather */ 2472 c_chain:1, /* Chaining */ 2473 c_count:16; /* Requested byte count */ 2474 #endif /* LE_HOST */ 2475 uint32 mh0; /* T21.2: Module Header word 0 */ 2476 uint32 mh1; /* T21.3: Module Header word 1 */ 2477 uint32 mh2; /* T21.4: Module Header word 2 */ 2478 uint32 mh3; /* T21.5: Module Header word 3 */ 2479 #ifdef LE_HOST 2480 /* T21.6 */ 2481 uint32 :3, /* Reserved */ 2482 mtp_index:5, /* MTP index */ 2483 cpu_cos:8, /* Queue number for CPU packets */ 2484 inner_vid:12, /* Inner VLAN ID */ 2485 inner_cfi:1, /* Inner Canoncial Format Indicator */ 2486 inner_pri:3; /* Inner priority */ 2487 2488 /* T21.7 */ 2489 uint32 reason_hi:16, /* CPU opcode (high bits) */ 2490 pkt_len:14, /* Packet length */ 2491 :2; /* Reserved */ 2492 2493 /* T21.8 */ 2494 uint32 reason; /* CPU opcode (low bits) */ 2495 2496 /* T21.9 */ 2497 uint32 dscp:6, /* New DSCP */ 2498 :2, /* Reserved */ 2499 chg_tos:1, /* DSCP has been changed by HW */ 2500 decap_tunnel_type:4, /* Tunnel type that was decapsulated */ 2501 regen_crc:1, /* Packet modified and needs new CRC */ 2502 :2, /* Reserved */ 2503 outer_vid:12, /* Outer VLAN ID */ 2504 outer_cfi:1, /* Outer Canoncial Format Indicator */ 2505 outer_pri:3; /* Outer priority */ 2506 2507 /* T21.10 */ 2508 uint32 timestamp; /* Timestamp */ 2509 2510 /* T21.11 */ 2511 uint32 :12, /* Reserved */ 2512 ecn:2, /* New ECN value */ 2513 chg_ecn:1, /* ECN changed */ 2514 mcq:1, /* Multicast queue indicator */ 2515 vfi:12, /* Internal VFI value */ 2516 vfi_valid:1, /* Validates VFI field */ 2517 dvp_nhi_sel:1, /* DVP overlay indicator */ 2518 vntag_action:2; /* VN tag action */ 2519 2520 /* T21.12 */ 2521 uint32 srcport:8, /* Source port number */ 2522 hgi:2, /* Higig Interface Format Indicator */ 2523 itag_status:2, /* Ingress Inner tag status */ 2524 otag_action:2, /* Ingress Outer tag action */ 2525 itag_action:2, /* Ingress Inner tag action */ 2526 service_tag:1, /* SD tag present */ 2527 switch_pkt:1, /* Switched packet */ 2528 hg_type:1, /* 0: Higig+, 1: Higig2 */ 2529 src_hg:1, /* Source is Higig */ 2530 l3routed:1, /* Any IP routed packet */ 2531 l3only:1, /* L3 only IPMC packet */ 2532 replicated:1, /* Replicated copy */ 2533 :2, /* Reserved */ 2534 do_not_change_ttl:1, /* Do not change TTL */ 2535 bpdu:1, /* BPDU Packet */ 2536 :5; /* Reserved */ 2537 2538 /* T21.13 */ 2539 uint32 uc_cos:4, /* COS value for unicast packet */ 2540 eh_seg_sel:3, /* Extended Higig Seg Sel*/ 2541 next_pass_cp:2, /* Next pass code point */ 2542 oam_pkt:1, /* OAM packet */ 2543 :2, /* Reserved */ 2544 eh_tag_type:2, /* Extended Higig tag type */ 2545 eh_tm:1, /* Extended Higig traffic mgr ctrl */ 2546 eh_queue_tag:16, /* Extended Higig queue tag */ 2547 hg2_ext_hdr:1; /* Extended Higig2 header valid */ 2548 2549 /* T21.14 */ 2550 uint32 l3_intf:15, /* L3 Intf num / Next hop idx */ 2551 all_switch_drop:1, /* All switched copies dropped */ 2552 match_rule:8, /* Matched FP rule */ 2553 mc_cos2:4, /* COS2 value for multicast packets */ 2554 mc_cos1:4; /* COS1 value for multicast packets */ 2555 2556 /* T21.15: DMA Status 0 */ 2557 uint32 count:16, /* Transferred byte count */ 2558 end:1, /* End bit (RX) */ 2559 start:1, /* Start bit (RX) */ 2560 error:1, /* Cell Error (RX) */ 2561 :12, /* Reserved */ 2562 done:1; /* Descriptor Done */ 2563 #else 2564 /* T21.6 */ 2565 uint32 inner_pri:3, /* Inner priority */ 2566 inner_cfi:1, /* Inner Canoncial Format Indicator */ 2567 inner_vid:12, /* Inner VLAN ID */ 2568 cpu_cos:8, /* Queue number for CPU packets */ 2569 mtp_index:5, /* MTP index */ 2570 :3; /* Reserved */ 2571 2572 /* T21.7 */ 2573 uint32 :2, /* Reserved */ 2574 pkt_len:14, /* Packet length */ 2575 reason_hi:16; /* CPU opcode (high bits) */ 2576 2577 /* T21.8 */ 2578 uint32 reason; /* CPU opcode (low bits) */ 2579 2580 /* T21.9 */ 2581 uint32 outer_pri:3, /* Outer priority */ 2582 outer_cfi:1, /* Outer Canoncial Format Indicator */ 2583 outer_vid:12, /* Outer VLAN ID */ 2584 :2, /* Reserved */ 2585 regen_crc:1, /* Packet modified and needs new CRC */ 2586 decap_tunnel_type:4, /* Tunnel type that was decapsulated */ 2587 chg_tos:1, /* DSCP has been changed by HW */ 2588 :2, /* Reserved */ 2589 dscp:6; /* New DSCP */ 2590 2591 /* T21.10 */ 2592 uint32 timestamp; /* Timestamp */ 2593 2594 /* T21.11 */ 2595 uint32 vntag_action:2, /* VN tag action */ 2596 dvp_nhi_sel:1, /* DVP overlay indicator */ 2597 vfi_valid:1, /* Validates VFI field */ 2598 vfi:12, /* Internal VFI value */ 2599 mcq:1, /* Multicast queue indicator */ 2600 chg_ecn:1, /* ECN changed */ 2601 ecn:2, /* New ECN value */ 2602 :12, /* Reserved */ 2603 2604 /* T21.12 */ 2605 uint32 :5, /* Reserved */ 2606 bpdu:1, /* BPDU Packet */ 2607 do_not_change_ttl:1, /* Do not change TTL */ 2608 :2, /* Reserved */ 2609 replicated:1, /* Replicated copy */ 2610 l3only:1, /* L3 only IPMC packet */ 2611 l3routed:1, /* Any IP routed packet */ 2612 src_hg:1, /* Source is Higig */ 2613 hg_type:1, /* 0: Higig+, 1: Higig2 */ 2614 switch_pkt:1, /* Switched packet */ 2615 service_tag:1, /* SD tag present */ 2616 itag_action:2, /* Ingress Inner tag action */ 2617 otag_action:2, /* Ingress Outer tag action */ 2618 itag_status:2, /* Ingress Inner tag status */ 2619 hgi:2, /* Higig Interface Format Indicator */ 2620 srcport:8; /* Source port number */ 2621 2622 /* T21.13 */ 2623 uint32 hg2_ext_hdr:1, /* Extended Higig2 header valid */ 2624 eh_queue_tag:16, /* Extended Higig queue tag */ 2625 eh_tm:1, /* Extended Higig traffic mgr ctrl */ 2626 eh_tag_type:2, /* Extended Higig tag type */ 2627 :2, /* Reserved */ 2628 oam_pkt:1, /* OAM packet */ 2629 next_pass_cp:2, /* Next pass code point */ 2630 eh_seg_sel:3, /* Extended Higig Seg Sel*/ 2631 uc_cos:4; /* COS value for unicast packet */ 2632 2633 /* T21.14 */ 2634 uint32 mc_cos1:4, /* COS1 value for multicast packets */ 2635 mc_cos2:4, /* COS2 value for multicast packets */ 2636 match_rule:8, /* Matched FP rule */ 2637 all_switch_drop:1, /* All switched copies dropped */ 2638 l3_intf:15; /* L3 Intf num / Next hop idx */ 2639 2640 /* T21.15: DMA Status 0 */ 2641 uint32 done:1, /* Descriptor Done */ 2642 :12, /* Reserved */ 2643 error:1, /* Cell Error (RX) */ 2644 start:1, /* Start bit (RX) */ 2645 end:1, /* End bit (RX) */ 2646 count:16; /* Transferred byte count */ 2647 #endif 2648 } dcb21_t; 2649 #endif /* BCM_TRIDENT_SUPPORT */ 2650 2651 #ifdef BCM_SHADOW_SUPPORT 2652 /* 2653 * DMA Control Block - Type 22 2654 * Used on 88732 devices 2655 * 11 words 2656 */ 2657 typedef struct { 2658 uint32 addr; /* T22.0: physical address */ 2659 /* T22.1: Control 0 */ 2660 #ifdef LE_HOST 2661 uint32 c_count:16, /* Requested byte count */ 2662 c_chain:1, /* Chaining */ 2663 c_sg:1, /* Scatter Gather */ 2664 c_reload:1, /* Reload */ 2665 c_hg:1, /* Higig (TX) */ 2666 c_stat:1, /* update stats (TX) */ 2667 c_pause:1, /* Pause packet (TX) */ 2668 c_purge:1, /* Purge packet (TX) */ 2669 :9; /* Don't care */ 2670 #else 2671 uint32 :9, /* Don't care */ 2672 c_purge:1, /* Purge packet (TX) */ 2673 c_pause:1, 2674 c_stat:1, 2675 c_hg:1, 2676 c_reload:1, 2677 c_sg:1, 2678 c_chain:1, 2679 c_count:16; 2680 #endif /* LE_HOST */ 2681 uint32 mh0; /* T22.2: Module Header word 0 */ 2682 uint32 mh1; /* T22.3: Module Header word 1 */ 2683 uint32 mh2; /* T22.4: Module Header word 2 */ 2684 uint32 mh3; /* T22.5: Module Header word 3 */ 2685 #ifdef LE_HOST 2686 /* T22.6: RX Status 0 */ 2687 uint32 :6, /* Reserved */ 2688 dscp:8, /* DSCP */ 2689 chg_tos:1, /* DSCP changed */ 2690 regen_crc:1, /* CRC to be regenerated */ 2691 ingress_untagged:1, /* Packet came in untagged */ 2692 :2, /* Reserved */ 2693 src_port_mode:3, /* Source port mode */ 2694 :10; /* Reserved */ 2695 2696 /* T22.7 */ 2697 uint32 reason:16, /* CPU opcode */ 2698 pkt_len:14, /* Packet length */ 2699 :2; /* Reserved */ 2700 2701 /* T22.8 */ 2702 uint32 :8, /* Reserved */ 2703 outer_vid:12, /* Outer VID (EP) */ 2704 outer_cfi:1, /* Outer CFI (EP) */ 2705 outer_pri:3, /* Outer pri (EP) */ 2706 match_rule:8; /* Matched rule */ 2707 2708 /* T22.9 */ 2709 uint32 :19, /* Reserved */ 2710 msec_no_error:1, /* MACSEC no error */ 2711 msec_replay_error:1, /* MACSEC replay error */ 2712 mirror:1, /* Mirrored copy */ 2713 bpdu:1, /* BPDU packet */ 2714 :1, /* Reserved */ 2715 pkt_di_match:1, /* Packet Dindex match */ 2716 stripped_bytes:6, /* MACSEC stripped bytes */ 2717 msec_icv_fail:1; /* MACSEC ICV fail */ 2718 2719 /* T22.10 */ 2720 uint32 timestamp_hi:24, /* Timestamp (high) */ 2721 :8; /* Reserved */ 2722 2723 /* T22.11 */ 2724 uint32 outer_tag_hi:13, /* OTAG (high) */ 2725 :11, /* Reserved */ 2726 timestamp_lo:8; /* Timestamp (lo) */ 2727 2728 /* T22.12 */ 2729 uint32 srcport:5, /* Source port number */ 2730 :3, /* Reserved */ 2731 msec_decap_status:2, /* MACSEC decap status */ 2732 unmodified:1, /* Packet was unmodified */ 2733 vlan_chk_disable:1, /* VLAN checks were disabled */ 2734 mpls_exp:3, /* MPLS EXP */ 2735 dei:1, /* DEI */ 2736 sci_index:10, /* SCI index */ 2737 sci_valid:1, /* SCI index valid */ 2738 otag_action:2, /* Ingress Outer tag action */ 2739 outer_tag_lo:3; /* OTAG (low) */ 2740 2741 /* T22.13 */ 2742 uint32 mpls_ptr:8, /* Pointer to first MPLS label */ 2743 num_labels:2, /* Number of MPLS labels */ 2744 l3_ptr:8, /* Pointer to L3 header */ 2745 l3_type:3, /* L3 protocol */ 2746 l4_ptr:8, /* Pointer to L4 header */ 2747 l4_type:2, /* L4 protocol */ 2748 time_req:1; /* Timestamping required by destport */ 2749 2750 /* T22.14 */ 2751 uint32 :1, /* Reserved */ 2752 src_hg:1, /* Source is Higig */ 2753 cng:2, /* Congestion */ 2754 ecn:2, /* ECN */ 2755 change_ecn:1, /* ECN change */ 2756 cell_error:1, /* Cell error */ 2757 destport:5, /* Destination port */ 2758 etype_ptr:7, /* Ethertype pointer */ 2759 frame_type:3, /* Frame type */ 2760 dot1q_ptr:7, /* Pointer to VLAN tag(s) */ 2761 num_tags:2; /* Number of tags */ 2762 2763 /* T22.15: DMA Status 0 */ 2764 uint32 count:16, /* Transferred byte count */ 2765 end:1, /* End bit (RX) */ 2766 start:1, /* Start bit (RX) */ 2767 error:1, /* Cell Error (RX) */ 2768 dc:12, /* Don't Care */ 2769 done:1; /* Descriptor Done */ 2770 #else 2771 /* T22.6: RX Status 0 */ 2772 uint32 :10, /* Reserved */ 2773 src_port_mode:3, /* Source port mode */ 2774 :2, /* Reserved */ 2775 ingress_untagged:1, /* Packet came in untagged */ 2776 regen_crc:1, /* CRC to be regenerated */ 2777 chg_tos:1, /* DSCP changed */ 2778 dscp:8, /* DSCP */ 2779 :6; /* Reserved */ 2780 2781 /* T22.7 */ 2782 uint32 :2, /* Reserved */ 2783 pkt_len:14, /* Packet length */ 2784 reason:16; /* CPU opcode */ 2785 2786 /* T22.8 */ 2787 uint32 match_rule:8, /* Matched rule */ 2788 outer_pri:3, /* Outer pri (EP) */ 2789 outer_cfi:1, /* Outer CFI (EP) */ 2790 outer_vid:12, /* Outer VID (EP) */ 2791 :8; /* Reserved */ 2792 2793 /* T22.9 */ 2794 uint32 msec_icv_fail:1, /* MACSEC ICV fail */ 2795 stripped_bytes:6, /* MACSEC stripped bytes */ 2796 pkt_di_match:1, /* Packet Dindex match */ 2797 :1, /* Reserved */ 2798 bpdu:1, /* BPDU packet */ 2799 mirror:1, /* Mirrored copy */ 2800 msec_replay_error:1, /* MACSEC replay error */ 2801 msec_no_error:1, /* MACSEC no error */ 2802 :19; /* Reserved */ 2803 2804 /* T22.10 */ 2805 uint32 :8, /* Reserved */ 2806 timestamp_hi:24; /* Timestamp (high) */ 2807 2808 /* T22.11 */ 2809 uint32 timestamp_lo:8, /* Timestamp (lo) */ 2810 :11, /* Reserved */ 2811 outer_tag_hi:13; /* OTAG (high) */ 2812 2813 /* T22.12 */ 2814 uint32 outer_tag_lo:3, /* OTAG (low) */ 2815 otag_action:2, /* Ingress Outer tag action */ 2816 sci_valid:1, /* SCI index valid */ 2817 sci_index:10, /* SCI index */ 2818 dei:1, /* DEI */ 2819 mpls_exp:3, /* MPLS EXP */ 2820 vlan_chk_disable:1, /* VLAN checks were disabled */ 2821 unmodified:1, /* Packet was unmodified */ 2822 msec_decap_status:2, /* MACSEC decap status */ 2823 :3, /* Reserved */ 2824 srcport:5; /* Source port number */ 2825 2826 /* T22.13 */ 2827 uint32 time_req:1, /* Timestamping required by destport */ 2828 l4_type:2, /* L4 protocol */ 2829 l4_ptr:8, /* Pointer to L4 header */ 2830 l3_type:3, /* L3 protocol */ 2831 l3_ptr:8, /* Pointer to L3 header */ 2832 num_labels:2, /* Number of MPLS labels */ 2833 mpls_ptr:8; /* Pointer to first MPLS label */ 2834 2835 /* T22.14 */ 2836 uint32 num_tags:2, /* Number of tags */ 2837 dot1q_ptr:7, /* Pointer to VLAN tag(s) */ 2838 frame_type:3, /* Frame type */ 2839 etype_ptr:7, /* Ethertype pointer */ 2840 destport:5, /* Destination port */ 2841 cell_error:1, /* Cell error */ 2842 change_ecn:1, /* ECN change */ 2843 ecn:2, /* ECN */ 2844 cng:2, /* Congestion */ 2845 src_hg:1, /* Source is Higig */ 2846 :1; /* Reserved */ 2847 2848 /* T22.15: DMA Status 0 */ 2849 uint32 done:1, /* Descriptor Done */ 2850 dc:12, /* Don't Care */ 2851 error:1, /* Cell Error (RX) */ 2852 start:1, /* Start bit (RX) */ 2853 end:1, /* End bit (RX) */ 2854 count:16; /* Transferred byte count */ 2855 #endif 2856 } dcb22_t; 2857 #endif /* BCM_SHADOW_SUPPORT */ 2858 2859 2860 2861 2862 #if defined(BCM_PETRA_SUPPORT) 2863 typedef struct { 2864 uint32 addr; /* T9.0: physical address */ 2865 #ifdef LE_HOST 2866 uint32 c_count:16, /* Requested byte count */ 2867 c_chain:1, /* Chaining */ 2868 c_sg:1, /* Scatter Gather */ 2869 c_reload:1, /* Reload */ 2870 c_hg:1, /* Higig (TX) */ 2871 c_stat:1, /* update stats (TX) */ 2872 c_pause:1, /* Pause packet (TX) */ 2873 c_purge:1, /* Purge packet (TX) */ 2874 :9; /* Don't care */ 2875 #else 2876 uint32 :9, /* Don't care */ 2877 c_purge:1, /* Purge packet (TX) */ 2878 c_pause:1, 2879 c_stat:1, 2880 c_hg:1, 2881 c_reload:1, 2882 c_sg:1, 2883 c_chain:1, 2884 c_count:16; 2885 #endif /* LE_HOST */ 2886 uint32 mh0; /* T9.2: Module Header word 0 */ 2887 uint32 mh1; /* T9.3: Module Header word 1 */ 2888 uint32 mh2; /* T9.4: Module Header word 2 */ 2889 uint32 mh3; /* T11.5: Module Header word 3 */ 2890 #ifdef LE_HOST 2891 uint32 mtp_index_hi:5, /* Mirror-to-Port Index */ 2892 l3uc:1, /* L3 UC */ 2893 l3only:1, /* L3 only */ 2894 l3ipmc:1, /* L3 IPMC */ 2895 l3_intf:12, /* L3 Intf number */ 2896 imirror:1, /* Ingress Mirroring */ 2897 emirror:1, /* Egress Mirroring */ 2898 cos:3, /* Packet Priority */ 2899 cpu_cos:3, /* CPU COS */ 2900 chg_tos:1, /* DSCP Changed */ 2901 cell_error:1, /* Cell CRC Checksum Error Detected */ 2902 bpdu:1, /* BPDU Packet */ 2903 add_vid:1; /* VLAN ID Added */ 2904 uint32 reason:25, /* CPU opcode */ 2905 regen_crc:1, /* Regenerate CRC */ 2906 switch_pkt:1, /* Switched packet */ 2907 src_hg:1, /* Source is Higig */ 2908 purge_cell:1, /* Packet is marked Purged */ 2909 pkt_aged:1, /* Pkt is Aged */ 2910 mtp_index_lo:2; /* Mirror-to-Port Index */ 2911 uint32 dscp_hi:2, /* New DSCP */ 2912 srcport:5, /* Source port */ 2913 nh_index:13, /* Next hop index */ 2914 match_rule:10, /* Matched Rule */ 2915 match_rule_valid:1, /* Matched Rule valid */ 2916 decap_iptunnel:1; /* Decap IP Tunneling Packet */ 2917 uint32 :11, 2918 ingress_untagged:1, /* Pkt came in untagged */ 2919 outer_vid:12, /* VID */ 2920 outer_cfi:1, /* CFI */ 2921 outer_pri:3, /* Priority */ 2922 dscp_lo:4; /* New DSCP */ 2923 #else 2924 uint32 add_vid:1, /* VLAN ID Added */ 2925 bpdu:1, /* BPDU Packet */ 2926 cell_error:1, /* Cell CRC Checksum Error Detected */ 2927 chg_tos:1, /* DSCP Changed */ 2928 cpu_cos:3, /* CPU COS */ 2929 cos:3, /* Packet Priority */ 2930 emirror:1, /* Egress Mirroring */ 2931 imirror:1, /* Ingress Mirroring */ 2932 l3_intf:12, /* L3 Intf number */ 2933 l3ipmc:1, /* L3 IPMC */ 2934 l3only:1, /* L3 only */ 2935 l3uc:1, /* L3 UC */ 2936 mtp_index_hi:5; /* Mirror-to-Port Index */ 2937 uint32 mtp_index_lo:2, /* Mirror-to-Port Index */ 2938 pkt_aged:1, /* Pkt is Aged */ 2939 purge_cell:1, /* Packet is marked Purged */ 2940 src_hg:1, /* Source is Higig */ 2941 switch_pkt:1, /* Switched packet */ 2942 regen_crc:1, /* Regenerate CRC */ 2943 reason:25; /* CPU opcode */ 2944 uint32 decap_iptunnel:1, /* Decap IP Tunneling Packet */ 2945 match_rule_valid:1, /* Matched Rule valid */ 2946 match_rule:10, /* Matched Rule */ 2947 nh_index:13, /* Next hop index */ 2948 srcport:5, /* Source port */ 2949 dscp_hi:2; /* New DSCP */ 2950 uint32 dscp_lo:4, /* New DSCP */ 2951 outer_pri:3, /* Priority (D)*/ 2952 outer_cfi:1, /* CFI (D)*/ 2953 outer_vid:12, /* VID (D)*/ 2954 ingress_untagged:1, /* Pkt came in untagged (D)*/ 2955 :11; 2956 #endif 2957 uint32 s_4; /* T9.9: RX Status 4 */ 2958 uint32 s_41; /* T9.9: RX Status 4 */ 2959 uint32 s_42; /* T9.9: RX Status 4 */ 2960 uint32 s_43; /* T9.9: RX Status 4 */ 2961 uint32 s_44; /* T9.9: RX Status 4 */ 2962 /* T9.10: DMA Status 0 */ 2963 #ifdef LE_HOST 2964 uint32 count:16, /* Transferred byte count */ 2965 end:1, /* End bit (RX) */ 2966 start:1, /* Start bit (RX) */ 2967 error:1, /* Cell Error (RX) */ 2968 dc:12, /* Don't Care */ 2969 done:1; /* Descriptor Done */ 2970 #else 2971 uint32 done:1, 2972 dc:12, 2973 error:1, 2974 start:1, 2975 end:1, 2976 count:16; 2977 #endif 2978 } dcb28_t; 2979 #endif /* BCM_XGS3_SWITCH_SUPPORT */ 2980 2981 #if defined(BCM_TRIUMPH3_SUPPORT) || defined(BCM_KATANA_SUPPORT) || \ 2982 defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_GREYHOUND_SUPPORT) 2983 /* 2984 * DMA Control Block - Type 23 2985 * Used on 56640 devices 2986 * 16 words 2987 */ 2988 #include <soc/shared/dcbformats/type23.h> 2989 2990 #endif /* BCM_TRIUMPH3_SUPPORT || BCM_KATANA_SUPPORT || \ 2991 BCM_TRIDENT2_SUPPORT || BCM_GREYHOUND_SUPPORT */ 2992 2993 #if defined(BCM_KATANA_SUPPORT) 2994 /* 2995 * DMA Control Block - Type 24 2996 * Used on 56440 devices 2997 * 16 words 2998 */ 2999 #include <soc/shared/dcbformats/type24.h> 3000 3001 #endif /* BCM_KATANA_SUPPORT */ 3002 3003 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_HURRICANE2_SUPPORT) 3004 /* 3005 * DMA Control Block - Type 26 3006 * Used on 56850 devices 3007 * 16 words 3008 */ 3009 #include <soc/shared/dcbformats/type26.h> 3010 3011 #endif /* BCM_TRIDENT2_SUPPORT */ 3012 3013 #if defined(BCM_KATANA2_SUPPORT) 3014 /* 3015 * DMA Control Block - Type 29 3016 * Used on 56450 devices 3017 * 16 words 3018 */ 3019 #include <soc/shared/dcbformats/type29.h> 3020 3021 #endif /* BCM_KATANA2_SUPPORT */ 3022 3023 #if defined(BCM_GREYHOUND_SUPPORT) 3024 /* 3025 * DMA Control Block - Type 31 3026 * Used on 53400 devices 3027 * 16 words 3028 */ 3029 #include <soc/shared/dcbformats/type31.h> 3030 3031 #endif /* BCM_GREYHOUND_SUPPORT */ 3032 3033 #if defined(BCM_TOMAHAWK_SUPPORT) 3034 /* 3035 * DMA Control Block - Type 32 3036 * Used on 5696X devices 3037 * 16 words 3038 */ 3039 #include <soc/shared/dcbformats/type32.h> 3040 3041 #endif /* BCM_TOMAHAWK_SUPPORT */ 3042 3043 #if defined(BCM_TRIDENT2PLUS_SUPPORT) 3044 /* 3045 * DMA Control Block - Type 33 3046 * Used on 56860 devices 3047 * 16 words 3048 */ 3049 #include <soc/shared/dcbformats/type33.h> 3050 3051 #endif /* BCM_TRIDENT2PLUS_SUPPORT */ 3052 3053 #if defined(BCM_HURRICANE3_SUPPORT) 3054 /* 3055 * DMA Control Block - Type 34 3056 * Used on 56160 devices 3057 * 16 words 3058 */ 3059 #include <soc/shared/dcbformats/type34.h> 3060 3061 #endif /* BCM_HURRICANE3_SUPPORT */ 3062 3063 #if defined(BCM_APACHE_SUPPORT) 3064 /* 3065 * DMA Control Block - Type 35 3066 * Used on 56560 devices 3067 * 16 words 3068 */ 3069 #include <soc/shared/dcbformats/type35.h> 3070 3071 #endif /* BCM_APACHE_SUPPORT */ 3072 3073 #if defined(BCM_TRIDENT3_SUPPORT) 3074 /* 3075 * DMA Control Block - Type 36 3076 * Used on 56870 devices 3077 * 16 words 3078 */ 3079 #include <soc/shared/dcbformats/type36.h> 3080 3081 #endif /* BCM_TRIDENT3_SUPPORT */ 3082 #if defined(BCM_GREYHOUND2_SUPPORT) 3083 /* 3084 * DMA Control Block - Type 37 3085 * Used on XXXXX devices 3086 * 16 words 3087 */ 3088 #include <soc/shared/dcbformats/type37.h> 3089 3090 #endif /* BCM_GREYHOUND2_SUPPORT */ 3091 3092 #if defined(BCM_TOMAHAWK3_SUPPORT) 3093 /* 3094 * DMA Control Block - Type 38 3095 * Used on 56980 devices 3096 * 16 words 3097 */ 3098 #include <soc/shared/dcbformats/type38.h> 3099 3100 #endif /* BCM_TOMAHAWK3_SUPPORT */ 3101 3102 #if defined(BCM_DNX_SUPPORT) 3103 /* 3104 * DMA Control Block - Type 39 3105 * Used on 88690 devices 3106 * 16 words 3107 */ 3108 #include <soc/shared/dcbformats/type39.h> 3109 3110 #endif /* BCM_DNX_SUPPORT */ 3111 3112 3113 #endif /* _SOC_DCBFORMATS_H */