cprif_drv_private.h (45263B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 * 9 * This file is private to cprif_drv and should not be included 10 * by any other file. 11 */ 12 #ifndef _CPRIH_DRV_PRIVATE_H_ 13 #define _CPRIF_DRV_PRIVATE_H_ 14 15 16 /* CPRI ECC interrupt information structure */ 17 18 typedef struct _cpri_ecc_interrupts_info_s { 19 soc_reg_t ecc_en_reg; /* ecc enable reg */ 20 soc_field_t ecc2b_en_fld; /* 2-bit ecc */ 21 soc_field_t ecc1b_en_fld; /* 1-bit ecc */ 22 soc_reg_t ecc_status_reg; /* ecc status reg */ 23 soc_field_t ecc_event_addr; /* ecc error address */ 24 soc_field_t ecc_multib_err_status_fld; /* multi-bit ecc error */ 25 soc_field_t ecc2b_err_status_fld; /* 2-bit ecc error */ 26 soc_field_t ecc1b_err_status_fld; /* 1-bit ecc error */ 27 soc_mem_t mem; /* mem info */ 28 char *mem_str; /* mem description */ 29 }_cpri_ecc_interrupts_info_t; 30 31 /* CPRI ECC interrupt information structure */ 32 33 typedef struct _cpri_ecc_intr_report_s { 34 int port; 35 soc_mem_t err_mem_info; /* ecc error mem */ 36 soc_reg_t err_reg_info; /* ecc error reg */ 37 int ecc_num_bits_err; /* num bits ecc error */ 38 uint32 err_addr; /* error address */ 39 char *mem_str; /* mem description */ 40 }_cpri_ecc_intr_report_t; 41 42 STATIC _cpri_ecc_interrupts_info_t _cpri_port_ecc_intrs_info[] = { 43 { 44 CPRI_DECAP_CLS_QUEUE_INTR_ENABLE_CONTROLr, 45 CLS_QUEUE_ECC_2BIT_INTERRUPT_ENf, 46 CLS_QUEUE_ECC_1BIT_INTERRUPT_ENf, 47 CPRI_DECAP_CLS_QUEUE_ECC_INTR_STATUSr, 48 CLS_QUEUE_ERR_ADDRf, 49 CLS_QUEUE_MULTIPLE_ECC_ERRf, 50 CLS_QUEUE_ECC_2BIT_INTERRUPT_STATUSf, 51 CLS_QUEUE_ECC_1BIT_INTERRUPT_STATUSf, 52 CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_0m, 53 "CPRI Decap Classification to Queue Control Memory for port" 54 }, 55 { 56 CPRI_DECAP_COMP_TAB_I_0_INTR_ENABLE_CONTROLr, 57 COMP_TAB_I_0_ECC_2BIT_INTERRUPT_ENf, 58 COMP_TAB_I_0_ECC_1BIT_INTERRUPT_ENf, 59 CPRI_DECAP_COMP_TAB_I_0_ECC_INTR_STATUSr, 60 COMP_TAB_I_0_ERR_ADDRf, 61 COMP_TAB_I_0_MULTIPLE_ECC_ERRf, 62 COMP_TAB_I_0_ECC_2BIT_INTERRUPT_STATUSf, 63 COMP_TAB_I_0_ECC_1BIT_INTERRUPT_STATUSf, 64 CPRI_DECAP_COMP_TAB_0m, 65 "CPRI Decap Compression Table I_0 for port" 66 }, 67 { 68 CPRI_DECAP_COMP_TAB_I_1_INTR_ENABLE_CONTROLr, 69 COMP_TAB_I_1_ECC_2BIT_INTERRUPT_ENf, 70 COMP_TAB_I_1_ECC_1BIT_INTERRUPT_ENf, 71 CPRI_DECAP_COMP_TAB_I_1_ECC_INTR_STATUSr, 72 COMP_TAB_I_1_ERR_ADDRf, 73 COMP_TAB_I_1_MULTIPLE_ECC_ERRf, 74 COMP_TAB_I_1_ECC_2BIT_INTERRUPT_STATUSf, 75 COMP_TAB_I_1_ECC_1BIT_INTERRUPT_STATUSf, 76 CPRI_DECAP_COMP_TAB_0m, 77 "CPRI Decap Compression Table I_1 for port" 78 }, 79 { 80 CPRI_DECAP_COMP_TAB_Q_0_INTR_ENABLE_CONTROLr, 81 COMP_TAB_Q_0_ECC_2BIT_INTERRUPT_ENf, 82 COMP_TAB_Q_0_ECC_1BIT_INTERRUPT_ENf, 83 CPRI_DECAP_COMP_TAB_Q_0_ECC_INTR_STATUSr, 84 COMP_TAB_Q_0_ERR_ADDRf, 85 COMP_TAB_Q_0_MULTIPLE_ECC_ERRf, 86 COMP_TAB_Q_0_ECC_2BIT_INTERRUPT_STATUSf, 87 COMP_TAB_Q_0_ECC_1BIT_INTERRUPT_STATUSf, 88 CPRI_DECAP_COMP_TAB_0m, 89 "CPRI Decap Compression Table Q_0 for port" 90 }, 91 { 92 CPRI_DECAP_COMP_TAB_Q_1_INTR_ENABLE_CONTROLr, 93 COMP_TAB_Q_1_ECC_2BIT_INTERRUPT_ENf, 94 COMP_TAB_Q_1_ECC_1BIT_INTERRUPT_ENf, 95 CPRI_DECAP_COMP_TAB_Q_1_ECC_INTR_STATUSr, 96 COMP_TAB_Q_1_ERR_ADDRf, 97 COMP_TAB_Q_1_MULTIPLE_ECC_ERRf, 98 COMP_TAB_Q_1_ECC_2BIT_INTERRUPT_STATUSf, 99 COMP_TAB_Q_1_ECC_1BIT_INTERRUPT_STATUSf, 100 CPRI_DECAP_COMP_TAB_0m, 101 "CPRI Decap Compression Table Q_1 for port" 102 }, 103 { 104 CPRI_DECAP_DATA_MEM_INTR_ENABLE_CONTROLr, 105 DATA_MEM_ECC_2BIT_INTERRUPT_ENf, 106 DATA_MEM_ECC_1BIT_INTERRUPT_ENf, 107 CPRI_DECAP_DATA_MEM_ECC_INTR_STATUSr, 108 DECAP_DATA_MEM_ERR_ADDRf, 109 DECAP_DATA_MEM_MULTIPLE_ECC_ERRf, 110 DECAP_DATA_MEM_ECC_2BIT_INTERRUPT_STATUSf, 111 DECAP_DATA_MEM_ECC_1BIT_INTERRUPT_STATUSf, 112 INVALIDm, 113 "CPRI Decap AxC Data Memory" 114 }, 115 { 116 CPRI_DECAP_FLOWID_QUEUE_INTR_ENABLE_CONTROLr, 117 FLOWID_QUEUE_ECC_2BIT_INTERRUPT_ENf, 118 FLOWID_QUEUE_ECC_1BIT_INTERRUPT_ENf, 119 CPRI_DECAP_FLOWID_QUEUE_ECC_INTR_STATUSr, 120 FLOWID_QUEUE_ERR_ADDRf, 121 FLOWID_QUEUE_MULTIPLE_ECC_ERRf, 122 FLOWID_QUEUE_ECC_2BIT_INTERRUPT_STATUSf, 123 FLOWID_QUEUE_ECC_1BIT_INTERRUPT_STATUSf, 124 CPRI_DECAP_FLOWID_QUE_LOOKUP_0m, 125 "CPRI Decap Flow-id to Queue Lookup Table for port" 126 }, 127 { 128 CPRI_DECAP_MEMBUF_0_INTR_ENABLE_CONTROLr, 129 MEMBUF_0_ECC_2BIT_INTERRUPT_ENf, 130 MEMBUF_0_ECC_1BIT_INTERRUPT_ENf, 131 CPRI_DECAP_MEMBUF_0_ECC_INTR_STATUSr, 132 MEMBUF_0_ERR_ADDRf, 133 MEMBUF_0_MULTIPLE_ECC_ERRf, 134 MEMBUF_0_ECC_2BIT_INTERRUPT_STATUSf, 135 MEMBUF_0_ECC_1BIT_INTERRUPT_STATUSf, 136 INVALIDm, 137 "CPRI Decap TX MEMBUF-0 Memory" 138 }, 139 { 140 CPRI_DECAP_MEMBUF_1_INTR_ENABLE_CONTROLr, 141 MEMBUF_1_ECC_2BIT_INTERRUPT_ENf, 142 MEMBUF_1_ECC_1BIT_INTERRUPT_ENf, 143 CPRI_DECAP_MEMBUF_1_ECC_INTR_STATUSr, 144 MEMBUF_1_ERR_ADDRf, 145 MEMBUF_1_MULTIPLE_ECC_ERRf, 146 MEMBUF_1_ECC_2BIT_INTERRUPT_STATUSf, 147 MEMBUF_1_ECC_1BIT_INTERRUPT_STATUSf, 148 INVALIDm, 149 "CPRI Decap TX MEMBUF-1 Memory" 150 }, 151 { 152 CPRI_DECAP_ORDERING_INFO_INTR_ENABLE_CONTROLr, 153 DECAP_ORDERING_INFO_ECC_2BIT_INTERRUPT_ENf, 154 DECAP_ORDERING_INFO_ECC_1BIT_INTERRUPT_ENf, 155 CPRI_DECAP_ORDERING_INFO_ECC_INTR_STATUSr, 156 DECAP_ORDERING_INFO_ERR_ADDRf, 157 DECAP_ORDERING_INFO_MULTIPLE_ECC_ERRf, 158 DECAP_ORDERING_INFO_ECC_2BIT_INTERRUPT_STATUSf, 159 DECAP_ORDERING_INFO_ECC_1BIT_INTERRUPT_STATUSf, 160 CPRI_DECAP_ORDERING_INFO_TAB_0m, 161 "CPRI Decap Ordering Table Infor memory for port" 162 }, 163 { 164 CPRI_DECAP_PKT_CNT_INTR_ENABLE_CONTROLr, 165 DECAP_PKT_CNT_ECC_2BIT_INTERRUPT_ENf, 166 DECAP_PKT_CNT_ECC_1BIT_INTERRUPT_ENf, 167 CPRI_DECAP_PKT_CNT_ECC_INTR_STATUSr, 168 DECAP_PKT_CNT_ERR_ADDRf, 169 DECAP_PKT_CNT_MULTIPLE_ECC_ERRf, 170 DECAP_PKT_CNT_ECC_2BIT_INTERRUPT_STATUSf, 171 DECAP_PKT_CNT_ECC_1BIT_INTERRUPT_STATUSf, 172 CPRI_DECAP_QUEUE_STATS_0m, 173 "CPRI Decap Queue Statistics for Port" 174 }, 175 { 176 CPRI_DECAP_Q_CFG_INTR_ENABLE_CONTROLr, 177 DECAP_Q_CFG_ECC_2BIT_INTERRUPT_ENf, 178 DECAP_Q_CFG_ECC_1BIT_INTERRUPT_ENf, 179 CPRI_DECAP_Q_CFG_ECC_INTR_STATUSr, 180 DECAP_Q_CFG_ERR_ADDRf, 181 DECAP_Q_CFG_MULTIPLE_ECC_ERRf, 182 DECAP_Q_CFG_ECC_2BIT_INTERRUPT_STATUSf, 183 DECAP_Q_CFG_ECC_1BIT_INTERRUPT_STATUSf, 184 CPRI_DECAP_DATA_0m, 185 "CPRI Decap Queue Setup memory" 186 }, 187 { 188 CPRI_DECAP_SEQ_OFF_INTR_ENABLE_CONTROLr, 189 SEQ_OFF_ECC_2BIT_INTERRUPT_ENf, 190 SEQ_OFF_ECC_1BIT_INTERRUPT_ENf, 191 CPRI_DECAP_SEQ_OFF_ECC_INTR_STATUSr, 192 SEQ_OFF_ERR_ADDRf, 193 SEQ_OFF_MULTIPLE_ECC_ERRf, 194 SEQ_OFF_ECC_2BIT_INTERRUPT_STATUSf, 195 SEQ_OFF_ECC_1BIT_INTERRUPT_STATUSf, 196 CPRI_DECAP_ORDERING_SEQOFF_TAB_0m, 197 "CPRI Decap Ordering Seqoff Table" 198 }, 199 { 200 CPRI_TXFRM_BFA_MAP_TAB0_INTR_ENABLE_CONTROLr, 201 BFA_MAP_TAB0_ECC_2BIT_INTERRUPT_ENf, 202 BFA_MAP_TAB0_ECC_1BIT_INTERRUPT_ENf, 203 CPRI_TXFRM_BFA_MAP_TAB0_INTR_STATUSr, 204 BFA_MAP_TAB0_ERR_EVENT_ADDRESSf, 205 BFA_MAP_TAB0_MULTIPLE_ECC_ERRf, 206 BFA_MAP_TAB0_ECC_2BIT_INTERRUPT_STATUSf, 207 BFA_MAP_TAB0_ECC_1BIT_INTERRUPT_STATUSf, 208 CPRI_BFA_TAB0_CFG_0m, 209 "Basic frame assembly mapping table copy 0" 210 }, 211 { 212 CPRI_TXFRM_BFA_MAP_TAB1_INTR_ENABLE_CONTROLr, 213 BFA_MAP_TAB1_ECC_2BIT_INTERRUPT_ENf, 214 BFA_MAP_TAB1_ECC_1BIT_INTERRUPT_ENf, 215 CPRI_TXFRM_BFA_MAP_TAB1_INTR_STATUSr, 216 BFA_MAP_TAB1_ERR_EVENT_ADDRESSf, 217 BFA_MAP_TAB1_MULTIPLE_ECC_ERRf, 218 BFA_MAP_TAB1_ECC_2BIT_INTERRUPT_STATUSf, 219 BFA_MAP_TAB1_ECC_1BIT_INTERRUPT_STATUSf, 220 CPRI_BFA_TAB1_CFG_0m, 221 "Basic frame assembly mapping table copy 1" 222 }, 223 { 224 CPRI_TXFRM_CA_MAP_TAB_INTR_ENABLE_CONTROLr, 225 CA_MAP_TAB_ECC_2BIT_INTERRUPT_ENf, 226 CA_MAP_TAB_ECC_1BIT_INTERRUPT_ENf, 227 CPRI_TXFRM_CA_MAP_TAB_INTR_STATUSr, 228 CA_MAP_TAB_ERR_EVENT_ADDRESSf, 229 CA_MAP_TAB_MULTIPLE_ECC_ERRf, 230 CA_MAP_TAB_ECC_2BIT_INTERRUPT_STATUSf, 231 CA_MAP_TAB_ECC_1BIT_INTERRUPT_STATUSf, 232 CPRI_CA_MAP_TAB_CFG_0m, 233 "CPRI Container Assembly Mapping Table memory" 234 }, 235 { 236 CPRI_TXFRM_CA_PAY_TAB_INTR_ENABLE_CONTROLr, 237 CA_PAY_TAB_ECC_2BIT_INTERRUPT_ENf, 238 CA_PAY_TAB_ECC_1BIT_INTERRUPT_ENf, 239 CPRI_TXFRM_CA_PAY_TAB_INTR_STATUSr, 240 CA_PAY_TAB_ERR_EVENT_ADDRESSf, 241 CA_PAY_TAB_MULTIPLE_ECC_ERRf, 242 CA_PAY_TAB_ECC_2BIT_INTERRUPT_STATUSf, 243 CA_PAY_TAB_ECC_1BIT_INTERRUPT_STATUSf, 244 CPRI_CA_PAY_TAB_CFG_0m, 245 "CPRI Container Assembly Payload Table memory" 246 }, 247 { 248 CPRI_TXFRM_CA_STATE_TAB_INTR_ENABLE_CONTROLr, 249 CA_STATE_TAB_ECC_2BIT_INTERRUPT_ENf, 250 CA_STATE_TAB_ECC_1BIT_INTERRUPT_ENf, 251 CPRI_TXFRM_CA_STATE_TAB_INTR_STATUSr, 252 CA_STATE_TAB_ERR_EVENT_ADDRESSf, 253 CA_STATE_TAB_MULTIPLE_ECC_ERRf, 254 CA_STATE_TAB_ECC_2BIT_INTERRUPT_STATUSf, 255 CA_STATE_TAB_ECC_1BIT_INTERRUPT_STATUSf, 256 INVALIDm, 257 "CPRI container assembly state memory" 258 }, 259 { 260 CPRI_TXFRM_CWA_FLOW_BUFFER0_INTR_ENABLE_CONTROLr, 261 FLOW_BUFFER0_ECC_2BIT_INTERRUPT_ENf, 262 FLOW_BUFFER0_ECC_1BIT_INTERRUPT_ENf, 263 CPRI_TXFRM_CWA_FLOW_BUFFER0_INTR_STATUSr, 264 FLOW_BUFFER0_ERR_EVENT_ADDRESSf, 265 FLOW_BUFFER0_MULTIPLE_ECC_ERRf, 266 FLOW_BUFFER0_ECC_2BIT_INTERRUPT_STATUSf, 267 FLOW_BUFFER0_ECC_1BIT_INTERRUPT_STATUSf, 268 CPRI_CWA_VSD_CTRL_FLOW_BUFFER0_STS_0m, 269 "CPRI TX Per flow control axc data config table" 270 }, 271 { 272 CPRI_TXFRM_CWA_FLOW_BUFFER1_INTR_ENABLE_CONTROLr, 273 FLOW_BUFFER1_ECC_2BIT_INTERRUPT_ENf, 274 FLOW_BUFFER1_ECC_1BIT_INTERRUPT_ENf, 275 CPRI_TXFRM_CWA_FLOW_BUFFER1_INTR_STATUSr, 276 FLOW_BUFFER1_ERR_EVENT_ADDRESSf, 277 FLOW_BUFFER1_MULTIPLE_ECC_ERRf, 278 FLOW_BUFFER1_ECC_2BIT_INTERRUPT_STATUSf, 279 FLOW_BUFFER1_ECC_1BIT_INTERRUPT_STATUSf, 280 CPRI_CWA_VSD_CTRL_FLOW_BUFFER1_STS_0m, 281 "CPRI TX Per flow control axc data config table" 282 }, 283 { 284 CPRI_TXFRM_CWA_FLOW_CONFIG_INTR_ENABLE_CONTROLr, 285 FLOW_CONFIG_ECC_2BIT_INTERRUPT_ENf, 286 FLOW_CONFIG_ECC_1BIT_INTERRUPT_ENf, 287 CPRI_TXFRM_CWA_FLOW_CONFIG_INTR_STATUSr, 288 FLOW_CONFIG_ERR_EVENT_ADDRESSf, 289 FLOW_CONFIG_MULTIPLE_ECC_ERRf, 290 FLOW_CONFIG_ECC_2BIT_INTERRUPT_STATUSf, 291 FLOW_CONFIG_ECC_1BIT_INTERRUPT_STATUSf, 292 CPRI_CWA_VSD_CTRL_CONFIG_CFG_0m, 293 "CPRI TX Per flow axc data config table" 294 }, 295 { 296 CPRI_TXFRM_IQU_BUFFER_INTR_ENABLE_CONTROLr, 297 IQU_BUFFER_ECC_2BIT_INTERRUPT_ENf, 298 IQU_BUFFER_ECC_1BIT_INTERRUPT_ENf, 299 CPRI_TXFRM_IQU_BUFFER_INTR_STATUSr, 300 IQU_BUFFER_ERR_EVENT_ADDRESSf, 301 IQU_BUFFER_MULTIPLE_ECC_ERRf, 302 IQU_BUFFER_ECC_2BIT_INTERRUPT_STATUSf, 303 IQU_BUFFER_ECC_1BIT_INTERRUPT_STATUSf, 304 CPRI_IQU_BUFFER_STS_0m, 305 "CPRI IQ unpacking buffer payload table" 306 }, 307 { 308 CPRI_TXFRM_IQU_STATE_INTR_ENABLE_CONTROLr, 309 IQU_STATE_ECC_2BIT_INTERRUPT_ENf, 310 IQU_STATE_ECC_1BIT_INTERRUPT_ENf, 311 CPRI_TXFRM_IQU_STATE_INTR_STATUSr, 312 IQU_STATE_ERR_EVENT_ADDRESSf, 313 IQU_STATE_MULTIPLE_ECC_ERRf, 314 IQU_STATE_ECC_2BIT_INTERRUPT_STATUSf, 315 IQU_STATE_ECC_1BIT_INTERRUPT_STATUSf, 316 CPRI_IQU_STATE_STS_0m, 317 "IQ unpacking buffer state table" 318 }, 319 { 320 CPRI_TXPCS_TX_FIFO_INTR_ENABLE_CONTROLr, 321 TX_FIFO_ECC_2BIT_INTERRUPT_ENf, 322 TX_FIFO_ECC_1BIT_INTERRUPT_ENf, 323 CPRI_TXPCS_TX_FIFO_INTR_STATUSr, 324 TX_FIFO_ERR_EVENT_ADDRESSf, 325 TX_FIFO_MULTIPLE_ECC_ERRf, 326 TX_FIFO_ECC_2BIT_INTERRUPT_STATUSf, 327 TX_FIFO_ECC_1BIT_INTERRUPT_STATUSf, 328 INVALIDm, 329 "CPRI TX PCS FIFO" 330 }, 331 { 332 CPRI_ENCAP_DATA_MEM_INTR_ENABLE_CONTROLr, 333 ENCAP_DATA_MEM_ECC_2BIT_INTERRUPT_ENf, 334 ENCAP_DATA_MEM_ECC_1BIT_INTERRUPT_ENf, 335 CPRI_ENCAP_DATA_MEM_ECC_INTR_STATUSr, 336 ENCAP_DATA_MEM_ERR_ADDRf, 337 ENCAP_DATA_MEM_MULTIPLE_ECC_ERRf, 338 ENCAP_DATA_MEM_ECC_2BIT_INTERRUPT_STATUSf, 339 ENCAP_DATA_MEM_ECC_1BIT_INTERRUPT_STATUSf, 340 INVALIDm, 341 "CPRI Encap AxC Data Memory" 342 }, 343 { 344 CPRI_ENCAP_ETH_HDR_INTR_ENABLE_CONTROLr, 345 ENCAP_ETH_HDR_ECC_2BIT_INTERRUPT_ENf, 346 ENCAP_ETH_HDR_ECC_1BIT_INTERRUPT_ENf, 347 CPRI_ENCAP_ETH_HDR_ECC_INTR_STATUSr, 348 ENCAP_ETH_HDR_ERR_ADDRf, 349 ENCAP_ETH_HDR_MULTIPLE_ECC_ERRf, 350 ENCAP_ETH_HDR_ECC_2BIT_INTERRUPT_STATUSf, 351 ENCAP_ETH_HDR_ECC_1BIT_INTERRUPT_STATUSf, 352 CPRI_ENCAP_QUE_ETH_HDR_0m, 353 "CPRI Encap Ethernet Header Encapsualtion Type memory" 354 }, 355 { 356 CPRI_ENCAP_ORDERING_INFO_INTR_ENABLE_CONTROLr, 357 ENCAP_ORDERING_INFO_ECC_2BIT_INTERRUPT_ENf, 358 ENCAP_ORDERING_INFO_ECC_1BIT_INTERRUPT_ENf, 359 CPRI_ENCAP_ORDERING_INFO_ECC_INTR_STATUSr, 360 ENCAP_ORDERING_INFO_ERR_ADDRf, 361 ENCAP_ORDERING_INFO_MULTIPLE_ECC_ERRf, 362 ENCAP_ORDERING_INFO_ECC_2BIT_INTERRUPT_STATUSf, 363 ENCAP_ORDERING_INFO_ECC_1BIT_INTERRUPT_STATUSf, 364 CPRI_ENCAP_ORDERING_INFO_TAB_0m, 365 "CPRI Encap Ordering Table Info memory" 366 }, 367 { 368 CPRI_ENCAP_PKT_CNT_INTR_ENABLE_CONTROLr, 369 ENCAP_PKT_CNT_ECC_2BIT_INTERRUPT_ENf, 370 ENCAP_PKT_CNT_ECC_1BIT_INTERRUPT_ENf, 371 CPRI_ENCAP_PKT_CNT_ECC_INTR_STATUSr, 372 ENCAP_PKT_CNT_ERR_ADDRf, 373 ENCAP_PKT_CNT_MULTIPLE_ECC_ERRf, 374 ENCAP_PKT_CNT_ECC_2BIT_INTERRUPT_STATUSf, 375 ENCAP_PKT_CNT_ECC_1BIT_INTERRUPT_STATUSf, 376 INVALIDm, 377 "CPRI Encap Packet Count Memory" 378 }, 379 { 380 CPRI_ENCAP_Q_CFG_INTR_ENABLE_CONTROLr, 381 ENCAP_Q_CFG_ECC_2BIT_INTERRUPT_ENf, 382 ENCAP_Q_CFG_ECC_1BIT_INTERRUPT_ENf, 383 CPRI_ENCAP_Q_CFG_ECC_INTR_STATUSr, 384 ENCAP_Q_CFG_ERR_ADDRf, 385 ENCAP_Q_CFG_MULTIPLE_ECC_ERRf, 386 ENCAP_Q_CFG_ECC_2BIT_INTERRUPT_STATUSf, 387 ENCAP_Q_CFG_ECC_1BIT_INTERRUPT_STATUSf, 388 CPRI_ENCAP_DATA_0m, 389 "CPRI Encap Data Queue memory error" 390 }, 391 { 392 CPRI_ENCAP_RXFRM_0_INTR_ENABLE_CONTROLr, 393 RXFRM_0_ECC_2BIT_INTERRUPT_ENf, 394 RXFRM_0_ECC_1BIT_INTERRUPT_ENf, 395 CPRI_ENCAP_RXFRM_0_ECC_INTR_STATUSr, 396 RXFRM_0_ERR_ADDRf, 397 RXFRM_0_MULTIPLE_ECC_ERRf, 398 RXFRM_0_ECC_2BIT_INTERRUPT_STATUSf, 399 RXFRM_0_ECC_1BIT_INTERRUPT_STATUSf, 400 INVALIDm, 401 "CPRI Encap RX Framer-1 Memory" 402 }, 403 { 404 CPRI_ENCAP_RXFRM_1_INTR_ENABLE_CONTROLr, 405 RXFRM_1_ECC_2BIT_INTERRUPT_ENf, 406 RXFRM_1_ECC_1BIT_INTERRUPT_ENf, 407 CPRI_ENCAP_RXFRM_1_ECC_INTR_STATUSr, 408 RXFRM_1_ERR_ADDRf, 409 RXFRM_1_MULTIPLE_ECC_ERRf, 410 RXFRM_1_ECC_2BIT_INTERRUPT_STATUSf, 411 RXFRM_1_ECC_1BIT_INTERRUPT_STATUSf, 412 INVALIDm, 413 "CPRI Encap RX Framer-1 Memory" 414 }, 415 { 416 CPRI_ENCAP_SEQ_NUM_CTL_INTR_ENABLE_CONTROLr, 417 SEQ_NUM_CTL_ECC_2BIT_INTERRUPT_ENf, 418 SEQ_NUM_CTL_ECC_1BIT_INTERRUPT_ENf, 419 CPRI_ENCAP_SEQ_NUM_CTL_ECC_INTR_STATUSr, 420 SEQ_NUM_CTL_ERR_ADDRf, 421 SEQ_NUM_CTL_MULTIPLE_ECC_ERRf, 422 SEQ_NUM_CTL_ECC_2BIT_INTERRUPT_STATUSf, 423 SEQ_NUM_CTL_ECC_1BIT_INTERRUPT_STATUSf, 424 CPRI_ENCAP_ORDERING_INFO_STS_0m, 425 "CPRI Encap Ordering Info Table for Control" 426 }, 427 { 428 CPRI_ENCAP_SEQ_NUM_DATA_INTR_ENABLE_CONTROLr, 429 SEQ_NUM_DATA_ECC_2BIT_INTERRUPT_ENf, 430 SEQ_NUM_DATA_ECC_1BIT_INTERRUPT_ENf, 431 CPRI_ENCAP_SEQ_NUM_DATA_ECC_INTR_STATUSr, 432 SEQ_NUM_DATA_ERR_ADDRf, 433 SEQ_NUM_DATA_MULTIPLE_ECC_ERRf, 434 SEQ_NUM_DATA_ECC_2BIT_INTERRUPT_STATUSf, 435 SEQ_NUM_DATA_ECC_1BIT_INTERRUPT_STATUSf, 436 CPRI_ENCAP_ORDERING_INFO_STS_0m, 437 "CPRI Encap Ordering Info Table for Data" 438 }, 439 { 440 CPRI_ENCAP_WQ_0_INTR_ENABLE_CONTROLr, 441 WQ_0_ECC_2BIT_INTERRUPT_ENf, 442 WQ_0_ECC_1BIT_INTERRUPT_ENf, 443 CPRI_ENCAP_WQ_0_ECC_INTR_STATUSr, 444 WQ_0_ERR_ADDRf, 445 WQ_0_MULTIPLE_ECC_ERRf, 446 WQ_0_ECC_2BIT_INTERRUPT_STATUSf, 447 WQ_0_ECC_1BIT_INTERRUPT_STATUSf, 448 INVALIDm, 449 "CPRI Encap WQ-0 Memory" 450 }, 451 { 452 CPRI_ENCAP_WQ_1_INTR_ENABLE_CONTROLr, 453 WQ_1_ECC_2BIT_INTERRUPT_ENf, 454 WQ_1_ECC_1BIT_INTERRUPT_ENf, 455 CPRI_ENCAP_WQ_1_ECC_INTR_STATUSr, 456 WQ_1_ERR_ADDRf, 457 WQ_1_MULTIPLE_ECC_ERRf, 458 WQ_1_ECC_2BIT_INTERRUPT_STATUSf, 459 WQ_1_ECC_1BIT_INTERRUPT_STATUSf, 460 INVALIDm, 461 "CPRI Encap WQ-1 Memory" 462 }, 463 { 464 CPRI_ENCAP_WQ_2_INTR_ENABLE_CONTROLr, 465 WQ_2_ECC_2BIT_INTERRUPT_ENf, 466 WQ_2_ECC_1BIT_INTERRUPT_ENf, 467 CPRI_ENCAP_WQ_2_ECC_INTR_STATUSr, 468 WQ_2_ERR_ADDRf, 469 WQ_2_MULTIPLE_ECC_ERRf, 470 WQ_2_ECC_2BIT_INTERRUPT_STATUSf, 471 WQ_2_ECC_1BIT_INTERRUPT_STATUSf, 472 INVALIDm, 473 "CPRI Encap WQ-2 Memory" 474 }, 475 { 476 CPRI_ENCAP_WQ_3_INTR_ENABLE_CONTROLr, 477 WQ_3_ECC_2BIT_INTERRUPT_ENf, 478 WQ_3_ECC_1BIT_INTERRUPT_ENf, 479 CPRI_ENCAP_WQ_3_ECC_INTR_STATUSr, 480 WQ_3_ERR_ADDRf, 481 WQ_3_MULTIPLE_ECC_ERRf, 482 WQ_3_ECC_2BIT_INTERRUPT_STATUSf, 483 WQ_3_ECC_1BIT_INTERRUPT_STATUSf, 484 INVALIDm, 485 "CPRI Encap WQ-3 Memory" 486 }, 487 { 488 CPRI_RXFRM_BFRM_MAP_TAB0_INTR_ENABLE_CONTROLr, 489 BFRM_MAP_TAB0_ECC_2BIT_INTERRUPT_ENf, 490 BFRM_MAP_TAB0_ECC_1BIT_INTERRUPT_ENf, 491 CPRI_RXFRM_BFRM_MAP_TAB0_INTR_STATUSr, 492 BFRM_MAP_TAB0_ERR_EVENT_ADDRESSf, 493 BFRM_MAP_TAB0_MULTIPLE_ECC_ERRf, 494 BFRM_MAP_TAB0_ECC_2BIT_INTERRUPT_STATUSf, 495 BFRM_MAP_TAB0_ECC_1BIT_INTERRUPT_STATUSf, 496 CPRI_BFP_TAB0_CFG_0m, 497 "CPRI Basic Frame Parser Mapping Table Copy 0" 498 }, 499 { 500 CPRI_RXFRM_BFRM_MAP_TAB1_INTR_ENABLE_CONTROLr, 501 BFRM_MAP_TAB1_ECC_2BIT_INTERRUPT_ENf, 502 BFRM_MAP_TAB1_ECC_1BIT_INTERRUPT_ENf, 503 CPRI_RXFRM_BFRM_MAP_TAB1_INTR_STATUSr, 504 BFRM_MAP_TAB1_ERR_EVENT_ADDRESSf, 505 BFRM_MAP_TAB1_MULTIPLE_ECC_ERRf, 506 BFRM_MAP_TAB1_ECC_2BIT_INTERRUPT_STATUSf, 507 BFRM_MAP_TAB1_ECC_1BIT_INTERRUPT_STATUSf, 508 CPRI_BFP_TAB1_CFG_0m, 509 "CPRI Basic Frame Parser Mapping Table Copy 1" 510 }, 511 { 512 CPRI_RXFRM_CFLW_BUF_TAB_INTR_ENABLE_CONTROLr, 513 CFLW_BUF_TAB_ECC_2BIT_INTERRUPT_ENf, 514 CFLW_BUF_TAB_ECC_1BIT_INTERRUPT_ENf, 515 CPRI_RXFRM_CFLW_BUF_TAB_INTR_STATUSr, 516 CFLW_BUF_TAB_ERR_EVENT_ADDRESSf, 517 CFLW_BUF_TAB_MULTIPLE_ECC_ERRf, 518 CFLW_BUF_TAB_ECC_2BIT_INTERRUPT_STATUSf, 519 CFLW_BUF_TAB_ECC_1BIT_INTERRUPT_STATUSf, 520 CPRI_VSDCTRL_CFLW_BUF_TAB_STS_0m, 521 "CPRI Control Flow Buffer memory" 522 }, 523 { 524 CPRI_RXFRM_CFLW_PGC_TAB_INTR_ENABLE_CONTROLr, 525 CFLW_PGC_TAB_ECC_2BIT_INTERRUPT_ENf, 526 CFLW_PGC_TAB_ECC_1BIT_INTERRUPT_ENf, 527 CPRI_RXFRM_CFLW_PGC_TAB_INTR_STATUSr, 528 CFLW_PGC_TAB_ERR_EVENT_ADDRESSf, 529 CFLW_PGC_TAB_MULTIPLE_ECC_ERRf, 530 CFLW_PGC_TAB_ECC_2BIT_INTERRUPT_STATUSf, 531 CFLW_PGC_TAB_ECC_1BIT_INTERRUPT_STATUSf, 532 CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_0m, 533 "CPRI Control Flow Packet Generation Config Memory" 534 }, 535 { 536 CPRI_RXFRM_CPRSR_MAP_TAB_INTR_ENABLE_CONTROLr, 537 CPRSR_MAP_TAB_ECC_2BIT_INTERRUPT_ENf, 538 CPRSR_MAP_TAB_ECC_1BIT_INTERRUPT_ENf, 539 CPRI_RXFRM_CPRSR_MAP_TAB_INTR_STATUSr, 540 CPRSR_MAP_TAB_ERR_EVENT_ADDRESSf, 541 CPRSR_MAP_TAB_MULTIPLE_ECC_ERRf, 542 CPRSR_MAP_TAB_ECC_2BIT_INTERRUPT_STATUSf, 543 CPRSR_MAP_TAB_ECC_1BIT_INTERRUPT_STATUSf, 544 CPRI_CPRSR_MAP_TAB_CFG_0m, 545 "CPRI Container parser mapping table" 546 }, 547 { 548 CPRI_RXFRM_CPRSR_STATE_MEM_INTR_ENABLE_CONTROLr, 549 CPRSR_MAP_STATE_TAB_ECC_2BIT_INTERRUPT_ENf, 550 CPRSR_MAP_STATE_TAB_ECC_1BIT_INTERRUPT_ENf, 551 CPRI_RXFRM_CPRSR_STATE_MEM_INTR_STATUSr, 552 CPRSR_MAP_STATE_TAB_ERR_EVENT_ADDRESSf, 553 CPRSR_MAP_STATE_TAB_MULTIPLE_ECC_ERRf, 554 CPRSR_MAP_STATE_TAB_ECC_2BIT_INTERRUPT_STATUSf, 555 CPRSR_MAP_STATE_TAB_ECC_1BIT_INTERRUPT_STATUSf, 556 CPRI_CPRSR_MAP_STATE_TAB_STS_0m, 557 "CPRI Container parser mapping state table" 558 }, 559 { 560 CPRI_RXFRM_IQ_PK_BUFF_AXC_PLD_MEM_INTR_ENABLE_CONTROLr, 561 IQ_PK_BUFF_AXC_PLD_ECC_2BIT_INTERRUPT_ENf, 562 IQ_PK_BUFF_AXC_PLD_ECC_1BIT_INTERRUPT_ENf, 563 CPRI_RXFRM_IQ_PK_BUFF_AXC_PLD_MEM_INTR_STATUSr, 564 IQ_PK_BUFF_AXC_PLD_ERR_EVENT_ADDRESSf, 565 IQ_PK_BUFF_AXC_PLD_MULTIPLE_ECC_ERRf, 566 IQ_PK_BUFF_AXC_PLD_ECC_2BIT_INTERRUPT_STATUSf, 567 IQ_PK_BUFF_AXC_PLD_ECC_1BIT_INTERRUPT_STATUSf, 568 CPRI_IQ_PK_BUFF_AXC_PLD_STS_0m, 569 "IQ packing buffer payload table memory" 570 }, 571 { 572 CPRI_RXFRM_IQ_PK_BUFF_AXC_STATE_MEM_INTR_ENABLE_CONTROLr, 573 IQ_PK_BUFF_AXC_STATE_ECC_2BIT_INTERRUPT_ENf, 574 IQ_PK_BUFF_AXC_STATE_ECC_1BIT_INTERRUPT_ENf, 575 CPRI_RXFRM_IQ_PK_BUFF_AXC_STATE_MEM_INTR_STATUSr, 576 IQ_PK_BUFF_AXC_STATE_ERR_EVENT_ADDRESSf, 577 IQ_PK_BUFF_AXC_STATE_MULTIPLE_ECC_ERRf, 578 IQ_PK_BUFF_AXC_STATE_ECC_2BIT_INTERRUPT_STATUSf, 579 IQ_PK_BUFF_AXC_STATE_ECC_1BIT_INTERRUPT_STATUSf, 580 CPRI_IQ_PK_BUFF_AXC_STATE_STS_0m, 581 "CPRI IQ packing buffer state table memory" 582 }, 583 { 584 CPRI_RXFRM_IQ_PK_BUFF_MEM_INTR_ENABLE_CONTROLr, 585 IQ_PK_BUFF_ECC_2BIT_INTERRUPT_ENf, 586 IQ_PK_BUFF_ECC_1BIT_INTERRUPT_ENf, 587 CPRI_RXFRM_IQ_PK_BUFF_MEM_INTR_STATUSr, 588 IQ_PK_BUFF_ERR_EVENT_ADDRESSf, 589 IQ_PK_BUFF_MULTIPLE_ECC_ERRf, 590 IQ_PK_BUFF_ECC_2BIT_INTERRUPT_STATUSf, 591 IQ_PK_BUFF_ECC_1BIT_INTERRUPT_STATUSf, 592 CPRI_CPRSR_IQ_PK_BUFF_CFG_0m, 593 "CPRI Container Parser iq_pk buff memory" 594 }, 595 { 596 CPRI_RXPCS_EXTRACT_INTR_ENABLE_CONTROLr, 597 RXPCS_EXTRACT_ECC_2BIT_INTERRUPT_ENf, 598 RXPCS_EXTRACT_ECC_1BIT_INTERRUPT_ENf, 599 CPRI_RXPCS_EXTRACT_INTR_STATUSr, 600 RXPCS_EXTRACT_ERR_EVENT_ADDRESSf, 601 RXPCS_EXTRACT_MULTIPLE_ECC_ERRf, 602 RXPCS_EXTRACT_ECC_2BIT_INTERRUPT_STATUSf, 603 RXPCS_EXTRACT_ECC_1BIT_INTERRUPT_STATUSf, 604 INVALIDm, 605 "CPRI RX Extract FIFO" 606 }, 607 { 608 CPRI_RXPCS_FEC_DECODER_RAM1_INTR_ENABLE_CONTROLr, 609 RXPCS_FEC_DECODER_RAM1_ECC_2BIT_INTERRUPT_ENf, 610 RXPCS_FEC_DECODER_RAM1_ECC_1BIT_INTERRUPT_ENf, 611 CPRI_RXPCS_FEC_DECODER_RAM1_INTR_STATUSr, 612 RXPCS_FEC_DECODER_RAM1_ERR_EVENT_ADDRESSf, 613 RXPCS_FEC_DECODER_RAM1_MULTIPLE_ECC_ERRf, 614 RXPCS_FEC_DECODER_RAM1_ECC_2BIT_INTERRUPT_STATUSf, 615 RXPCS_FEC_DECODER_RAM1_ECC_1BIT_INTERRUPT_STATUSf, 616 INVALIDm, 617 "CPRI RX FEC RAM1 Memory" 618 }, 619 { 620 CPRI_RXPCS_FEC_DECODER_RAM2_INTR_ENABLE_CONTROLr, 621 RXPCS_FEC_DECODER_RAM2_ECC_2BIT_INTERRUPT_ENf, 622 RXPCS_FEC_DECODER_RAM2_ECC_1BIT_INTERRUPT_ENf, 623 CPRI_RXPCS_FEC_DECODER_RAM2_INTR_STATUSr, 624 RXPCS_FEC_DECODER_RAM2_ERR_EVENT_ADDRESSf, 625 RXPCS_FEC_DECODER_RAM2_MULTIPLE_ECC_ERRf, 626 RXPCS_FEC_DECODER_RAM2_ECC_2BIT_INTERRUPT_STATUSf, 627 RXPCS_FEC_DECODER_RAM2_ECC_1BIT_INTERRUPT_STATUSf, 628 INVALIDm, 629 "CPRI RX FEC RAM2 Memory" 630 }, 631 { 632 INVALIDr, INVALIDf, INVALIDf, 633 INVALIDr, INVALIDf, INVALIDf, INVALIDf, INVALIDf, 634 INVALIDm, "" 635 } 636 }; 637 638 /* CPRI Interrupts enable reg-fields info */ 639 typedef struct _cpri_interrupts_info_s { 640 int is_64bit; 641 soc_reg_t enable_reg; 642 soc_field_t enable_field; 643 int min_id; /* min queue num or AxC id */ 644 int max_id; /* max queue num or AxC id */ 645 646 int is_status_64bit; 647 soc_reg_t status_reg; 648 soc_field_t status_field; 649 650 }_cpri_interrupts_info_t; 651 652 STATIC _cpri_interrupts_info_t _cpri_port_intrs_info[_shrCpriIntrCount] = { 653 { /* _shrCpriIntrRx1588CapturedTs */ 654 0, 655 CPRI_RX_1588_CAP_INTR_ENABLE_CONTROLr, 656 RX_CAPTURED_TS_INTERRUPT_ENf, 0, 0, 657 1, 658 CPRI_RX_1588_CAP_INTR_STATUSr, 659 RX_CAPTURED_TS_INTERRUPT_STATUSf 660 }, 661 { /* _shrCpriIntrRx1588TsFifo */ 662 0, 663 CPRI_RX_1588_FIFO_INTR_ENABLE_CONTROLr, 664 RX_TS_FIFO_INTERRUPT_ENf, 0, 0, 665 1, 666 CPRI_RX_1588_FIFO_INTR_STATUSr, 667 RX_TS_FIFO_INTERRUPT_STATUSf 668 }, 669 { /* _shrCpriIntrRxEncapCtrlQOverflow */ 670 0, 671 CPRI_ENCAP_CTRL_QUEUE_INTR_ENABLEr, 672 ENCAP_CTRL_QUEUE_FAULT_INTERRUPT_ENABLE_0f, 0, 15, 673 0, 674 CPRI_ENCAP_CTRL_QUEUE_INTR_STATUSr, 675 ENCAP_CTRL_QUEUE_FAULT_INTERRUPT_STATUS_0f 676 }, 677 { /* _shrCpriIntrRxEncapDataQOverflow, */ 678 1, 679 CPRI_ENCAP_DATA_QUEUE_INTR_ENABLEr, 680 ENCAP_DATA_QUEUE_FAULT_INTERRUPT_ENABLE_0f, 0, 63, 681 1, 682 CPRI_ENCAP_DATA_QUEUE_INTR_STATUSr, 683 ENCAP_DATA_QUEUE_FAULT_INTERRUPT_STATUS_0f 684 }, 685 { /* _shrCpriIntrRxEncapGsmTsQErr */ 686 1, 687 CPRI_ENCAP_GSM_TS_ERR_QUEUE_INTR_ENABLEr, 688 ENCAP_GSM_TS_ERR_QUEUE_INTERRUPT_ENABLE_0f, 0, 63, 689 1, 690 CPRI_ENCAP_GSM_TS_ERR_QUEUE_INTR_STATUSr, 691 ENCAP_GSM_TS_ERR_QUEUE_INTERRUPT_STATUS_0f 692 }, 693 { /* _shrCpriIntrRxEncapIpsmCdcFifoErr */ 694 0, 695 CPRI_ENCAP_MISC_FIFO_QUEUE_INTR_ENABLEr, 696 ENCAP_IPSM_CDC_FIFO_FAULT_INTERRUPT_ENABLEf, 0, 0, 697 0, 698 CPRI_ENCAP_MISC_FIFO_INTR_STATUSr, 699 ENCAP_IPSM_CDC_FIFO_FAULT_INTERRUPT_STATUSf 700 }, 701 { /* _shrCpriIntrRxEncapRxFrmInFifoOverflow */ 702 0, 703 CPRI_ENCAP_MISC_FIFO_QUEUE_INTR_ENABLEr, 704 ENCAP_RXFRM_IN_FIFO_FAULT_INTERRUPT_ENABLEf, 0, 0, 705 0, 706 CPRI_ENCAP_MISC_FIFO_INTR_STATUSr, 707 ENCAP_RXFRM_IN_FIFO_FAULT_INTERRUPT_STATUSf 708 }, 709 { /* _shrCpriIntrRxEncapWqFiFoOverflow */ 710 0, 711 CPRI_ENCAP_MISC_FIFO_QUEUE_INTR_ENABLEr, 712 ENCAP_WQ_FIFO_FAULT_INTERRUPT_ENABLE_0f, 0, 3, 713 0, 714 CPRI_ENCAP_MISC_FIFO_INTR_STATUSr, 715 ENCAP_WQ_FIFO_FAULT_INTERRUPT_STATUS_0f 716 }, 717 { /* _shrCpriIntrRxFrmL1SigChange */ 718 1, 719 CPRI_RXFRM_CPRSR_INTR_ENABLE_CONTROLr, 720 RXFRM_L1_SIG_CHANGE_INTERRUPT_MASKf, 0, 0, 721 1, 722 CPRI_RXFRM_CPRSR_STATUSr, 723 RXFRM_L1_SIG_CHANGE_INTERRUPT_STATUSf 724 }, 725 { /* _shrCpriIntrRxFrmRsvd4SingleTsErr */ 726 1, 727 BRCM_RESERVED_CPM_305r, 728 BRCM_RESERVED_CPM_305_0f, 0, 63, 729 1, 730 BRCM_RESERVED_CPM_304r, 731 BRCM_RESERVED_CPM_304_0f 732 }, 733 { /* _shrCpriIntrRxFrmRsvd4Ts */ 734 1, 735 BRCM_RESERVED_CPM_303r, 736 BRCM_RESERVED_CPM_303_0f, 0, 63, 737 BRCM_RESERVED_CPM_302r, 738 BRCM_RESERVED_CPM_302_0f 739 }, 740 { /* _shrCpriIntrRxGcw */ 741 0, 742 CPRI_RX_GCW_INTR_ENABLE_CONTROLr, 743 RXFRM_GCW_INTERRUPT_ENf, 0, 15, 744 0, 745 CPRI_RX_GCW_INTR_STATUSr, 746 RXFRM_GCW_WORD_0_INTERRUPT_STATUSf 747 }, 748 { /* _shrCpriIntrRxPcs64B66BBlkLckLh */ 749 0, 750 CPRI_RXPCS_INTR_ENABLEr, 751 RXPCS_64B66B_BLOCK_LOCK_LH_INTERRUPT_ENf, 0, 0, 752 0, 753 CPRI_RXPCS_INTR_STATUSr, 754 RXPCS_64B66B_BLOCK_LOCK_LH_INTERRUPT_STATUSf 755 }, 756 { /* _shrCpriIntrRxPcs64B66BBlkLckLl */ 757 0, 758 CPRI_RXPCS_INTR_ENABLEr, 759 RXPCS_64B66B_BLOCK_LOCK_LL_INTERRUPT_ENf, 0, 0, 760 0, 761 CPRI_RXPCS_INTR_STATUSr, 762 RXPCS_64B66B_BLOCK_LOCK_LL_INTERRUPT_STATUSf 763 }, 764 { /* _shrCpriIntrRxPcs64B66BHiBerLh */ 765 0, 766 CPRI_RXPCS_INTR_ENABLEr, 767 RXPCS_64B66B_HI_BER_LH_INTERRUPT_ENf, 0, 0, 768 0, 769 CPRI_RXPCS_INTR_STATUSr, 770 RXPCS_64B66B_HI_BER_LH_INTERRUPT_STATUSf 771 }, 772 { /* _shrCpriIntrRxPcs64B66BHiBerLl */ 773 0, 774 CPRI_RXPCS_INTR_ENABLEr, 775 RXPCS_64B66B_HI_BER_LL_INTERRUPT_ENf, 0, 0, 776 0, 777 CPRI_RXPCS_INTR_STATUSr, 778 RXPCS_64B66B_HI_BER_LL_INTERRUPT_STATUSf 779 }, 780 { /* _shrCpriIntrRxPcsExtractFifoOvrFlow */ 781 0, 782 CPRI_RXPCS_INTR_ENABLEr, 783 RXPCS_EXTRACT_FIFO_OVERFLOW_INTERRUPT_ENf, 0, 0, 784 0, 785 CPRI_RXPCS_INTR_STATUSr, 786 RXPCS_EXTRACT_FIFO_OVERFLOW_INTERRUPT_STATUSf 787 }, 788 { /* _shrCpriIntrRxPcsFecCsCwBad */ 789 0, 790 CPRI_RXPCS_FEC_INTR_ENABLE_CONTROLr, 791 RXPCS_FEC_CS_CW_BAD_DURING_SYNC_INTERRUPT_ENf, 0, 0, 792 0, 793 CPRI_RXPCS_FEC_INTR_STATUSr, 794 RXPCS_FEC_CS_CW_BAD_DURING_SYNC_INTERRUPT_STATUSf 795 }, 796 { /* _shrCpriIntrRxPcsLinkStatusLh */ 797 0, 798 CPRI_RXPCS_INTR_ENABLEr, 799 RXPCS_LINK_STATUS_LH_INTERRUPT_ENf, 0, 0, 800 0, 801 CPRI_RXPCS_INTR_STATUSr, 802 RXPCS_LINK_STATUS_LH_INTERRUPT_STATUSf 803 }, 804 { /* _shrCpriIntrRxPcsLinkStatusLl */ 805 0, 806 CPRI_RXPCS_INTR_ENABLEr, 807 RXPCS_LINK_STATUS_LL_INTERRUPT_ENf, 0, 0, 808 0, 809 CPRI_RXPCS_INTR_STATUSr, 810 RXPCS_LINK_STATUS_LL_INTERRUPT_STATUSf 811 }, 812 { /* _shrCpriIntrRxPcsLosLh */ 813 0, 814 CPRI_RXPCS_INTR_ENABLEr, 815 RXPCS_LOS_LH_INTERRUPT_ENf, 0, 0, 816 0, 817 CPRI_RXPCS_INTR_STATUSr, 818 RXPCS_LOS_LH_INTERRUPT_STATUSf 819 }, 820 { /* _shrCpriIntrRxPcsLosLl */ 821 0, 822 CPRI_RXPCS_INTR_ENABLEr, 823 RXPCS_LOS_LL_INTERRUPT_ENf, 0, 0, 824 0, 825 CPRI_RXPCS_INTR_STATUSr, 826 RXPCS_LOS_LL_INTERRUPT_STATUSf 827 }, 828 { /* _shrCpriIntrTx1588CapturedTs */ 829 0, 830 CPRI_TX_1588_CAP_INTR_ENABLE_CONTROLr, 831 TX_CAPTURED_TS_INTERRUPT_ENf, 0, 0, 832 0, 833 CPRI_TX_1588_CAP_INTR_STATUSr, 834 TX_CAPTURED_TS_INTERRUPT_STATUSf 835 }, 836 { /* _shrCpriIntrTx1588TsFifo */ 837 0, 838 CPRI_TX_1588_FIFO_INTR_ENABLE_CONTROLr, 839 TX_TS_FIFO_INTERRUPT_ENf, 0, 0, 840 0, 841 CPRI_TX_1588_FIFO_INTR_STATUSr, 842 TX_TS_FIFO_INTERRUPT_STATUSf 843 }, 844 { /* _shrCpriIntrTxDecapAgModePktMiss */ 845 1, 846 CPRI_DECAP_AGNOSTIC_MODE_INTR_ENABLEr, 847 DECAP_AGNOSTIC_MODE_MISSING_PKT_INTERRUPT_ENABLEf, 0, 0, 848 1, 849 CPRI_DECAP_AGNOSTIC_MODE_INTR_STATUSr, 850 DECAP_AGNOSTIC_MODE_MISSING_PKT_INTERRUPT_STATUSf 851 }, 852 { /* _shrCpriIntrTxDecapDataQBuffSizeErr */ 853 1, 854 CPRI_DECAP_DATA_QUEUE_BUFFSIZE_INTR_ENABLEr, 855 DECAP_DATA_QUEUE_BUFFSIZE_INTERRUPT_ENABLE_0f, 0, 63, 856 1, 857 CPRI_DECAP_DATA_QUEUE_BUFFSIZE_INTR_STATUSr, 858 DECAP_DATA_QUEUE_BUFFSIZE_INTERRUPT_STATUS_0f 859 }, 860 { /* _shrCpriIntrTxDecapDataQOvflErr */ 861 1, 862 CPRI_DECAP_DATA_QUEUE_OVERFLOW_INTR_ENABLEr, 863 DECAP_DATA_QUEUE_OVERFLOW_INTERRUPT_ENABLE_0f, 0,63, 864 1, 865 CPRI_DECAP_DATA_QUEUE_OVERFLOW_INTR_STATUSr, 866 DECAP_DATA_QUEUE_OVERFLOW_INTERRUPT_STATUS_0f 867 }, 868 { /* _shrCpriIntrTxDecapDataQUdfllErr */ 869 1, 870 CPRI_DECAP_DATA_QUEUE_UNDERFLOW_INTR_ENABLEr, 871 DECAP_DATA_QUEUE_UNDERFLOW_INTERRUPT_ENABLE_0f, 0, 63, 872 1, 873 CPRI_DECAP_DATA_QUEUE_UNDERFLOW_INTR_STATUSr, 874 DECAP_DATA_QUEUE_UNDERFLOW_INTERRUPT_STATUS_0f 875 }, 876 { /* _shrCpriIntrTxFrmArbCpriAckMismatch */ 877 1, 878 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 879 TXFRM_ARB_CPRI_ACK_MISMATCH_INTERRUPT_ENf, 0, 0, 880 1, 881 CPRI_TXFRM_INTR_STATUSr, 882 TXFRM_ARB_CPRI_ACK_MISMATCH_INTERRUPT_STATUSf 883 }, 884 { /* _shrCpriIntrTxFrmArbOBSAIAckMisalign */ 885 1, 886 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 887 BRCM_RESERVED_CPM_11_4f, 0, 0, 888 1, 889 CPRI_TXFRM_INTR_STATUSr, 890 BRCM_RESERVED_CPM_10_4f 891 }, 892 { /* _shrCpriIntrTxFrmArbOBSAIReqConflict */ 893 1, 894 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 895 BRCM_RESERVED_CPM_11_3f, 0, 0, 896 1, 897 CPRI_TXFRM_INTR_STATUSr, 898 BRCM_RESERVED_CPM_10_3f 899 }, 900 { /* _shrCpriIntrTxFrmArbPsizeZero */ 901 1, 902 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 903 TXFRM_ARB_PSIZE_ZERO_INTERRUPT_ENf, 0, 0, 904 1, 905 CPRI_TXFRM_INTR_STATUSr, 906 TXFRM_ARB_PSIZE_ZERO_INTERRUPT_STATUSf 907 }, 908 { /* _shrCpriIntrTxFrmBfaHfStartMisalign */ 909 1, 910 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 911 TXFRM_BFA_HF_START_MISALIGN_INTERRUPT_ENf, 0, 0, 912 1, 913 CPRI_TXFRM_INTR_STATUSr, 914 TXFRM_BFA_HF_START_MISALIGN_INTERRUPT_STATUSf 915 }, 916 { /* _shrCpriIntrTxFrmCwaCtrlPktFlowIdErr */ 917 1, 918 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 919 TXFRM_CWA_CTRL_PACKET_FLOW_ID_ERR_INTERRUPT_ENf, 0, 0, 920 1, 921 CPRI_TXFRM_INTR_STATUSr, 922 TXFRM_CWA_CTRL_PACKET_FLOW_ID_ERR_INTERRUPT_STATUSf 923 }, 924 { /* _shrCpriIntrTxFrmCwaFastEthBufferOverflow */ 925 1, 926 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 927 TXFRM_CWA_FAST_ETH_BUFFER_OVERFLOW_INTERRUPT_ENf, 0, 0, 928 1, 929 CPRI_TXFRM_INTR_STATUSr, 930 TXFRM_CWA_FAST_ETH_BUFFER_OVERFLOW_INTERRUPT_STATUSf 931 }, 932 { /* _shrCpriIntrTxFrmCwaHdlcBufferOverflow */ 933 1, 934 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 935 TXFRM_CWA_HDLC_BUFFER_OVERFLOW_INTERRUPT_ENf, 0, 0, 936 1, 937 CPRI_TXFRM_INTR_STATUSr, 938 TXFRM_CWA_HDLC_BUFFER_OVERFLOW_INTERRUPT_STATUSf 939 }, 940 { /* _shrCpriIntrTxFrmCwaMultipleValids */ 941 1, 942 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 943 TXFRM_CWA_MULTIPLE_VALIDS_INTERRUPT_ENf, 0, 0, 944 1, 945 CPRI_TXFRM_INTR_STATUSr, 946 TXFRM_CWA_MULTIPLE_VALIDS_INTERRUPT_STATUSf 947 }, 948 { /* _shrCpriIntrTxFrmCwaSdvmBufferOverflow */ 949 1, 950 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 951 BRCM_RESERVED_CPM_11_5f, 0, 0, 952 1, 953 CPRI_TXFRM_INTR_STATUSr, 954 BRCM_RESERVED_CPM_10_6f 955 }, 956 { /* _shrCpriIntrTxFrmCwaSdvmProcOverflow */ 957 1, 958 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 959 BRCM_RESERVED_CPM_11_2f, 0, 0, 960 1, 961 CPRI_TXFRM_INTR_STATUSr, 962 BRCM_RESERVED_CPM_10_3f 963 }, 964 { /* _shrCpriIntrTxFrmCwaVsdRawBufferOverflow */ 965 1, 966 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 967 TXFRM_CWA_VSD_RAW_BUFFER_OVERFLOW_INTERRUPT_ENf, 0, 0, 968 1, 969 CPRI_TXFRM_INTR_STATUSr, 970 TXFRM_CWA_VSD_RAW_BUFFER_OVERFLOW_INTERRUPT_STATUSf 971 }, 972 { /* _shrCpriIntrTxFrmDrAckMisalign */ 973 1, 974 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 975 BRCM_RESERVED_CPM_11_1f, 0, 0, 976 1, 977 CPRI_TXFRM_INTR_STATUSr, 978 BRCM_RESERVED_CPM_10_2f 979 }, 980 { /* _shrCpriIntrTxFrmDrMultiEthPsizeUndersize */ 981 1, 982 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 983 BRCM_RESERVED_CPM_11_0f, 0, 0, 984 1, 985 CPRI_TXFRM_INTR_STATUSr, 986 BRCM_RESERVED_CPM_10_1f 987 }, 988 { /* _shrCpriIntrTxFrmMultiEthBufferOverflow */ 989 1, 990 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 991 BRCM_RESERVED_CPM_11_6f, 0, 0, 992 1, 993 CPRI_TXFRM_INTR_STATUSr, 994 BRCM_RESERVED_CPM_10_7f 995 }, 996 { /* _shrCpriIntrTxFrmMultiEthBufferUnderflow */ 997 1, 998 CPRI_TXFRM_INTR_ENABLE_CONTROLr, 999 BRCM_RESERVED_CPM_11_7f, 0, 0, 1000 1, 1001 CPRI_TXFRM_INTR_STATUSr, 1002 BRCM_RESERVED_CPM_10_8f 1003 }, 1004 { /* _shrCpriIntrTxGcw */ 1005 0, 1006 CPRI_TXFRM_CWA_GCW_INTR_ENABLE_CONTROLr, 1007 TXFRM_GCW_WORD_INSERTED_INTERRUPT_ENf, 0, 15, 1008 0, 1009 CPRI_TXFRM_CWA_GCW_INTR_STATUSr, 1010 TXFRM_GCW_WORD_INSERTED_0_INTERRUPT_STATUSf 1011 }, 1012 { /* _shrCpriIntrTxPcsFifoOverflow */ 1013 1, 1014 CPRI_TXPCS_INTR_ENABLE_CONTROLr, 1015 TX_PCS_FIFO_OVERFLOW_INTERRUPT_ENf, 0, 0, 1016 1, 1017 CPRI_TXPCS_INTR_STATUSr, 1018 TX_PCS_FIFO_OVERFLOW_INTERRUPT_STATUSf 1019 }, 1020 { /* _shrCpriIntrTxPcsFifoUnderflow */ 1021 1, 1022 CPRI_TXPCS_INTR_ENABLE_CONTROLr, 1023 TX_PCS_FIFO_UNDERFLOW_INTERRUPT_ENf, 0, 0, 1024 1, 1025 CPRI_TXPCS_INTR_STATUSr, 1026 TX_PCS_FIFO_UNDERFLOW_INTERRUPT_STATUSf 1027 }, 1028 { /* _shrCpriIntrTxPcsGboxOverflow */ 1029 1, 1030 CPRI_TXPCS_INTR_ENABLE_CONTROLr, 1031 TX_PCS_GBOX_OVERFLOW_INTERRUPT_ENf, 0, 0, 1032 1, 1033 CPRI_TXPCS_INTR_STATUSr, 1034 TX_PCS_GBOX_OVERFLOW_INTERRUPT_STATUSf 1035 }, 1036 { /* _shrCpriIntrTxPcsGboxUnderflow */ 1037 1, 1038 CPRI_TXPCS_INTR_ENABLE_CONTROLr, 1039 TX_PCS_GBOX_UNDERFLOW_INTERRUPT_ENf, 0, 0, 1040 1, 1041 CPRI_TXPCS_INTR_STATUSr, 1042 TX_PCS_GBOX_UNDERFLOW_INTERRUPT_STATUSf 1043 } 1044 }; 1045 1046 #ifdef CPRIMOD_SUPPORT_ECC_INJECT 1047 1048 /* CPRI ECC error inject types */ 1049 typedef enum _cpri_ecc_inject_type_e{ 1050 _cpriEccInjectnoErr = 0, 1051 _cpriEccInject2bErrOnWrite = 1, 1052 _cpriEccInject1bErrOnRead = 2, 1053 _cpriEccInject2bErrOnRead = 3, 1054 _cpriEccInjectCount 1055 }_cpri_ecc_inject_type_t; 1056 1057 /* CPRI ECC inject enable/disable info */ 1058 1059 typedef struct _cpri_ecc_inject_ctl_s { 1060 soc_reg_t en_r; /* ecc error inject enable reg */ 1061 soc_field_t en_f; /* ecc(i-bit, 2-bit) error inject field */ 1062 soc_reg_t dis_r; /* ecc error inject disable reg */ 1063 soc_field_t dis_f; /* ecc error disable field */ 1064 }_cpri_ecc_inject_ctrl_t; 1065 1066 STATIC _cpri_ecc_inject_ctrl_t _cpri_ecc_err_ctrl_info[] = 1067 { 1068 { 1069 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1070 WQ_3_CORRUPT_ECCf, 1071 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1072 WQ_3_DISABLE_ECCf 1073 }, 1074 { 1075 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1076 WQ_2_CORRUPT_ECCf, 1077 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1078 WQ_2_DISABLE_ECCf 1079 }, 1080 { 1081 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1082 WQ_1_CORRUPT_ECCf, 1083 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1084 WQ_1_DISABLE_ECCf 1085 }, 1086 { 1087 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1088 WQ_0_CORRUPT_ECCf, 1089 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1090 WQ_0_DISABLE_ECCf 1091 }, 1092 { 1093 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1094 SEQ_NUM_DATA_CORRUPT_ECCf, 1095 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1096 SEQ_NUM_DATA_DISABLE_ECCf 1097 }, 1098 { 1099 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1100 SEQ_NUM_CTL_CORRUPT_ECCf, 1101 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1102 SEQ_NUM_CTL_DISABLE_ECCf 1103 }, 1104 { 1105 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1106 RX_FRM_1_CORRUPT_ECCf, 1107 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1108 RX_FRM_1_DISABLE_ECCf 1109 }, 1110 { 1111 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1112 RX_FRM_0_CORRUPT_ECCf, 1113 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1114 RX_FRM_0_DISABLE_ECCf 1115 }, 1116 { 1117 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1118 QUEUE_CFG_CORRUPT_ECCf, 1119 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1120 QUEUE_CFG_DISABLE_ECCf 1121 }, 1122 { 1123 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1124 PKT_CNT_CORRUPT_ECCf, 1125 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1126 PKT_CNT_DISABLE_ECCf 1127 }, 1128 { 1129 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1130 ORDERING_INFO_CORRUPT_ECCf, 1131 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1132 ORDERING_INFO_DISABLE_ECCf 1133 }, 1134 { 1135 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1136 ETH_HDR_CORRUPT_ECCf, 1137 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1138 ETH_HDR_DISABLE_ECCf 1139 }, 1140 { 1141 CPRI_ENCAP_CORRUPT_ECC_CTRLr, 1142 ENCAP_MEM_CORRUPT_ECCf, 1143 CPRI_ENCAP_DISABLE_ECC_CTRLr, 1144 ENCAP_MEM_DISABLE_ECCf 1145 }, 1146 { 1147 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1148 SEQ_OFF_CORRUPT_ECCf, 1149 CPRI_DECAP_DISABLE_ECC_CTRLr, 1150 SEQ_OFF_DISABLE_ECCf 1151 }, 1152 { 1153 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1154 QUEUE_CFG_CORRUPT_ECCf, 1155 CPRI_DECAP_DISABLE_ECC_CTRLr, 1156 QUEUE_CFG_DISABLE_ECCf 1157 }, 1158 { 1159 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1160 PKT_CNT_CORRUPT_ECCf, 1161 CPRI_DECAP_DISABLE_ECC_CTRLr, 1162 PKT_CNT_DISABLE_ECCf 1163 }, 1164 { 1165 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1166 ORDERING_INFO_CORRUPT_ECCf, 1167 CPRI_DECAP_DISABLE_ECC_CTRLr, 1168 ORDERING_INFO_DISABLE_ECCf 1169 }, 1170 { 1171 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1172 MEM_BUF_1_CORRUPT_ECCf, 1173 CPRI_DECAP_DISABLE_ECC_CTRLr, 1174 MEM_BUF_1_DISABLE_ECCf 1175 }, 1176 { 1177 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1178 MEM_BUF_0_CORRUPT_ECCf, 1179 CPRI_DECAP_DISABLE_ECC_CTRLr, 1180 MEM_BUF_0_DISABLE_ECCf 1181 }, 1182 { 1183 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1184 FLOWID_QUEUE_CORRUPT_ECCf, 1185 CPRI_DECAP_DISABLE_ECC_CTRLr, 1186 FLOWID_QUEUE_DISABLE_ECCf 1187 }, 1188 { 1189 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1190 DECAP_MEM_CORRUPT_ECCf, 1191 CPRI_DECAP_DISABLE_ECC_CTRLr, 1192 DECAP_MEM_DISABLE_ECCf 1193 }, 1194 { 1195 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1196 COMP_TAB_Q_CORRUPT_ECC_Bf, 1197 CPRI_DECAP_DISABLE_ECC_CTRLr, 1198 COMP_TAB_Q_DISABLE_ECCf 1199 }, 1200 { 1201 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1202 COMP_TAB_Q_CORRUPT_ECC_Af, 1203 CPRI_DECAP_DISABLE_ECC_CTRLr, 1204 COMP_TAB_Q_DISABLE_ECCf 1205 }, 1206 { 1207 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1208 COMP_TAB_I_CORRUPT_ECC_Bf, 1209 CPRI_DECAP_DISABLE_ECC_CTRLr, 1210 COMP_TAB_I_DISABLE_ECCf 1211 }, 1212 { 1213 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1214 COMP_TAB_I_CORRUPT_ECC_Af, 1215 CPRI_DECAP_DISABLE_ECC_CTRLr, 1216 COMP_TAB_I_DISABLE_ECCf 1217 }, 1218 { 1219 CPRI_DECAP_CORRUPT_ECC_CTRLr, 1220 CLS_QUEUE_CORRUPT_ECCf, 1221 CPRI_DECAP_DISABLE_ECC_CTRLr, 1222 CLS_QUEUE_DISABLE_ECCf 1223 }, 1224 { 1225 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1226 RXPCS_FEC_DECODER_RAM2_CORRUPT_ECCf, 1227 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1228 RXPCS_FEC_DECODER_RAM2_DISABLE_ECCf 1229 }, 1230 { 1231 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1232 RXPCS_FEC_DECODER_RAM1_CORRUPT_ECCf, 1233 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1234 RXPCS_FEC_DECODER_RAM1_DISABLE_ECCf 1235 }, 1236 { 1237 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1238 RXPCS_EXTRACT_CORRUPT_ECCf, 1239 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1240 RXPCS_EXTRACT_DISABLE_ECCf 1241 }, 1242 { 1243 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1244 IQ_PK_BUFF_CORRUPT_ECCf, 1245 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1246 IQ_PK_BUFF_DISABLE_ECCf 1247 }, 1248 { 1249 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1250 IQ_PK_BUFF_AXC_STATE_CORRUPT_ECCf, 1251 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1252 IQ_PK_BUFF_AXC_STATE_DISABLE_ECCf 1253 }, 1254 { 1255 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1256 IQ_PK_BUFF_AXC_PLD_CORRUPT_ECCf, 1257 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1258 IQ_PK_BUFF_AXC_PLD_DISABLE_ECCf 1259 }, 1260 { 1261 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1262 CPRSR_MAP_TAB_CORRUPT_ECCf, 1263 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1264 CPRSR_MAP_TAB_DISABLE_ECCf 1265 }, 1266 { 1267 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1268 CPRSR_MAP_STATE_TAB_CORRUPT_ECCf, 1269 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1270 CPRSR_MAP_STATE_TAB_DISABLE_ECCf 1271 }, 1272 { 1273 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1274 CFLW_PGC_TAB_CORRUPT_ECCf, 1275 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1276 CFLW_PGC_TAB_DISABLE_ECCf 1277 }, 1278 { 1279 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1280 CFLW_BUF_TAB_CORRUPT_ECCf, 1281 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1282 CFLW_BUF_TAB_DISABLE_ECCf 1283 }, 1284 { 1285 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1286 BFRM_MAP_TAB1_CORRUPT_ECCf, 1287 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1288 BFRM_MAP_TAB1_DISABLE_ECCf 1289 }, 1290 { 1291 CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRLr, 1292 BFRM_MAP_TAB0_CORRUPT_ECCf, 1293 CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRLr, 1294 BFRM_MAP_TAB0_DISABLE_ECCf 1295 }, 1296 { 1297 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1298 TX_FIFO_CORRUPT_ECCf, 1299 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1300 TX_FIFO_DISABLE_ECCf 1301 }, 1302 { 1303 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1304 IQU_STATE_CORRUPT_ECCf, 1305 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1306 IQU_STATE_DISABLE_ECCf 1307 }, 1308 { 1309 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1310 IQU_BUFFER_CORRUPT_ECCf, 1311 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1312 IQU_BUFFER_DISABLE_ECCf 1313 }, 1314 { 1315 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1316 FLOW_CONFIG_CORRUPT_ECCf, 1317 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1318 FLOW_CONFIG_DISABLE_ECCf 1319 }, 1320 { 1321 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1322 FLOW_BUFFER1_CORRUPT_ECCf, 1323 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1324 FLOW_BUFFER1_DISABLE_ECCf 1325 }, 1326 { 1327 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1328 FLOW_BUFFER0_CORRUPT_ECCf, 1329 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1330 FLOW_BUFFER0_DISABLE_ECCf 1331 }, 1332 { 1333 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1334 CA_STATE_TAB_CORRUPT_ECCf, 1335 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1336 CA_STATE_TAB_DISABLE_ECCf 1337 }, 1338 { 1339 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1340 CA_PAY_TAB_CORRUPT_ECCf, 1341 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1342 CA_PAY_TAB_DISABLE_ECCf 1343 }, 1344 { 1345 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1346 CA_MAP_TAB_CORRUPT_ECCf, 1347 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1348 CA_MAP_TAB_DISABLE_ECCf 1349 }, 1350 { 1351 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1352 BFA_MAP_TAB1_CORRUPT_ECCf, 1353 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1354 BFA_MAP_TAB1_DISABLE_ECCf 1355 }, 1356 { 1357 CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRLr, 1358 BFA_MAP_TAB0_CORRUPT_ECCf, 1359 CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRLr, 1360 BFA_MAP_TAB0_DISABLE_ECCf 1361 }, 1362 { 1363 INVALIDr, 1364 INVALIDf, 1365 INVALIDr, 1366 INVALIDf 1367 } 1368 }; 1369 #endif /* CPRIMOD_SUPPORT_ECC_INJECT */ 1370 1371 #endif /* _CPRIF_DRV_PRIVATE_H_ */