cprif_drv.h (99035B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #ifndef _CPRIF_DRV_H_ 11 #define _CPRIF_DRV_H_ 12 13 #include <soc/cprimod/cprimod.h> 14 #include <appl/diag/diag.h> 15 16 17 #define CPRIF_REV_LETTER_A 0 18 #define CPRIF_REV_LETTER_B 1 19 #define CPRIF_REV_LETTER_C 2 20 #define CPRIF_REV_LETTER_D 3 21 22 #define CPRIF_REV_NUMBER_0 0 23 #define CPRIF_REV_NUMBER_1 1 24 #define CPRIF_REV_NUMBER_2 2 25 #define CPRIF_REV_NUMBER_3 3 26 #define CPRIF_REV_NUMBER_4 4 27 #define CPRIF_REV_NUMBER_5 5 28 #define CPRIF_REV_NUMBER_6 6 29 #define CPRIF_REV_NUMBER_7 7 30 31 #define CPRIF_TECH_PROCESS_28NM 0 32 #define CPRIF_TECH_PROCESS_16NM 1 33 34 #define CPRIF_PM_TYPE_PM4X10 0 35 #define CPRIF_PM_TYPE_PM4X25 1 36 #define CPRIF_PM_TYPE_PM12X10 2 37 #define CPRIF_PM_TYPE_PM4X10Q 3 38 #define CPRIF_PM_TYPE_FCPM 4 39 #define CPRIF_PM_TYPE_PM4X10_GEN3 5 40 #define CPRIF_PM_TYPE_PM4X25_GEN3 6 41 #define CPRIF_PM_TYPE_CPM4X25_GEN3 7 42 43 #define CPRIF_MAX_NUM_OF_QUEUES 80 44 #define CPRIF_MAX_NUM_OF_DATA_QUEUES 64 45 #define CPRIF_MAX_NUM_OF_AXC 64 46 #define CPRIF_BASIC_FRAME_TABLE_0 0 47 #define CPRIF_BASIC_FRAME_TABLE_1 1 48 49 /*! 50 * @struct cprimod_bfa_bfp_table_entry_s 51 * @brief Basic Frame Parse/Assembler HW Table Entry 52 */ 53 typedef struct cprif_pm_version_s { 54 uint32 pm_type; /**< 0 pm4x10 1 pm4x25 etc. */ 55 uint32 tech_process; /**< 0 28nm 1 16nm etc */ 56 uint32 rev_number; /**< Rev Number */ 57 uint32 rev_letter; /**< Rev Letter 0 A 1 B 2 C .. */ 58 }cprif_pm_version_t; 59 60 typedef enum cprif_reset_en_s { 61 cpriResetEnAssert=1, 62 cpriResetEnDeassert=0 63 } cprif_reset_en_t; 64 65 #define CPRIF_CLPORT_IS_A0(pm_version) ((pm_version.rev_letter == CPRIF_REV_LETTER_A) && (pm_version.rev_number == CPRIF_REV_NUMBER_0)) 66 #define CPRIF_CLPORT_IS_B0(pm_version) ((pm_version.rev_letter == CPRIF_REV_LETTER_B) && (pm_version.rev_number == CPRIF_REV_NUMBER_0)) 67 68 #define CPRIF_RX_INTR 0x1 69 #define CPRIF_TX_INTR 0x2 70 71 /* CPRI port Rx/Tx interrupt status */ 72 #define CPRIF_PORT_0_RX_INTR 0x1 73 #define CPRIF_PORT_1_RX_INTR 0x2 74 #define CPRIF_PORT_2_RX_INTR 0x4 75 #define CPRIF_PORT_3_RX_INTR 0x8 76 #define CPRIF_PORT_0_TX_INTR 0x10 77 #define CPRIF_PORT_1_TX_INTR 0x20 78 #define CPRIF_PORT_2_TX_INTR 0x40 79 #define CPRIF_PORT_3_TX_INTR 0x80 80 81 #define CPRIF_RX_OP_ERR_INTR 0x1 82 #define CPRIF_RX_FUNC_ERR_INTR 0x2 83 #define CPRIF_RX_ECC_ERR_INTR 0x4 84 #define CPRIF_RX_INTR_ALL 0x7 85 86 /* Macros for RX Operational Error Interrupts */ 87 #define CPRI_INTR_RX_ENCAP_DATA_Q_OVRFLOW 0x1 88 #define CPRI_INTR_RX_ENCAP_CTRL_Q_OVRFLOW 0x2 89 #define CPRI_INTR_RX_ENCAP_GSM_TIMESTAMP 0x4 90 #define CPRI_INTR_RX_ENCAP_MISC_ERROR 0x8 91 #define CPRI_INTR_RX_ENCAP_RSVD4_EVENTS 0x10 92 #define CPRI_INTR_RX_OP_ERR_INTR_ALL 0x1F 93 94 /* Macros for RX Functional Error Interrupts */ 95 #define CPRI_INTR_RXFRM_CW_PARSER 0x1 96 #define CPRI_INTR_RX_1588_SW 0x2 97 #define CPRI_INTR_RX_1588_FIFO 0x4 98 #define CPRI_INTR_RXFRM_GCW 0x8 99 #define CPRI_INTR_RXPCS 0x10 100 #define CPRI_INTR_RXPCS_FEC 0x20 101 #define CPRI_INTR_RX_FUNC_ERR_INTR_ALL 0x3F 102 103 104 #define CPRIF_TX_OP_ERR_INTR 0x1 105 #define CPRIF_TX_FUNC_ERR_INTR 0x2 106 #define CPRIF_TX_ECC_ERR_INTR 0x4 107 #define CPRIF_TX_INTR_ALL 0x7 108 109 /* Macros for RX Operational Error Interrupts */ 110 #define CPRI_INTR_TX_DECAP_DATA_Q_OVRFLOW 0x1 111 #define CPRI_INTR_TX_DECAP_DATA_Q_UNDRFLOW 0x2 112 #define CPRI_INTR_TX_DECAP_DATA_Q_BUFFSIZE_ERR 0x4 113 #define CPRI_INTR_TX_DECAP_AG_MODE_INTR 0x8 114 #define CPRI_INTR_TX_TXPCS_MISC_INTR 0x10 115 #define CPRI_INTR_TX_OP_ERR_INTR_ALL 0x1F 116 117 /* Macros for TX Functional Error Interrupts */ 118 #define CPRI_INTR_TX_1588_SW 0x1 119 #define CPRI_INTR_TX_1588_FIFO 0x2 120 #define CPRI_INTR_TX_GCW 0x4 121 #define CPRI_INTR_TX_FUNC_ERR_INTR_ALL 0x7 122 123 124 /*! 125 * @struct cprimod_bfa_bfp_table_entry_s 126 * @brief Basic Frame Parse/Assembler HW Table Entry 127 */ 128 typedef struct cprimod_bfa_bfp_table_entry_s { 129 uint8 axc_id; /**< AxC Id */ 130 uint8 rsrv_bit_cnt; /**< Number of Reserve Bits */ 131 uint8 data_bit_cnt; /**< Number of Data Bits */ 132 }cprif_bfa_bfp_table_entry_t; 133 134 #define CPRIF_CONTAINER_MAP_CPRI_METHOD_1 0 135 #define CPRIF_CONTAINER_MAP_CPRI_METHOD_3 2 136 #define CPRIF_CONTAINER_MAP_RSVD4 3 137 138 #define CPRIF_CONTAINER_MAP_STUFFING_AT_END 1 139 #define CPRIF_CONTAINER_MAP_STUFFING_AT_BEGINNING 0 140 141 142 /*! 143 * @struct cprif_cpri_container_map_entry_s 144 * @brief CPRI Container Parser Entry Parameter. 145 */ 146 typedef struct cprif_cpri_container_map_entry_s { 147 uint8 map_method; /**< Map Method. */ 148 uint8 axc_id; /**< AxC Id. */ 149 uint8 stuffing_at_end; /**< Stuff at the end. */ 150 uint32 stuff_cnt; /**< Stuff Cnt */ 151 uint32 cblk_cnt; /**< Container Block Cnt */ 152 uint32 naxc_cnt; /**< Container size */ 153 uint32 Nv; /**< Number of Stuffing Bits for Method 3. */ 154 uint32 Na; /**< Number of AxC for Method 3. */ 155 uint8 rfrm_sync; /**< Radio Frame Sync . */ 156 uint8 hfrm_sync; /**< Hyper Frame Sync . */ 157 uint32 bfn_offset; /**< Radio Frame Offset */ 158 uint32 hfn_offset; /**< Hyper Frame Offset. */ 159 uint32 bfrm_offset; /**< Basic Frame Offset. */ 160 }cprif_cpri_container_map_entry_t; 161 162 /*! 163 * @struct cprif_rsvd4_container_map_entry_s 164 * @brief CPRI Container Parser Entry Parameter. 165 */ 166 typedef struct cprif_rsvd4_container_map_entry_s { 167 uint8 map_method; /**< Map Method. */ 168 uint8 axc_id; /**< AxC Id. */ 169 uint8 stuffing_at_end; /**< Stuff at the end. */ 170 uint32 stuff_cnt; /**< Stuff Cnt */ 171 uint32 cblk_cnt; /**< Container Block Cnt */ 172 uint32 rfrm_offset; /**< Radio Frame Offset MG. */ 173 uint32 bfn_offset; /**< Master Frame Offset BFN . */ 174 cprimod_rsvd4_msg_ts_mode_t msg_ts_mode; /**< MSG timestamp mode */ 175 uint8 rfrm_sync; /**< Radio Frame Sync . */ 176 uint8 hfrm_sync; /**< Hyper Frame Sync . */ 177 uint8 msg_ts_cnt; /**< Num of Msg Per Timeslot */ 178 uint8 msg_ts_sync; /**< MSG timestamp mode Rx only */ 179 uint8 use_ts_dbm; /**< use secondary DBM - Tx only */ 180 uint8 ts_dbm_prof_num; /**< secondary DBM Profile Num - Tx only */ 181 uint8 num_active_slots; /**< Num Active Slots - Tx only */ 182 uint32 msg_addr; /**< Header Addr - Tx only */ 183 uint32 msg_type; /**< Header Type- Tx Only */ 184 uint32 msg_ts_offset; /**< TS offset- Tx Only */ 185 }cprif_rsvd4_container_map_entry_t; 186 187 #define CPRIF_CONTAINER_MAP_MSG_TS_MODE_WCDMA 0 188 #define CPRIF_CONTAINER_MAP_MSG_TS_MODE_LTE 1 189 #define CPRIF_CONTAINER_MAP_MSG_TS_MODE_GSM_DL 2 190 #define CPRIF_CONTAINER_MAP_MSG_TS_MODE_GSM_UL 3 191 192 /*! 193 * @struct cprif_iq_buffer_config_t 194 * @brief CPRI IQ Buffer Config 195 */ 196 typedef struct cprif_iq_buffer_config_s{ 197 uint16 payload_size; /**< Packet Size. */ 198 uint8 last_packet_num; /**< Last Packet Num. */ 199 uint16 last_payload_size; /**< Last Packet Size. */ 200 }cprif_iq_buffer_config_t; 201 202 /*! 203 * @struct cprifi_speed_osmod_div_table_s 204 * @brief CPRI speed_id, osr_mode and pll_div mapping table. 205 */ 206 typedef struct cprif_speed_osmod_div_lkup_table_s{ 207 uint8 speed_id; 208 uint8 osr_mode; 209 uint8 pll_mode; 210 uint8 pll_multiplier; 211 }cprif_speed_osmod_div_lkup_table_t; 212 213 #define OS_MODE_1 0 214 #define OS_MODE_2 1 215 #define OS_MODE_4 2 216 #define OS_MODE_8 5 217 #define OS_MODE_16 9 218 #define OS_MODE_32 13 219 220 #define CPRIF_DATA_SIGN_EXT_15_TO_16 0 221 #define CPRIF_DATA_SIGN_EXT_ADD_0 1 222 #define CPRIF_DATA_SIGN_EXT_16_TO_15 2 223 #define CPRIF_DATA_SIGN_EXT_ADD_1 3 224 225 #define CPRIF_DATA_BUFFER_BLOCK_SIZE 16 /* 16 bytess per block of encap/decap queue. */ 226 227 #define CPRIF_PBMP_WORD_WIDTH 32 /* 32 bits */ 228 #define CPRIF_ENCAP_BUFFER_NUM_ENTRIES 3648 229 #define CPRIF_DECAP_BUFFER_NUM_ENTRIES 8192 230 #define CPRIF_NUM_OF_BUFFER_ENTRIES(size_in_bytes) ((size_in_bytes + \ 231 CPRIF_DATA_BUFFER_BLOCK_SIZE-1)\ 232 / CPRIF_DATA_BUFFER_BLOCK_SIZE) 233 234 #define CPRIF_NUM_PBMP_WORDS(entries) \ 235 ((entries+CPRIF_PBMP_WORD_WIDTH-1)/CPRIF_PBMP_WORD_WIDTH) 236 237 #define CPRIF_PBMP_WORD_GET(bm,word) (bm[(word)]) 238 #define CPRIF_PBMP_WENT(idx) ((idx)/CPRIF_PBMP_WORD_WIDTH) 239 #define CPRIF_PBMP_WBIT(idx) \ 240 (1U << ((idx) % CPRIF_PBMP_WORD_WIDTH)) 241 242 #define CPRIF_PBMP_WORD_ENTRY(bm, idx) \ 243 (CPRIF_PBMP_WORD_GET(bm,CPRIF_PBMP_WENT(idx))) 244 245 #define CPRIF_PBMP_AVAILABLE(bm, idx) \ 246 ((CPRIF_PBMP_WORD_ENTRY(bm, idx) & CPRIF_PBMP_WBIT(idx)) == 0) 247 248 #define CPRIF_PBMP_IS_SET(bm, idx) \ 249 ((CPRIF_PBMP_WORD_ENTRY(bm, idx) & CPRIF_PBMP_WBIT(idx)) != 0) 250 251 #define CPRIF_PBMP_IDX_MARK(bm, idx) \ 252 ( CPRIF_PBMP_WORD_ENTRY(bm, idx) |= CPRIF_PBMP_WBIT(idx)) 253 254 #define CPRIF_PBMP_IDX_UNMARK(bm, idx) \ 255 ( CPRIF_PBMP_WORD_ENTRY(bm, idx) &= ~CPRIF_PBMP_WBIT(idx)) 256 257 #define CPRIF_PBMP_NEXT_AVAILABLE(bm, tot , idx) \ 258 for ((idx) = (idx); (idx) < tot ; (idx)++) \ 259 if (CPRIF_PBMP_AVAILABLE((bm), (idx))) 260 261 262 /*! 263 * @struct cprif_encap_decap_data_entry_t 264 * @brief Encapsulation Data Configuration 265 */ 266 typedef struct cprif_encap_decap_data_entry_s{ 267 uint8 sample_size; /**< sample size in bits. */ 268 uint8 out_sample_size; /**< out sample size in bits. */ 269 uint8 valid; /**< valid. */ 270 uint8 mux_enable; /**< mux/demux enable. */ 271 uint16 queue_offset; /**< queue offset. */ 272 uint16 queue_size; /**< queue size. Num of 16bytes*/ 273 uint8 sign_ext_enable; /**< . */ 274 uint8 sign_ext_type; /**< . */ 275 uint8 work_queue_select; /**< work queue. */ 276 uint8 bit_reversal; /**< bit reversal. */ 277 uint8 tx_cycle_size; /**< Num of packet in buffer */ 278 }cprif_encap_decap_data_entry_t; 279 280 281 #define CPRIF_RSVD4_GSM_CONTROL_LOCATION_127_120 1 282 #define CPRIF_RSVD4_GSM_CONTROL_LOCATION_63_56 0 283 284 285 #define CPRIF_RSVD4_GSM_PAD_DISABLE 0 286 #define CPRIF_RSVD4_GSM_PAD_ENABLE 1 287 288 /*! 289 * @struct cprif_rsvd4_gsm_config_t 290 * @brief Encapsulation Data Configuration 291 */ 292 typedef struct cprif_rsvd4_encap_decap_data_entry_s{ 293 uint8 gsm_pad_size; /**< GSM Pad Size */ 294 uint8 valid; /**< valid. */ 295 uint16 queue_offset; /**< queue offset. */ 296 uint32 queue_size; /**< queue size. Num of bytes*/ 297 uint8 gsm_extra_pad_size; /**< GSM extra Pad Size */ 298 uint8 work_queue_select; /**< work queue. */ 299 uint8 tx_cycle_size; /**< Num of packet in buffer */ 300 uint8 gsm_pad_enable; /**< out sample size in bits. */ 301 uint8 gsm_control_location; /**< GSM control location 1: 127:120 0: 63:56 RxOnly */ 302 uint8 bit_reversal; /**< Bit reversal control. */ 303 }cprif_rsvd4_encap_decap_data_entry_t; 304 305 306 #define CPRIF_ENCAP_HEADER_HDR_TYPE_ROE 0 307 #define CPRIF_ENCAP_HEADER_HDR_TYPE_ENCAP_NONE 1 308 309 310 #define CPRIF_ENCAP_HEADER_VLAN_TYPE_UNTAGGED 0 311 #define CPRIF_ENCAP_HEADER_VLAN_TYPE_TAGGED_VLAN_0 1 /* tagged use vlan 0 id. */ 312 #define CPRIF_ENCAP_HEADER_VLAN_TYPE_Q_IN_Q 2 313 #define CPRIF_ENCAP_HEADER_VLAN_TYPE_TAGGED_VLAN_1 3 /* tagged use vlan 1 id. */ 314 315 316 317 #define CPRIF_ENCAP_HEADER_ETHER_TYPE_INDEX_0 0 318 #define CPRIF_ENCAP_HEADER_ETHER_TYPE_INDEX_1 1 319 320 #define CPRIF_ENCAP_HEADER_FLAGS_HDR_CONFIG_SET 0x1 321 #define CPRIF_ENCAP_HEADER_FLAGS_GSM_CONFIG_SET 0x2 322 323 324 /*! 325 * @struct cprif_encap_header_entry_t 326 * @brief Encapsulation Header Configuration 327 */ 328 typedef struct cprif_encap_header_entry_s{ 329 uint8 header_type; /**< Encap Header Type 0: ROE 1: no encap */ 330 uint16 flow_id; /**< ROE flow id */ 331 uint32 ver; /**< Ver Field in Reg. */ 332 uint32 pkttype; /**< PktType Field in Reg. */ 333 uint8 ordering_info_index; 334 uint8 mac_da_index; 335 uint8 mac_sa_index; 336 uint8 vlan_type; 337 uint8 vlan_id_0_index; 338 uint8 vlan_id_1_index; 339 uint8 vlan_0_priority; 340 uint8 vlan_1_priority; 341 uint8 ether_type_index; 342 uint8 use_tagid_for_vlan; 343 uint8 use_tagid_for_flowid; 344 uint8 use_opcode; 345 uint8 roe_opcode; 346 uint8 tsn_bitmap; /* overlay */ 347 uint8 gsm_q_cnt_disable; 348 }cprif_encap_header_entry_t; 349 350 351 #define CPRIF_ORDERING_INFO_TYPE_ROE 0x0 352 #define CPRIF_ORDERING_INFO_TYPE_BFN_FOR_QCNT 0x1 353 #define CPRIF_ORDERING_INFO_TYPE_USE_PINFO 0x2 354 355 356 #define CPRIF_ORDERING_INFO_PROP_NO_INC 0x0 357 #define CPRIF_ORDERING_INFO_PROP_INC_CONST 0x1 358 #define CPRIF_ORDERING_INFO_PROP_INC_BY_PAYLOAD 0x2 359 360 361 #define CPRIF_ORDERING_INFO_TABLE_SIZE 24 362 363 364 /*! 365 * @struct cprif_encap_ordering_info_entry_t 366 * @brief Encapsulation Ordering info Entry 367 */ 368 typedef struct cprif_encap_ordering_info_entry_s{ 369 uint8 type; 370 uint8 p_size; 371 uint8 q_size; 372 uint32 max; 373 uint32 increment; 374 uint8 pcnt_prop; 375 uint8 qcnt_prop; 376 377 }cprif_encap_ordering_info_entry_t; 378 379 380 381 /*! 382 * @struct cprif_decap_ordering_info_entry_t 383 * @brief Decapsulation Ordering info + TSN Entry 384 */ 385 typedef struct cprif_decap_ordering_info_entry_s{ 386 uint8 type; 387 uint8 p_size; 388 uint8 q_size; 389 uint32 max; 390 uint32 increment; 391 uint8 pcnt_inc_p2; 392 uint8 qcnt_inc_p2; 393 uint8 pcnt_extended; 394 uint8 pcnt_pkt_count; 395 uint8 modulo_2; 396 uint32 bias; 397 uint8 gsm_tsn_bitmap; 398 }cprif_decap_ordering_info_entry_t; 399 400 #define CPRIF_NUM_BYTES_IN_MAC_ADDR 6 401 402 /* Number of MAC Addr in SA and DA table. */ 403 #define CPRIF_MAC_ADDR_TABLE_SIZE 16 404 405 #define CPRIF_VLAN_ID_TABLE_SIZE 64 406 407 #define CPRIF_DECAP_CLS_OPTION_USE_QUEUE_NUM 0 408 #define CPRIF_DECAP_CLS_OPTION_USE_FLOW_ID_TO_QUEUE 1 409 #define CPRIF_DECAP_CLS_OPTION_USE_USE_OPCODE_QUEUE 2 410 411 #define CPRIF_DECAP_CLS_FLOW_TYPE_DATA 0 412 #define CPRIF_DECAP_CLS_FLOW_TYPE_DATA_WITH_EXT 1 /* NOT USED */ 413 #define CPRIF_DECAP_CLS_FLOW_TYPE_CTRL_WITH_OPCODE 2 414 #define CPRIF_DECAP_CLS_FLOW_TYPE_CTRL 3 415 416 #define CPRIF_ETHTYPE_ROE_ETHTYPE_0 0 417 #define CPRIF_ETHTYPE_ROE_ETHTYPE_1 1 418 #define CPRIF_ETHTYPE_VLAN_TAGGED 2 419 #define CPRIF_ETHTYPE_VLAN_QINQ 3 420 421 #define CPRIF_DECAP_ROE_ETHTYPE 0 422 #define CPRIF_DECAP_FAST_ETH_ETHTYPE 1 423 #define CPRIF_DECAP_VLAN_TAGGED_ETHTYPE 2 424 #define CPRIF_DECAP_VLAN_QINQ_ETHTYPE 3 425 426 427 428 #define CPRIF_TX_TGEN_DIVIDER_NO_DIV 1 429 #define CPRIF_TX_TGEN_DIVIDER_DIV_BY_2 2 430 #define CPRIF_TX_TGEN_DIVIDER_DIV_BY_4 4 431 #define CPRIF_TX_TGEN_DIVIDER_DIV_BY_8 8 432 #define CPRIF_TX_TGEN_DIVIDER_DIV_BY_16 16 433 #define CPRIF_TX_TGEN_DIVIDER_DIV_BY_32 32 434 435 #define CPRIF_TX_TGEN_USE_BFN 0 436 #define CPRIF_TX_TGEN_USE_HFN 1 437 438 439 440 #define CPRIF_HEADER_COMPARE_DATA_FLOW 0 441 #define CPRIF_HEADER_COMPARE_CTRL_FLOW 1 442 443 /*! 444 * @struct cprif_rsvd4_header_compare_entry_t 445 * @brief RSVD4 Header Compare entry 446 */ 447 typedef struct cprif_header_compare_entry_s{ 448 uint32 valid; 449 uint32 match_data; 450 uint32 mask; 451 uint32 flow_id; 452 uint32 ctrl_flow; 453 }cprif_header_compare_entry_t; 454 455 #define CPRIF_HEADER_COMPARE_TABLE_SIZE 80 456 457 /*! 458 * @struct cprif_modulo_rule_entry_t 459 * @brief RSVD4 Modulo Rule Entry 460 */ 461 typedef struct cprif_modulo_rule_entry_s{ 462 uint8 active; 463 uint8 modulo; 464 uint8 modulo_index; 465 uint8 dbm_enable; 466 uint8 flow_id; 467 uint8 ctrl_flow; 468 }cprif_modulo_rule_entry_t; 469 470 471 472 #define CPRIF_MODULO_RULE_USE_DATA_RULE 0 473 #define CPRIF_MODULO_RULE_USE_CTRL_RULE 1 474 475 #define CPRIF_MODULO_RULE_DATA_RULE_SIZE 72 476 #define CPRIF_MODULO_RULE_CTRL_RULE_SIZE 16 477 478 #define CPRIF_MODULO_RULE_DATA_FLOW 0 479 #define CPRIF_MODULO_RULE_CTRL_FLOW 1 480 481 #define CPRIF_MODULO_RULE_MOD_1 0 482 #define CPRIF_MODULO_RULE_MOD_2 1 483 #define CPRIF_MODULO_RULE_MOD_4 2 484 #define CPRIF_MODULO_RULE_MOD_8 3 485 #define CPRIF_MODULO_RULE_MOD_16 4 486 #define CPRIF_MODULO_RULE_MOD_32 5 487 #define CPRIF_MODULO_RULE_MOD_64 6 488 489 #define CPRIF_MODULO_RULE_DBM_PROFILE_TABLE_SIZE 8 490 #define CPRIF_MODULO_RULE_MAX_DATA_FLOW 64 /* 0-63 */ 491 #define CPRIF_MODULO_RULE_MAX_CTRK_FLOW 18 /* 0-17 */ 492 493 494 /*! 495 * @struct cprif_rsvd4_dbm_rule_entry_t 496 * @brief RSVD4 Dual Bit Map Rule Entry 497 */ 498 typedef struct cprif_rsvd4_dbm_rule_entry_s{ 499 uint8 bm1_mult; 500 uint32 bm1[3]; 501 uint8 bm1_size; 502 uint32 bm2[2]; 503 uint8 bm2_size; 504 uint8 num_slots; 505 uint8 pos_index; 506 uint8 pos_entries; 507 }cprif_rsvd4_dbm_rule_entry_t; 508 509 510 #define CPRIF_DBM_RULE_PROFILE_TABLE_SIZE 8 511 #define CPRIF_DBM_RULE_POS_INDEX_START_0 0 512 #define CPRIF_DBM_RULE_POS_INDEX_START_10 1 513 #define CPRIF_DBM_RULE_POS_INDEX_START_30 2 514 #define CPRIF_DBM_RULE_POS_INDEX_START_40 3 515 #define CPRIF_DBM_RULE_POS_INDEX_START_50 4 516 #define CPRIF_DBM_RULE_POS_INDEX_START_60 5 517 #define CPRIF_DBM_RULE_POS_INDEX_START_70 6 518 519 520 #define CPRIF_DBM_RULE_POS_ENTRIES_10_IN_GROUP 0 521 #define CPRIF_DBM_RULE_POS_ENTRIES_20_IN_GROUP 1 522 #define CPRIF_DBM_RULE_POS_ENTRIES_40_IN_GROUP 2 523 #define CPRIF_DBM_RULE_POS_ENTRIES_80_IN_GROUP 3 524 525 typedef struct cprif_rsvd4_secondary_dbm_rule_entry_s{ 526 uint8 bm1_mult; 527 uint8 bm1; 528 uint8 bm1_size; 529 uint8 bm2; 530 uint8 bm2_size; 531 uint8 num_slots; 532 }cprif_rsvd4_secondary_dbm_rule_entry_t; 533 534 #define CPRIF_SECONDARY_DBM_RULE_PROFILE_TABLE_SIZE 8 535 536 typedef struct cprif_rsvd4_dbm_pos_table_entry_s{ 537 uint8 valid; 538 uint8 flow_id; 539 uint8 ctrl_flow; 540 uint8 flow_index; 541 }cprif_rsvd4_dbm_pos_table_entry_t; 542 543 #define CPRIF_DBM_POSITION_TABLE_SIZE 80 544 545 /* Standard HDLC rate definition. */ 546 #define CPRIF_HDLC_RATE_NO_HDLC 0 547 #define CPRIF_HDLC_RATE_240KBP 1 548 #define CPRIF_HDLC_RATE_480KBP 2 549 #define CPRIF_HDLC_RATE_960KBP 3 550 #define CPRIF_HDLC_RATE_1920KBP 4 551 #define CPRIF_HDLC_RATE_2400KBP 5 552 #define CPRIF_HDLC_RATE_HIGHEST 6 553 #define CPRIF_HDLC_RATE_NEGOTIATE 7 554 555 556 557 typedef struct cprif_drv_rx_control_word_status_s{ 558 uint32 hyper_frame; 559 uint32 radio_frame; 560 uint32 basic_frame; 561 uint32 protocol_ver; 562 uint32 hdlc_rate; 563 uint32 reset; 564 uint32 l1_lof; 565 uint32 l1_los; 566 uint32 l1_sdi; 567 uint32 l1_rai; 568 uint32 eth_pointer; 569 }cprif_drv_rx_control_word_status_t; 570 571 572 typedef struct cprif_drv_tx_control_word_status_s{ 573 uint32 enet_ptr; 574 uint32 l1_fun; 575 uint32 hdlc_rate; 576 uint32 protocol_ver; 577 }cprif_drv_tx_control_word_t; 578 579 580 #define CPRIF_HDLC_CRC_BYTE_NO_SWAP 0 /* [15:8][7:0] */ 581 #define CPRIF_HDLC_CRC_BYTE_SWAP 1 /* [7:0][15:8] */ 582 583 #define CPRIF_HDLC_CRC_INIT_VAL_ALL_0S 0 584 #define CPRIF_HDLC_CRC_INIT_VAL_ALL_1S 1 585 586 #define CPRIF_HDLC_USE_HDLC 0 587 #define CPRIF_HDLC_USE_FE_MAC 1 588 589 #define CPRIF_HDLC_FCS_SIZE_8_BITS 0 590 #define CPRIF_HDLC_FCS_SIZE_16_BITS 1 591 #define CPRIF_HDLC_FCS_SIZE_32_BITS 2 592 593 #define CPRIF_HDLC_FCS_CHECK 0 594 #define CPRIF_HDLC_FCS_NO_CHECK 1 /* ignore fcs */ 595 596 #define CPRIF_HDLC_FILLING_FLAG_PATTERN_7E 0 597 #define CPRIF_HDLC_FILLING_FLAG_PATTERN_7F 1 598 #define CPRIF_HDLC_FILLING_FLAG_PATTERN_FF 3 599 600 #define CPRIF_HDLC_CRC_MODE_APPEND 0 601 #define CPRIF_HDLC_CRC_MODE_REPLACE 1 602 #define CPRIF_HDLC_CRC_MODE_NO_UPDATE 2 603 604 #define CPRIF_HDLC_FLAG_SIZE_1_BYTE 0 605 #define CPRIF_HDLC_FLAG_SIZE_2_BYTE 1 606 607 typedef struct cprif_cpri_rx_hdlc_config_s{ 608 uint32 cw_sel; 609 uint32 cw_size; 610 uint32 crc_byte_swap; /* CPRIF_HDLC_CRC_BYTE_ */ 611 uint32 crc_init_val; /* CPRIF_HDLC_CRC_INIT_VAL .. */ 612 uint32 queue_num; 613 uint32 use_fe_mac; /* 0 - HDLC 1- use Fast Ethernet MAC */ 614 uint32 ignore_fcs_err; /* 0 - check fcs error. 1 - ignore fcs error. */ 615 uint32 fcs_size; /* CPRIF_HDLC_FCS_SIZE_ */ 616 uint32 runt_frame_drop; 617 uint32 long_frame_drop; 618 uint32 min_frame_size; /* in bits */ 619 uint32 max_frame_size; /* in bits */ 620 }cprif_cpri_rx_hdlc_config_t; 621 622 typedef struct cprif_cpri_tx_hdlc_config_s{ 623 uint32 cw_sel; 624 uint32 cw_size; 625 uint32 filling_flag_pattern; /* CPRIF_HDLC_FLAG_FILL_PATTERN */ 626 uint32 flag_size; /* CPRIF_HDLC_FLAG_SIZE .. */ 627 uint32 crc_byte_swap; /* CPRIF_HDLC_CRC_BYTE_ */ 628 uint32 crc_init_val; /* CPRIF_HDLC_CRC_INIT_VA */ 629 uint32 queue_num; 630 uint32 use_fe_mac; /* 0 - HDLC 1- use Fast Ethernet MAC */ 631 uint32 fcs_size; /* CPRIF_HDLC_FCS_SIZE_ */ 632 uint32 crc_mode; /* CPRIF_HDLC_CRC_MODE_ */ 633 }cprif_cpri_tx_hdlc_config_t; 634 635 636 #define CPRIF_FAST_ETH_FCS_CHECK 0 637 #define CPRIF_FAST_ETH_FCS_NO_CHECK 1 /* ignore fcs */ 638 639 #define CPRIF_FAST_ETH_CRC_NO_STRIP 0 640 #define CPRIF_FAST_ETH_CRC_STRIP 1 641 642 #define CPRIF_FAST_ETH_CRC_MODE_APPEND 0 643 #define CPRIF_FAST_ETH_CRC_MODE_REPLACE 1 644 #define CPRIF_FAST_ETH_CRC_MODE_NO_UPDATE 2 645 646 typedef struct cprif_cpri_rx_fast_eth_word_config_s{ 647 uint32 sub_channel_start; 648 uint32 sub_channel_size; 649 uint32 cw_sel; 650 uint32 cw_size; 651 }cprif_cpri_rx_fast_eth_word_config_t; 652 653 654 typedef struct cprif_cpri_rx_fast_eth_config_s{ 655 uint32 queue_num; 656 uint32 ignore_fcs_err; /* 0 - check fcs error. 1 - ignore fcs error. */ 657 uint32 min_packet_drop; 658 uint32 max_packet_drop; 659 uint32 min_packet_size; /* in bytes */ 660 uint32 max_packet_size; /* in bytes */ 661 uint32 strip_crc; 662 }cprif_cpri_rx_fast_eth_config_t; 663 664 665 typedef struct cprif_cpri_tx_fast_eth_config_s{ 666 uint32 sub_channel_start; 667 uint32 sub_channel_size; 668 uint32 cw_sel; 669 uint32 cw_size; 670 uint32 min_ipg; /* in bytes */ 671 uint32 queue_num; 672 uint32 crc_mode; /* CPRIF_FAST_ETH_CRC_MODE_ */ 673 }cprif_cpri_tx_fast_eth_config_t; 674 675 #define CPRIF_VSD_SCHAN_NUM_OF_BYTES_1 0 676 #define CPRIF_VSD_SCHAN_NUM_OF_BYTES_2 1 677 #define CPRIF_VSD_SCHAN_NUM_OF_BYTES_4 2 678 679 #define CPRIF_VSD_FLOW_NUM_OF_BYTES_2 0 680 #define CPRIF_VSD_FLOW_NUM_OF_BYTES_4 1 681 682 683 #define CPRIF_VSD_CTRL_BYTE_NO_SWAP 0 /* [15:8][7:0] */ 684 #define CPRIF_VSD_CTRL_BYTE_SWAP 1 /* [7:0][15:8] */ 685 #define CPRIF_VSD_CTRL_MAX_NUM_SECTION 128 686 #define CPRIF_VSD_CTRL_MAX_NUM_SECTOR 64 687 #define CPRIF_VSD_CTRL_NUM_GROUPS 64 688 #define CPRIF_VSD_CTRL_NUM_GROUP_PTR 64 689 #define CPRIF_VSD_CTRL_MAX_GROUP_SIZE 4 690 #define CPRIF_VSD_CTRL_MAX_FLOW_ID 128 691 692 693 694 typedef struct cprif_cpri_vsd_config_s{ 695 uint32 sub_channel_start; 696 uint32 sub_channel_size; 697 uint32 sub_channel_num_bytes; /* CPRIF_VSD_NUM_OF_BYTES .. */ 698 uint32 sub_channel_steps; 699 uint32 flow_bytes; /* CPRIF_VSD_FLOW_NUM_OF_BYTES */ 700 uint32 queue_num; 701 uint32 byte_order; 702 uint64 rsvd_mask[2]; 703 }cprif_cpri_vsd_config_t; 704 705 typedef struct cprif_cpri_rx_vsd_ctrl_flow_config_s{ 706 uint32 group_id; 707 uint32 hyper_frame_number; 708 uint32 hyper_frame_modulo; 709 uint32 filter_zero_data; 710 }cprif_cpri_rx_vsd_ctrl_flow_config_t; 711 712 typedef struct cprif_cpri_vsd_ctrl_group_config_s{ 713 uint32 hyper_frame_number; 714 uint32 hyper_frame_modulo; 715 uint32 filter_zero_data; 716 uint32 num_sec; 717 uint32 sec_num[4]; 718 }cprif_cpri_vsd_ctrl_group_config_t; 719 720 typedef struct cprif_cpri_tx_vsd_ctrl_flow_config_s{ 721 uint32 hyper_frame_number; 722 uint32 hyper_frame_modulo; 723 uint32 repeat_mode; 724 }cprif_cpri_tx_vsd_ctrl_flow_config_t; 725 726 727 #define CPRIF_VSD_RAW_FILTER_MODE_DISABLE 0 728 #define CPRIF_VSD_RAW_FILTER_MODE_NON_ZERO 1 729 #define CPRIF_VSD_RAW_FILTER_MODE_PERIODIC 2 730 #define CPRIF_VSD_RAW_FILTER_MODE_CHANGE 3 731 #define CPRIF_VSD_RAW_FILTER_MODE_PATTERN_MATCH 4 732 733 734 735 736 737 738 typedef struct cprif_cpri_vsd_raw_config_s{ 739 uint32 schan_start; 740 uint32 schan_size; 741 uint32 cw_select; 742 uint32 cw_size; 743 }cprif_cpri_vsd_raw_config_t; 744 745 typedef struct cprif_cpri_rx_vsd_raw_filter_config_s{ 746 uint32 filter_mode; 747 uint32 hfn_index; 748 uint32 hfn_modulo; 749 uint32 match_offset; 750 uint32 match_value; 751 uint32 match_mask; 752 uint32 queue_num; 753 }cprif_cpri_rx_vsd_raw_filter_config_t; 754 755 #define CPRIF_VSD_RAW_MAX_GROUP 8 756 #define CPRIF_VSD_RAW_MAP_MODE_USE_MODULO 0 757 #define CPRIF_VSD_RAW_MAP_MODE_USE_ROE_HDR 1 758 759 #define CPRIF_CW_REPEAT_MODE_ONCE 0 760 #define CPRIF_CW_REPEAT_MODE_CONTINUOUS 1 761 762 #define CPRIF_GCW_MAX_GROUP 16 763 #define CPRIF_GCW_MASK_NONE 0 764 #define CPRIF_GCW_MASK_LSB 1 765 #define CPRIF_GCW_MASK_MSB 2 766 #define CPRIF_GCW_MASK_BOTH 3 767 768 #define CPRIF_GCW_NUM_WORD_IN_STATUS 4 769 770 771 typedef struct cprif_cpri_tx_vsd_raw_filter_config_s{ 772 uint32 queue_num; 773 uint32 map_mode; 774 uint32 repeat_mode; 775 uint32 bfn0_filter_enable; 776 uint32 bfn1_filter_enable; 777 uint32 hfn_index; 778 uint32 hfn_modulo; 779 uint32 idle_value; 780 }cprif_cpri_tx_vsd_raw_filter_config_t; 781 782 typedef struct cprif_cpri_rx_gcw_config_s{ 783 uint32 Ns; 784 uint32 Xs; 785 uint32 Y; 786 uint32 mask; 787 uint32 filter_mode; 788 uint32 hfn_index; 789 uint32 hfn_modulo; 790 uint32 match_value; 791 uint32 match_mask; 792 }cprif_cpri_rx_gcw_config_t; 793 794 typedef struct cprif_cpri_tx_gcw_config_s{ 795 uint32 Ns; 796 uint32 Xs; 797 uint32 Y; 798 uint32 mask; 799 uint32 repeat_mode; 800 uint32 bfn0_filter_enable; 801 uint32 bfn1_filter_enable; 802 uint32 hfn_index; 803 uint32 hfn_modulo; 804 }cprif_cpri_tx_gcw_config_t; 805 806 #define CPRIF_CTRL_FLOW_PROC_TYPE_ETH 0 807 #define CPRIF_CTRL_FLOW_PROC_TYPE_FCB 1 808 #define CPRIF_CTRL_FLOW_PROC_TYPE_PAYLOAD 2 809 #define CPRIF_CTRL_FLOW_PROC_TYPE_FULL_MSG 3 810 #define CPRIF_CTRL_FLOW_PROC_TYPE_FULL_MSG_WITH_TAG 4 811 812 #define CPRIF_CTRL_FLOW_MAX 16 813 814 #define CPRIF_CTRL_MAX_ROE_FLOW_ID 256 815 816 typedef struct cprif_rsvd4_rx_ctrl_flow_config_s{ 817 uint32 proc_type; 818 uint32 queue_num; 819 uint32 sync_profile; 820 uint32 sync_enable; 821 }cprif_rsvd4_rx_ctrl_flow_config_t; 822 823 824 #define CPRIF_SYNC_PROFILE_MAX 4 825 826 #define CPRIF_SYNC_PROFILE_EVERY_MF 0 /* every frame */ 827 #define CPRIF_SYNC_PROFILE_UP_TO_6MF 1 /* up to 6 MF */ 828 829 typedef struct cprif_rsvd4_rx_sync_profile_entry_s{ 830 uint32 bfn_offset; 831 uint32 rfrm_offset; 832 uint32 count_cycle; 833 }cprif_rsvd4_rx_sync_profile_entry_t; 834 835 #define CPRIF_TAG_FLOW_MAP_MAX 64 836 #define CPRIF_TAG_GEN_MAX_ENTRY 64 837 typedef struct cprif_rx_tag_gen_entry_s{ 838 uint32 valid; 839 uint32 header; 840 uint32 mask; 841 uint32 tag_id; 842 uint32 rtwp_word_count; 843 844 }cprif_rx_tag_gen_entry_t; 845 846 #define CPRIF_TX_CONTROL_MAX_MEMBER 4 847 #define CPRIF_TX_CONTROL_MAX_GROUP 2 848 typedef struct cprif_control_group_entry_t{ 849 uint32 valid_mask; 850 uint32 queue_num[4]; 851 uint32 proc_type[4]; 852 }cprif_control_group_entry_t; 853 854 #define CPRIF_TX_HEADER_CONFIG_TABLE_SIZE 64 855 856 /*! 857 * @struct cprif_cpri_ingress_pres_time_ctrl_s 858 * @brief CPRI Presentation time control. 859 */ 860 typedef struct cprif_cpri_ingress_pres_time_ctrl_s{ 861 uint32 pres_mod_cnt; /**< Presentation Mod Count. */ 862 uint32 rfrm_sync; /**< Radio Frame Sync . */ 863 uint32 hfrm_sync; /**< Hyper Frame Sync . */ 864 uint32 bfn_offset; /**< Radio Frame Offset */ 865 uint32 hfn_offset; /**< Hyper Frame Offset. */ 866 int approx_inc_disable; /* Disable Approximate Increment. */ 867 }cprif_cpri_ingress_pres_time_ctrl_t; 868 869 /*! 870 * @struct cprif_cpri_egress_agn_config_s 871 * @brief CPRI Egress Agnostic Config. 872 */ 873 typedef struct cprif_cpri_egress_agnostic_config_s{ 874 uint32 rd_ptr_max; /**< Max Buffer Ptr.# of 16 bytes buffers. */ 875 uint32 queue_num; /**< Queue number, ususally 0 . */ 876 uint32 mod_cnt ; /**< Mode Count, equivalent to Cycle Size. */ 877 }cprif_cpri_egress_agnostic_config_t; 878 879 880 #define CPRIF_COMPRESSION_TABLE_SIZE 1024 881 #define CPRIF_DECOMPRESSION_TABLE_SIZE 256 882 883 #define CPRIF_CONTROL_FLOW_TABLE_SIZE 16 884 #define CPRIF_CONTROL_FLOW_MIN_QUEUE_NUM 64 885 886 #define CPRIF_TUNNEL_MODE_NUM_OF_BFP_ENTRIES 24 887 #define CPRIF_TUNNEL_MODE_NUM_OF_BFA_ENTRIES 48 888 889 #define CPRIF_RSVD4_AGNOSTIC_MODE_NUM_OF_BFP_ENTRIES 25 890 #define CPRIF_RSVD4_AGNOSTIC_MODE_NUM_OF_BFA_ENTRIES 25 891 892 893 894 895 /* Field IDs for CPRI_ENCAP_HDR_FLD_MAPPING */ 896 #define CPRIF_ENCAP_HEADER_FIELD_ID_SUBTYPE 0 897 #define CPRIF_ENCAP_HEADER_FIELD_ID_FLOW_ID 1 898 #define CPRIF_ENCAP_HEADER_FIELD_ID_LENGTH_15_8 2 899 #define CPRIF_ENCAP_HEADER_FIELD_ID_LENGTH_7_0 3 900 #define CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_31_24 4 901 #define CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_23_16 5 902 #define CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_15_8 6 903 #define CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_7_0 7 904 #define CPRIF_ENCAP_HEADER_FIELD_ID_OPCODE 8 905 #define CPRIF_ENCAP_HEADER_FIELD_ID_UNMAPPED 0xf 906 907 908 /*! 909 * @struct cprif_cpri_encap_hdr_field_mapping_s 910 * @brief CPRI_ENCAP_HDR_FLD_MAPPING. 911 */ 912 typedef struct cprif_drv_encap_hdr_field_mapping_s{ 913 uint32 hdr_byte0_sel; /**< Header Byte 0 select */ 914 uint32 hdr_byte1_sel; /**< Header Byte 1 select */ 915 uint32 hdr_byte2_sel; /**< Header Byte 2 select */ 916 uint32 hdr_byte3_sel; /**< Header Byte 3 select */ 917 uint32 hdr_byte4_sel; /**< Header Byte 4 select */ 918 uint32 hdr_byte5_sel; /**< Header Byte 5 select */ 919 uint32 hdr_byte6_sel; /**< Header Byte 6 select */ 920 uint32 hdr_byte7_sel; /**< Header Byte 7 select */ 921 uint32 hdr_byte8_sel; /**< Header Byte 8 select */ 922 uint32 hdr_byte9_sel; /**< Header Byte 9 select */ 923 uint32 hdr_byte10_sel; /**< Header Byte 10 select */ 924 uint32 hdr_byte11_sel; /**< Header Byte 11 select */ 925 }cprif_drv_encap_hdr_field_mapping_t; 926 927 928 929 930 /* Field IDs for CPRI_DECAP_HDR_FLD_MAPPING */ 931 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_0 0 932 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_1 1 933 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_2 2 934 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_3 3 935 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_4 4 936 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_5 5 937 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_6 6 938 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_7 7 939 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_8 8 940 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_9 9 941 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_10 10 942 #define CPRIF_DECAP_HEADER_FIELD_ID_HDR_BYTE_11 11 943 #define CPRIF_DECAP_HEADER_FIELD_ID_VLAN_0_BYTE_0 12 944 #define CPRIF_DECAP_HEADER_FIELD_ID_VLAN_0_BYTE_1 13 945 #define CPRIF_DECAP_HEADER_FIELD_ID_VLAN_1_BYTE_0 14 946 #define CPRIF_DECAP_HEADER_FIELD_ID_VLAN_1_BYTE_1 15 947 948 /*! 949 * @struct cprif_drv_cpri_decap_hdr_field_mapping_s 950 * @brief CPRI_DECAP_HDR_FLD_MAPPING. 951 */ 952 typedef struct cprif_drv_decap_hdr_field_mapping_s{ 953 uint32 subtype; /**< SubType Field select */ 954 uint32 flowid; /**< FlowID Field select */ 955 uint32 length_15_8; /**< Length 15:8 Field select */ 956 uint32 length_7_0; /**< Length 7:0 Field select */ 957 uint32 orderinginfo_31_24; /**< OrderingInfo 31:24 Field select */ 958 uint32 orderinginfo_23_16; /**< OrderingInfo 23:16 Field select */ 959 uint32 orderinginfo_15_8; /**< OrderingInfo 15:8 Field select */ 960 uint32 orderinginfo_7_0; /**< OrderingInfo 7:0 Field select */ 961 }cprif_drv_decap_hdr_field_mapping_t; 962 963 964 /* LEN field adjustment */ 965 966 #define CPRIF_LEN_ADJUST_POS_MAX 8 967 #define CPRIF_LEN_ADJUST_NEG_MAX (-8) 968 #define CPRIF_LEN_ADJUST_SIGNED_BIT 0x00000010 969 #define CPRIF_LEN_ADJUST_VALUE_BITS 0x0000000F 970 971 #define CPRIF_LEN_ADJUST_ZERO 0 972 #define CPRIF_LEN_ADJUST_ADD_1 1 /* Add 1 */ 973 #define CPRIF_LEN_ADJUST_ADD_2 2 /* Add 2 */ 974 #define CPRIF_LEN_ADJUST_ADD_3 3 /* Add 3 */ 975 #define CPRIF_LEN_ADJUST_ADD_4 4 /* Add 4 */ 976 #define CPRIF_LEN_ADJUST_ADD_5 5 /* Add 5 */ 977 #define CPRIF_LEN_ADJUST_ADD_6 6 /* Add 6 */ 978 #define CPRIF_LEN_ADJUST_ADD_7 7 /* Add 7 */ 979 #define CPRIF_LEN_ADJUST_ADD_8 8 /* Add 8 */ 980 981 #define CPRIF_LEN_ADJUST_SUB_1 0x1F /* Subtract 1 */ 982 #define CPRIF_LEN_ADJUST_SUB_2 0x1E /* Subtract 2 */ 983 #define CPRIF_LEN_ADJUST_SUB_3 0x1D /* Subtract 3 */ 984 #define CPRIF_LEN_ADJUST_SUB_4 0x1C /* Subtract 4 */ 985 #define CPRIF_LEN_ADJUST_SUB_5 0x1B /* Subtract 5 */ 986 #define CPRIF_LEN_ADJUST_SUB_6 0x1A /* Subtract 6 */ 987 #define CPRIF_LEN_ADJUST_SUB_7 0x19 /* Subtract 7 */ 988 #define CPRIF_LEN_ADJUST_SUB_8 0x18 /* Subtract 8 */ 989 990 /* CMPPORT_TOP_LANE_CTRL , ingress rate control */ 991 #define CPRIF_INGRESS_RATE_FULL 3 /* Full rate of IP TDM. */ 992 #define CPRIF_INGRESS_RATE_TWO_THIRD 2 /* 2/3 rate of IP TDM. */ 993 #define CPRIF_INGRESS_RATE_HALF 1 /* half rate of IP TDM. */ 994 #define CPRIF_INGRESS_RATE_ONE_THIRD 0 /* 1/3 rate of IP TDM. */ 995 996 #define CPRIF_RSVD4_MSG_GRP_SIZE 3200 997 998 999 int cprif_bfa_bfp_table_entry_t_init( cprif_bfa_bfp_table_entry_t* cprimod_bfa_bfp_table_entry); 1000 int cprif_cpri_container_map_entry_t_init( cprif_cpri_container_map_entry_t* cprif_cpri_container_map_entry); 1001 int cprif_rsvd4_container_map_entry_t_init( cprif_rsvd4_container_map_entry_t* cprif_rsvd4_container_map_entry); 1002 int cprif_iq_buffer_config_t_init( cprif_iq_buffer_config_t* cprif_iq_buffer_config_entry); 1003 int cprif_encap_decap_data_entry_t_init( cprif_encap_decap_data_entry_t* cprif_encap_decap_data_entry); 1004 int cprif_rsvd4_encap_decap_data_entry_t_init( cprif_rsvd4_encap_decap_data_entry_t* cprif_rsvd4_encap_decap_data_entry); 1005 int cprif_encap_header_entry_t_init( cprif_encap_header_entry_t* cprif_encap_header_entry); 1006 int cprif_encap_ordering_info_entry_t_init( cprif_encap_ordering_info_entry_t* cprif_encap_ordering_info_entry); 1007 int cprif_decap_ordering_info_entry_t_init( cprif_decap_ordering_info_entry_t* cprif_decap_ordering_info_entry); 1008 int cprif_header_compare_entry_t_init( cprif_header_compare_entry_t* cprif_header_compare_entry); 1009 int cprif_modulo_rule_entry_t_init( cprif_modulo_rule_entry_t* cprif_rsvd4_modulo_rule_entry); 1010 int cprif_rsvd4_dbm_rule_entry_t_init( cprif_rsvd4_dbm_rule_entry_t* cprif_rsvd4_dbm_rule_entry); 1011 int cprif_rsvd4_secondary_dbm_rule_entry_t_init( cprif_rsvd4_secondary_dbm_rule_entry_t* cprif_rsvd4_secondary_dbm_rule_entry); 1012 1013 /* use for both encap and decap */ 1014 int cprif_drv_encap_data_allocate_buffer(int unit, int port, 1015 cprimod_direction_t dir, 1016 uint16 size_in_bytes, 1017 uint16* offset); 1018 1019 int cprif_drv_basic_frame_parser_active_table_set(int unit, int port, uint8 table); 1020 int cprif_drv_basic_frame_parser_active_table_get(int unit, int port, uint8* table); 1021 int cprif_drv_basic_frame_parser_table_num_entries_set(int unit, int port, uint8 table, uint32 num_entries); 1022 int cprif_drv_basic_frame_parser_table_num_entries_get(int unit, int port, uint8 table, uint32* num_entries); 1023 int cprif_drv_rx_framer_agnostic_mode_set(int unit, int port, uint32 axc_id, int enable, cprimod_agnostic_mode_type_t mode); 1024 int cprif_drv_rx_framer_agnostic_mode_get(int unit, int port, uint32* axc_id, int* enable, cprimod_agnostic_mode_type_t* mode); 1025 int cprif_drv_tx_framer_rsvd4_agnostic_mode_set(int unit, int port, int enable); 1026 int cprif_drv_basic_frame_parser_cw_to_encap_config_set(int unit, int port, uint32 axc_id, int fwd_cw_to_encap); 1027 int cprif_drv_basic_frame_assembly_active_table_set(int unit, int port, uint8 table); 1028 int cprif_drv_basic_frame_assembly_active_table_get(int unit, int port, uint8* table); 1029 int cprif_drv_basic_frame_assembly_table_num_entries_set(int unit, int port, uint8 table, uint32 num_entries); 1030 int cprif_drv_basic_frame_assembly_table_num_entries_get(int unit, int port, uint8 table, uint32* num_entries); 1031 1032 int cprif_drv_basic_frame_entry_set (int unit, int port, 1033 uint8 table, 1034 cprimod_direction_t dir, 1035 uint8 index, 1036 const cprif_bfa_bfp_table_entry_t *entry); 1037 1038 int cprif_drv_basic_frame_entry_get (int unit, int port, 1039 uint8 table, 1040 cprimod_direction_t dir, 1041 uint8 index, 1042 cprif_bfa_bfp_table_entry_t *entry); 1043 1044 int cprif_drv_basic_frame_usage_entry_add (int unit, int port, 1045 uint8 table, 1046 cprimod_direction_t dir, 1047 cprimod_basic_frame_usage_entry_t new_entry, 1048 cprimod_basic_frame_usage_entry_t *user_table, 1049 int num_entries_in_table, 1050 int *num_entries ); 1051 1052 int cprif_drv_basic_frame_usage_entry_delete (int unit, int port, 1053 uint8 table, 1054 cprimod_direction_t dir, 1055 uint8 axc_id, 1056 cprimod_basic_frame_usage_entry_t *user_table, 1057 int num_entries_in_table, 1058 int *num_entries ); 1059 int cprif_drv_basic_frame_usage_entries_get (int unit, int port, 1060 uint8 table, 1061 cprimod_direction_t dir, 1062 uint8 axc_id, 1063 cprimod_basic_frame_usage_entry_t *user_table, 1064 int num_entries_in_table, 1065 int *num_entries ); 1066 1067 int cprif_drv_basic_frame_usage_table_to_hw_table_set (int unit, int port, 1068 uint8 table, 1069 cprimod_direction_t dir, 1070 int basic_frm_len, 1071 cprimod_basic_frame_usage_entry_t *user_table, 1072 int *num_entries); 1073 1074 int cprif_drv_basic_frame_debug_usage (int unit, int port, uint32 axc_id, uint8 table, uint8 tx_table); 1075 int cprif_drv_basic_frame_debug_raw(int unit, int port, uint32 axc_id, uint8 rx_table, uint8 tx_table); 1076 1077 int cprif_drv_cpri_container_entry_set (int unit, int port, 1078 cprimod_direction_t dir, 1079 uint8 index, 1080 const cprif_cpri_container_map_entry_t *entry); 1081 int cprif_drv_cpri_container_entry_get (int unit, int port, 1082 cprimod_direction_t dir, 1083 uint8 index, 1084 cprif_cpri_container_map_entry_t *entry); 1085 1086 int cprif_drv_rsvd4_container_entry_set (int unit, int port, 1087 cprimod_direction_t dir, 1088 uint8 index, 1089 const cprif_rsvd4_container_map_entry_t *entry); 1090 1091 int cprif_drv_rsvd4_container_entry_get (int unit, int port, 1092 cprimod_direction_t dir, 1093 uint8 index, 1094 cprif_rsvd4_container_map_entry_t *entry); 1095 int cprif_drv_iq_buffer_config_set(int unit, int port, 1096 cprimod_direction_t dir, 1097 uint8 index, 1098 cprif_iq_buffer_config_t* entry); 1099 1100 int cprif_drv_iq_buffer_config_get(int unit, int port, 1101 cprimod_direction_t dir, 1102 uint8 index, 1103 cprif_iq_buffer_config_t* entry); 1104 1105 int cprif_drv_encap_data_entry_set (int unit, int port, 1106 cprimod_direction_t dir, 1107 uint32 queue_num, 1108 const cprif_encap_decap_data_entry_t *entry); 1109 1110 int cprif_drv_encap_data_entry_get (int unit, int port, 1111 cprimod_direction_t dir, 1112 uint32 queue_num, 1113 cprif_encap_decap_data_entry_t *entry); 1114 1115 int cprif_drv_rsvd4_encap_data_entry_set (int unit, int port, 1116 cprimod_direction_t dir, 1117 uint32 queue_num, 1118 const cprif_rsvd4_encap_decap_data_entry_t *entry); 1119 1120 int cprif_drv_rsvd4_encap_data_entry_get (int unit, int port, 1121 cprimod_direction_t dir, 1122 uint32 queue_num, 1123 cprif_rsvd4_encap_decap_data_entry_t *entry); 1124 1125 int cprif_drv_encap_header_entry_set (int unit, int port, 1126 uint32 queue_num, 1127 uint32 flags, 1128 const cprif_encap_header_entry_t *entry); 1129 1130 int cprif_drv_encap_header_entry_get (int unit, int port, 1131 uint32 queue_num, 1132 cprif_encap_header_entry_t *entry); 1133 1134 1135 int cprif_drv_cprimod_to_cprif_ordering_info_type (cprimod_ordering_info_type_t cprimod_type, uint8* cprif_type); 1136 int cprif_drv_cprif_to_cprimod_ordering_info_type (uint8 cprif_type , cprimod_ordering_info_type_t *cprimod_type); 1137 int cprif_drv_cprimod_to_cprif_ordering_info_inc_prop (cprimod_ordering_info_prop_t cprimod_prop, uint8 *cprif_prop); 1138 int cprif_drv_cprif_to_cprimod_ordering_info_inc_prop (uint8 cprif_prop, cprimod_ordering_info_prop_t *cprimod_prop); 1139 1140 1141 int cprif_drv_encap_ordering_info_entry_set (int unit, int port, 1142 uint8 index, 1143 const cprif_encap_ordering_info_entry_t *entry); 1144 1145 int cprif_drv_encap_ordering_info_entry_get (int unit, int port, 1146 uint8 index, 1147 cprif_encap_ordering_info_entry_t *entry); 1148 1149 int cprif_drv_decap_ordering_info_entry_set (int unit, int port, 1150 uint8 index, 1151 const cprif_decap_ordering_info_entry_t *entry); 1152 1153 int cprif_drv_decap_ordering_info_entry_get (int unit, int port, 1154 uint8 index, 1155 cprif_decap_ordering_info_entry_t *entry); 1156 1157 int cprif_drv_decap_queue_to_ordering_info_index_set(int unit, int port, 1158 uint32 queue, 1159 uint32 index); 1160 1161 int cprif_drv_decap_queue_to_ordering_info_index_get(int unit, int port, 1162 uint32 queue, 1163 uint32* index); 1164 1165 int cprif_drv_encap_queue_ordering_info_sequence_offset_set (int unit, int port, 1166 uint32 queue, 1167 uint8 control, 1168 uint32 pq_offset); 1169 1170 int cprif_drv_encap_queue_ordering_info_sequence_offset_get (int unit, int port, 1171 uint32 queue, 1172 uint8 control, 1173 uint32* pq_offset); 1174 1175 int cprif_drv_decap_queue_ordering_info_sequence_offset_set (int unit, int port, 1176 uint32 queue, 1177 uint32 pq_offset); 1178 1179 int cprif_drv_decap_queue_ordering_info_sequence_offset_get (int unit, int port, 1180 uint32 queue, 1181 uint32* pq_offset); 1182 1183 1184 1185 int cprif_drv_encap_mac_da_set (int unit, int port, 1186 uint32 index, 1187 uint64 mac_addr); 1188 1189 int cprif_drv_encap_mac_da_get (int unit, int port, 1190 uint32 index, 1191 uint64* mac_addr); 1192 1193 int cprif_drv_encap_mac_sa_set (int unit, int port, 1194 uint32 index, 1195 uint64 mac_addr); 1196 1197 int cprif_drv_encap_mac_sa_get (int unit, int port, 1198 uint32 index, 1199 uint64* mac_addr); 1200 1201 int cprif_drv_encap_vlan_entry_set (int unit, int port, 1202 uint32 vlan_table_num, 1203 uint32 index, 1204 uint32 vlan_id); 1205 1206 int cprif_drv_encap_vlan_entry_get (int unit, int port, 1207 uint32 vlan_table_num, 1208 uint32 index, 1209 uint32* vlan_id); 1210 1211 int cprif_drv_decap_vlan_ethtype_set (int unit, int port, 1212 uint8 ethtype_id, 1213 uint16 ethtype); 1214 1215 int cprif_drv_decap_vlan_ethtype_get (int unit, int port, 1216 uint8 ethtype_id, 1217 uint16* ethtype); 1218 1219 int cprif_drv_encap_vlan_ethtype_set (int unit, int port, 1220 uint8 ethtype_id, 1221 uint16 ethtype); 1222 1223 int cprif_drv_encap_vlan_ethtype_get (int unit, int port, 1224 uint8 ethtype_id, 1225 uint16* ethtype); 1226 1227 int cprif_drv_decap_pkt_type_config_set(int unit, int port, 1228 uint16 roe_ethtype, 1229 uint16 fast_eth_ethtype, 1230 uint16 vlan_ethtype, 1231 uint16 qinq_ethtype); 1232 1233 int cprif_drv_decap_pkt_type_config_get(int unit, int port, 1234 uint16* roe_ethtype, 1235 uint16* fast_eth_ethtype, 1236 uint16* vlan_ethtype, 1237 uint16* qinq_ethtype); 1238 1239 int cprif_drv_decap_flow_classification_entry_set (int unit, int port, 1240 uint8 subtype, 1241 uint32 queue_num, 1242 uint32 option, 1243 uint32 flow_type ); 1244 int cprif_drv_decap_flow_classification_entry_get (int unit, int port, 1245 uint8 subtype, 1246 uint32* queue_num, 1247 uint32* option, 1248 uint32* flow_type ); 1249 1250 int cprif_drv_decap_flow_to_queue_map_set (int unit, int port, 1251 uint32 flow_id, 1252 uint32 queue_num); 1253 1254 int cprif_drv_decap_flow_to_queue_map_get (int unit, int port, 1255 uint32 flow_id, 1256 uint32* queue_num); 1257 1258 int cprif_drv_tx_framer_tgen_tick_set (int unit, int port, 1259 uint32 divider, 1260 uint32 bfrm_ticks, 1261 uint32 bfrm_ticks_bitmap, 1262 uint32 bitmap_size); 1263 1264 int cprif_drv_tx_framer_tgen_tick_get (int unit, int port, 1265 uint32* divider, 1266 uint32* bfrm_ticks, 1267 uint32* bfrm_ticks_bitmap, 1268 uint32* bitmap_size); 1269 1270 int cprif_drv_tx_framer_tgen_enable (int unit, int port, uint8 enable); 1271 int cprif_drv_tx_framer_tgen_offset_set (int unit, int port, uint64 offset); 1272 int cprif_drv_tx_framer_tgen_offset_get (int unit, int port, uint64* offset); 1273 int cprif_drv_tx_framer_tgen_next_bfn_config_set (int unit, int port, 1274 uint32 bfn); 1275 int cprif_drv_tx_framer_tgen_next_bfn_config_get (int unit, int port, 1276 uint32* bfn); 1277 int cprif_drv_tx_framer_tgen_next_hfn_config_set (int unit, int port, 1278 uint32 hfn); 1279 int cprif_drv_tx_framer_tgen_next_hfn_config_get (int unit, int port, 1280 uint32* hfn); 1281 int cprif_drv_tx_framer_next_bfn_get (int unit, int port, uint32* bfn); 1282 int cprif_drv_tx_framer_next_hfn_get (int unit, int port, uint32* bfn); 1283 1284 int cprif_drv_tx_framer_tgen_select_counter_set (int unit, int port, 1285 uint8 hfn_bfn); 1286 int cprif_drv_tx_framer_tgen_select_counter_get (int unit, int port, 1287 uint8* hfn_bfn); 1288 1289 int cprif_drv_rsvd4_header_compare_entry_set (int unit, int port, 1290 int index, 1291 cprimod_header_compare_entry_t* entry); 1292 int cprif_drv_rsvd4_header_compare_entry_get (int unit, int port, 1293 int index, 1294 cprimod_header_compare_entry_t* entry); 1295 1296 int cprif_drv_rsvd4_modulo_rule_entry_set (int unit, int port, 1297 uint8 index, 1298 uint8 control_rule, 1299 cprimod_modulo_rule_entry_t* entry); 1300 int cprif_drv_rsvd4_modulo_rule_entry_get (int unit, int port, 1301 uint8 index, 1302 uint8 control_rule, 1303 cprimod_modulo_rule_entry_t* entry); 1304 1305 int cprif_drv_rsvd4_dual_bitmap_rule_entry_set (int unit, int port, 1306 uint8 index, 1307 cprimod_dbm_rule_entry_t* entry); 1308 int cprif_drv_rsvd4_dual_bitmap_rule_entry_get (int unit, int port, 1309 uint8 index, 1310 cprimod_dbm_rule_entry_t* entry); 1311 1312 int cprif_drv_rsvd4_secondary_dual_bitmap_rule_entry_set (int unit, int port, 1313 uint8 index, 1314 cprimod_secondary_dbm_rule_entry_t* entry); 1315 int cprif_drv_rsvd4_secondary_dual_bitmap_rule_entry_get (int unit, int port, 1316 uint8 index, 1317 cprimod_secondary_dbm_rule_entry_t* entry); 1318 1319 int cprif_drv_rsvd4_dbm_position_entry_set(int unit, int port, 1320 uint8 index, 1321 cprimod_dbm_pos_table_entry_t* entry); 1322 1323 int cprif_drv_rsvd4_dbm_position_entry_get(int unit, int port, 1324 uint8 index, 1325 cprimod_dbm_pos_table_entry_t* entry); 1326 1327 int cprif_drv_encap_queue_sts_clear(int unit, int port, 1328 int queue_num); 1329 1330 int cprif_drv_encap_ordering_info_sts_clear(int unit, int port, 1331 int queue_num); 1332 1333 int cprif_drv_encap_eth_hdr_clear(int unit, int port, 1334 int queue_num); 1335 1336 int cprif_drv_encap_data_tab_clear(int unit, int port, 1337 int queue_num); 1338 1339 int cprif_drv_container_parser_mapp_state_tab_clear(int unit, int port, 1340 int axc_id); 1341 1342 int cprif_drv_iq_pak_buff_state_tab_clear(int unit, int port, 1343 int axc_id); 1344 1345 int cprif_drv_iq_pak_buff_payld_tab_clear(int unit, int port, 1346 int axc_id); 1347 1348 int cprif_drv_iq_unpsk_buff_state_tbl_clear(int unit, int port, 1349 int axc_id); 1350 1351 int cprif_drv_cont_assembly_map_state_tbl_clear(int unit, int port, 1352 int axc_id); 1353 1354 int cprif_drv_decap_queue_state_tbl_clear(int unit, int port, 1355 int queue_num); 1356 1357 int cprif_drv_decap_queue_data_tbl_clear(int unit, int port, 1358 int queue_num); 1359 1360 int cprif_drv_rxpcs_interface_width_get(int unit, int port, int *is_10bit); 1361 int cprif_drv_rxpcs_tunnel_mode_set(int unit, int port, int enable, uint32 timestamp_interval); 1362 int cprif_drv_rxpcs_tunnel_mode_get(int unit, int port, int* enable, uint32* timestamp_interval); 1363 int cprif_drv_txpcs_agnostic_mode_set(int unit, int port, int enable, cprimod_agnostic_mode_type_t mode, uint32 timestamp_interval); 1364 int cprif_drv_txpcs_agnostic_mode_get(int unit, int port, int* enable, cprimod_agnostic_mode_type_t* mode, uint32* timestamp_interval); 1365 1366 int cprif_drv_txpcs_tunnel_mode_set(int unit, int port, int enable, uint32 timestamp_interval); 1367 int cprif_drv_txpcs_tunnel_mode_get(int unit, int port, int* enable, uint32* timestamp_interval); 1368 1369 int cprif_drv_cpri_rxpcs_speed_set(int unit, int port, const phymod_phy_access_t* phy, 1370 cprimod_port_speed_t speed); 1371 1372 int cprif_drv_cpri_rxpcs_speed_get(int unit, int port, 1373 cprimod_port_speed_t *speed); 1374 1375 int cprif_drv_cpri_txpcs_speed_set(int unit, int port, const phymod_phy_access_t* phy, 1376 cprimod_port_speed_t speed); 1377 1378 int cprif_drv_cpri_txpcs_speed_get(int unit, int port, 1379 cprimod_port_speed_t *speed); 1380 1381 int cprif_drv_rsvd4_rxpcs_speed_set(int unit, int port, const phymod_phy_access_t* phy, 1382 cprimod_port_rsvd4_speed_mult_t speed); 1383 1384 int cprif_drv_rsvd4_rxpcs_speed_get(int unit, int port, 1385 cprimod_port_rsvd4_speed_mult_t *speed); 1386 1387 int cprif_drv_rsvd4_txpcs_speed_set(int unit, int port, const phymod_phy_access_t* phy, 1388 cprimod_port_rsvd4_speed_mult_t speed); 1389 1390 int cprif_drv_rsvd4_txpcs_speed_get(int unit, int port, 1391 cprimod_port_rsvd4_speed_mult_t *speed); 1392 1393 int cprif_drv_txcpri_port_type_get(int unit, int port, 1394 cprimod_port_interface_type_t *interface); 1395 1396 int cprif_drv_rxcpri_port_type_get(int unit, int port, 1397 cprimod_port_interface_type_t *interface); 1398 1399 int cprif_drv_rx_frame_optional_config_set(int unit, int port, 1400 cprimod_rx_config_field_t field, 1401 int value); 1402 1403 int cprif_drv_rx_frame_optional_config_get(int unit, int port, 1404 cprimod_rx_config_field_t field, 1405 int* value); 1406 1407 int cprif_drv_tx_frame_optional_config_set(int unit, int port, 1408 cprimod_tx_config_field_t field, 1409 uint32 value); 1410 1411 int cprif_drv_tx_frame_optional_config_get(int unit, int port, 1412 cprimod_tx_config_field_t field, 1413 uint32* value); 1414 1415 int cprif_drv_rsvd4_rx_frame_optional_config_set(int unit, int port, 1416 cprimod_rsvd4_rx_config_field_t field, 1417 int value); 1418 1419 int cprif_drv_rsvd4_rx_frame_optional_config_get(int unit, int port, 1420 cprimod_rsvd4_rx_config_field_t field, 1421 int* value); 1422 1423 int cprif_drv_rsvd4_rx_fsm_state_set(int unit, int port, 1424 cprimod_rsvd4_rx_fsm_state_t state); 1425 1426 int cprif_drv_rsvd4_rx_fsm_state_get(int unit, int port, 1427 cprimod_rsvd4_rx_fsm_state_t* state); 1428 1429 int cprif_drv_rsvd4_rx_overide_set(int unit, int port, 1430 cprimod_rsvd4_rx_overide_t parameter, 1431 int enable, int value); 1432 1433 int cprif_drv_rsvd4_rx_overide_get(int unit, int port, 1434 cprimod_rsvd4_rx_overide_t parameter, 1435 int* enable, int* value); 1436 1437 int cprif_drv_rsvd4_tx_frame_optional_config_set(int unit, int port, 1438 cprimod_rsvd4_tx_config_field_t field, 1439 int value); 1440 1441 int cprif_drv_rsvd4_tx_frame_optional_config_get(int unit, int port, 1442 cprimod_rsvd4_tx_config_field_t field, 1443 int* value); 1444 1445 int cprif_drv_rsvd4_tx_fsm_state_set(int unit, int port, 1446 cprimod_rsvd4_tx_fsm_state_t state); 1447 1448 int cprif_drv_rsvd4_tx_fsm_state_get(int unit, int port, 1449 cprimod_rsvd4_tx_fsm_state_t* state); 1450 1451 int cprif_drv_rsvd4_tx_overide_set(int unit, int port, 1452 cprimod_rsvd4_tx_overide_t parameter, 1453 int enable, int value); 1454 1455 int cprif_drv_rsvd4_tx_overide_get(int unit, int port, 1456 cprimod_rsvd4_tx_overide_t parameter, 1457 int* enable, int* value); 1458 1459 int cprif_drv_pmd_port_status_get(int unit, int port, cprimod_pmd_port_status_t status, 1460 uint32* value); 1461 1462 int cprif_drv_rx_pcs_status_get(int unit, int port, 1463 cprimod_rx_pcs_status_t status, uint32* value); 1464 1465 int cprif_drv_cip_top_ctrl_set(int unit, int port, int val); 1466 1467 int cprif_drv_cip_top_ctrl_get(int unit, int port, int *val); 1468 1469 int cprif_drv_pmd_iddq_set(int unit, int port, int val); 1470 1471 int cprif_drv_pmd_iddq_get(int unit, int port, int *val); 1472 1473 int cprif_drv_top_ctrl_config_pll_ctrl_set(int unit, int port, int pll_num, 1474 int cip_pll_ctrl); 1475 1476 int cprif_drv_top_ctrl_config_pll_ctrl_get(int unit, int port, int pll_num, 1477 int *cip_pll_ctrl); 1478 1479 int cprif_drv_top_ctrl_config_ref_clk_ctrl_set(int unit, int port, int pll_num, 1480 int refin, int refout); 1481 1482 int cprif_drv_top_ctrl_config_ref_clk_ctrl_get(int unit, int port, int pll_num, 1483 int *refin, int *refout); 1484 1485 int cprif_drv_pmd_ctrl_por_h_rstb_set(int unit, int port, int por_h_rstb); 1486 1487 int cprif_drv_pmd_ctrl_ln_por_h_rstb_set(int unit, int port); 1488 1489 int cprif_drv_pmd_ctrl_por_h_rstb_get(int unit, int port, int *por_h_rstb); 1490 1491 int cprif_drv_pmd_core_datapath_hard_reset_set(int unit, int port, int pll_num, int rst); 1492 1493 int cprif_drv_pmd_core_datapath_hard_reset_get(int unit, int port, int pll_num, int *rst); 1494 1495 int cprif_drv_cpmport_pll_ctrl_config_set(int unit, int port, int pll_num, int lcref_sel); 1496 1497 int cprif_drv_cpmport_pll_ctrl_config_get(int unit, int port, int pll_num, int *lcref_sel); 1498 1499 int cprif_drv_lane_swap_set(int unit, int port, int lane, cprimod_direction_t dir, 1500 int phyport); 1501 1502 int cprif_drv_lane_swap_get(int unit, int port, int lane, cprimod_direction_t dir, 1503 int *phyport); 1504 1505 int cprif_drv_rsvd4_rx_master_frame_sync_config_set(int unit, int port, 1506 uint32 master_frame_number, 1507 uint64 master_frame_start_time); 1508 1509 int cprif_drv_rsvd4_rx_master_frame_sync_config_get(int unit, int port, 1510 uint32* master_frame_number, 1511 uint64* master_frame_start_time); 1512 int cprif_drv_rx_control_word_status_get(int unit, int port, cprif_drv_rx_control_word_status_t* info); 1513 int cprif_drv_cpri_rx_l1_signal_signal_protection_set(int unit, int port, uint32 signal_map, uint32 enable); 1514 int cprif_drv_cpri_rx_l1_signal_signal_protection_get(int unit, int port, uint32 signal_map, uint32* enable); 1515 int cprif_drv_cpri_port_rx_cw_slow_hdlc_config_set(int unit, int port, cprif_cpri_rx_hdlc_config_t* config_info); 1516 int cprif_drv_cpri_port_rx_cw_slow_hdlc_config_get(int unit, int port, cprif_cpri_rx_hdlc_config_t* config_info); 1517 int cprif_drv_cpri_port_tx_cw_slow_hdlc_config_set(int unit, int port, cprif_cpri_tx_hdlc_config_t* config_info); 1518 int cprif_drv_cpri_port_tx_cw_slow_hdlc_config_get(int unit, int port, cprif_cpri_tx_hdlc_config_t* config_info); 1519 int cprif_drv_cpri_port_rx_cw_fast_eth_word_config_set(int unit, int port, cprif_cpri_rx_fast_eth_word_config_t* config_info); 1520 int cprif_drv_cpri_port_rx_cw_fast_eth_word_config_get(int unit, int port, cprif_cpri_rx_fast_eth_word_config_t* config_info); 1521 int cprif_drv_cpri_port_rx_cw_fast_eth_config_set(int unit, int port, cprif_cpri_rx_fast_eth_config_t* config_info); 1522 int cprif_drv_cpri_port_rx_cw_fast_eth_config_get(int unit, int port, cprif_cpri_rx_fast_eth_config_t* config_info); 1523 int cprif_drv_cpri_port_tx_cw_fast_eth_config_set(int unit, int port, cprif_cpri_tx_fast_eth_config_t* config_info); 1524 int cprif_drv_cpri_port_tx_cw_fast_eth_config_get(int unit, int port, cprif_cpri_tx_fast_eth_config_t* config_info); 1525 1526 int cprif_drv_rx_vsd_ctrl_copy_id_get(int unit, int port, uint32* copy_id); 1527 int cprif_drv_rx_vsd_ctrl_copy_id_set(int unit, int port, uint32 copy_id); 1528 int cprif_drv_rx_vsd_ctrl_config_set(int unit, int port, cprif_cpri_vsd_config_t* config_info); 1529 int cprif_drv_rx_vsd_ctrl_config_get(int unit, int port, cprif_cpri_vsd_config_t* config_info); 1530 int cprif_drv_rx_vsd_ctrl_rsvd_mask_set(int unit, int port, uint32* rsvd_mask); 1531 int cprif_drv_rx_vsd_ctrl_rsvd_mask_get(int unit, int port, uint32* rsvd_mask); 1532 int cprif_drv_rx_vsd_ctrl_ctrl_mask_set(int unit, int port, uint32 copy_id, uint32* ctrl_mask); 1533 int cprif_drv_rx_vsd_ctrl_ctrl_mask_get(int unit, int port, uint32 copy_id, uint32* ctrl_mask); 1534 int cprif_drv_rx_vsd_ctrl_flow_config_set(int unit, int port, 1535 uint32 sector_num, 1536 const cprif_cpri_rx_vsd_ctrl_flow_config_t *entry); 1537 int cprif_drv_rx_vsd_ctrl_flow_config_get(int unit, int port, 1538 uint32 sector_num, 1539 cprif_cpri_rx_vsd_ctrl_flow_config_t *entry); 1540 int cprif_drv_rx_vsd_ctrl_group_num_sector_set(int unit, int port, 1541 uint32 group_id, 1542 uint32 num_sector); 1543 int cprif_drv_rx_vsd_ctrl_group_num_sector_get(int unit, int port, 1544 uint32 group_id, 1545 uint32* num_sector); 1546 int cprif_drv_rx_vsd_ctrl_group_config_set(int unit, int port, 1547 uint32 group_id, 1548 uint32 tag_id, 1549 uint32 grp_ptr_index); 1550 int cprif_drv_rx_vsd_ctrl_group_config_get(int unit, int port, 1551 uint32 group_id, 1552 uint32* tag_id, 1553 uint32* grp_ptr_index); 1554 int cprif_drv_rx_vsd_ctrl_group_assign_ptr_set(int unit, int port, 1555 uint32 ptr_index, 1556 uint32 sec_num); 1557 int cprif_drv_rx_vsd_ctrl_group_assign_ptr_get(int unit, int port, 1558 uint32 ptr_index, 1559 uint32* sec_num); 1560 int cprif_drv_allocate_grp_ptr (uint32* grp_ptr_mask, uint32 num_sec, uint32* ptr_index); 1561 1562 1563 int cprif_drv_tx_vsd_ctrl_copy_id_get(int unit, int port, uint32* copy_id); 1564 int cprif_drv_tx_vsd_ctrl_copy_id_set(int unit, int port, uint32 copy_id); 1565 int cprif_drv_tx_vsd_ctrl_rsvd_mask_set(int unit, int port, uint32* rsvd_mask); 1566 int cprif_drv_tx_vsd_ctrl_rsvd_mask_get(int unit, int port, uint32* rsvd_mask); 1567 int cprif_drv_tx_vsd_ctrl_ctrl_mask_set(int unit, int port, uint32 copy_id, uint32* ctrl_mask); 1568 int cprif_drv_tx_vsd_ctrl_ctrl_mask_get(int unit, int port, uint32 copy_id, uint32* ctrl_mask); 1569 int cprif_drv_tx_vsd_ctrl_flow_config_set(int unit, int port, 1570 uint32 sector_num, 1571 const cprif_cpri_tx_vsd_ctrl_flow_config_t *entry); 1572 int cprif_drv_tx_vsd_ctrl_flow_config_get(int unit, int port, 1573 uint32 sector_num, 1574 cprif_cpri_tx_vsd_ctrl_flow_config_t *entry); 1575 int cprif_drv_tx_vsd_ctrl_flow_id_to_group_mapping_set(int unit, int port, 1576 uint32 roe_flow_id, 1577 uint32 group_id); 1578 int cprif_drv_tx_vsd_ctrl_flow_id_to_group_mapping_get(int unit, int port, 1579 uint32 roe_flow_id, 1580 uint32* group_id); 1581 int cprif_drv_tx_vsd_ctrl_group_config_set(int unit, int port, 1582 uint32 group_id, 1583 uint32 num_sector, 1584 uint32 grp_ptr_index); 1585 int cprif_drv_tx_vsd_ctrl_group_config_get(int unit, int port, 1586 uint32 group_id, 1587 uint32* num_sector, 1588 uint32* grp_ptr_index); 1589 int cprif_drv_tx_vsd_ctrl_group_assign_ptr_set(int unit, int port, 1590 uint32 ptr_index, 1591 uint32 sec_num); 1592 int cprif_drv_tx_vsd_ctrl_group_assign_ptr_get(int unit, int port, 1593 uint32 ptr_index, 1594 uint32* sec_num); 1595 int cprif_drv_encap_tag_to_flow_id_set(int unit, int port, 1596 uint32 tag_id, 1597 uint32 flow_ida); 1598 int cprif_drv_encap_tag_to_flow_id_get(int unit, int port, 1599 uint32 tag_id, 1600 uint32* flow_id); 1601 int cprif_drv_tx_vsd_ctrl_config_set(int unit, int port, const cprif_cpri_vsd_config_t* config_info); 1602 int cprif_drv_tx_vsd_ctrl_config_get(int unit, int port, cprif_cpri_vsd_config_t* config_info); 1603 int cprif_drv_rx_vsd_raw_config_set(int unit, int port, 1604 uint32 index, 1605 cprif_cpri_vsd_raw_config_t* config); 1606 int cprif_drv_rx_vsd_raw_config_get(int unit, int port, 1607 uint32 index, 1608 cprif_cpri_vsd_raw_config_t* config); 1609 int cprif_drv_rx_vsd_raw_filter_config_set(int unit, int port, 1610 uint32 index, 1611 cprif_cpri_rx_vsd_raw_filter_config_t* config); 1612 int cprif_drv_rx_vsd_raw_filter_config_get(int unit, int port, 1613 uint32 index, 1614 cprif_cpri_rx_vsd_raw_filter_config_t* config); 1615 1616 1617 int cprif_drv_tx_vsd_raw_config_set(int unit, int port, 1618 uint32 index, 1619 cprif_cpri_vsd_raw_config_t* config); 1620 int cprif_drv_tx_vsd_raw_config_get(int unit, int port, 1621 uint32 index, 1622 cprif_cpri_vsd_raw_config_t* config); 1623 int cprif_drv_tx_vsd_raw_filter_config_set(int unit, int port, 1624 uint32 index, 1625 cprif_cpri_tx_vsd_raw_filter_config_t* config); 1626 int cprif_drv_tx_vsd_raw_filter_config_get(int unit, int port, 1627 uint32 index, 1628 cprif_cpri_tx_vsd_raw_filter_config_t* config); 1629 int cprif_drv_tx_vsd_raw_radio_frame_filter_set(int inst_num, int port_num, 1630 uint32 bfn0_value, 1631 uint32 bfn0_mask, 1632 uint32 bfn1_value, 1633 uint32 bfn1_mask); 1634 int cprif_drv_tx_vsd_raw_radio_frame_filter_get(int unit, int port_num, 1635 uint32* bfn0_value, 1636 uint32* bfn0_mask, 1637 uint32* bfn1_value, 1638 uint32* bfn1_mask); 1639 int cprif_drv_rx_brcm_rsvd5_config_set(int unit, int port, uint32 schan_start, uint32 schan_size, uint32 queue_num, int parity_disable); 1640 int cprif_drv_rx_brcm_rsvd5_config_get(int unit, int port, uint32* schan_start, uint32* schan_size, uint32*queue_num, int* parity_disable); 1641 int cprif_drv_tx_brcm_rsvd5_config_set(int unit, int port, 1642 uint32 schan_start, 1643 uint32 schan_size, 1644 uint32 queue_num, 1645 int crc_enable); 1646 int cprif_drv_tx_brcm_rsvd5_config_get(int unit, int port, 1647 uint32* schan_start, 1648 uint32* schan_size, 1649 uint32* queue_num, 1650 int* crc_enable); 1651 1652 int cprif_drv_rx_gcw_config_set(int unit, int port, 1653 uint32 index, 1654 cprif_cpri_rx_gcw_config_t* config); 1655 int cprif_drv_rx_gcw_config_get(int unit, int port, 1656 uint32 index, 1657 cprif_cpri_rx_gcw_config_t* config); 1658 int cprif_drv_tx_gcw_config_set(int unit, int port, 1659 uint32 index, 1660 cprif_cpri_tx_gcw_config_t* config); 1661 int cprif_drv_tx_gcw_config_get(int unit, int port, 1662 uint32 index, 1663 cprif_cpri_tx_gcw_config_t* config); 1664 int cprif_drv_tx_gcw_filter_set(int unit, int port, 1665 uint32 bfn0_value, uint32 bfn0_mask, 1666 uint32 bfn1_value, uint32 bfn1_mask); 1667 int cprif_drv_tx_gcw_filter_get(int unit, int port, 1668 uint32* bfn0_value, uint32* bfn0_mask, 1669 uint32* bfn1_value, uint32* bfn1_mask); 1670 int cprif_drv_tx_control_word_set(int unit, int port, 1671 cprif_drv_tx_control_word_t* control); 1672 int cprif_drv_tx_control_word_size_set(int unit, int port, 1673 uint32 cw_size_in_bytes); 1674 1675 1676 /* RSVD4 control */ 1677 int cprif_drv_rsvd4_rx_control_message_config_set( int unit, int port, 1678 uint32 sm_queue_num, 1679 uint32 default_tag, 1680 uint32 no_match_tag); 1681 1682 int cprif_drv_rsvd4_rx_control_flow_config_set ( int unit, int port, 1683 uint32 control_flow_id, 1684 cprif_rsvd4_rx_ctrl_flow_config_t* config); 1685 int cprif_drv_rsvd4_rx_control_flow_config_get( int unit, int port, 1686 uint32 control_flow_id, 1687 cprif_rsvd4_rx_ctrl_flow_config_t* config); 1688 1689 int cprif_drv_rx_control_flow_tag_option_set(int unit, int port, 1690 uint32 control_flow_id, 1691 uint32 tag_option); 1692 1693 int cprif_drv_rx_sync_profile_entry_set (int unit, int port, 1694 uint32 profile_id, 1695 cprif_rsvd4_rx_sync_profile_entry_t* profile); 1696 int cprif_drv_rx_sync_profile_entry_get (int unit, int port, 1697 uint32 profile_id, 1698 cprif_rsvd4_rx_sync_profile_entry_t* profile); 1699 1700 int cprif_drv_rx_tag_config_set ( int unit, int port, 1701 uint32 default_tag, 1702 uint32 no_match_tag); 1703 1704 int cprif_drv_rx_tag_gen_entry_set( int unit, int port, 1705 uint32 index, 1706 cprif_rx_tag_gen_entry_t* entry); 1707 int cprif_drv_rx_tag_gen_entry_get( int unit, int port, 1708 uint32 index, 1709 cprif_rx_tag_gen_entry_t* entry); 1710 int cprif_drv_brcm_rsvd4_tx_control_group_entry_set( int unit, int port, 1711 uint32 index, 1712 cprif_control_group_entry_t* entry); 1713 int cprif_drv_brcm_rsvd4_tx_control_group_entry_get( int unit, int port, 1714 uint32 index, 1715 cprif_control_group_entry_t* entry); 1716 1717 int cprif_drv_tx_control_eth_msg_config_set(int unit, int port, 1718 uint32 msg_node, 1719 uint32 msg_subnode, 1720 uint32 msg_type, 1721 uint32 msg_padding); 1722 int cprif_drv_tx_control_eth_msg_config_get(int unit, int port, 1723 uint32* msg_node, 1724 uint32* msg_subnode, 1725 uint32* msg_type, 1726 uint32* msg_padding); 1727 int cprif_drv_tx_control_single_msg_config_set(int unit, int port, 1728 uint32 msg_id, 1729 uint32 msg_type); 1730 int cprif_drv_tx_control_single_msg_config_get(int unit, int port, 1731 uint32* msg_id, 1732 uint32* msg_type); 1733 int cprif_drv_tx_control_single_tunnel_msg_config_set(int unit, int port, 1734 uint32 crc_option); 1735 1736 int cprif_drv_brcm_rsvd4_tx_control_flow_config_set( int unit, int port, 1737 uint32 index, 1738 uint32 queue_num, 1739 uint32 proc_type); 1740 int cprif_drv_brcm_rsvd4_tx_control_flow_config_get( int unit, int port, 1741 uint32 index, 1742 uint32* queue_num, 1743 uint32* proc_type); 1744 1745 int cprif_drv_brcm_rsvd4_control_flow_header_index_set( int unit, int port, 1746 uint32 flow_id, 1747 uint32 header_index); 1748 int cprif_drv_brcm_rsvd4_control_flow_header_index_get( int unit, int port, 1749 uint32 flow_id, 1750 uint32* header_index); 1751 1752 int cprif_drv_brcm_rsvd4_control_header_entry_set( int unit, int port, 1753 uint32 index, 1754 uint32 header_node, 1755 uint32 header_subnode, 1756 uint32 node); 1757 1758 int cprif_drv_brcm_rsvd4_control_header_entry_get( int unit, int port, 1759 uint32 index, 1760 uint32* header_node, 1761 uint32* header_subnode, 1762 uint32* node); 1763 1764 int cprif_drv_datapath_credit_reset_set(int unit, int port, int val); 1765 1766 int cprif_drv_datapath_credit_reset_get(int unit, int port, int* val); 1767 1768 int cprif_drv_cip_rx_dp_reset_set(int unit, int port, int val); 1769 1770 int cprif_drv_cip_rx_dp_reset_get(int unit, int port, int* val); 1771 1772 int cprif_drv_cip_tx_dp_reset_set(int unit, int port, int val); 1773 1774 int cprif_drv_cip_tx_dp_reset_get(int unit, int port, int* val); 1775 1776 int cprif_drv_cip_tx_h_reset_set(int unit, int port, int val); 1777 1778 int cprif_drv_cip_tx_h_reset_get(int unit, int port, int* val); 1779 1780 int cprif_drv_cip_rx_h_reset_set(int unit, int port, int val); 1781 1782 int cprif_drv_cip_rx_h_reset_get(int unit, int port, int* val); 1783 1784 int cprif_drv_datapath_rx_dp_reset_set(int unit, int port, int val); 1785 1786 int cprif_drv_datapath_rx_dp_reset_get(int unit, int port, int* val); 1787 1788 int cprif_drv_datapath_tx_dp_reset_set(int unit, int port, int val); 1789 1790 int cprif_drv_datapath_tx_dp_reset_get(int unit, int port, int* val); 1791 1792 int cprif_drv_datapath_rx_h_reset_set(int unit, int port, int val); 1793 1794 int cprif_drv_datapath_rx_h_reset_get(int unit, int port, int* val); 1795 1796 int cprif_drv_datapath_tx_h_reset_set(int unit, int port, int val); 1797 1798 int cprif_drv_datapath_tx_h_reset_get(int unit, int port, int* val); 1799 1800 int cprif_drv_rx_dp_reset_set(int unit, int port, int val); 1801 1802 int cprif_drv_rx_dp_reset_get(int unit, int port, int* val); 1803 1804 int cprif_drv_rx_h_reset_set(int unit, int port, int val); 1805 1806 int cprif_drv_rx_h_reset_get(int unit, int port, int* val); 1807 1808 int cprif_drv_tx_dp_reset_set(int unit, int port, int val); 1809 1810 int cprif_drv_tx_dp_reset_get(int unit, int port, int* val); 1811 1812 int cprif_drv_tx_h_reset_set(int unit, int port, int val); 1813 1814 int cprif_drv_tx_h_reset_get(int unit, int port, int* val); 1815 1816 int cprif_drv_glas_reset_set(int unit, int port, int val); 1817 1818 int cprif_drv_glas_reset_get(int unit, int port, int* val); 1819 1820 int cprif_drv_disable_cip_clk_set(int unit, int port, int val); 1821 1822 int cprif_drv_disable_cip_clk_get(int unit, int port, int* val); 1823 1824 int cprif_drv_disable_glas_clk_set(int unit, int port, int val); 1825 1826 int cprif_drv_disable_glas_clk_get(int unit, int port, int* val); 1827 1828 int cprif_drv_disable_rx_clk_set(int unit, int port, int val); 1829 1830 int cprif_drv_disable_rx_clk_get(int unit, int port, int* val); 1831 1832 int cprif_drv_disable_tx_clk_set(int unit, int port, int val); 1833 1834 int cprif_drv_disable_tx_clk_get(int unit, int port, int* val); 1835 1836 int cprif_drv_cip_clk_pll_select_set(int unit, int port, int val); 1837 1838 int cprif_drv_cip_clk_pll_select_get(int unit, int port, int* val); 1839 1840 int cprif_drv_cip_clk_div_ctrl_set(int unit, int port, int val); 1841 1842 int cprif_drv_cip_clk_div_ctrl_get(int unit, int port, int* val); 1843 1844 int cprif_drv_tx_flush_set(int unit, int port, int val); 1845 1846 int cprif_drv_tx_flush_get(int unit, int port, int* val); 1847 1848 int cprif_drv_rx_disable_set(int unit, int port, int val); 1849 1850 int cprif_drv_rx_disable_get(int unit, int port, int* val); 1851 1852 int cprif_drv_cpri_or_enet_port_set(int unit, int port, int val); 1853 1854 int cprif_drv_cpri_or_enet_port_get(int unit, int port, int* val); 1855 1856 int cprif_drv_stuff_rsrv_bits_set( int unit, int port, 1857 int roe_stuffing_bit, 1858 int roe_reserved_bit); 1859 1860 int cprif_drv_pmd_reset_seq(int unit, int port, int pmd_touched); 1861 1862 int cprif_drv_cpri_port_interrupt_enable_set(int unit, int port, 1863 int int_dir, int enable); 1864 int cprif_drv_cpri_port_interrupt_enable_get(int unit, int port, 1865 int int_dir, int *enable); 1866 int cprif_drv_cpri_port_interrupt_status_get(int unit, int port, int *status); 1867 1868 int cprif_drv_cpri_port_rx_interrupts_enable_set(int unit, 1869 int port, 1870 int rx_intr_flags, 1871 int enable); 1872 int cprif_drv_cpri_port_rx_interrupt_enable_get(int unit, 1873 int port, 1874 int rx_intr_flags, 1875 int *status); 1876 int cprif_drv_cpri_port_rx_func_interrupts_enable_set(int unit, 1877 int port, 1878 int rx_func_intr_flags, 1879 int enable); 1880 int cprif_drv_cpri_port_rx_func_interrupts_enable_get(int unit, 1881 int port, 1882 int rx_func_intr_flags, 1883 int *status); 1884 /* Enable interrupt to detect link down - LOS signal is latched low */ 1885 int cprif_drv_rx_pcs_link_down_intr_enable_set(int unit, 1886 int port, 1887 int enable); 1888 /* Enable interrupt to detect link up - LOS signal is latched low */ 1889 int cprif_drv_rx_pcs_link_up_intr_enable_set(int unit, 1890 int port, 1891 int enable); 1892 /* Get interrupt enable Status to detect LOS signal - latched high */ 1893 int cprif_drv_rx_pcs_link_up_intr_enable_get(int unit, 1894 int port, 1895 int *status); 1896 int cprif_drv_rx_pcs_link_up_intr_status_get(int unit, 1897 int port, 1898 int *status); 1899 int cprif_drv_rx_pcs_link_up_intr_status_clr_get(int unit, 1900 int port, 1901 int *status); 1902 /* Get interrupt enable Status to detect LOS signal - latched low */ 1903 int cprif_drv_rx_pcs_link_down_intr_enable_get(int unit, 1904 int port, 1905 int *status); 1906 int cprif_drv_rx_pcs_link_down_intr_status_get(int unit, 1907 int port, 1908 int *status); 1909 int cprif_drv_rx_pcs_link_down_intr_status_clr_get(int unit, 1910 int port, 1911 int *status); 1912 1913 int cprif_drv_rx_1588_fifo_intr_enable_set(int unit, int port, int enable); 1914 1915 int cprif_drv_rx_1588_fifo_intr_enable_get(int unit, int port, int *status); 1916 1917 int cprif_drv_tx_1588_fifo_intr_enable_set(int unit, int port, int enable); 1918 int cprif_drv_tx_1588_fifo_intr_enable_get(int unit, int port, int *status); 1919 1920 int cprif_drv_rx_1588_sw_intr_enable_set(int unit, int port, int enable); 1921 1922 int cprif_drv_rx_1588_sw_intr_enable_get(int unit, int port, int *status); 1923 1924 int cprif_drv_rx_1588_sw_intr_status_clr_get(int unit, int port, 1925 uint64 *rx_captured_ts, 1926 int *status); 1927 int cprif_drv_tx_1588_sw_intr_enable_set(int unit, int port, int enable); 1928 int cprif_drv_tx_1588_sw_intr_enable_get(int unit, int port, int *status); 1929 1930 int cprif_drv_fast_clk_bit_time_period_set(int unit, int port, uint32 bit_time_period); 1931 int cprif_drv_fast_clk_bit_time_period_get(int unit, int port, uint32* bit_time_period); 1932 int cprif_drv_1588_bit_time_period_set(int unit, int port, cprimod_direction_t direction, cprimod_port_speed_t speed); 1933 int cprif_drv_1588_bit_time_period_get(int unit, int port, cprimod_direction_t direction, uint32* bit_time_period); 1934 int cprif_drv_1588_timestamp_capture_config_set(int unit, int port, cprimod_direction_t direction, cprimod_1588_capture_config_t *config); 1935 int cprif_drv_1588_timestamp_capture_config_get(int unit, int port, cprimod_direction_t direction, cprimod_1588_capture_config_t* config); 1936 int cprif_drv_1588_captured_timestamp_get(int unit, int port, cprimod_direction_t direction, cprimod_1588_ts_type_t ts_type, uint8 mx_cnt, uint8* count, uint64* captured_time); 1937 int cprif_drv_1588_timestamp_adjust_set(int unit, int port, cprimod_direction_t direction, cprimod_1588_time_t *adjust_time); 1938 int cprif_drv_1588_timestamp_adjust_get(int unit, int port, cprimod_direction_t direction, cprimod_1588_time_t* adjust_time); 1939 int cprif_drv_1588_timestamp_fifo_config_set(int unit, int port, cprimod_direction_t direction, uint16 modulo); 1940 int cprif_drv_1588_timestamp_fifo_config_get(int unit, int port, cprimod_direction_t direction, uint16* modulo); 1941 int cprif_drv_1588_timestamp_cmic_config_set(int unit, int port, cprimod_direction_t direction, uint16 modulo); 1942 int cprif_drv_1588_timestamp_cmic_config_get(int unit, int port, cprimod_direction_t direction, uint16* modulo); 1943 1944 int cprif_drv_ingress_presentation_time_enable_set(int unit, int port, int enable); 1945 int cprif_drv_ingress_presentation_time_enable_get(int unit, int port, int* enable); 1946 int cprif_drv_ingress_presentation_time_config_set(int unit, int port, cprif_cpri_ingress_pres_time_ctrl_t* config); 1947 int cprif_drv_ingress_presentation_time_config_get(int unit, int port, cprif_cpri_ingress_pres_time_ctrl_t* config); 1948 int cprif_drv_ingress_presentation_time_adjust_set(int unit, int port, uint32 time); 1949 int cprif_drv_ingress_presentation_time_adjust_get(int unit, int port, uint32* time); 1950 int cprif_drv_ingress_presentation_time_approximate_increment_set(int unit, int port, uint32 time); 1951 int cprif_drv_ingress_presentation_time_approximate_increment_get(int unit, int port, uint32* time); 1952 int cprif_drv_egress_agnostic_mode_enable_set(int unit, int port, int enable, cprimod_cpri_roe_ordering_info_option_t mode); 1953 int cprif_drv_egress_agnostic_mode_enable_get(int unit, int port, int* enable, cprimod_cpri_roe_ordering_info_option_t* mode); 1954 int cprif_drv_egress_agnostic_mode_config_set(int unit, int port, cprif_cpri_egress_agnostic_config_t* config); 1955 int cprif_drv_egress_agnostic_mode_config_get(int unit, int port, cprif_cpri_egress_agnostic_config_t* config); 1956 int cprif_drv_egress_presentation_time_config_set(int unit, int port, uint32 mod_offset, uint32 mod_count); 1957 int cprif_drv_egress_presentation_time_config_get(int unit, int port, uint32* mod_offset, uint32* mod_count); 1958 1959 int cprif_drv_cpri_port_interrupt_type_num_subid_get ( int unit, int port, 1960 cprimod_cpri_port_intr_type_t intr, 1961 int* num_subid); 1962 1963 int cprif_drv_cpri_port_interrupt_type_enable_set(int unit, int port, 1964 cprimod_cpri_port_intr_type_t intr, 1965 int data, int enable); 1966 int cprif_drv_cpri_port_interrupt_type_enable_get(int unit, int port, 1967 cprimod_cpri_port_intr_type_t intr, 1968 int data, int *enable); 1969 int cprif_drv_cpri_port_interrupt_type_status_get(int unit, int port, 1970 cprimod_cpri_port_intr_type_t intr, 1971 int data, int *status); 1972 1973 /* 1974 * Enable CPRI port RX Operational error interrupts. 1975 * RX Lane Operational Error Interrupts. 1976 * 1. RX Lane Combined DATA Queue Overflow Error 1977 * 2. RX Lane Combined Control Queue Overflow Error 1978 * 3. RX Lane Combined GSM Time-stamp Error 1979 * 4. RX Lane MISC WQ and CDC Overflow Error 1980 * 5. RX RX Lane RxFramer BRCM_RSVD4 Time-stamp 1981 * detection Error 1982 */ 1983 extern 1984 int cprif_drv_cpri_port_rx_op_err_interrupts_enable_set(int unit, 1985 int port, 1986 int rx_op_err_intr_flags, 1987 int enable); 1988 1989 /* 1990 * Enable CPRI port RX Operational error interrupts. 1991 * RX Lane Operational Error Interrupts. 1992 * 1. RX Lane Combined DATA Queue Overflow Error 1993 * 2. RX Lane Combined Control Queue Overflow Error 1994 * 3. RX Lane Combined GSM Time-stamp Error 1995 * 4. RX Lane MISC WQ and CDC Overflow Error 1996 * 5. RX RX Lane RxFramer BRCM_RSVD4 Time-stamp 1997 * detection Error 1998 */ 1999 extern 2000 int cprif_drv_cpri_port_rx_op_err_interrupts_enable_get(int unit, 2001 int port, 2002 int rx_op_err_intr_flags, 2003 int *status); 2004 2005 /* 2006 * Enable CPRI port TX interrupts. 2007 * TX interrupts can be of 3 types 2008 * 1. TX operational error type interrupts. 2009 * 2. TX functional error type interrupts. 2010 * 3. TX memory ECC error type interrupts. 2011 */ 2012 extern 2013 int cprif_drv_cpri_port_tx_interrupts_enable_set(int unit, 2014 int port, 2015 int tx_intr_flags, 2016 int enable); 2017 2018 /* 2019 * Get CPRI port TX interrupts enable status. 2020 */ 2021 extern 2022 int cprif_drv_cpri_port_tx_interrupt_enable_get(int unit, 2023 int port, 2024 int tx_intr_flags, 2025 int *status); 2026 2027 /* 2028 * Enable CPRI port TX Functional interrupts. 2029 * TX Functional interrupts can be of 3 types 2030 * 1. TX 2031 * 2. TX functional error type interrupts. 2032 * 3. TX memory ECC error type interrupts. 2033 */ 2034 extern 2035 int cprif_drv_cpri_port_tx_op_err_interrupts_enable_set(int unit, 2036 int port, 2037 int tx_op_err_intr_flags, 2038 int enable); 2039 2040 /* 2041 * Get CPRI port TX functional interrupts enable status. 2042 */ 2043 extern 2044 int cprif_drv_cpri_port_tx_op_err_interrupts_enable_get(int unit, 2045 int port, 2046 int tx_op_err_intr_flags, 2047 int *status); 2048 2049 /* 2050 * Enable CPRI port TX Functional interrupts. 2051 * TX Functional interrupts can be of 3 types 2052 * 1. TX 2053 * 2. TX functional error type interrupts. 2054 * 3. TX memory ECC error type interrupts. 2055 */ 2056 extern 2057 int cprif_drv_cpri_port_tx_func_interrupts_enable_set(int unit, 2058 int port, 2059 int tx_func_intr_flags, 2060 int enable); 2061 2062 /* 2063 * Get CPRI port TX functional interrupts enable status. 2064 */ 2065 extern 2066 int cprif_drv_cpri_port_tx_func_interrupts_enable_get(int unit, 2067 int port, 2068 int tx_func_intr_flags, 2069 int *status); 2070 2071 int cprif_drv_compression_entry_set (int unit, int port, int index, 2072 uint32 comp_val_0, uint32 comp_val_1); 2073 int cprif_drv_compression_entry_get (int unit, int port, int index, 2074 uint32* comp_val_0, uint32* comp_val_1); 2075 int cprif_drv_decompression_entry_set (int unit, int port, int index, 2076 uint32 decomp_val); 2077 int cprif_drv_decompression_entry_get (int unit, int port, int index, 2078 uint32* decomp_val); 2079 int cprif_drv_decap_queue_flow_control_entry_set(int unit, int port, 2080 int index, 2081 int enable, 2082 uint32 queue_num, 2083 uint32 xon_buff_count, 2084 uint32 xoff_buff_count); 2085 int cprif_drv_decap_queue_flow_control_entry_get(int unit, int port, 2086 int index, 2087 int* enable, 2088 uint32* queue_num, 2089 uint32* xon_buff_count, 2090 uint32* xoff_buff_count); 2091 int cprif_drv_cpri_port_fec_enable_set(int unit, int port, cprimod_direction_t dir, int enable); 2092 int cprif_drv_cpri_port_fec_enable_get(int unit, int port, cprimod_direction_t dir, int* enable); 2093 int cprif_drv_cpri_port_fec_timestamp_config_set(int unit, int port, cprimod_direction_t dir, 2094 const cprimod_fec_timestamp_config_t* config); 2095 int cprif_drv_cpri_port_fec_timestamp_config_get(int unit, int port, cprimod_direction_t dir, 2096 cprimod_fec_timestamp_config_t* config); 2097 int cprif_drv_cpri_port_fec_aux_config_set(int unit, int port, 2098 cprimod_fec_aux_config_para_t parameter_id, 2099 uint32 value); 2100 int cprif_drv_cpri_port_fec_aux_config_get(int unit, int port, 2101 cprimod_fec_aux_config_para_t parameter_id, 2102 uint32* value); 2103 2104 int cprif_drv_init(int unit, int port); 2105 int cprif_drv_port_link_down_reset(int unit, int port); 2106 2107 int cprif_drv_rx_gcw_word_get(int unit, int port, int group_index, uint16* word); 2108 int cprif_drv_tx_gcw_word_set(int unit, int port, int group_index, uint16 word); 2109 2110 int cprif_drv_encap_header_field_mapping_set(int unit, int port, cprif_drv_encap_hdr_field_mapping_t *mapping); 2111 int cprif_drv_encap_header_field_mapping_get(int unit, int port, cprif_drv_encap_hdr_field_mapping_t *mapping); 2112 int cprif_drv_decap_header_field_mapping_set(int unit, int port, cprif_drv_decap_hdr_field_mapping_t *mapping); 2113 int cprif_drv_decap_header_field_mapping_get(int unit, int port, cprif_drv_decap_hdr_field_mapping_t *mapping); 2114 int cprif_drv_decap_header_field_mask_set(int unit, int port, cprif_drv_decap_hdr_field_mapping_t *mask); 2115 int cprif_drv_decap_header_field_mask_get(int unit, int port, cprif_drv_decap_hdr_field_mapping_t *mask); 2116 int cprif_drv_length_field_adjustment_set (int unit, int port, cprimod_direction_t dir, int adjust_value); 2117 int cprif_drv_length_field_adjustment_get (int unit, int port, cprimod_direction_t dir, int* adjust_value); 2118 int cprif_drv_extended_header_enable_set (int unit, int port, cprimod_direction_t dir, int enable); 2119 int cprif_drv_extended_header_enable_get (int unit, int port, cprimod_direction_t dir, int* enable); 2120 2121 int cprif_drv_compression_negative_saturation_threshold_set( int unit, int port, uint32 threshold_value); 2122 int cprif_drv_compression_negative_saturation_threshold_get( int unit, int port, uint32* threshold_value); 2123 int cprif_drv_decompression_negative_saturation_value_set( int unit, int port, uint32 sat_value); 2124 int cprif_drv_decompression_negative_saturation_value_get( int unit, int port, uint32* sat_value); 2125 int cprif_drv_ingress_traffic_rate_set(int unit, int port, uint32 rate); 2126 int cprif_drv_ingress_traffic_rate_get(int unit, int port, uint32* rate); 2127 int cprif_drv_rsvd4_tx_padding_size_set(int unit, int port, uint32 padding_size); 2128 int cprif_drv_rsvd4_tx_padding_size_get(int unit, int port, uint32* padding_size); 2129 int cprif_drv_cpri_work_queue_interrupt_status_clear(int unit, int port); 2130 int cprif_drv_cpri_byte_error_count_clear(int unit, int port); 2131 2132 int cprif_drv_cpri_port_ecc_interrupt_enable_set(int unit, int port, 2133 int enable); 2134 2135 int cprif_drv_cpri_port_ecc_interrupt_status_get(int unit, int port, 2136 cprimod_cpri_ecc_intr_info_t *ecc_err_info); 2137 2138 int cprif_drv_cpri_port_ecc_interrupt_test(int unit, int port); 2139 #endif /*_CPRIF_DRV_H_*/ 2140