counter.h (31636B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: counter.h 8 * Purpose: Defines map of counter register addresses, as well 9 * as structures and routines for driver management of 10 * packet statistics counters. 11 */ 12 13 #ifndef _SOC_COUNTER_H 14 #define _SOC_COUNTER_H 15 16 #include <soc/defs.h> 17 #include <soc/types.h> 18 #include <sal/types.h> 19 #include <soc/sbusdma.h> 20 21 #define SOC_REG_HAS_COUNTER_FIELDS(unit, socreg) \ 22 (SOC_REG_INFO(unit, socreg).flags1 & SOC_REG_FLAG_COUNTER_FEILDS) 23 24 #define SOC_COUNTER_EXTRA_CB_MAX 5 25 26 /* 27 * Counter map structure. 28 * Each chip has an array of these structures indexed by soc_ctr_type_t 29 */ 30 31 typedef struct soc_ctr_tbl_entry_s { 32 soc_field_t ctr_field; 33 soc_mem_t mem; 34 soc_format_t format; 35 int row_offset; 36 int ctr_idx; /* index of accumulated counter 37 value in SW, similar to 38 SOC_REG_INFO(unit, reg).ctr_idx */ 39 int dma_offset; /* dword offset for counter DMA use */ 40 } soc_ctr_tbl_entry_t; 41 42 typedef struct soc_ctr_tbl_info_s { 43 int num; 44 soc_ctr_tbl_entry_t *tables; 45 } soc_ctr_tbl_info_t; 46 47 typedef struct soc_ctr_ref_s { 48 soc_reg_t reg; 49 int index; 50 } soc_ctr_ref_t; 51 52 typedef struct soc_cmap_s { 53 soc_ctr_ref_t *cmap_base; /* The array of counters as they are DMA'd */ 54 int cmap_size; /* The number of elements in the array */ 55 } soc_cmap_t; 56 57 /* 58 * Non CMIC counter DMA supported counters 59 * These counters are included by show counter output 60 */ 61 typedef enum soc_counter_non_dma_id_e { 62 SOC_COUNTER_NON_DMA_START = NUM_SOC_REG, 63 SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT = SOC_COUNTER_NON_DMA_START, 64 SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE, 65 SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_UC, 66 SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_UC, 67 SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_EXT, 68 SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_EXT, 69 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT, 70 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE, 71 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC, 72 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC, 73 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_EXT, 74 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_EXT, 75 SOC_COUNTER_NON_DMA_COSQ_DROP_WRED_PKT, 76 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING, 77 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING, 78 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING_METER, 79 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING_METER, 80 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_IBP, 81 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_CFAP, 82 SOC_COUNTER_NON_DMA_PORT_DROP_PKT, 83 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW, 84 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED, 85 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN, 86 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW, 87 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED, 88 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW_UC, 89 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED_UC, 90 SOC_COUNTER_NON_DMA_DROP_RQ_PKT, 91 SOC_COUNTER_NON_DMA_DROP_RQ_BYTE, 92 SOC_COUNTER_NON_DMA_DROP_RQ_PKT_YELLOW, 93 SOC_COUNTER_NON_DMA_DROP_RQ_PKT_RED, 94 SOC_COUNTER_NON_DMA_POOL_PEAK, 95 SOC_COUNTER_NON_DMA_POOL_CURRENT, 96 SOC_COUNTER_NON_DMA_PG_MIN_PEAK, 97 SOC_COUNTER_NON_DMA_PG_MIN_CURRENT, 98 SOC_COUNTER_NON_DMA_PG_SHARED_PEAK, 99 SOC_COUNTER_NON_DMA_PG_SHARED_CURRENT, 100 SOC_COUNTER_NON_DMA_PG_HDRM_PEAK, 101 SOC_COUNTER_NON_DMA_PG_HDRM_CURRENT, 102 SOC_COUNTER_NON_DMA_QUEUE_PEAK, 103 SOC_COUNTER_NON_DMA_QUEUE_CURRENT, 104 SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK, 105 SOC_COUNTER_NON_DMA_UC_QUEUE_CURRENT, 106 SOC_COUNTER_NON_DMA_EXT_QUEUE_PEAK, 107 SOC_COUNTER_NON_DMA_EXT_QUEUE_CURRENT, 108 SOC_COUNTER_NON_DMA_COSQ_WRED_PKT_RED, 109 SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT, 110 SOC_COUNTER_NON_DMA_COSQ_ACCEPT_BYTE, 111 SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT_YELLOW, 112 SOC_COUNTER_NON_DMA_COSQ_ACCEPT_BYTE_YELLOW, 113 SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT_RED, 114 SOC_COUNTER_NON_DMA_COSQ_ACCEPT_BYTE_RED, 115 SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT_GREEN, 116 SOC_COUNTER_NON_DMA_COSQ_ACCEPT_BYTE_GREEN, 117 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_YELLOW, 118 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_YELLOW, 119 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_RED, 120 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_RED, 121 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_GREEN, 122 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_GREEN, 123 SOC_COUNTER_NON_DMA_TX_LLFC_MSG_CNT, 124 SOC_COUNTER_NON_DMA_MMU_QCN_CNM, 125 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM0_HIGH_PRI, 126 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM0_LOW_PRI, 127 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM0_HIGH_PRI, 128 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM0_LOW_PRI, 129 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM1_HIGH_PRI, 130 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM1_LOW_PRI, 131 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM1_HIGH_PRI, 132 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM1_LOW_PRI, 133 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM2_HIGH_PRI, 134 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM2_LOW_PRI, 135 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM2_HIGH_PRI, 136 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM2_LOW_PRI, 137 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM3_HIGH_PRI, 138 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM3_LOW_PRI, 139 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM3_HIGH_PRI, 140 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM3_LOW_PRI, 141 SOC_COUNTER_NON_DMA_COSQ_GLOBAL_HDR_COUNT_X_PEAK, 142 SOC_COUNTER_NON_DMA_COSQ_GLOBAL_HDR_COUNT_X_CURRENT, 143 SOC_COUNTER_NON_DMA_COSQ_GLOBAL_HDR_COUNT_Y_PEAK, 144 SOC_COUNTER_NON_DMA_COSQ_GLOBAL_HDR_COUNT_Y_CURRENT, 145 SOC_COUNTER_NON_DMA_EGR_PERQ_ECN_MARKED, 146 SOC_COUNTER_NON_DMA_PORT_WRED_DROP_PKT, 147 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 148 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 149 SOC_COUNTER_NON_DMA_EGR_FLEX_PKT, 150 SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE, 151 SOC_COUNTER_NON_DMA_EFP_PKT, 152 SOC_COUNTER_NON_DMA_EFP_BYTE, 153 SOC_COUNTER_NON_DMA_SFLOW_ING_PKT, 154 SOC_COUNTER_NON_DMA_SFLOW_FLEX_PKT, 155 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO, 156 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO, 157 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI, 158 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI, 159 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0, 160 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0, 161 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1, 162 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1, 163 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_EXPRESS, 164 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_EXPRESS, 165 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_PKT_OBM_LOSSY_LO, 166 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_BYTE_OBM_LOSSY_LO, 167 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_PKT_OBM_LOSSY_HI, 168 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_BYTE_OBM_LOSSY_HI, 169 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_PKT_OBM_LOSSLESS0, 170 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_BYTE_OBM_LOSSLESS0, 171 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_PKT_OBM_LOSSLESS1, 172 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_BYTE_OBM_LOSSLESS1, 173 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_PKT_OBM_EXPRESS, 174 SOC_COUNTER_NON_DMA_PORT_ENQUEUE_BYTE_OBM_EXPRESS, 175 SOC_COUNTER_NON_DMA_TAS_TXOVERRUN_EXPRESS, 176 SOC_COUNTER_NON_DMA_TAS_TXOVERRUN_PREEMPT, 177 SOC_COUNTER_NON_DMA_PREEMPT_MAC_MERGE_HOLD_CNT, 178 SOC_COUNTER_NON_DMA_ING_RX_COUNTER_NON_PREEMPTABLE_CNT, 179 SOC_COUNTER_NON_DMA_ING_RX_COUNTER_PREEMPTABLE_CNT, 180 SOC_COUNTER_NON_DMA_EGR_TX_COUNTER_NON_PREEMPTABLE_CNT, 181 SOC_COUNTER_NON_DMA_EGR_TX_COUNTER_PREEMPTABLE_CNT, 182 SOC_COUNTER_NON_DMA_E2E_DROP_COUNT, 183 SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS, 184 SOC_COUNTER_NON_DMA_PG0_MIN_CURRENT, 185 SOC_COUNTER_NON_DMA_PG1_MIN_CURRENT, 186 SOC_COUNTER_NON_DMA_PG2_MIN_CURRENT, 187 SOC_COUNTER_NON_DMA_PG3_MIN_CURRENT, 188 SOC_COUNTER_NON_DMA_PG4_MIN_CURRENT, 189 SOC_COUNTER_NON_DMA_PG5_MIN_CURRENT, 190 SOC_COUNTER_NON_DMA_PG6_MIN_CURRENT, 191 SOC_COUNTER_NON_DMA_PG7_MIN_CURRENT, 192 SOC_COUNTER_NON_DMA_PG0_SHARED_CURRENT, 193 SOC_COUNTER_NON_DMA_PG1_SHARED_CURRENT, 194 SOC_COUNTER_NON_DMA_PG2_SHARED_CURRENT, 195 SOC_COUNTER_NON_DMA_PG3_SHARED_CURRENT, 196 SOC_COUNTER_NON_DMA_PG4_SHARED_CURRENT, 197 SOC_COUNTER_NON_DMA_PG5_SHARED_CURRENT, 198 SOC_COUNTER_NON_DMA_PG6_SHARED_CURRENT, 199 SOC_COUNTER_NON_DMA_PG7_SHARED_CURRENT, 200 SOC_COUNTER_NON_DMA_PG0_HDRM_CURRENT, 201 SOC_COUNTER_NON_DMA_PG1_HDRM_CURRENT, 202 SOC_COUNTER_NON_DMA_PG2_HDRM_CURRENT, 203 SOC_COUNTER_NON_DMA_PG3_HDRM_CURRENT, 204 SOC_COUNTER_NON_DMA_PG4_HDRM_CURRENT, 205 SOC_COUNTER_NON_DMA_PG5_HDRM_CURRENT, 206 SOC_COUNTER_NON_DMA_PG6_HDRM_CURRENT, 207 SOC_COUNTER_NON_DMA_PG7_HDRM_CURRENT, 208 SOC_COUNTER_NON_DMA_SP0_CURRENT, 209 SOC_COUNTER_NON_DMA_SP1_CURRENT, 210 SOC_COUNTER_NON_DMA_SP2_CURRENT, 211 SOC_COUNTER_NON_DMA_SP3_CURRENT, 212 SOC_COUNTER_NON_DMA_PRIQ_DROP_PKT, 213 SOC_COUNTER_NON_DMA_PRIQ_DROP_BYTE, 214 SOC_COUNTER_NON_DMA_PRIQ_DROP_PKT_YELLOW, 215 SOC_COUNTER_NON_DMA_PRIQ_DROP_PKT_RED, 216 SOC_COUNTER_NON_DMA_HDRM_POOL_DROP_PKT, 217 #if defined(BCM_MONTEREY_SUPPORT) && defined (CPRIMOD_SUPPORT) 218 SOC_COUNTER_NON_DMA_CPRI_START, 219 SOC_COUNTER_NON_DMA_CPRI_RX_SYMBOL_ERR = SOC_COUNTER_NON_DMA_CPRI_START, 220 SOC_COUNTER_NON_DMA_CPRI_RX_SEED_VECTOR_MISMATCH, 221 SOC_COUNTER_NON_DMA_CPRI_RX_STATE_TRANSITION_ERR, 222 SOC_COUNTER_NON_DMA_CPRI_TX_VSD_CTRL_PKT_FLOW_ID_ERR, 223 SOC_COUNTER_NON_DMA_CPRI_TX_VSD_CTRL_PKT_SIZE_ERR, 224 SOC_COUNTER_NON_DMA_CPRI_TX_VSD_RAW_PKT_SIZE_ERR, 225 SOC_COUNTER_NON_DMA_RSVD5_TX_DROP_CRC_ERR, 226 SOC_COUNTER_NON_DMA_RSVD4_RX_SINGLE_MSG_DROP_CRC_ERR, 227 SOC_COUNTER_NON_DMA_RSVD4_RX_TAG_LKUP_FAIL, 228 SOC_COUNTER_NON_DMA_RSVD4_RX_SINGLE_MSG_CTRL_STREAMS, 229 SOC_COUNTER_NON_DMA_RSVD4_RX_MULPILE_MSG_CTRL_STREAMS, 230 SOC_COUNTER_NON_DMA_RSVD4_RX_INCORRECT_TIME_STAMP_SEQ, 231 SOC_COUNTER_NON_DMA_CPRI_RX_DATA_BYTES_ERR, 232 SOC_COUNTER_NON_DMA_CPRI_RX_RSVD4_HDR_MSG_ERR, 233 SOC_COUNTER_NON_DMA_CPRI_RX_RSVD4_MSG_HDR_LKUP_FAIL, 234 SOC_COUNTER_NON_DMA_CPRI_RX_RSVD4_TOTAL_MSG_COUNT, 235 SOC_COUNTER_NON_DMA_CPRI_RX_INCORRECT_HFN_EXTRACT, 236 SOC_COUNTER_NON_DMA_CPRI_RX_INCORRECT_BFN_EXTRACT, 237 SOC_COUNTER_NON_DMA_CPRI_RX_CTRL_WORD_ERR, 238 SOC_COUNTER_NON_DMA_CPRI_RX_GENERIC_CTRL_WORD_ERR, 239 SOC_COUNTER_NON_DMA_CPRI_RX_VSD_RAW_PKT_DROP, 240 SOC_COUNTER_NON_DMA_CPRI_RX_VSD_CTRL_PKT_DROP, 241 SOC_COUNTER_NON_DMA_CPRI_TX_RSVD4_DATA_SLOT_DATA_MSG, 242 SOC_COUNTER_NON_DMA_CPRI_TX_RSVD4_DATA_SLOT_EMPTY_MSG, 243 SOC_COUNTER_NON_DMA_CPRI_TX_RSVD4_CTRL_SLOT_CTRL_MSG, 244 SOC_COUNTER_NON_DMA_CPRI_TX_RSVD4_CTRL_SLOT_EMPTY_MSG, 245 SOC_COUNTER_NON_DMA_RSVD5_RX_MSG_PARITY_ERR, 246 SOC_COUNTER_NON_DMA_CPRI_RX_HDLC_FRAME_ERR, 247 SOC_COUNTER_NON_DMA_CPRI_RX_HDLC_FRAME_OK, 248 SOC_COUNTER_NON_DMA_CPRI_RX_FAST_ETH_PKT_MAC_DROP, 249 SOC_COUNTER_NON_DMA_CPRI_RX_FAST_ETH_PKT_MAC_OK, 250 SOC_COUNTER_NON_DMA_CPRI_END = 251 SOC_COUNTER_NON_DMA_CPRI_RX_FAST_ETH_PKT_MAC_OK, 252 #endif /* BCM_MONTEREY_SUPPORT && CPRIMOD_SUPPORT */ 253 SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_NUM_EXCEEDED_CNT, 254 SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_LEARNT_CNT, 255 SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_AGE_OUT_CNT, 256 SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_MISSED_CNT, 257 SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_METER_EXCEEDED_CNT, 258 259 SOC_COUNTER_NON_DMA_END 260 } soc_counter_non_dma_id_t; 261 262 #define SOC_COUNTER_TABLE_FIELD_START SOC_COUNTER_NON_DMA_END 263 #define SOC_COUNTER_TABLE_FIELD_END (SOC_COUNTER_TABLE_FIELD_START + NUM_SOC_FIELD) 264 #define NUM_PORTS_PER_CDMIB_MEM (8) 265 #define NUM_CDMIB_MEM_ROWS_PER_PORT (16) 266 #define SOC_COUNTER_TABLE_BASE_PORT (1) /* counter table is starting from physical port 1 */ 267 268 #ifdef SOC_COUNTER_TABLE_SUPPORT 269 270 #define SOC_REG_IS_COUNTER_TABLE(unit, socreg) \ 271 ((SOC_CTR_TBL_INFO(unit) != NULL) && \ 272 (socreg >= SOC_COUNTER_TABLE_FIELD_START) && \ 273 (socreg < SOC_COUNTER_TABLE_FIELD_END)) 274 #else 275 #define SOC_REG_IS_COUNTER_TABLE(unit, socreg) (0) 276 #endif 277 278 #define SOC_COUNTER_INVALID(unit, reg) \ 279 ((reg == INVALIDr) ||\ 280 (!SOC_REG_IS_COUNTER_TABLE(unit, reg) &&\ 281 !SOC_REG_IS_ENABLED(unit, reg))\ 282 ) 283 284 #ifdef BCM_IPROC_SUPPORT 285 #define SOC_REG_IS_COUNTER(unit, socreg) \ 286 ((socreg >= SOC_COUNTER_TABLE_FIELD_START) || \ 287 ((SOC_REG_INFO(unit, socreg).flags & SOC_REG_FLAG_COUNTER) && \ 288 (SOC_REG_INFO(unit, socreg).regtype != soc_cpureg) && \ 289 (SOC_REG_INFO(unit, socreg).regtype != soc_iprocreg))) 290 #else 291 #define SOC_REG_IS_COUNTER(unit, socreg) \ 292 ((SOC_REG_INFO(unit, socreg).flags & SOC_REG_FLAG_COUNTER) && \ 293 (SOC_REG_INFO(unit, socreg).regtype != soc_cpureg)) 294 #endif 295 296 /* flags for soc_counter_non_dma_t.flags */ 297 #define _SOC_COUNTER_NON_DMA_VALID 0x0001 298 #define _SOC_COUNTER_NON_DMA_DO_DMA 0x0002 299 #define _SOC_COUNTER_NON_DMA_ALLOC 0x0004 300 #define _SOC_COUNTER_NON_DMA_PEAK 0x0008 301 #define _SOC_COUNTER_NON_DMA_CURRENT 0x0010 302 #define _SOC_COUNTER_NON_DMA_PERQ_REG 0x0020 /* for register with variable 303 * number of queue per port */ 304 #define _SOC_COUNTER_NON_DMA_CLEAR_ON_READ 0x0040 305 #define _SOC_COUNTER_NON_DMA_EXTRA_COUNT 0x0080 306 #define _SOC_COUNTER_NON_DMA_CTR_EVICT 0x0100 307 #define _SOC_COUNTER_NON_DMA_SUBSET_PARENT 0x0200 308 #define _SOC_COUNTER_NON_DMA_SUBSET_CHILD 0x0400 309 #define _SOC_COUNTER_NON_DMA_SLOWDMA 0x0800 310 /* For counters mapped to queue flexibly, 311 * such as QCN counters to UC queuesin TD2 */ 312 #define _SOC_COUNTER_NON_DMA_FLEX_MAPPING 0x1000 313 #define _SOC_COUNTER_NON_DMA_OBM 0x2000 314 #define _SOC_COUNTER_NON_DMA_NO_SHOW_C 0x4000 /* Counters Not picked for 315 * Show counter output */ 316 /* Counter saturate on overflow and do not wrap around */ 317 #define _SOC_COUNTER_NON_DMA_SATURATE_ON_OVERFLOW 0x8000 318 #define _SOC_COUNTER_NON_DMA_READ_ONLY 0x10000 319 320 /* DMA Rate profile Macros */ 321 #define _SOC_COUNTER_DMA_RATE_PROFILE0 0x0001 322 #define _SOC_COUNTER_DMA_RATE_PROFILE1 0x0002 323 #define _SOC_COUNTER_DMA_RATE_PROFILE2 0x0004 324 #define _SOC_COUNTER_DMA_RATE_PROFILE3 0x0008 325 326 #define _SOC_COUNTER_DMA_RATE_PROFILE_MAX 4 327 #define _SOC_COUNTER_DMA_RATE_PROFILE_OFFSET 0 328 #define _SOC_COUNTER_DMA_RATE_PROFILE_MASK 0x00ff 329 #define _SOC_COUNTER_DMA_RATE_PROFILE_ALL _SOC_COUNTER_DMA_RATE_PROFILE_MASK 330 331 /* Macros for default counter / counter eviction config variables */ 332 #define _SOC_CTR_THREAD_PRI 50 333 /* hostbuf size should be in order of 2 power */ 334 #define _SOC_CTR_EVICT_HOSTBUF_SIZE 8192 335 #define _SOC_CTR_EVICT_THREAD_PRI 50 336 #define _SOC_CTR_EVICT_ENTRIES_MAX 0 337 338 /* Support for sFlow counters */ 339 typedef enum soc_sflow_ctr_type_e { 340 SOC_SFLOW_CTR_TYPE_SAMPLE_POOL, 341 SOC_SFLOW_CTR_TYPE_SAMPLE_POOL_SNAPSHOT, 342 SOC_SFLOW_CTR_TYPE_SAMPLE_COUNT, 343 SOC_SFLOW_CTR_TYPE_COUNT 344 } soc_sflow_ctr_type_t; 345 346 /* one structure per each soc_counter_non_dma_id_t */ 347 typedef int (*soc_counter_hw_idx_get_f)(int unit, soc_port_t port, 348 int index, int *qindex); 349 typedef struct soc_counter_non_dma_s { 350 soc_reg_t id; 351 uint32 flags; /* _SOC_COUNTER_NON_DMA_XXX */ 352 uint16 dma_rate_profile; /* contains the profile info for DMA purpose */ 353 soc_pbmp_t pbmp; 354 int base_index; /* first index into soc_control_t.counter_val[] and etc. */ 355 int entries_per_port; /* max possible number of entries per port */ 356 int num_entries; 357 int num_valid_pipe; 358 soc_mem_t mem; 359 soc_reg_t reg; 360 soc_field_t field; 361 char *cname; 362 /* TH3 has max pipe number of 8 */ 363 uint32 *dma_buf[8]; 364 int dma_index_min[8]; 365 int dma_index_max[8]; 366 soc_mem_t dma_mem[8]; 367 int dma_num_entries[8]; 368 sbusdma_desc_handle_t handle; 369 370 /* below are for subset children */ 371 struct soc_counter_non_dma_s *extra_ctrs; 372 uint32 extra_ctr_ct; 373 uint32 extra_ctr_fld_ct; 374 375 /* Routine used to retrieve the table index 376 * for flexible mapping Non-DMA counter */ 377 soc_counter_hw_idx_get_f soc_counter_hw_idx_get; 378 379 } soc_counter_non_dma_t; 380 381 typedef struct soc_counter_evict_s { 382 int pkt_counter_id; /* soc_counter_non_dma_id_t */ 383 int byte_counter_id; /* soc_counter_non_dma_id_t */ 384 int offset[SOC_MAX_NUM_PIPES]; /* offset into above counter id buffer */ 385 int pool_id; 386 soc_mem_t mem[SOC_MAX_NUM_PIPES]; 387 } soc_counter_evict_t; 388 389 #define _SOC_CONTROLLED_COUNTER_FLAG_NOT_PRINTABLE 0x1 390 #define _SOC_CONTROLLED_COUNTER_FLAG_RX 0x2 391 #define _SOC_CONTROLLED_COUNTER_FLAG_TX 0x4 392 #define _SOC_CONTROLLED_COUNTER_FLAG_LOW 0x8 393 #define _SOC_CONTROLLED_COUNTER_FLAG_MEDIUM 0x10 394 #define _SOC_CONTROLLED_COUNTER_FLAG_HIGH 0x20 395 #define _SOC_CONTROLLED_COUNTER_FLAG_NIF 0x40 396 #define _SOC_CONTROLLED_COUNTER_FLAG_MAC 0x80 397 #define _SOC_CONTROLLED_COUNTER_FLAG_ILKN 0x100 398 #define _SOC_CONTROLLED_COUNTER_FLAG_INVALID 0xffffffff 399 400 401 /* controlled (programmable) counters*/ 402 typedef int (*soc_get_counter_f)(int unit, int counter_id, int port, uint64* val, uint32* clear_on_read); 403 typedef int (*soc_clear_counter_f)(int unit, int counter_id, int port); 404 typedef int (*soc_get_counter_length_f)(int unit, int counter_id, int *length); 405 typedef struct soc_controlled_counter_s { 406 soc_get_counter_f controlled_counter_f; 407 int counter_id; 408 char* cname; 409 char* short_cname; /*up to 18 chars*/ 410 uint32 flags; 411 uint32 counter_idx; 412 soc_clear_counter_f controlled_counter_clear_f; 413 soc_get_counter_length_f controlled_counter_length_f; 414 } soc_controlled_counter_t; 415 416 #define _SOC_CONTROLLED_COUNTER_NOF(unit) SOC_CONTROL(unit)->soc_controlled_counter_all_num 417 #define _SOC_CONTROLLED_COUNTER_USE(unit, port) ( \ 418 SOC_IS_DFE(unit) || SOC_IS_DNXF(unit) || SOC_IS_DNX(unit) || \ 419 (SOC_IS_ARAD(unit) && (IS_SFI_PORT(unit, port) || IS_IL_PORT(unit, port))) \ 420 ) 421 422 /* this is the init value for counter_idx field (from struct soc_controlled_counter_t), */ 423 /* while the counter_idx is equal to COUNTER_IDX_NOT_INITIALIZED it means the counter */ 424 /* is not collected by the counter thread. */ 425 #define COUNTER_IDX_NOT_INITIALIZED 0xFFFFFFFF 426 427 #define COUNTER_IS_COLLECTED(ctr) (COUNTER_IDX_NOT_INITIALIZED != ctr.counter_idx) 428 429 /* 430 * Nomenclature: 431 * 432 * Counter register: enum value such as RPKTr 433 * Counter port_offset: Physical S-Channel address with port included 434 * Counter offset: Physical S-Channel address, lower 8 bits only 435 * Counter port_index: Index of counter in DMA buffer given port 436 * Counter index: Index of counter in counter map 437 */ 438 439 #define COUNTER_OFF_MIN_STRATA 0x20 /* Strata stat reg offset */ 440 #define COUNTER_OFF_MIN_DRACO 0x20 /* Draco stat offs, 0x20-0x75 */ 441 #define COUNTER_OFF_MIN_TUCANA 0x20 442 #define COUNTER_OFF_MIN_DEFAULT 0x20 /* Default matches all above */ 443 #define COUNTER_OFF_MIN_HERC 0x09 /* Herc stat offs, 0x09-0x49 */ 444 #define COUNTER_OFF_MIN_LYNX 0x1d0 /* Lynx stat offs, 0x1d0-0x239 */ 445 #define COUNTER_OFF_MIN_HERC15 0x1d0 /* Herc15 stat, 0x1d0-0x23d */ 446 447 448 /* 449 * Counter thread control 450 */ 451 #define SOC_COUNTER_F_DMA 0x00000001 452 #define SOC_COUNTER_F_SWAP64 0x00010000 /* DMA buf 64 bit vals 453 * must be word swapped 454 * (internal only) 455 */ 456 #define SOC_COUNTER_F_HOLD 0x00020000 /* Special handling of 457 * HOLD counter 458 * (internal only) 459 */ 460 461 typedef enum soc_ctr_type_e { 462 SOC_CTR_TYPE_FE, 463 SOC_CTR_TYPE_GE, 464 SOC_CTR_TYPE_GFE, 465 SOC_CTR_TYPE_HG, 466 SOC_CTR_TYPE_XE, 467 SOC_CTR_TYPE_CE, 468 SOC_CTR_TYPE_CD, 469 SOC_CTR_TYPE_CPU, 470 SOC_CTR_TYPE_RX, 471 SOC_CTR_TYPE_TX, 472 SOC_CTR_NUM_TYPES /* Last please */ 473 } soc_ctr_type_t; 474 475 #define SOC_CTR_TYPE_NAMES_INITIALIZER { \ 476 "FE", \ 477 "GE", \ 478 "GFE", \ 479 "HG", \ 480 "XE", \ 481 "CE", \ 482 "CD", \ 483 "CPU", \ 484 "RX", \ 485 "TX", \ 486 "XGE", \ 487 } 488 489 /* Counter Instance Encode */ 490 #define CTR_INSTANCE_BIT_SHIFT_PIPE (0) 491 #define CTR_INSTANCE_BIT_MASK_PIPE (0x0000000F) 492 #define CTR_INSTANCE_BIT_SHIFT_POOL (4) 493 #define CTR_INSTANCE_BIT_MASK_POOL (0x000003F0) 494 #define CTR_INSTANCE_BIT_SHIFT_XPE (10) 495 #define CTR_INSTANCE_BIT_MASK_XPE (0x00003C00) 496 #define CTR_INSTANCE_BIT_SHIFT_PORT (14) 497 #define CTR_INSTANCE_BIT_MASK_PORT (0x00FFC000) 498 #define CTR_INSTANCE_BIT_SHIFT_ITM (24) 499 #define CTR_INSTANCE_BIT_MASK_ITM (0x03000000) 500 501 502 typedef enum soc_ctr_instance_type_e { 503 SOC_CTR_INSTANCE_TYPE_PORT, 504 SOC_CTR_INSTANCE_TYPE_POOL, 505 SOC_CTR_INSTANCE_TYPE_PIPE, 506 SOC_CTR_INSTANCE_TYPE_XPE, /*Supports for mmu type port */ 507 SOC_CTR_INSTANCE_TYPE_ITM, 508 SOC_CTR_INSTANCE_TYPE_POOL_PIPE, /* Support for pool_pipe combination */ 509 SOC_CTR_INSTANCE_TYPE_XPE_PORT, /* Support for xpe_port combination */ 510 SOC_CTR_INSTANCE_TYPE_SFLOW, /* Support for sFlow counters */ 511 SOC_CTR_INSTANCE_TYPE_FT_GROUP, /* Support for FT counters. */ 512 SOC_CTR_INSTANCE_TYPE_ITM_PORT /* Support for itm_port combination */ 513 } soc_ctr_instance_type_t; 514 515 typedef struct soc_ctr_control_info_s{ 516 soc_ctr_instance_type_t instance_type; 517 uint32 instance; 518 } soc_ctr_control_info_t; 519 520 /* Flags for Generic Get/MultiGet */ 521 #define SOC_COUNTER_SYNC_ENABLE 0x1 522 523 typedef enum soc_ctr_ctrl_type_e { 524 SOC_CTR_CTRL_CONFIG_DMA_ENABLE, /* Enable/Disable Counter DMA */ 525 SOC_CTR_CTRL_CONFIG_DMA_MINIDX, /* Config Min idx for DMA */ 526 SOC_CTR_CTRL_CONFIG_DMA_MAXIDX, /* Config Max idx for DMA */ 527 SOC_CTR_CTRL_CONFIG_DMA_RATE_PROFILE_ALL, /* DMA profile: 1 - Enable ALL, 528 * 0 - Disable ALL profiles */ 529 SOC_CTR_CTRL_CONFIG_DMA_RATE_PROFILE_AUTO, /* AUTO profile choice */ 530 SOC_CTR_CTRL_CONFIG_DMA_RATE_PROFILE_WFS, /* Selection based on Weights */ 531 SOC_CTR_CTRL_CONFIG_COUNT 532 }soc_ctr_ctrl_type_t; 533 534 typedef struct soc_ctr_ctrl_config_s { 535 soc_ctr_ctrl_type_t config_type; 536 int config_val; 537 }soc_ctr_ctrl_config_t; 538 539 typedef int (*soc_counter_dma_config_update)(int unit, 540 soc_counter_non_dma_t *dma, 541 uint32 profile, int val); 542 typedef int (*soc_counter_get_child_dma)(int unit, soc_reg_t id, 543 soc_ctr_control_info_t ctrl_info, 544 soc_counter_non_dma_t **child_dma); 545 typedef void (*soc_counter_collect_non_dma)(int unit, int tmp_port, 546 int port_idx, int ar_idx, 547 soc_reg_t ctr_reg); 548 typedef int (*soc_counter_port_obm_info_get)(int unit, soc_port_t port, 549 int *obm_id, int *lane); 550 typedef struct soc_counter_control_s { 551 soc_counter_dma_config_update dma_config_update; 552 soc_counter_get_child_dma get_child_dma; 553 soc_counter_collect_non_dma collect_non_stat_dma; 554 soc_counter_port_obm_info_get port_obm_info_get; /* Get obm_id, lane_id 555 * for logical port */ 556 uint32 total_dma_entries; /* total num of non stat 557 * dma entries */ 558 } soc_counter_control_t; 559 560 extern int soc_ser_update_counter(int unit, int is_reg, 561 soc_reg_t restore_reg, 562 soc_mem_t restore_mem, int index, 563 int copyno, soc_reg_t base_reg, 564 soc_mem_t base_mem, int inst_num, 565 int pipe, int restore_last); 566 567 extern soc_counter_control_t *soc_counter_control[SOC_MAX_NUM_DEVICES]; 568 #define SOC_CTR_CTRL(unit) soc_counter_control[(unit)] 569 570 571 typedef struct soc_ctr_reg_desc { 572 soc_regtype_t reg; 573 uint8 width; 574 uint16 entries; 575 uint16 shift; 576 } soc_ctr_reg_desc_t; 577 578 #define MAX_CTR_REG_PER_BLK 20 579 580 typedef struct soc_blk_ctr_reg_desc { 581 soc_block_t blk; 582 soc_ctr_reg_desc_t desc[MAX_CTR_REG_PER_BLK]; 583 } soc_blk_ctr_reg_desc_t; 584 585 typedef struct soc_blk_ctr_process { 586 soc_block_t blk; 587 uint16 bindex; 588 uint16 entries; 589 uint64 *buff; 590 uint64 *hwval; 591 uint64 *swval; 592 } soc_blk_ctr_process_t; 593 594 #define SOC_COUNTER_INTERVAL_DEFAULT 1000000 595 #define SOC_COUNTER_INTERVAL_SIM_DEFAULT 25000000 596 597 extern int soc_counter_attach(int unit); 598 extern int soc_counter_detach(int unit); 599 extern int soc_counter_start(int unit, uint32 flags, 600 int interval, pbmp_t pbmp); 601 extern int soc_counter_status(int unit, uint32 *flags, 602 int *interval, pbmp_t *pbmp); 603 extern int soc_counter_sync(int unit); 604 extern int soc_counter_stop(int unit); 605 extern int soc_counter_port_collect_enable_set(int unit, 606 int port, int enable); 607 extern void soc_counter_ctr_reset_to_zero(int unit); 608 extern int soc_counter_non_dma_pbmp_update(int unit); 609 /* 610 * Routines to fetch counter values. 611 * These return non-zero if the counter changed since the last 'get'. 612 */ 613 614 extern int soc_counter_generic_multi_get(int unit, soc_reg_t ctr_reg, 615 soc_ctr_control_info_t ctrl_info, 616 uint32 flags, int ar_idx, int count, 617 uint64 *val); 618 extern int soc_counter_generic_get_info(int unit, 619 soc_ctr_control_info_t ctrl_info, 620 soc_reg_t id, int *base_index, 621 int *num_entries); 622 extern int soc_counter_generic_get(int unit, soc_reg_t ctr_reg, 623 soc_ctr_control_info_t ctrl_info, 624 uint32 flags, int ar_idx, uint64 *val); 625 extern int soc_counter_get(int unit, soc_port_t port, soc_reg_t ctr_reg, 626 int ar_idx, uint64 *val); 627 extern int soc_counter_get32(int unit, soc_port_t port, soc_reg_t ctr_reg, 628 int ar_idx, uint32 *val); 629 extern int soc_counter_get_zero(int unit, soc_port_t port, soc_reg_t ctr_reg, 630 int ar_idx, uint64 *val); 631 extern int soc_counter_get32_zero(int unit, soc_port_t port, soc_reg_t ctr_reg, 632 int ar_idx, uint32 *val); 633 extern int soc_counter_get_rate(int unit, soc_port_t port, soc_reg_t ctr_reg, 634 int ar_idx, uint64 *rate); 635 extern int soc_counter_get32_rate(int unit, soc_port_t port, soc_reg_t ctr_reg, 636 int ar_idx, uint32 *rate); 637 extern int soc_counter_sync_get(int unit, soc_port_t port, soc_reg_t ctr_reg, 638 int ar_idx, uint64 *val); 639 extern int soc_counter_sync_get32(int unit, soc_port_t port, soc_reg_t ctr_reg, 640 int ar_idx, uint32 *val); 641 extern int soc_counter_direct_get(int unit, soc_port_t port, soc_reg_t ctr_reg, 642 int ar_idx, uint64 *val); 643 644 extern int soc_counter_port_pbmp_add(int unit, int port); 645 extern int soc_counter_port_pbmp_remove(int unit, int port); 646 647 648 /* 649 * Routines to set counter values, normally used to clear them to zero. 650 * These work by reading the counters to synchronize the software and 651 * hardware counters, then set the software counters. 652 */ 653 654 extern int soc_counter_generic_multi_set(int unit, soc_reg_t ctr_reg, 655 soc_ctr_control_info_t ctrl_info, 656 uint32 flags, int ar_idx, int count, 657 uint64 *val); 658 659 extern int soc_counter_generic_set(int unit, soc_reg_t id, 660 soc_ctr_control_info_t ctrl_info, 661 uint32 flags, int ar_idx, uint64 val); 662 663 extern int soc_counter_config_multi_get(int unit, soc_reg_t ctr_reg, int count, 664 soc_ctr_control_info_t *ctrl_info, 665 soc_ctr_ctrl_config_t *ctrl_config); 666 667 extern int soc_counter_config_multi_set(int unit, soc_reg_t ctr_reg, int count, 668 soc_ctr_control_info_t *ctrl_info, 669 soc_ctr_ctrl_config_t *ctrl_config); 670 671 extern int soc_counter_set(int unit, soc_port_t port, soc_reg_t id, 672 int ar_idx, uint64 val); 673 extern int soc_counter_set32(int unit, soc_port_t port, soc_reg_t ctr_reg, 674 int ar_idx, uint32 val); 675 extern int soc_counter_set_by_port(int unit, pbmp_t pbmp, uint64 val); 676 extern int soc_counter_set32_by_port(int unit, pbmp_t pbmp, uint32 val); 677 extern int soc_counter_set_by_reg(int unit, soc_reg_t ctr_reg, 678 int ar_idx, uint64 val); 679 extern int soc_counter_set32_by_reg(int unit, soc_reg_t ctr_reg, 680 int ar_idx, uint32 val); 681 extern int soc_counter_clear_by_port_reg(int unit, soc_port_t port, 682 soc_reg_t ctr_reg, 683 int ar_idx, uint64 val); 684 extern int soc_controlled_counter_update_by_port(int unit, soc_port_t dst_port, 685 soc_port_t src_port); 686 extern int soc_controlled_counter_clear(int unit, soc_port_t port); 687 extern int soc_port_cmap_set(int unit, soc_port_t port, soc_ctr_type_t ctype); 688 extern soc_cmap_t *soc_port_cmap_get(int unit, soc_port_t port); 689 690 extern int soc_counter_idx_get(int unit, soc_reg_t reg, int ar_idx, int port); 691 692 #if defined(BCM_XGS5_SWITCH_PORT_SUPPORT) 693 extern int 694 soc_counter_port_sbusdma_desc_alloc(int unit, soc_port_t port); 695 696 extern int 697 soc_counter_port_sbusdma_desc_free(int unit, soc_port_t port); 698 #endif /* BCM_XGS5_SWITCH_PORT_SUPPORT */ 699 700 #ifdef BCM_SBUSDMA_SUPPORT 701 extern int soc_blk_counter_set(int unit, soc_block_t blk, soc_reg_t ctr_reg, 702 int ar_idx, uint64 val); 703 extern int soc_blk_counter_get(int unit, soc_block_t blk, soc_reg_t ctr_reg, 704 int ar_idx, uint64 *val); 705 #endif 706 707 /* Counter eviction functions */ 708 extern int soc_counter_eviction_sync(int unit); 709 /* For encoding different instance types into one instance for generic get/set 710 */ 711 extern int soc_counter_instance_encode(soc_ctr_control_info_t *input_ctrl_info, 712 int count, 713 soc_ctr_control_info_t *output_ctrl_info); 714 715 /* 716 * Driver internal and debugging use only 717 */ 718 extern int soc_counter_autoz(int unit, int enable); 719 extern int soc_counter_timestamp_get(int unit, soc_port_t port, 720 uint32 *timestamp); 721 722 /* For registering additional counter collection */ 723 typedef void (*soc_counter_extra_f)(int unit); 724 725 extern int soc_counter_extra_register(int unit, soc_counter_extra_f fn); 726 extern int soc_counter_extra_unregister(int unit, soc_counter_extra_f fn); 727 728 #ifdef BROADCOM_DEBUG 729 extern void _soc_counter_verify(int unit); /* Verify counter map consistent */ 730 #endif /* BROADCOM_DEBUG */ 731 732 #endif /* !_SOC_COUNTER_H */