cmicx_miim.h (4107B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * CMICx MIIM (MDIO) functions 8 */ 9 10 #ifndef _SOC_CMICX_MIIM_H 11 #define _SOC_CMICX_MIIM_H 12 13 #include <sal/types.h> 14 15 #define SOC_CLAUSE_45 45 16 #define SOC_CLAUSE_22 22 17 18 #define CMICX_MIIM_RING_INDEX_START 0 19 #define CMICX_MIIM_RING_INDEX_END 7 20 #define CMICX_MIIM_12R_RING_INDEX_END 11 21 22 /* MDIO CYCLE types for iProc 15 and higher devices 23 * with support for 12 MDIO rings */ 24 25 #define MIIM_CYCLE_12R_C22_REG_WR 0x0 26 #define MIIM_CYCLE_12R_C22_REG_RD 0x1 27 #define MIIM_CYCLE_12R_C45_AUTO_WR 0x2 28 #define MIIM_CYCLE_12R_C45_AUTO_RD 0x3 29 #define MIIM_CYCLE_12R_C45_REG_AD 0x4 30 #define MIIM_CYCLE_12R_C45_REG_WR 0x5 31 #define MIIM_CYCLE_12R_C45_REG_RD 0x6 32 #define MIIM_CYCLE_12R_C45_REG_RD_ADINC 0x7 33 34 #define MIIM_INTERNAL_EXTERNAL_DELAY_INVALID -1 35 36 /******************************************* 37 * @function soc_cmicx_miim_init 38 * purpose Initialization required for MIIM module 39 * 40 * @param unit [in] unit 41 * 42 * @returns SOC_E_NONE 43 * @returns SOC_E_XXX 44 * 45 * @end 46 * @comments This function give MDIO access to IPROC 47 */ 48 extern int soc_cmicx_miim_init(int unit); 49 50 /******************************************* 51 * @function soc_cmicx_miim_divider_set_ring 52 * purpose set MDIO frequency related properties for a given MIIM ring 53 * 54 * @param unit [in] unit # 55 * @param unit [in] ring_idx - MIIM ring index. 56 * @param unit [in] int_divider - The clock divider configuration register for Internal MDIO. use -1 to keep current configuration. 57 * @param unit [in] ext_divider - The clock divider configuration register for External MDIO. use -1 to keep current configuration. 58 * @param unit [in] out_delay - MDIO Output Delay. use -1 to keep current configuration. 59 * 60 * @returns SOC_E_BUSY 61 * @returns SOC_E_NONE 62 * 63 * @end 64 * @comments This function configure all MDIO rings 65 */ 66 extern int soc_cmicx_miim_divider_set_ring(int unit, int ring_index, int int_divider, int ext_divider, int out_delay); 67 68 /******************************************* 69 * @function soc_cmicx_miim_divider_set_all 70 * purpose set MDIO frequency related properties for all MIIM rings (0 to 7) 71 * 72 * @param unit [in] unit # 73 * @param unit [in] int_divider - The clock divider configuration register for Internal MDIO. use -1 to keep current configuration. 74 * @param unit [in] ext_divider - The clock divider configuration register for External MDIO. use -1 to keep current configuration. 75 * @param unit [in] out_delay - MDIO Output Delay. use -1 to keep current configuration. 76 * 77 * @returns SOC_E_BUSY 78 * @returns SOC_E_NONE 79 * 80 * @end 81 * @comments This function configure all MDIO rings 82 */ 83 extern int soc_cmicx_miim_divider_set_all(int unit, int int_divider, int ext_divider, int out_delay); 84 85 /******************************************* 86 * @function soc_cmicx_miim_operation 87 * purpose perform miim read or write operation 88 * 89 * @param unit [in] unit # 90 * @param unit [in] is_write - whether to perform read or write operation 91 * @param unit [in] clause - whether to perform clause 45 or clause 22 operation 92 * @param unit [in] phy_id - phy to access. phy_id encoding: 93 * bit7, 1: internal MDIO bus, 0: external MDIO bus 94 * bit9,8,6,5, mdio bus number 95 * bit4-0, mdio addresses 96 * @param unit [in] phy_reg_addr - CL45/CL22 register address. For CL45, Encoded according to SOC_PHY_CLAUSE45_ADDR macro. 97 * @param unit [inout] phy_data - data to wrote in case is_write is true, data read from register otehrwise. 98 * 99 * @returns SOC_E_BUSY 100 * @returns SOC_E_NONE 101 * 102 * @end 103 * @comments 104 * This function takes MIIM lock 105 * Waiting for MIIM done is done by polling (interrupt mode isn't supported) 106 */ 107 extern int soc_cmicx_miim_operation(int unit, int is_write, int clause, 108 int int_delay, int ext_delay, uint32 phy_id, 109 uint32 phy_reg_addr, uint16 *phy_data); 110 111 #endif /* !_SOC_CMICX_MIIM_H */ 112