cmicx.h (18731B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: cmicx.h 8 * Purpose: CMICX registers include file 9 */ 10 #ifndef _SOC_CMICX_H 11 #define _SOC_CMICX_H 12 13 #include <soc/mcm/cmicx.h> 14 #include <soc/cmic.h> 15 16 /* Use this file for stuff that are not Auto-Generated */ 17 #define CMIC_CMC_NUM_MAX (2) 18 19 #define CMIC_SCHAN_NUM_MAX (3) 20 #define CMIC_CCMDMA_NUM_MAX (2) 21 #define CMIC_TOP_SBUS_RING_ARB_CTRL_SET (0xEEEEEEEE) 22 23 #define CMIC_COMMON_POOL_SCHAN_CHx_MESSAGEn(ch, n) \ 24 (CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE_OFFSET + (ch*0x100) + (4*n)) 25 #define CMIC_COMMON_POOL_SCHAN_CHx_CTRL(ch) \ 26 (CMIC_COMMON_POOL_SCHAN_CH0_CTRL_OFFSET + (ch*0x100)) 27 28 #define CMIC_COMMON_POOL_SCHAN_CHx_ERR(ch) \ 29 (CMIC_COMMON_POOL_SCHAN_CH0_ERR_OFFSET + (ch*0x100)) 30 31 32 /* CMIC_COMMON_POOL_SCHAN_CHx_CTRL(x) */ 33 #define SC_CHx_MSG_CLR (0x00000000) 34 #define SC_CHx_MSG_START (0x00000001) 35 #define SC_CHx_MSG_DONE (0x00000002) 36 #define SC_CHx_SCHAN_ABORT (0x00000004) 37 #define SC_CHx_MSG_SER_CHECK_FAIL (0x00100000) 38 #define SC_CHx_MSG_NAK (0x00200000) 39 #define SC_CHx_MSG_TIMEOUT_TST (0x00400000) 40 #define SC_CHx_MSG_SCHAN_ERR (0x00800000) 41 42 /* CMIC_COMMON_POOL_SCHAN_CHx_ERR(x) */ 43 #define SC_CHx_SCHAN_ERR_NACK_BIT (0x00000001) 44 #define SC_CHx_SCHAN_ERR_ERR_BIT (0x00000040) 45 46 /* CMC */ 47 #define CMIC_CMCx_PCI (0x0) 48 #define CMIC_CMCx_AXI (0x1) 49 50 /* SBUSDMA stuff */ 51 52 #define CMIC_CMCx_SBUSDMA_CHAN_MAX (4) 53 #define CMIC_CMC0_SBUSDMA_CH_MASK (0xf) 54 #define CMIC_CMC1_SBUSDMA_CH_MASK (0xf) 55 56 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL(x, y) \ 57 (CMIC_CMCx_SBUSDMA_CH0_CONTROL_OFFSET(x) + (y * 0x100)) 58 #define CMIC_CMCx_SBUSDMA_CHy_REQUEST(x, y) \ 59 (CMIC_CMCx_SBUSDMA_CH0_REQUEST_OFFSET(x) + (y * 0x100)) 60 #define CMIC_CMCx_SBUSDMA_CHy_COUNT(x, y) \ 61 (CMIC_CMCx_SBUSDMA_CH0_COUNT_OFFSET(x) + (y * 0x100)) 62 #define CMIC_CMCx_SBUSDMA_CHy_OPCODE(x, y) \ 63 (CMIC_CMCx_SBUSDMA_CH0_OPCODE_OFFSET(x) + (y * 0x100)) 64 #define CMIC_CMCx_SBUSDMA_CHy_ADDRESS(x, y) \ 65 (CMIC_CMCx_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET(x) + (y * 0x100)) 66 #define CMIC_CMCx_SBUSDMA_CHy_HOSTADDR_LO(x, y) \ 67 (CMIC_CMCx_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO_OFFSET(x) + (y * 0x100)) 68 #define CMIC_CMCx_SBUSDMA_CHy_HOSTADDR_HI(x, y) \ 69 (CMIC_CMCx_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI_OFFSET(x) + (y * 0x100)) 70 #define CMIC_CMCx_SBUSDMA_CHy_DESCADDR_LO(x, y) \ 71 (CMIC_CMCx_SBUSDMA_CH0_DESC_START_ADDRESS_LO_OFFSET(x) + (y * 0x100)) 72 #define CMIC_CMCx_SBUSDMA_CHy_DESCADDR_HI(x, y) \ 73 (CMIC_CMCx_SBUSDMA_CH0_DESC_START_ADDRESS_HI_OFFSET(x) + (y * 0x100)) 74 #define CMIC_CMCx_SBUSDMA_CHy_STATUS(x, y) \ 75 (CMIC_CMCx_SBUSDMA_CH0_STATUS_OFFSET(x) + (y * 0x100)) 76 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSDMA_CONFIG_OPCODE(x, y) \ 77 (CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET(x) + (y * 0x100)) 78 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSDMA_CONFIG_ADDR_LO(x, y) \ 79 (CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO_OFFSET(x) + (y * 0x100)) 80 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSDMA_CONFIG_ADDR_HI(x, y) \ 81 (CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI_OFFSET(x) + (y * 0x100)) 82 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSDMA_CONFIG_COUNT(x, y) \ 83 (CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT_OFFSET(x) + (y * 0x100)) 84 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSDMA_CONFIG_REQUEST(x, y) \ 85 (CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST_OFFSET(x) + (y * 0x100)) 86 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS(x, y) \ 87 (CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET(x) + (y * 0x100)) 88 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSDMA_ITER_COUNT(x, y) \ 89 (CMIC_CMCx_SBUSDMA_CH0_ITER_COUNT_OFFSET(x) + (y * 0x100)) 90 #define CMIC_CMCx_SBUSDMA_CHy_CUR_HOSTMEM_ADDRESS_LO(x, y) \ 91 (CMIC_CMCx_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO_OFFSET(x) + (y * 0x100)) 92 #define CMIC_CMCx_SBUSDMA_CHy_CUR_HOSTMEM_ADDRESS_HI(x, y) \ 93 (CMIC_CMCx_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI_OFFSET(x) + (y * 0x100)) 94 #define CMIC_CMCx_SBUSDMA_CHy_CUR_DESC_ADDRESS_LO(x, y) \ 95 (CMIC_CMCx_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO_OFFSET(x) + (y * 0x100)) 96 #define CMIC_CMCx_SBUSDMA_CHy_CUR_DESC_ADDRESS_HI(x, y) \ 97 (CMIC_CMCx_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI_OFFSET(x) + (y * 0x100)) 98 99 /* CMIC_CMCx_SBUSDMA_CHy_CONTROL */ 100 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_START 1 101 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_ABORT 2 102 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_MODE 4 103 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_DESCRIPTOR_ENDIANESS 8 104 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_DESC_PREFETCH_ENABLE 0x10 105 106 /* CMIC_CMCx_SBUSDMA_CHy_STATUS */ 107 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_DONE 1 108 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_ERROR 2 109 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_HOSTMEMWR_ERROR 4 110 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_HOSTMEMRD_ERROR 8 111 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_SER_CHECK_FAIL 0x10 112 113 /* CMIC_CMCx_SBUSDMA_CHy_CONTROL */ 114 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_START 1 115 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_ABORT 2 116 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_MODE 4 117 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_DESCRIPTOR_ENDIANESS 8 118 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL_DESC_PREFETCH_ENABLE 0x10 119 120 /* CMIC_CMCx_SBUSDMA_CHy_STATUS */ 121 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_DONE 1 122 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_ERROR 2 123 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_HOSTMEMWR_ERROR 4 124 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_HOSTMEMRD_ERROR 8 125 #define CMIC_CMCx_SBUSDMA_CHy_STATUS_SER_CHECK_FAIL 0x10 126 127 128 /* SCHAN FIFO */ 129 #define CMIC_SCHAN_FIFO_NUM_MAX (2) 130 /* Number of commands SCHAN FIFO can accomodate in one channel */ 131 #define CMIC_SCHAN_FIFO_CMD_SIZE_MAX (16) 132 #define MAP_SCHAN_FIFO_MEMWR_REQ_CMC0 (0x00) 133 #define MAP_SCHAN_FIFO_MEMWR_REQ_CMC1 (0x01) 134 #define SCHAN_FIFO_MEMWR_WRR_WEIGHT (0x0E) 135 #define SCHAN_FIFO_AXI_ID (0x05) 136 #define SCHAN_FIFO_RESPONSE_WORD_SIZE (32) /*128 bytes aligned */ 137 #define SCHAN_FIFO_SUMMARY_ACKDATA_MASK (0xFF) 138 #define SCHAN_FIFO_SUMMARY_STAT_SHIFT (8) 139 140 141 142 #define CMIC_SCHAN_FIFO_CHx_CTRL(x) \ 143 (CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_CTRL_OFFSET + x*0x18) 144 #define CMIC_SCHAN_FIFO_CHx_RESP_ADDR_LOWER(x) \ 145 (CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_LOWER_OFFSET + x * 0x18) 146 #define CMIC_SCHAN_FIFO_CHx_RESP_ADDR_UPPER(x) \ 147 (CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_UPPER_OFFSET + x * 0x18) 148 149 #define CMIC_SCHAN_FIFO_CHx_STATUS(x) \ 150 (CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_STATUS_OFFSET + x * 0x18) 151 #define CMIC_SCHAN_FIFO_CHx_SUMMARY_ADDR_LOWER(x) \ 152 (CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_LOWER_OFFSET + x * 0x18) 153 #define CMIC_SCHAN_FIFO_CHx_SUMMARY_ADDR_UPPER(x) \ 154 (CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_UPPER_OFFSET + x * 0x18) 155 #define CMIC_SCHAN_FIFO_CHx_COMMAND(x, n) \ 156 (CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY_OFFSET + (x * 0x580) + (4 * n)) 157 158 #define SCHAN_FIFO_SUMRY_STAT_COMPLETE (0x00 << (5 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 159 #define SCHAN_FIFO_SUMRY_STAT_ECCERR (0x01 << (5 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 160 #define SCHAN_FIFO_SUMRY_STAT_SBUSERR (0x02 << (5 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 161 #define SCHAN_FIFO_SUMRY_STAT_OTHERR (0x03 << (5 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 162 163 #define SCHAN_FIFO_SUMRY_ERR_SBUSNACK (0x01 + SCHAN_FIFO_SUMMARY_STAT_SHIFT) 164 #define SCHAN_FIFO_SUMRY_ERR_SBUSECODE (0x03 << (1 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 165 #define SCHAN_FIFO_SUMRY_ERR_SBUSERR (0x01 << (3 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 166 #define SCHAN_FIFO_SUMRY_ERR_OPCODE (0x01 << (4 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 167 168 #define SCHAN_FIFO_SUMRY_ABRT_ECCCMD (0x01 + SCHAN_FIFO_SUMMARY_STAT_SHIFT) 169 #define SCHAN_FIFO_SUMRY_ABRT_OPCODE (0x01 << (1 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 170 #define SCHAN_FIFO_SUMRY_ABRT_CMDLEN (0x01 << (2 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 171 #define SCHAN_FIFO_SUMRY_ABRT_TIMOUT (0x01 << (3 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 172 #define SCHAN_FIFO_SUMRY_ABRT_DBEAT (0x01 << (4 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 173 #define SCHAN_FIFO_SUMRY_ABRT_ECCMEM (0x01 << (5 + SCHAN_FIFO_SUMMARY_STAT_SHIFT)) 174 175 #define SCHAN_FIFO_SUMMARY_UPDATE_INTERVAL (0x10) 176 #define SCHAN_FIFO_MSG_DONE (0x01) 177 178 /* fields of CMIC_COMMON_POOL_SCHAN_FIFO_0_CHy_CTRL / CMIC_SCHAN_FIFO_CHx_CTRL */ 179 #define SCHAN_FIFO_CTRL_START 1 180 #define SCHAN_FIFO_CTRL_ABORT 2 181 /* fields of CMIC_COMMON_POOL_SCHAN_FIFO_0_CHy_STATUS / CMIC_SCHAN_FIFO_CHx_STATUS(x) */ 182 #define SCHAN_FIFO_STATUS_DONE 1 183 #define SCHAN_FIFO_STATUS_ERROR 2 184 185 /* CCM DMA */ 186 #define CMICX_N_CCMDMA_CHAN 2 187 188 #define CMIC_CMCx_CCMDMA_CHy_HOST0_MEM_START_ADDR_LO_OFFSET(x,y) \ 189 (CMIC_CMCx_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO_OFFSET(x) + (y * 0x80)) 190 #define CMIC_CMCx_CCMDMA_CHy_HOST0_MEM_START_ADDR_HI_OFFSET(x,y) \ 191 (CMIC_CMCx_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI_OFFSET(x) + (y * 0x80)) 192 #define CMIC_CMCx_CCMDMA_CHy_HOST1_MEM_START_ADDR_LO_OFFSET(x,y) \ 193 (CMIC_CMCx_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO_OFFSET(x) + (y * 0x80)) 194 #define CMIC_CMCx_CCMDMA_CHy_HOST1_MEM_START_ADDR_HI_OFFSET(x,y) \ 195 (CMIC_CMCx_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI_OFFSET(x) + (y * 0x80)) 196 #define CMIC_CMCx_CCMDMA_CHy_ENTRY_COUNT_OFFSET(x,y) \ 197 (CMIC_CMCx_CCMDMA_CH0_ENTRY_COUNT_OFFSET(x) + (y * 0x80)) 198 #define CMIC_CMCx_CCMDMA_CHy_CFG_OFFSET(x,y) \ 199 (CMIC_CMCx_CCMDMA_CH0_CFG_OFFSET(x) + (y * 0x80)) 200 #define CMIC_CMCx_CCMDMA_CHy_STAT_OFFSET(x,y) \ 201 (CMIC_CMCx_CCMDMA_CH0_STAT_OFFSET(x) + (y * 0x80)) 202 203 /* CMIC_CMCx_CCMDMA_CHy_CFG fields */ 204 #define CMIC_CMCx_CCMDMA_CHy_CFG_EN 1 205 #define CMIC_CMCx_CCMDMA_CHy_CFG_ABORT 2 206 /* CMIC_CMCx_CCMDMA_CHy_STAT fields */ 207 #define CMIC_CMCx_CCMDMA_CHy_STAT_DONE 1 208 #define CMIC_CMCx_CCMDMA_CHy_STAT_ERROR 2 209 210 /* PCI SLAVE OFFSET */ 211 #define CMIC_PCIE_SO_OFFSET (0x10000000) 212 213 /* Packet DMA related macros */ 214 #define CMIC_CMCx_PKTDMA_NOF_CHANS 8 215 216 #define CMIC_CMCx_PKTDMA_CHy_CTRL_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_CTRL_OFFSET(x) + (y*0x80)) 217 #define CMIC_CMCx_PKTDMA_CHy_CURR_DESC_HI_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_CURR_DESC_HI_OFFSET(x) + (y*0x80)) 218 #define CMIC_CMCx_PKTDMA_CHy_CURR_DESC_LO_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_CURR_DESC_LO_OFFSET(x) + (y*0x80)) 219 #define CMIC_CMCx_PKTDMA_CHy_DESC_ADDR_HI_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DESC_ADDR_HI_OFFSET(x) + (y*0x80)) 220 #define CMIC_CMCx_PKTDMA_CHy_DESC_ADDR_LO_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DESC_ADDR_LO_OFFSET(x) + (y*0x80)) 221 #define CMIC_CMCx_PKTDMA_CHy_DESC_HALT_ADDR_HI_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DESC_HALT_ADDR_HI_OFFSET(x) + (y*0x80)) 222 #define CMIC_CMCx_PKTDMA_CHy_DESC_HALT_ADDR_LO_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DESC_HALT_ADDR_LO_OFFSET(x) + (y*0x80)) 223 #define CMIC_CMCx_PKTDMA_CHy_INTR_COAL_OFFSET(x,y) (CMIC_CMCx_PKTDMA_CH0_INTR_COAL_OFFSET(x) + (y*0x80)) 224 #define CMIC_CMCx_PKTDMA_CHy_PKT_COUNT_RXPKT_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_PKT_COUNT_RXPKT_OFFSET(x) + (y*0x80)) 225 #define CMIC_CMCx_PKTDMA_CHy_PKT_COUNT_RXPKT_DROP_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP_OFFSET(x) + (y*0x80)) 226 #define CMIC_CMCx_PKTDMA_CHy_PKT_COUNT_TXPKT_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_PKT_COUNT_TXPKT_OFFSET(x) + (y*0x80)) 227 #define CMIC_CMCx_PKTDMA_CHy_RXBUF_THRESHOLD_CONFIG_OFFSET(x,y) (CMIC_CMCx_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET(x) + (y*0x80)) 228 #define CMIC_CMCx_PKTDMA_CHy_STAT_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_STAT_OFFSET(x) + (y*0x80)) 229 #define CMIC_CMCx_PKTDMA_CHy_COS_CTRL_RX_0_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_COS_CTRL_RX_0_OFFSET(x) + (y*0x80)) 230 #define CMIC_CMCx_PKTDMA_CHy_COS_CTRL_RX_1_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_COS_CTRL_RX_1_OFFSET(x) + (y*0x80)) 231 #define CMIC_CMCx_PKTDMA_CHy_DESC_COUNT_REQ_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DESC_COUNT_REQ_OFFSET(x) + (y*0x80)) 232 #define CMIC_CMCx_PKTDMA_CHy_DESC_COUNT_RX_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DESC_COUNT_RX_OFFSET(x) + (y*0x80)) 233 #define CMIC_CMCx_PKTDMA_CHy_DESC_COUNT_STATUS_WR_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DESC_COUNT_STATUS_WR_OFFSET(x) + (y*0x80)) 234 #define CMIC_CMCx_PKTDMA_CHy_DEBUG_CONTROL_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DEBUG_CONTROL_OFFSET(x) + (y*0x80)) 235 #define CMIC_CMCx_PKTDMA_CHy_DEBUG_STATUS_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DEBUG_STATUS_OFFSET(x) + (y*0x80)) 236 #define CMIC_CMCx_PKTDMA_CHy_DEBUG_SM_STATUS_OFFSET(x, y) (CMIC_CMCx_PKTDMA_CH0_DEBUG_SM_STATUS_OFFSET(x) + (y*0x80)) 237 238 /* CMIC_CMCx_CHy_DMA_CTRL */ 239 #define PKTDMA_DIRECTION (0x00000001) 240 #define PKTDMA_ENABLE (0x00000002) 241 #define PKTDMA_ABORT (0x00000004) 242 #define PKTDMA_BIG_ENDIAN (0x00000008) 243 #define PKTDMA_DESC_BIG_ENDIAN (0x00000010) 244 #define PKTDMA_DROP_RX_PKT_ON_CHAIN_END (0x00000020) 245 #define PKTDMA_RLD_STATUS_UPD_DIS (0x00000040) 246 #define PKTDMA_DESC_DONE_INTR_MODE (0x00000080) 247 #define PKTDMA_CONTINUOUS_ENABLE (0x00000100) 248 #define PKTDMA_CONTIGUOUS_DESCRIPTORS (0x00000200) 249 #define PKTDMA_HEADER_ENDIAN (0x00001000) 250 #define PKTDMA_DISABLE_ABORT_ON_ERROR (0x00002000) 251 #define PKTDMA_ALMNT_BYTES (0x00000c00) 252 253 #define PKTDMA_CHAIN_DONE (0x00000001) 254 #define PKTDMA_CH_IS_ACTIVE (0x00000002) 255 #define PKTDMA_CH_IN_HALT (0x00000040) 256 257 /* TBD */ 258 #define IRQ_CMCx_CHy_CNTLD_INTR(cmc, chan) 0xFFFFFFFF 259 #define IRQ_CMCx_CHy_DESC_DONE(cmc, chan) 0xEEEEEEEE 260 #define IRQ_CMCx_CHy_CHAIN_DONE(cmc, chan) 0xDDDDDDDD 261 #define IRQ_CMCx_CHy_COAL_INTR(cmc, chan) 0xCCCCCCCC 262 263 /* CMIC_CMC0_SHARED_IRQ_STAT0(x) */ 264 #define DS_CMCx_CHy_DMA_DESC_DONE(y) (0x00000001 << (y * 4)) 265 #define DS_CMCx_CHy_DMA_CHAIN_DONE(y) (0x00000002 << (y * 4)) 266 #define DS_CMCx_CHy_COALESCING_INTR(y) (0x00000004 << (y * 4)) 267 #define DS_CMCx_CHy_DESC_CONTROLLED_INTR(y) (0x00000008 << (y * 4)) 268 269 /* CMIC_CMC0_SHARED_IRQ_STAT_CLR0(x) */ 270 #define DS_CMCx_CHy_DMA_DESC_DONE_CLR(y) (0x00000001 << (y * 4)) 271 #define DS_CMCx_CHy_DMA_CHAIN_DONE_CLR(y) (0x00000002 << (y * 4)) 272 #define DS_CMCx_CHy_COALESCING_INTR_CLR(y) (0x00000004 << (y * 4)) 273 #define DS_CMCx_CHy_DESC_CONTROLLED_INTR_CLR(y) (0x00000008 << (y * 4)) 274 275 /* FIFO DMA stuff */ 276 #define MAP_FIFO_DMA_MEMWR_REQ_CMC0 (0x00) 277 #define MAP_FIFO_DMA_MEMWR_REQ_CMC1 (0x01) 278 #define CMICX_FIFO_DMA_MEMWR_WRR_WEIGHT (0x0E) 279 #define CMICX_FIFO_DMA_AXI_ID (0x06) 280 281 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_CFG_OFFSET(y) (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG_OFFSET + (y*0x80)) 282 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_CFG_1_OFFSET(y) (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG_1_OFFSET + (y*0x80)) 283 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_SBUS_START_ADDRESS_OFFSET(y) (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS_OFFSET + (y*0x80)) 284 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET(y) (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_LO_OFFSET + (y*0x80)) 285 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET(y) (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_HI_OFFSET + (y*0x80)) 286 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET(y) \ 287 (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET + (y*0x80)) 288 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET(y) \ 289 (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET + (y*0x80)) 290 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_HOSTMEM_THRESHOLD_OFFSET(y) (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD_OFFSET + (y*0x80)) 291 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_STAT_OFFSET(y) (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT_OFFSET + (y*0x80)) 292 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_STAT_CLR_OFFSET(y) (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT_CLR_OFFSET + (y*0x80)) 293 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_OPCODE_OFFSET(y) \ 294 (CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_OPCODE_OFFSET + (y*0x80)) 295 /* CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_CFG fields */ 296 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_CFG_ENABLE 1 297 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_CFG_ABORT 0x80000000 298 /* CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_STAT fields */ 299 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_STAT_ERROR 1 300 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_STAT_ACTIVE 2 301 #define CMIC_COMMON_POOL_FIFO_CHy_RD_DMA_STAT_ABORTED 0x10 302 303 /* 304 * This macro may be used to transfer T from microseconds to the value to be entered into 305 * CMIC_COMMON_POOL_FIFO_CH*_RD_DMA_CFG*.TIMEOUT_COUNT*. 306 * Timer runs on reference clock 25MHz. 307 */ 308 #define CMIC_COMMON_POOL_FIFO_USEC_TO_DMA_CFG_TIMEOUT_COUNT(T) (T *= 25); 309 310 #endif /* !_SOC_CMICX_H */