cmicm.h (14332B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 #ifndef _SOC_CMICM_H 8 #define _SOC_CMICM_H 9 10 #include <soc/register.h> 11 #if defined(BCM_ESW_SUPPORT) || defined(BCM_SAND_SUPPORT) 12 #include <soc/mcm/cmicm.h> 13 #include <soc/cmic.h> 14 #endif 15 #include <soc/shared/mos_intr_common.h> 16 17 /* Use this file for stuff that are not Auto-Generated */ 18 19 #define CMIC_CMC_NUM_MAX 3 20 21 #define CMC0 0 22 #define CMC1 1 23 #define CMC2 2 24 25 /* SBUSDMA stuff */ 26 #define CCMDMA_TIMEOUT (5 * SECOND_USEC) 27 #define CCMDMA_TIMEOUT_QT (120 * SECOND_USEC) 28 #define CMIC_CMCx_CCMDMA_CHAN_MAX (1) 29 #define CMIC_CMC0_CCMDMA_CH_MASK (0x1) 30 #define CMIC_CMC1_CCMDMA_CH_MASK (0x1) 31 #define CMIC_CMC2_CCMDMA_CH_MASK (0x1) 32 33 /* Extra "utility" Macros, based on the Auto-Generated addresses */ 34 /* x = CMC No, y=Channel No, n=index */ 35 36 #define CMIC_COMMON_SCHAN_MESSAGEn(n) (CMIC_COMMON_SCHAN_MESSAGE_OFFSET + (4*n)) 37 #define CMIC_CMCx_SCHAN_MESSAGEn(x, n) (CMIC_CMCx_SCHAN_MESSAGE_OFFSET(x) + (4*n)) 38 #define CMIC_SCHAN_MESSAGE_WORDS_MAX 22 39 40 #define CMIC_SEMAPHORE_n(n) (CMIC_SEMAPHORE_1_OFFSET + ((n-1)*8)) 41 #define CMIC_SEMAPHORE_n_SHADOW(n) (CMIC_SEMAPHORE_1_SHADOW_OFFSET + ((n-1)*8)) 42 #define CMIC_PKT_PRI_MAP_TABLE_ENTRY_n(n) (CMIC_PKT_PRI_MAP_TABLE_ENTRY_0_OFFSET + (n*4)) 43 #define CMIC_CMCx_CHy_DMA_CTRL_OFFSET(x,y) (CMIC_CMCx_CH0_DMA_CTRL_OFFSET(x)+(y*4)) 44 #define CMIC_CMCx_DMA_DESCy_OFFSET(x,y) (CMIC_CMCx_DMA_DESC0_OFFSET(x) + (y*4)) 45 #define CMIC_CMCx_CHy_COS_CTRL_RX_0_OFFSET(x,y) (CMIC_CMCx_CH0_COS_CTRL_RX_0_OFFSET(x) + (y*8)) 46 #define CMIC_CMCx_CHy_COS_CTRL_RX_1_OFFSET(x,y) (CMIC_CMCx_CH0_COS_CTRL_RX_1_OFFSET(x) + (y*8)) 47 #define CMIC_CMCx_DMA_CHy_INTR_COAL_OFFSET(x,y) (CMIC_CMCx_DMA_CH0_INTR_COAL_OFFSET(x) + (y*4)) 48 #define CMIC_CMCx_CHy_DMA_CURR_DESC_OFFSET(x,y) (CMIC_CMCx_CH0_DMA_CURR_DESC_OFFSET(x) + (y*4)) 49 #define CMIC_CMCx_FIFO_CHy_RD_DMA_CFG_OFFSET(x,y) (CMIC_CMCx_FIFO_CH0_RD_DMA_CFG_OFFSET(x) + (y*4)) 50 #define CMIC_CMCx_FIFO_CHy_RD_DMA_SBUS_START_ADDRESS_OFFSET(x,y) (CMIC_CMCx_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS_OFFSET(x) + (y*4)) 51 #define CMIC_CMCx_FIFO_CHy_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET(x,y) (CMIC_CMCx_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_OFFSET(x) + (y*4)) 52 #define CMIC_CMCx_FIFO_CHy_RD_DMA_HOSTMEM_READ_PTR_OFFSET(x,y) (CMIC_CMCx_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR_OFFSET(x) + (y*8)) 53 #define CMIC_CMCx_FIFO_CHy_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET(x,y) (CMIC_CMCx_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR_OFFSET(x) + (y*8)) 54 #define CMIC_CMCx_FIFO_CHy_RD_DMA_HOSTMEM_THRESHOLD_OFFSET(x,y) (CMIC_CMCx_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD_OFFSET(x) + (y*4)) 55 #define CMIC_CMCx_FIFO_CHy_RD_DMA_STAT_OFFSET(x,y) (CMIC_CMCx_FIFO_CH0_RD_DMA_STAT_OFFSET(x) + (y*4)) 56 #define CMIC_CMCx_FIFO_CHy_RD_DMA_STAT_CLR_OFFSET(x,y) (CMIC_CMCx_FIFO_CH0_RD_DMA_STAT_CLR_OFFSET(x) + (y*4)) 57 #define CMIC_CMCx_FIFO_CHy_RD_DMA_SBUS_CMD_CONFIG_OFFSET(x,y) (CMIC_CMCx_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG_OFFSET(x) + (y*4)) 58 #define CMIC_CMCx_PKT_COUNT_CHy_TXPKT_OFFSET(x,y) (CMIC_CMCx_PKT_COUNT_CH0_TXPKT_OFFSET(x) + (y*8)) 59 #define CMIC_CMCx_PKT_COUNT_CHy_RXPKT_OFFSET(x,y) (CMIC_CMCx_PKT_COUNT_CH0_RXPKT_OFFSET(x) + (y*8)) 60 #define CMIC_CMCx_CHy_RXBUF_THRESHOLD_CONFIG(x,y) (CMIC_CMCx_CH0_RXBUF_THRESHOLD_CONFIG_OFFSET(x) + (y*4)) 61 62 /* CMICDV2 supports continuous mode */ 63 #define CMIC_CMCx_DMA_CHy_DESC_HALT_ADDR_OFFSET(x,y) (CMIC_CMCx_DMA_CH0_DESC_HALT_ADDR_OFFSET(x) + (y*4)) 64 65 #define MSPI_TXRAM_nn(n) (MSPI_TXRAM_00_OFFSET + (4*n)) 66 #define MSPI_RXRAM_nn(n) (MSPI_RXRAM_00_OFFSET + (4*n)) 67 #define MSPI_CDRAM_nn(n) (MSPI_CDRAM_00_OFFSET + (4*n)) 68 69 /* Field Masks for some CMICm registers.*/ 70 /* Can be removed if we can use the more generic soc_reg_field_set/get() */ 71 72 /* CMIC_CMCx_CHy_DMA_CTRL */ 73 #define PKTDMA_DIRECTION (0x00000001) 74 #define PKTDMA_ENABLE (0x00000002) 75 #define PKTDMA_ABORT (0x00000004) 76 #define PKTDMA_SEL_INTR_ON_DESC_OR_PKT (0x00000008) 77 #define PKTDMA_BIG_ENDIAN (0x00000010) 78 #define PKTDMA_DESC_BIG_ENDIAN (0x00000020) 79 #define RLD_STATUS_UPD_DIS (0x00000080) 80 #define PKTDMA_CNTLD_DESC_INTR_MODE (0x00000100) 81 #define PKTDMA_CONTINUOUS_ENABLE (0x00000200) /* Bit 9 */ 82 83 /* CMIC_CMCx_FIFO_CHy_RD_DMA_CFG */ 84 #define FIFODMA_BIG_ENDIAN (0x00000800) 85 86 /* CMIC_CMCx_FSCHAN_STATUS(x) */ 87 #define FSCHAN_BUSY (0x00000001) 88 89 /* CMIC_CMCx_SCHAN_CTRL(x) */ 90 #define SC_CMCx_MSG_CLR (0x00000000) 91 #define SC_CMCx_MSG_START (0x00000001) 92 #define SC_CMCx_MSG_DONE (0x00000002) 93 #define SC_CMCx_SCHAN_ABORT (0x00000004) 94 #define SC_CMCx_MSG_SER_CHECK_FAIL (0x00100000) 95 #define SC_CMCx_MSG_NAK (0x00200000) 96 #define SC_CMCx_MSG_TIMEOUT_TST (0x00400000) 97 98 /* CMIC_CMCx_DMA_STAT(x) */ 99 #define DS_CMCx_DMA_CHAIN_DONE(y) (0x00000001 << (y)) 100 #define DS_CMCx_DMA_DESC_DONE(y) (0x00000010 << (y)) 101 #define DS_CMCx_DMA_ACTIVE(y) (0x00000100 << (y)) 102 #define DS_CMCx_DMA_ADDR_DECODE_ERR(y) (0x00111000 << (y)) 103 104 /* CMIC_CMCx_DMA_STAT_HI(x) */ 105 #define DS_CMCx_DMA_IN_HALT(y) (0x08000000 << (y)) 106 107 /* CMIC_CMCx_DMA_STAT_CLR(x) */ 108 #define DS_DESCRD_CMPLT_CLR(y) (0x00000001 << (y)) 109 #define DS_INTR_COALESCING_CLR(y) (0x00000010 << (y)) 110 #define DS_CNTLD_DESC_CLR(y) (0x00000100 << (y)) 111 112 /* CMIC_CMCx_SLAM_DMA_CFG(x) */ 113 #define SLDMA_BIG_ENDIAN (0x40000000) 114 #define SLDMA_CFG_DIR (0x00010000) 115 #define SLDMA_DONE (0x00000001) 116 117 /* CMIC_CMCx_TABLE_DMA_CFG(x) */ 118 #define TDMA_BIG_ENDIAN (0x00800000) 119 #define TDMA_DONE (0x00000001) 120 121 /* CMIC_CMCx_STAT_DMA_CFG(x) */ 122 #define STDMA_BIG_ENDIAN (0x00040000) 123 #define STDMA_ITER_DONE_CLR (0x00020000) 124 125 /* CMIC_CMCx_STAT_DMA_STAT(x) */ 126 #define ST_CMCx_DMA_ITER_DONE (0x00000002) 127 #define ST_CMCx_DMA_ERR (0x00000004) 128 #define ST_CMCx_DMA_ACTIVE (0x00000008) 129 130 /* CMIC_CMCx_MIIM_STAT(x) */ 131 #define CMIC_MIIM_OPN_DONE (0x00000001) 132 133 /* CMIC_MIIM_SCAN_STATUS */ 134 #define CMIC_MIIM_SCAN_BUSY (0x00000001) 135 136 /* CMIC_CPS_RESET */ 137 #define CMIC_CPS_RESET (0x00000001) 138 139 /* CMIC_MIIM_CLR_SCAN_STATUS */ 140 #define CLR_LINK_STATUS_CHANGE_MASK (0x00000010) /*bit 4 */ 141 142 /* CMIC RQ Mask/Stat 0 */ 143 #define IRQ_CMCx_TSLAM_DONE 0x00000001 /* Bit 0 */ 144 #define IRQ_CMCx_TDMA_DONE 0x00000002 /* Bit 1 */ 145 #define IRQ_CMCx_FIFO_CH_DMA(ch) (0x00000020 >> ch) /* Bits 5,4,3,2 */ 146 #define IRQ_CMCx_STAT_ITER_DONE 0x00000040 /* Bit 6 */ 147 #define IRQ_CMCx_SBUSDMA_CH_DONE(ch) ((ch) == 2 ? 0x40 : (1 << (ch))) 148 #define IRQ_CMCx_MIIM_OP_DONE 0x00000080 /* Bit 7 */ 149 #define IRQ_CMCx_DESC_DONE(ch) (0x00004000 >> (2 * (ch))) /* Bits 14,12,10,8 */ 150 #define IRQ_CMCx_CHAIN_DONE(ch) (0x00008000 >> (2 * (ch))) /* Bits 15,13,11,9 */ 151 #define IRQ_CMCx_INTR_COAL_INTR(ch) (0x00080000 >> ch) /* Bits 19,18,17,16 */ 152 #define IRQ_CMCx_SCH_OP_DONE 0x00100000 /* Bit 20 */ 153 #define IRQ_CMCx_CCMDMA_DONE 0x00200000 /* Bit 21 */ 154 #define IRQ_CMCx_SW_INTR(host) (0x00400000 << host) /* Bits 22-25 */ 155 #define IRQ_RCPU_MIIM_OP_DONE 0x00000001 /* Bit 0 */ 156 #define IRQ_CMCx_CNTLD_DESC_DONE(ch) (0x08000000 << ch) /* Bits 27-30 */ 157 158 /* CMICM updates */ 159 #define IRQ_SBUSDMA_CH0_DONE 0x00000002 160 #define IRQ_SBUSDMA_CH1_DONE 0x00000001 161 #define IRQ_SBUSDMA_CH2_DONE 0x00000040 162 163 /* CMIC RQ Mask/Stat 1 */ 164 #define IRQ_CMCx_I2C_INTR 0x00000001 /* Bit 0 */ 165 #define IRQ_CMCx_BROADSYNC_INTR 0x00000002 /* Bit 1 */ 166 #define IRQ_CMCx_TIMESYNC_INTR 0x00000004 /* Bit 2 */ 167 #define IRQ_CMCx_LINK_STAT_MOD 0x00000008 /* Bit 3 */ 168 #define IRQ_CMCx_PHY_PAUSESCAN_PAUSESTATUS_CHD 0x00000010 /* Bit 4 */ 169 #define IRQ_CMCx_SPI_INTERRUPT 0x00000020 /* Bit 5 */ 170 #define IRQ_CMCx_UART0_INTERRUPT 0x00000040 /* Bit 6 */ 171 #define IRQ_CMCx_UART1_INTERRUPT 0x00000080 /* Bit 7 */ 172 #define IRQ_CMCx_COMMON_SCHAN_DONE 0x00000100 /* Bit 8 */ 173 #define IRQ_CMCx_COMMON_MIIM_OP_DONE 0x00000200 /* Bit 9 */ 174 #define IRQ_CMCx_GPIO_INTR 0x00000400 /* Bit 10 */ 175 #define IRQ_CMCx_CHIP_FUNC_INTR 0x0007f800 /* Bit 11-18 */ 176 #define IRQ_CMCx_UC_0_PMUIRQ 0x00080000 /* Bit 19 */ 177 #define IRQ_CMCx_UC_1_PMUIRQ 0x00100000 /* Bit 20 */ 178 #define IRQ_CMCx_WDT_O_INTR 0x00200000 /* Bit 21 */ 179 #define IRQ_CMCx_WDT_1_INTR 0x00400000 /* Bit 22 */ 180 #define IRQ_CMCx_TIM0_INTR1 0x00800000 /* Bit 23 */ 181 #define IRQ_CMCx_TIM0_INTR2 0x01000000 /* Bit 24 */ 182 #define IRQ_CMCx_TIM1_INTR1 0x02000000 /* Bit 25 */ 183 #define IRQ_CMCx_TIM1_INTR2 0x04000000 /* Bit 26 */ 184 #define IRQ_CMCx_SER_INTR 0x20000000 /* Bit 29 */ 185 186 /* CMIC Mask/Stat 2 (Parity) */ 187 #define IRQ_CMCx_PARITY 0xFFFFFFFF /* 32 bits */ 188 189 /* CMIC PCI completion interrupt */ 190 #define IRQ_CMCx_PCI_CMPL_MASK 0x00080000 /* Bit 19 */ 191 #define PCIE_CMPL_TIMEOUT_INTR_MASK 0x00000040 192 #define PORTA_2B_ECC_ERR_INTR_EN 0x78000 193 194 /* CMIC Mask/Stat 3 (sbus slave 0-31) */ 195 /* CMIC Mask/Stat 4 (sbus slave 32-63) */ 196 #define IRQ_CMCx_BLOCK(bit) (1<<(bit) ) /* Bit 0-31 */ 197 198 199 /* SCHAN macros for common CMC, CMC 0, CMC 1, and CMC 2*/ 200 #define CMIC_COMMON_CMCx_SCHAN_CTRL_OFFSET(cmc) (cmc == CMIC_CMC_NUM_MAX) ? \ 201 CMIC_COMMON_SCHAN_CTRL_OFFSET : CMIC_CMCx_SCHAN_CTRL_OFFSET(cmc); 202 #define CMIC_COMMON_CMCx_SCHAN_ERR_OFFSET(cmc) (cmc == CMIC_CMC_NUM_MAX) ? \ 203 CMIC_COMMON_SCHAN_ERR_OFFSET : CMIC_CMCx_SCHAN_ERR_OFFSET(cmc); 204 #define CMIC_COMMON_CMCx_SCHAN_MESSAGEn(cmc, i) (cmc == CMIC_CMC_NUM_MAX) ? \ 205 CMIC_COMMON_SCHAN_MESSAGEn(i) :CMIC_CMCx_SCHAN_MESSAGEn(cmc, i); 206 207 208 /* SBUSDMA stuff */ 209 #define CMIC_CMCx_SBUSDMA_CHAN_MAX (3) 210 #define CMIC_CMC0_SBUSDMA_CH_MASK (0x7) 211 #define CMIC_CMC1_SBUSDMA_CH_MASK (0x7) 212 #define CMIC_CMC2_SBUSDMA_CH_MASK (0x7) 213 214 #define CMIC_CMCx_SBUSDMA_CHy_CONTROL(x, y) \ 215 (CMIC_CMCx_SBUSDMA_CH0_CONTROL_OFFSET(x) + (y * 0x50)) 216 #define CMIC_CMCx_SBUSDMA_CHy_REQUEST(x, y) \ 217 (CMIC_CMCx_SBUSDMA_CH0_REQUEST_OFFSET(x) + (y * 0x50)) 218 #define CMIC_CMCx_SBUSDMA_CHy_COUNT(x, y) \ 219 (CMIC_CMCx_SBUSDMA_CH0_COUNT_OFFSET(x) + (y * 0x50)) 220 #define CMIC_CMCx_SBUSDMA_CHy_OPCODE(x, y) \ 221 (CMIC_CMCx_SBUSDMA_CH0_OPCODE_OFFSET(x) + (y * 0x50)) 222 #define CMIC_CMCx_SBUSDMA_CHy_ADDRESS(x, y) \ 223 (CMIC_CMCx_SBUSDMA_CH0_SBUS_START_ADDRESS_OFFSET(x) + (y * 0x50)) 224 #define CMIC_CMCx_SBUSDMA_CHy_HOSTADDR(x, y) \ 225 (CMIC_CMCx_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_OFFSET(x) + (y * 0x50)) 226 #define CMIC_CMCx_SBUSDMA_CHy_DESCADDR(x, y) \ 227 (CMIC_CMCx_SBUSDMA_CH0_DESC_START_ADDRESS_OFFSET(x) + (y * 0x50)) 228 #define CMIC_CMCx_SBUSDMA_CHy_STATUS(x, y) \ 229 (CMIC_CMCx_SBUSDMA_CH0_STATUS_OFFSET(x) + (y * 0x50)) 230 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSADDR(x, y) \ 231 (CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS_OFFSET(x) + (y * 0x50)) 232 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSDMA_CONFIG_OPCODE(x, y) \ 233 (CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE_OFFSET(x) + (y * 0x50)) 234 #define CMIC_CMCx_SBUSDMA_CHy_CUR_SBUSDMA_CONFIG_ADDR(x, y) \ 235 (CMIC_CMCx_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_OFFSET(x) + (y * 0x50)) 236 237 /* CMIC_CMCx_SBUSDMA_CHy_STATUS fields */ 238 #define ST_CMCx_SBUSDMA_DONE (0x00000001) 239 240 /* FIFO DMA stuff */ 241 #define CMIC_CMCx_FIFO_CHy_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET(x, y) \ 242 (CMIC_CMCx_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM_OFFSET(x) + (y * 8)) 243 #define CMIC_CMCx_FIFO_CHy_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET(x, y) \ 244 (CMIC_CMCx_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM_OFFSET(x) + (y * 8)) 245 #define CMIC_CMCx_FIFO_CHy_RD_DMA_OPCODE_OFFSET(x, y) \ 246 (CMIC_CMCx_FIFO_CH0_RD_DMA_OPCODE_OFFSET(x) + (y * 4)) 247 248 /* This macro may be used to transfer T from microseconds to the value to be entered into 249 CMIC_CMC*_FIFO_CH*_RD_DMA_CFG.TIMEOUT_COUNT. */ 250 #define MICROSECONDS_TO_DMA_CFG__TIMEOUT_COUNT(T) (T = (T+249) / 250); 251 252 extern int _soc_mem_address_remap_allocation_init(int unit); 253 extern int _soc_mem_address_remap_alloc(int unit, int cmc, int ch, int nof_entries, uint32 remap_val, uint32 *remap_entry_base); 254 extern int _soc_mem_address_remap_dealloc(int unit, int cmc, int ch); 255 extern int _soc_mem_sbus_fifo_dma_start_memreg(int unit, int ch, 256 int is_mem, soc_mem_t mem, soc_reg_t reg, 257 int copyno, int force_entry_size, int host_entries, void *host_buff); 258 259 extern int _soc_mem_sbus_fifo_dma_start(int unit, int ch, soc_mem_t mem, int copyno, 260 int host_entries, void *host_buff); 261 extern int _soc_mem_sbus_fifo_dma_stop(int unit, int ch); 262 263 extern int _soc_mem_sbus_fifo_dma_get_num_entries(int unit, int ch, int *count); 264 265 extern int _soc_mem_sbus_fifo_dma_set_entries_read(int unit, int ch, uint32 num); 266 267 #endif /* !_SOC_CMICM_H */