cmic.h (42166B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: cmic.h 8 * Purpose: Maps out structures used for CMIC operations and 9 * exports routines and constants. 10 */ 11 12 #ifndef _SOC_CMIC_H 13 #define _SOC_CMIC_H 14 15 #include <soc/defs.h> 16 #include <soc/schanmsg.h> 17 #include <soc/register.h> 18 19 #define CMIC_OFFSET_MIN 0 20 21 #define CCMDMA_TIMEOUT (5 * SECOND_USEC) 22 #define CCMDMA_TIMEOUT_QT (120 * SECOND_USEC) 23 24 /* 25 * S-Channel Message Buffer Registers (0x00 -> 0x4c, or 0x800 -> 0x854). 26 * Block where S-Channel messages are written to CMIC. 27 */ 28 #define CMIC_SCHAN_MESSAGE(unit, word) \ 29 (soc_feature(unit, soc_feature_schmsg_alias) ? \ 30 (0x00000800 + 4 * (word)) : (0x00000000 + 4 * (word))) 31 32 #define CMIC_SCHAN_MESSAGE_WORDS(unit) \ 33 (soc_feature(unit, soc_feature_schmsg_alias) ? 22 : 20) 34 35 #define CMIC_SCHAN_MESSAGE_WORDS_MAX 22 36 37 /* S-Channel Control Register */ 38 #define CMIC_SCHAN_CTRL 0x00000050 39 40 /* 41 * SCHAN_CONTROL: control bits 42 * 43 * SC_xxx_SET and SC_xxx_CLR can be WRITTEN to CMIC_SCHAN_CTRL. 44 * SC_xxx_TST can be masked against values READ from CMIC_SCHAN_CTRL. 45 */ 46 #define SC_MSG_START_SET (0x80|0) 47 #define SC_MSG_START_CLR (0x00|0) 48 #define SC_MSG_START_TST 0x00000001 49 50 #define SC_MSG_DONE_SET (0x80|1) 51 #define SC_MSG_DONE_CLR (0x00|1) 52 #define SC_MSG_DONE_TST 0x00000002 53 54 #define SC_ARL_RDY_SET(msg) (0x80|((msg)+2)) /* 0 <= msg <= 3 */ 55 #define SC_ARL_RDY_CLR(msg) (0x00|((msg)+2)) 56 #define SC_ARL_RDY_TST(msg) (0x00000004 << (msg)) 57 #define SC_ARL_RDY_TST_ANY (0x0000003c) 58 59 #define SC_ARL_DMA_EN_SET (0x80|6) 60 #define SC_ARL_DMA_EN_CLR (0x00|6) 61 #define SC_ARL_DMA_EN_TST 0x00000040 62 63 #define SC_ARL_DMA_DONE_SET (0x80|7) 64 #define SC_ARL_DMA_DONE_CLR (0x00|7) 65 #define SC_ARL_DMA_DONE_TST 0x00000080 66 67 #define SC_LINK_STAT_MSG_SET (0x80|8) 68 #define SC_LINK_STAT_MSG_CLR (0x00|8) 69 #define SC_LINK_STAT_MSG_TST 0x00000100 70 71 #define SC_PCI_FATAL_ERR_SET (0x80|9) 72 #define SC_PCI_FATAL_ERR_CLR (0x00|9) 73 #define SC_PCI_FATAL_ERR_TST 0x00000200 74 75 #define SC_PCI_PARITY_ERR_SET (0x80|10) 76 #define SC_PCI_PARITY_ERR_CLR (0x00|10) 77 #define SC_PCI_PARITY_ERR_TST 0x00000400 78 79 #define SC_ARL_MSG_RCV_OFF_SET (0x80|11) 80 #define SC_ARL_MSG_RCV_OFF_CLR (0x00|11) 81 #define SC_ARL_MSG_RCV_OFF_TST 0x00000800 82 83 #define SC_ARL_MSG_DROPPED_SET (0x80|12) 84 #define SC_ARL_MSG_DROPPED_CLR (0x00|12) 85 #define SC_ARL_MSG_DROPPED_TST 0x00001000 86 87 #define SC_ARL_DMA_XFER_DONE_SET (0x80|13) 88 #define SC_ARL_DMA_XFER_DONE_CLR (0x00|13) 89 #define SC_ARL_DMA_XFER_DONE_TST 0x00002000 90 91 #define SC_MIIM_SCAN_BUSY_TST 0x00004000 92 93 #define SC_GBP_OK_SET (0x80|15) 94 #define SC_GBP_OK_CLR (0x00|15) 95 #define SC_GBP_OK_TST 0x00008000 96 97 98 99 #define SC_MIIM_RD_START_SET (0x80|16) 100 #define SC_MIIM_RD_START_CLR (0x00|16) 101 #define SC_MIIM_RD_START_TST 0x00010000 102 103 #define SC_MIIM_WR_START_SET (0x80|17) 104 #define SC_MIIM_WR_START_CLR (0x00|17) 105 #define SC_MIIM_WR_START_TST 0x00020000 106 107 #define SC_MIIM_OP_DONE_SET (0x80|18) 108 #define SC_MIIM_OP_DONE_CLR (0x00|18) 109 #define SC_MIIM_OP_DONE_TST 0x00040000 110 111 #define SC_MIIM_LINK_SCAN_EN_SET (0x80|19) 112 #define SC_MIIM_LINK_SCAN_EN_CLR (0x00|19) 113 #define SC_MIIM_LINK_SCAN_EN_TST 0x00080000 114 115 #define SC_MSG_SER_CHECK_FAIL_SET (0x80|20) 116 #define SC_MSG_SER_CHECK_FAIL_CLR (0x00|20) 117 #define SC_MSG_SER_CHECK_FAIL_TST 0x00100000 118 119 #define SC_MSG_NAK_SET (0x80|21) 120 #define SC_MSG_NAK_CLR (0x00|21) 121 #define SC_MSG_NAK_TST 0x00200000 122 123 #define SC_MSG_TIMEOUT_SET (0x80|22) 124 #define SC_MSG_TIMEOUT_CLR (0x00|22) 125 #define SC_MSG_TIMEOUT_TST 0x00400000 126 127 128 /* ARL DMA Address Register */ 129 #define CMIC_ARL_DMA_ADDR 0x00000054 /* 32-bit address */ 130 131 /* ARL DMA Packet count Register */ 132 #define CMIC_ARL_DMA_CNT 0x00000058 /* 16-bit counter */ 133 #define CMIC_ARL_DMA_CNT_MAX 0x0000FFFF /* max value */ 134 135 /* 136 * S-Channel Error Status Register. 137 * 138 * Use the SCERR_XXX macros to extract fields. Fields are valid only if 139 * VALID bit is on. VALID bit is cleared on register read, except on 140 * Lynx where the bit must be written to 0 to clear it (clear on read is 141 * very bad when PCI burst reads are in use). 142 * 143 * NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE: 144 * 145 * These values are not valid for Tucana, and probably not 146 * for Draco either. Use the regsfile defines. 147 */ 148 #define CMIC_SCHAN_ERR 0x0000005C 149 150 #define SCERR_VALID(reg) ((reg) >> 31 & 0x01) 151 #define SCERR_DST_PORT(reg) ((reg) >> 23 & 0xff) 152 #define SCERR_SRC_PORT(reg) ((reg) >> 15 & 0xff) 153 #define SCERR_OP_CODE(reg) ((reg) >> 8 & 0x7f) 154 #define SCERR_ERR_CODE(reg) ((reg) >> 0 & 0xff) 155 156 /* 157 * COS Port Status 158 * 159 * There is one Active Port register per class of service. 160 * Each register contains a port bitmap of active ports (see PBMP_*). 161 * There are 4 classes of service (0 <= cos <= 3), with room for 8 more. 162 * Not applicable on Lynx, reads as 0xffffffff. 163 */ 164 165 #define CMIC_COS_ENABLE(cos) (0x00000060 + 4 * (cos)) 166 167 /* 168 * ARL Message Buffers. These messages are in the format schan_msg_t: 169 * If msg.header.opcode==ARL_INSERT_CMD_MSG, use msg.arlins union member. 170 * If msg.header.opcode==ARL_DELETE_CMD_MSG, use msg.arldel union member. 171 * There are four buffers (0 <= num <= 3) and each is four words in size. 172 */ 173 174 #define NUM_ARL_MBUF 4 175 176 #define CMIC_ARL_MBUF(num) (0x00000080 + 0x20 * (num)) 177 178 /* DMA Control Register */ 179 #define CMIC_DMA_CTRL 0x00000100 180 181 #define DC_SOC_TO_MEM(ch) (0x00 << (8 * (ch))) /* 0 <= ch <= 3 */ 182 #define DC_MEM_TO_SOC(ch) (0x01 << (8 * (ch))) 183 #define DC_DIRECTION_MASK(ch) (0x01 << (8 * (ch))) 184 185 #define DC_MOD_BITMAP(ch) (0x00 << (8 * (ch))) /* 0 <= ch <= 3 */ 186 #define DC_NO_MOD_BITMAP(ch) (0x02 << (8 * (ch))) 187 #define DC_MOD_BITMAP_MASK(ch) (0x02 << (8 * (ch))) 188 189 #define DC_NO_ABORT_DMA(ch) (0x00 << (8 * (ch))) /* 0 <= ch <= 3 */ 190 #define DC_ABORT_DMA(ch) (0x04 << (8 * (ch))) 191 #define DC_ABORT_DMA_MASK(ch) (0x04 << (8 * (ch))) 192 193 #define DC_INTR_ON_PKT(ch) (0x00 << (8 * (ch))) /* 0 <= ch <= 3 */ 194 #define DC_INTR_ON_DESC(ch) (0x08 << (8 * (ch))) 195 #define DC_INTR_ON_MASK(ch) (0x08 << (8 * (ch))) 196 197 #define DC_NO_DROP_TX(ch) (0x00 << (8 * (ch))) /* 0 <= ch <= 3 */ 198 #define DC_DROP_TX(ch) (0x10 << (8 * (ch))) 199 #define DC_DROP_TX_MASK(ch) (0x10 << (8 * (ch))) 200 #define DC_DROP_TX_ALL 0x10101010 201 202 #define DC_CHAN_MASK(ch) (0xff << (8 * (ch))) 203 204 /* DMA Status Register */ 205 #define CMIC_DMA_STAT 0x00000104 206 207 /* 208 * DMA_STAT: control bits 209 * 210 * xxx_SET and xxx_CLR can be WRITTEN to CMIC_DMA_STAT 211 * xxx_TST can be masked against values read from CMIC_DMA_STAT. 212 * Argument required: 0 <= ch <= 3 213 */ 214 #define DS_DMA_EN_SET(ch) (0x80|(ch)) 215 #define DS_DMA_EN_CLR(ch) (0x00|(ch)) 216 #define DS_DMA_EN_TST(ch) (0x00000001 << (ch)) 217 218 #define DS_CHAIN_DONE_SET(ch) (0x80|(4+(ch))) 219 #define DS_CHAIN_DONE_CLR(ch) (0x00|(4+(ch))) 220 #define DS_CHAIN_DONE_TST(ch) (0x00000010 << (ch)) 221 222 #define DS_DESC_DONE_SET(ch) (0x80|(8+(ch))) 223 #define DS_DESC_DONE_CLR(ch) (0x00|(8+(ch))) 224 #define DS_DESC_DONE_TST(ch) (0x00000100 << (ch)) 225 226 #define DS_DMA_RESET 0x1000 227 #define _DS_DMA_RESET DS_DMA_RESET 228 229 #define DS_STAT_DMA_DONE_SET (0x80|13) 230 #define DS_STAT_DMA_DONE_CLR (0x00|13) 231 #define DS_STAT_DMA_DONE_TST 0x2000 232 233 #define DS_STAT_DMA_ITER_DONE_SET (0x80|14) 234 #define DS_STAT_DMA_ITER_DONE_CLR (0x00|14) 235 #define DS_STAT_DMA_ITER_DONE_TST 0x4000 236 237 #define DS_STAT_DMA_ACTIVE 0x20000 238 #define DS_STAT_DMA_ERROR_SET (0x80|16) 239 #define DS_STAT_DMA_ERROR_CLR (0x00|16) 240 #define DS_STAT_DMA_ERROR 0x10000 241 242 243 #define DS_DMA_ACTIVE(ch) (0x00040000 << (ch)) 244 245 /* These actually return the DMA channel number of failure */ 246 #define DS_PCI_PARITY_ERR(reg) ((reg) >> 24 & 3) 247 #define DS_PCI_FATAL_ERR(reg) ((reg) >> 29 & 3) 248 #define DS_EXT_PCI_PARITY_ERR(reg) ((reg) >> 22 & 0x1f) 249 #define DS_EXT_PCI_FATAL_ERR(reg) ((reg) >> 27 & 0x1f) 250 251 /* 252 * CMIC Head Of Line (HOL) Status. 253 * Contains a port bitmap (see PBMP_*) of ports that are 254 * currently AVAILABLE (NOT blocking on HOL) 255 * Not applicable on Lynx, reads as 0xffffffff. 256 */ 257 #define CMIC_HOL_STAT 0x00000108 258 259 /* CMIC Configuration Register */ 260 /* RD_BRST_EN defaults to 1 for Lynx */ 261 262 #define CMIC_CONFIG 0x0000010C 263 264 #define CC_RD_BRST_EN 0x00000001 /* enb PCI read bursts */ 265 #define CC_WR_BRST_EN 0x00000002 /* enb PCI write bursts */ 266 #define CC_BE_CHECK_EN 0x00000004 /* Big endian chk PCI Wr */ 267 #define CC_MSTR_Q_MAX_EN 0x00000008 /* Queue 4 PCI mastr reqs */ 268 #define CC_LINK_STAT_EN 0x00000010 /* enb linkstat autoupd */ 269 #define CC_RESET_CPS 0x00000020 /* Drive CPS bus reset */ 270 #define CC_ACT_LOW_INT 0x00000040 /* INTA# is active low */ 271 #define CC_SCHAN_ABORT 0x00000080 /* abort S-Channel opern */ 272 #define CC_STACK_ARCH_EN 0x00000100 /* (see databook) */ 273 #define CC_UNTAG_EN 0x00000200 /* (see databook) */ 274 #define CC_LE_DMA_EN 0x00000400 /* Little endian DMA fmt */ 275 #define CC_I2C_EN 0x00000800 /* enb CPU access to I2C */ 276 #define CC_LINK_SCAN_GIG 0x00001000 /* Also scan gig ports */ 277 #define CC_DMA_GARBAGE_COLL_EN 0x00008000 /* Collect 'purge' pkts */ 278 279 #define CC_ALN_OPN_EN 0x00002000 /* Unaligned DMA enable */ 280 #define CC_PCI_RST_ON_INIT_EN 0x00010000 281 #define CC_DIS_TIME_STAMP_CTR 0x00020000 282 #define CC_SG_OPN_EN 0x00040000 /* DMA S/G enable */ 283 #define CC_RLD_OPN_EN 0x00080000 /* DMA RLD enable */ 284 #define CC_DIS_RLD_STAT_UPDATE 0x00100000 285 #define CC_STOP_AUTO_SCAN_ON_LCHG 0x00200000 /* LS stop in intr */ 286 #define CC_ABORT_STAT_DMA 0x00400000 287 #define CC_ATO_SCAN_FROM_ID_ZERO 0x00800000 /* Scan from PHYID=0 */ 288 #define CC_COS_QUALIFIED_DMA_RX_EN 0x01000000 289 #define CC_ABORT_TBL_DMA 0x02000000 /* Abort Table DMA op */ 290 #define CC_EXT_MDIO_MSTR_DIS 0x04000000 /* Disable MDIO on ATE */ 291 #define CC_EXTENDED_DCB_ENABLE 0x08000000 /* type7 dcb (5695) */ 292 #define CC_INT_PHY_CLAUSE_45 0x08000000 /* MIIM 45 vs. 22 (5673) */ 293 294 #define N_DMA_CHAN 4 295 #define MAX_N_DMA_CHAN 8 296 #define CMICX_N_DMA_CHAN 8 297 #define CMICX_N_FIFODMA_CHAN 12 298 /* CMIC DMA Memory Address Registers (4 base addresses for 0 <= ch <= 3) */ 299 #define CMIC_DMA_DESC(ch) (0x00000110 + 4 * (ch)) 300 301 /* CMIC I2C Registers */ 302 #define CMIC_I2C_SLAVE_ADDR 0x00000120 303 #define CMIC_I2C_DATA 0x00000124 304 #define CMIC_I2C_CTRL 0x00000128 305 #define CMIC_I2C_STAT 0x0000012C 306 #define CMIC_I2C_SLAVE_XADDR 0x00000130 307 #define CMIC_I2C_GP0 0x00000134 308 #define CMIC_I2C_GP1 0x00000138 309 #define CMIC_I2C_RESET 0x0000013C 310 311 /* 312 * Link Status (UP/Down) Register 313 * Contains a port bitmap (see PBMP_*) of ports whose links are up. 314 */ 315 #define CMIC_LINK_STAT 0x00000140 316 /* For 5665 */ 317 #define CMIC_LINK_STAT_MOD1 0x00000540 318 319 /* IRQ Register (RO) 320 */ 321 322 #define CMIC_IRQ_STAT 0x00000144 323 #define CMIC_IRQ_STAT_1 0x00000064 324 #define CMIC_IRQ_STAT_2 0x00000068 325 326 /* IRQ Mask Register (R/W) 327 */ 328 329 #define CMIC_IRQ_MASK 0x00000148 330 #define CMIC_IRQ_MASK_1 0x0000006C 331 #define CMIC_IRQ_MASK_2 0x00000070 332 333 /* IRQ Mask bits */ 334 #define IRQ_SCH_MSG_DONE 0x00000001 /* Bit 0 */ 335 #define IRQ_ARL_MBUF 0x00000002 /* Bit 1 */ 336 #define IRQ_CHIP_FUNC_0 IRQ_ARL_MBUF 337 #define IRQ_ARL_MBUF_DROP 0x00000004 /* Bit 2 */ 338 #define IRQ_CHIP_FUNC_1 IRQ_ARL_MBUF_DROP 339 #define IRQ_GBP_FULL 0x00000008 /* Bit 3 */ 340 #define IRQ_CHIP_FUNC_2 IRQ_GBP_FULL 341 #define IRQ_LINK_STAT_MOD 0x00000010 /* Bit 4 */ 342 #define IRQ_ARL_DMA_XFER 0x00000020 /* Bit 5 */ 343 #define IRQ_L2_MOD_FIFO_NOT_EMPTY IRQ_ARL_DMA_XFER 344 #define IRQ_CHIP_FUNC_3 IRQ_ARL_DMA_XFER 345 #define IRQ_ARL_DMA_CNT0 0x00000040 /* Bit 6 */ 346 #define IRQ_CHIP_FUNC_4 IRQ_ARL_DMA_CNT0 347 #define IRQ_DESC_DONE(ch) (0x00000080 << (2 * (ch))) 348 #define IRQ_CHAIN_DONE(ch) (0x00000100 << (2 * (ch))) 349 #define IRQ_PCI_PARITY_ERR 0x00008000 /* Bit 15 */ 350 #define IRQ_PCI_FATAL_ERR 0x00010000 /* Bit 16 */ 351 #define IRQ_SCHAN_ERR 0x00020000 /* Bit 17 */ 352 #define IRQ_I2C_INTR 0x00040000 /* bit 18 */ 353 #define IRQ_MIIM_OP_DONE 0x00080000 /* Bit 19 */ 354 #define IRQ_STAT_ITER_DONE 0x00100000 /* Bit 20 */ 355 #define IRQ_BIT21 0x00200000 /* bit 21 */ 356 #define IRQ_MMU_IRQ_STAT IRQ_BIT21 /* Bit 21 - XGS Fabric */ 357 #define IRQ_ARL_ERROR IRQ_BIT21 /* Bit 21 - XGS Switch */ 358 #define IRQ_FIFO_CH0_DMA IRQ_BIT21 /* Bit 21 */ 359 #define IRQ_BIT22 0x00400000 /* Bit 22 */ 360 #define IRQ_IGBP_FULL IRQ_BIT22 /* Bit 22 */ 361 #define IRQ_FIFO_CH1_DMA IRQ_BIT22 /* Bit 22 */ 362 #define IRQ_BIT23 0x00800000 /* Unused */ 363 #define IRQ_FIFO_CH2_DMA IRQ_BIT23 /* Bit 23 */ 364 #define IRQ_ARL_LPM_LO_PAR 0x01000000 /* Bit 24 */ 365 #define IRQ_FIFO_CH3_DMA IRQ_ARL_LPM_LO_PAR /* Bit 24 */ 366 #define IRQ_BIT25 0x02000000 /* bit 25 */ 367 #define IRQ_ARL_LPM_HI_PAR IRQ_BIT25 /* bit 25 - 5665 etc. */ 368 #define IRQ_BSE_CMDMEM_DONE IRQ_BIT25 /* bit 25 - MCMD */ 369 #define IRQ_MEM_CMD_DONE IRQ_BIT25 370 #define IRQ_BIT26 0x04000000 /* Bit 26 */ 371 #define IRQ_ARL_L3_PAR IRQ_BIT26 /* Bit 26 - 5665 etc. */ 372 #define IRQ_CSE_CMDMEM_DONE IRQ_BIT26 /* bit 25 - MCMD */ 373 #define IRQ_BIT27 0x08000000 /* bit 27 */ 374 #define IRQ_ARL_L2_PAR IRQ_BIT27 /* Bit 27 - 5665 etc.*/ 375 #define IRQ_HSE_CMDMEM_DONE IRQ_BIT27 /* bit 27 - MCMD */ 376 #define IRQ_BIT28 0x10000000 /* Bit 28 */ 377 #define IRQ_ARL_VLAN_PAR IRQ_BIT28 /* Bit 28 */ 378 #define IRQ_MEM_FAIL IRQ_BIT28 /* Bit 28 */ 379 #define IRQ_TDMA_DONE 0x20000000 /* Bit 29 */ 380 #define IRQ_TSLAM_DONE 0x40000000 /* Bit 30 */ 381 #define IRQ_BIT31 0x80000000 /* Bit 31 */ 382 #define IRQ_BSAFE_OP_DONE IRQ_BIT31 /* Bit 31 */ 383 #define IRQ_BROADSYNC_INTR IRQ_BIT31 /* Bit 31 */ 384 385 /* should be used only with soc_intr_block_lo/hi_enable/disable */ 386 #define IRQ_BLOCK(bit) (1<<(bit) ) /* Bit 0-31 */ 387 388 /* Hercules CMIC MMU Status/Mask Registers */ 389 #define CMIC_MMUIRQ_STAT 0x1a0 /* One bit for each MMU */ 390 #define CMIC_MMUIRQ_MASK 0x1a4 /* Mask of enables */ 391 392 #define CMIC_MMUIRQ_ENABLE_MASK 0x1ff /* Set all MMU's enabled */ 393 394 /* Memory Fault Register */ 395 #define CMIC_MEM_FAIL 0x0000014C 396 397 /* Ingress Back Pressure Warning Register */ 398 #define CMIC_IGBP_WARN 0x00000150 399 400 /* Ingress Back Pressure Discard Register */ 401 #define CMIC_IGBP_DISCARD 0x00000154 402 403 /* MIIM Parameter Register */ 404 #define CMIC_MIIM_PARAM 0x00000158 405 406 #define MIIM_PARAM_ID_OFFSET 16 407 #define MIIM_PARAM_REG_ADDR_OFFSET 24 /* Ignored on Lynx; see */ 408 /* CMIC_MIIM_ADDRESS */ 409 410 /* MIIM Read Data Register */ 411 #define CMIC_MIIM_READ_DATA 0x0000015C 412 413 /* Scan Ports Register */ 414 #define CMIC_SCAN_PORTS 0x00000160 415 416 /* Counter DMA address register */ 417 #define CMIC_STAT_DMA_ADDR 0x00000164 418 419 /* Counter DMA setup register */ 420 #define CMIC_STAT_DMA_SETUP 0x00000168 421 422 #define SDS_EN 0x80000000 /* Stats DMA Enable */ 423 #define SDS_ET 0x40000000 /* Timer mode enable */ 424 #define SDS_TIMERVAL_SHFT 16 425 #define SDS_TIMERVAL_MASK (0x3fff << SDS_TIMERVAL_SHFT) 426 #define SDS_TIMER_USEC_PER_COUNT 64 427 #define SDS_TIMER_USEC_MAX (0x4000 * 64 - 1) 428 #define SDS_TIMER_USEC_TO_COUNT(usec) (usec / 64) 429 /* 430 * The next two fields are not present in Lynx. See instead 431 * CMIC_64BIT_STATS_CFG (0x198, below). 432 */ 433 #define SDS_LASTREG_SHFT 8 434 #define SDS_LASTREG_MASK (0xff << SDS_LASTREG_SHFT) 435 #define SDS_FIRSTREG_SHFT 0 436 #define SDS_FIRSTREG_MASK (0xff << SDS_FIRSTREG_SHFT) 437 438 /* Counter DMA valid ports register */ 439 #define CMIC_STAT_DMA_PORTS 0x0000016c 440 441 /* 442 * Counter DMA current position register 443 * Contains the internal address of the counter register currently 444 * being scanned. 445 */ 446 447 #define CMIC_STAT_DMA_CURRENT 0x00000170 448 449 /* Endian selection register */ 450 #define CMIC_ENDIAN_SELECT 0x00000174 451 452 #define ES_BIG_ENDIAN_PIO 0x01000001 453 #define ES_BIG_ENDIAN_DMA_PACKET 0x02000002 454 #define ES_BIG_ENDIAN_DMA_OTHER 0x04000004 455 #define ES_BIG_ENDIAN_CTR64_WORDS 0x08000008 /* Lynx only */ 456 #define EN_BIG_ENDIAN_EB2_2B_SEL 0x20000020 /* Raptor/Raven EB slave only */ 457 458 /* 459 * Revision ID register (read-only) 460 * 461 * Allows chip type to be read from I2C. 462 * On Draco, also contains externally jumpered module ID. 463 */ 464 465 #define CMIC_REVID_DEVID 0x00000178 466 467 #define CREV_DEVID(_a) ((_a) & 0xffff) 468 #define CREV_REVID(_a) (((_a) >> 16) & 0xff) 469 #define CREV_MODID(_a) (((_a) >> 24) & 0x1f) 470 471 /* Clock gate register (XGS) */ 472 473 #define CMIC_CLOCK_GATE 0x0000017c 474 475 #define CG_GATE_SHFT 0 476 #define CG_GATE_MASK 0x1fff 477 #define CG_RESET_SHFT 16 478 #define CG_RESET_MASK (0x1fff << CG_RESET_SHFT) 479 480 /* Receive COS mapping per channel (Draco) */ 481 482 #define CMIC_RX_COS_CONTROL 0x00000180 483 484 /* Receive cos mapping per channel (Triumph/Scorpion) */ 485 486 #define CMIC_RX_COS_CONTROL_0 0x00000D90 487 488 #define RCC_COS_MAP_SHFT(ch) ((ch) * 8) 489 #define RCC_COS_MAP_MASK(ch) (0xff << RCC_CHAN_SHFT(ch)) 490 491 /* 492 * Tx Control Registers (Draco, Lynx only). These registers specify a 493 * portion of the Higig header content that doesn't vary a lot, for 494 * packets sent from the CPU. Most of the rest of the header is 495 * supplied in the DCBs. 496 */ 497 498 #define CMIC_TX_CONTROL1 0x00000184 499 #define CMIC_TX_CONTROL2 0x00000188 500 501 /* CMIC Packet Mirror Control (Draco) */ 502 503 #define CMIC_MIRROR_CONTROL 0x0000018c 504 505 #define MIRC_INGRESS_EN 0x80000000 506 #define MIRC_EGRESS_PORTS_MASK 0x00001fff 507 508 #define CMIC_MIRROR_PORTS 0x00000190 509 510 /* Bitmap to specify which linkscan ports are internal PHY (Draco) */ 511 512 #define CMIC_SCAN_INTERNAL 0x00000194 513 514 /* Control for 64-bit stat DMA (Draco IPIC) */ 515 516 #define CMIC_STAT64_DMA_SETUP 0x00000198 517 518 #define SDS64_REG_COUNT_128 0x80000000 519 520 #define SDS64_LASTREG_SHFT 0 521 #define SDS64_LASTREG_MASK 0xff 522 523 /* For Lynx, this register is used to hold the first/last regs */ 524 #define SDS64_LYNX_LASTREG_SHFT 16 525 #define SDS64_LYNX_LASTREG_MASK (0x3ff << SDS64_LYNX_LASTREG_SHFT) 526 527 #define SDS64_LYNX_FIRSTREG_SHFT 0 528 #define SDS64_LYNX_FIRSTREG_MASK 0x3ff 529 530 /* 531 * Table DMA Switch Table Start Address Register (Draco). 532 * DMA transfer range is limited to 64k table entries (16 bits). 533 */ 534 535 #define CMIC_TABLE_DMA_START 0x0000019C 536 537 /* MIIM support for XGS PHYs (clause 45/22, Lynx only) */ 538 539 /* MIIM address selection (Lynx only) */ 540 541 #define MIIM_CL22_ADDR_SHFT 0 542 #define MIIM_CL22_ADDR_MASK 0x1f 543 544 #define MIIM_CL45_ADDR_SHFT 0 545 #define MIIM_CL45_ADDR_MASK 0xffff 546 547 #define MIIM_CL45_DTYPE_SHFT 16 548 #define MIIM_CL45_DTYPE_MASK (0x3ff << MIIM_CL45_DTYPE_SHFT) 549 550 551 /* MIIM port selection (bit map of clause selection, 1=22, 0=45; Lynx only) */ 552 553 #define MIIM_CYCLE_AUTO 0x0 554 #define MIIM_CYCLE_C22_REG_WR 0x1 555 #define MIIM_CYCLE_C22_REG_RD 0x2 556 #define MIIM_CYCLE_C45_REG_AD 0x4 557 #define MIIM_CYCLE_C45_REG_WR 0x5 558 #define MIIM_CYCLE_C45_REG_RD_ADINC 0x6 559 #define MIIM_CYCLE_C45_REG_RD 0x7 560 561 /* CL45 warmboot write disable override */ 562 #define MIIM_WB_C45 (1 << 0) 563 564 #define MIIM_CYCLE_C45_SHFT 6 565 #define MIIM_CYCLE_C45_MASK (0x3 << MIIM_CYCLE_C45_SHFT) 566 #define MIIM_CYCLE_C45_WR (1 << (MIIM_CYCLE_C45_SHFT + 0)) 567 #define MIIM_CYCLE_C45_WR_AD (1 << (MIIM_CYCLE_C45_SHFT + 1)) 568 #define MIIM_CYCLE_C45_RD (1 << (MIIM_CYCLE_C45_SHFT + 0)) 569 #define MIIM_CYCLE_C45_RD_ADINC (1 << (MIIM_CYCLE_C45_SHFT + 1)) 570 571 572 /* TAP protocol access for BIST (Lynx only) */ 573 574 #define CMIC_TAP_CONTROL 0x000001ac 575 576 /* 577 ** FB/ER TDMA/TSLAM 578 */ 579 #define CMIC_TABLE_DMA_PCIMEM_START_ADDR 0x00000420 580 #define CMIC_TABLE_DMA_SBUS_START_ADDR 0x00000424 581 #define CMIC_TABLE_DMA_ENTRY_COUNT 0x00000428 582 #define CMIC_TABLE_DMA_CFG 0x0000042C 583 #define CMIC_TDMA_CFG_EN (1 << 0) 584 #define CMIC_TDMA_CFG_DONE (1 << 2) 585 586 #define CMIC_SLAM_DMA_PCIMEM_START_ADDR 0x00000440 587 #define CMIC_SLAM_DMA_SBUS_START_ADDR 0x00000444 588 #define CMIC_SLAM_DMA_ENTRY_COUNT 0x00000448 589 #define CMIC_SLAM_DMA_CFG 0x0000044C 590 #define CMIC_SLAM_CFG_EN (1 << 0) 591 #define CMIC_SLAM_CFG_DONE (1 << 2) 592 #define CMIC_SLAM_CFG_DIR (1 << 21) 593 /* 594 * ----------------------------------------------------------------------- 595 * LED Microcontroller Registers 596 * ----------------------------------------------------------------------- 597 */ 598 599 #define CMIC_LED_CTRL 0x00001000 600 #define CMIC_LED_STATUS 0x00001004 601 #define CMIC_LED_PROGRAM_RAM_BASE 0x00001800 602 #define CMIC_LED_DATA_RAM_BASE 0x00001c00 603 #define CMIC_LED_PROGRAM_RAM(_a) (CMIC_LED_PROGRAM_RAM_BASE + 4 * (_a)) 604 #define CMIC_LED_PROGRAM_RAM_SIZE 0x100 605 #define CMIC_LED_DATA_RAM(_a) (CMIC_LED_DATA_RAM_BASE + 4 * (_a)) 606 #define CMIC_LED_DATA_RAM_SIZE 0x100 607 #define CMIC_LED_REG_SIZE 4 608 609 /* Trident Switch introduces two LED processors. LED0 handles first 36 ports 610 * LED1 handles the remaining 36 ports. 611 */ 612 #define CMICE_LEDUP0_CTRL 0x00001000 613 #define CMICE_LEDUP0_STATUS 0x00001004 614 #define CMICE_LEDUP0_PROGRAM_RAM_BASE 0x00001800 615 #define CMICE_LEDUP0_DATA_RAM_BASE 0x00001400 616 #define CMICE_LEDUP1_CTRL 0x00002000 617 #define CMICE_LEDUP1_STATUS 0x00002004 618 #define CMICE_LEDUP1_PROGRAM_RAM_BASE 0x00002800 619 #define CMICE_LEDUP1_DATA_RAM_BASE 0x00002400 620 621 #define LC_LED_ENABLE 0x1 /* Enable */ 622 623 #define LS_LED_INIT 0x200 /* Initializing */ 624 #define LS_LED_RUN 0x100 /* Running */ 625 #define LS_LED_PC 0xff /* Current PC */ 626 627 /* This is the offset from the data ram base that is scanned for */ 628 /* link status. One bit per port, 0-7 in 0x80, etc. 4 bytes. */ 629 #define LS_LED_DATA_OFFSET 0x80 630 #define LS_LED_DATA_OFFSET_A0 0xa0 631 #define LS_TUCANA_LED_DATA_OFFSET 0xa0 632 #define LS_RAPTOR_LED_DATA_OFFSET 0xa0 633 #define LS_RAVEN_LED_DATA_OFFSET 0xa0 634 #define LS_TR_VL_LED_DATA_OFFSET 0xa0 635 #define LS_SC_CQ_LED_DATA_OFFSET 0xa0 636 637 638 #define CMIC_OFFSET_MAX 0x19c /* For "dump pcim" */ 639 640 #define CMIC_OFFSET_TRIGGER 0x1fc 641 642 #define MIIM_INTR_RETRY_COUNT 5 643 /* 644 * Define the default number of microseconds before an S-Channel or MIIM 645 * operation times out and fails. Different values apply if the SAL 646 * boot flag BOOT_F_QUICKTURN or BOOT_F_PLISIM are set. 647 */ 648 649 #define SCHAN_TIMEOUT (300 * MILLISECOND_USEC) 650 #define SCHAN_TIMEOUT_QT (3 * SECOND_USEC) 651 #define SCHAN_TIMEOUT_PLI (40 * SECOND_USEC) 652 653 #define MIIM_INTR_RETRY_TIMEOUT (300 * MILLISECOND_USEC) 654 #define MIIM_TIMEOUT (1 * SECOND_USEC) 655 #define MIIM_TIMEOUT_RCPU (1 * SECOND_USEC) 656 #define MIIM_TIMEOUT_QT (3 * SECOND_USEC) 657 #define MIIM_TIMEOUT_PLI (40 * SECOND_USEC) 658 659 #define TDMA_TIMEOUT (1 * SECOND_USEC) 660 #define TDMA_TIMEOUT_QT (120 * SECOND_USEC) 661 662 #define TSLAM_TIMEOUT (1 * SECOND_USEC) 663 #define TSLAM_TIMEOUT_QT (120 * SECOND_USEC) 664 665 #define SBUS_TIMEOUT (1 * SECOND_USEC) 666 #define SBUS_TIMEOUT_QT (120 * SECOND_USEC) 667 668 #define FIFO_TIMEOUT (1 * SECOND_USEC) 669 #define FIFO_TIMEOUT_QT (120 * SECOND_USEC) 670 671 #define CDMA_TIMEOUT (1 * SECOND_USEC) 672 #define CDMA_TIMEOUT_QT (120 * SECOND_USEC) 673 #define CDMA_TIMEOUT_BCMSIM (200 * SECOND_USEC) 674 675 #define STAT_SYNC_TIMEOUT (40 * SECOND_USEC) 676 #define STAT_SYNC_TIMEOUT_QT (120 * SECOND_USEC) 677 #define STAT_SYNC_TIMEOUT_BCMSIM (600 * SECOND_USEC) 678 679 #define PAXB_TX_REQ_SEQ_EN 0 680 #define PAXB_TX_ARB_PRIORITY 2 681 682 /* 683 * CMIC Interface Routines 684 */ 685 686 /* Turn CMIC register offset into static pointer to descriptive name. */ 687 extern char *soc_pci_off2name(int unit, uint32 offset); 688 689 /* Turn CMIC opcode into static pointer to descriptive name */ 690 extern char *soc_schan_op_name(int op); 691 692 #define CMIC_SWAP32(_x) ((((_x) & 0xff000000) >> 24) \ 693 | (((_x) & 0x00ff0000) >> 8) \ 694 | (((_x) & 0x0000ff00) << 8) \ 695 | (((_x) & 0x000000ff) << 24)) 696 697 #define CMIC_SWAP32(_x) ((((_x) & 0xff000000) >> 24) \ 698 | (((_x) & 0x00ff0000) >> 8) \ 699 | (((_x) & 0x0000ff00) << 8) \ 700 | (((_x) & 0x000000ff) << 24)) 701 702 /* Get/Set CMIC PCI Register (function and inline versions) */ 703 #ifdef SOC_PCI_DEBUG 704 extern int soc_pci_getreg(int unit, uint32 addr, uint32 *data_ptr); 705 extern uint32 soc_pci_read(int unit, uint32 addr); 706 extern int soc_pci_write(int unit, uint32 addr, uint32 data); 707 extern uint32 soc_pci_conf_read(int unit, uint32 addr); 708 extern int soc_pci_conf_write(int unit, uint32 addr, uint32 data); 709 #else 710 extern int soc_pci_getreg(int unit, uint32 addr, uint32 *data_ptr); 711 #if defined(CMIC_SOFT_BYTE_SWAP) 712 #define soc_pci_read(unit, addr) ({uint32 _retval = CMREAD(unit, addr);\ 713 _retval = CMIC_SWAP32(_retval); \ 714 _retval;}) 715 #define soc_pci_write(unit, addr, data) ({uint32 _var = CMIC_SWAP32(data); \ 716 CMWRITE(unit, addr, _var);}) 717 718 719 #if defined(IPROC_ACCESS_DEBUG) && (defined(BCM_DNX_SUPPORT) || defined(BCM_DNXF_SUPPORT)) 720 #undef soc_pci_read 721 #undef soc_pci_write 722 /* check that the address is in the currently supported address range of the CMIC BAR in Jericho 2 and Ramon */ 723 #define soc_pci_read(unit, addr) ({uint32 _retval; \ 724 if (SOC_IS_DNX(unit) || SOC_IS_DNXF(unit)) { \ 725 assert(addr < 0x50000); \ 726 } \ 727 _retval = CMREAD(unit, addr); \ 728 _retval = CMIC_SWAP32(_retval); \ 729 _retval;}) 730 #define soc_pci_write(unit, addr, data) ({uint32 _var = CMIC_SWAP32(data); \ 731 if (SOC_IS_DNX(unit) || SOC_IS_DNXF(unit)) { \ 732 assert(addr < 0x50000); \ 733 } \ 734 CMWRITE(unit, addr, _var);}) 735 #endif /* IPROC_ACCESS_DEBUG) && (defined(BCM_DNX_SUPPORT) || defined(BCM_DNXF_SUPPORT) */ 736 737 #else 738 #define soc_pci_read(unit, addr) CMREAD(unit, addr) 739 #define soc_pci_write(unit, addr, data) CMWRITE(unit, addr, data) 740 741 #if defined(IPROC_ACCESS_DEBUG) && (defined(BCM_DNX_SUPPORT) || defined(BCM_DNXF_SUPPORT)) 742 #undef soc_pci_read 743 #undef soc_pci_write 744 /* check that the address is in the currently supported address range of the CMIC BAR in Jericho 2 and Ramon */ 745 #define soc_pci_read(unit, addr) ({ \ 746 if (SOC_IS_DNX(unit) || SOC_IS_DNXF(unit)) { \ 747 assert(addr < 0x50000); \ 748 } \ 749 CMREAD(unit, addr);}) 750 #define soc_pci_write(unit, addr, data) ({ \ 751 if (SOC_IS_DNX(unit) || SOC_IS_DNXF(unit)) { \ 752 assert(addr < 0x50000); \ 753 } \ 754 CMWRITE(unit, addr, data);}) 755 #endif /* IPROC_ACCESS_DEBUG) && (defined(BCM_DNX_SUPPORT) || defined(BCM_DNXF_SUPPORT) */ 756 757 #endif /* CMIC_SOFT_BYTE_SWAP */ 758 #define soc_pci_conf_read(unit, addr) CMCONFREAD(unit, addr) 759 #define soc_pci_conf_write(unit, addr, data) CMCONFWRITE(unit, addr, data) 760 #endif /* SOC_PCI_DEBUG */ 761 762 #ifndef _SOC_CMIC_OR_IPROC_REG 763 #define _SOC_CMIC_OR_IPROC_REG 764 extern int soc_cmic_or_iproc_getreg(int unit, soc_reg_t reg, uint32 *data); 765 extern int soc_cmic_or_iproc_setreg(int unit, soc_reg_t reg, uint32 data); 766 #endif 767 768 extern uint32 soc_pci_mcs_read(int unit, uint32 addr); 769 extern int soc_pci_mcs_getreg(int unit, uint32 addr, uint32 *data_ptr); 770 extern int soc_pci_mcs_write(int unit, uint32 addr, uint32 data); 771 772 773 /* Test PCI memory range 0x00-0x4f */ 774 extern int soc_is_cmicx(int unit); 775 extern int soc_cmicx_pci_test(int unit); 776 extern int soc_pci_test(int unit); 777 extern int soc_pcie_phy_read(int unit, uint32 addr, uint16 *val); 778 extern int soc_pcie_phy_write(int unit, uint32 addr, uint16 val); 779 extern int soc_pcie_fw_status_get(int unit, uint32 *valid); 780 extern int soc_cmicx_iproc_version_get(int unit, 781 unsigned int *iproc_ver, unsigned int *cmic_ver, unsigned int *cmic_rev); 782 783 extern int soc_cmicx_paxb_tx_arbiter_set(int unit, uint8 enable, uint8 priority); 784 extern void soc_cmicx_reg_offset_get(uint32 *min, uint32 *max); 785 786 /* 787 * Do a "harmless" memory read from a special location. 788 */ 789 extern void soc_pci_analyzer_trigger(int unit); 790 791 extern int soc_anyreg_read(int unit, soc_regaddrinfo_t *ainfo, uint64 *data); 792 extern int soc_anyreg_write(int unit, soc_regaddrinfo_t *ainfo, uint64 data); 793 794 /* Read/write internal registers */ 795 extern int soc_reg_read(int unit, soc_reg_t reg, uint32 addr, uint64 *data); 796 extern int soc_reg_write(int unit, soc_reg_t reg, uint32 addr, uint64 data); 797 798 extern int soc_reg_get(int unit, soc_reg_t reg, int port, int index, uint64 *data); 799 extern int soc_reg_set(int unit, soc_reg_t reg, int port, int index, uint64 data); 800 extern int soc_reg_set_nocache(int unit, soc_reg_t reg, int port, int index, uint64 data); 801 extern int _soc_reg32_get(int unit, soc_block_t block, int acc, uint32 addr, uint32 *data); 802 extern int _soc_reg32_set(int unit, soc_block_t block, int acc, uint32 addr, uint32 data); 803 extern int soc_reg32_read(int unit, uint32 addr, uint32 *data); 804 extern int soc_reg32_write(int unit, uint32 addr, uint32 data); 805 806 extern int soc_reg32_get(int unit, soc_reg_t reg, int port, int index, uint32 *data); 807 extern int soc_reg32_set(int unit, soc_reg_t reg, int port, int index, uint32 data); 808 809 extern int soc_reg64_read(int unit, uint32 addr, uint64 *data); 810 extern int soc_reg64_write(int unit, uint32 addr, uint64 data); 811 812 extern int soc_reg64_get(int unit, soc_reg_t reg, int port, int index, uint64 *data); 813 extern int soc_reg64_set(int unit, soc_reg_t reg, int port, int index, uint64 data); 814 extern int _soc_reg64_get(int unit, soc_block_t block, int acc, uint32 addr, uint64 *data); 815 extern int _soc_reg64_set(int unit, soc_block_t block, int acc, uint32 addr, uint64 data); 816 817 extern int soc_reg_rawport_get(int unit, soc_reg_t reg, int port, int index, uint64 *data); 818 extern int soc_reg_rawport_set(int unit, soc_reg_t reg, int port, int index, uint64 data); 819 extern int soc_reg32_rawport_get(int unit, soc_reg_t reg, int port, int index, uint32 *data); 820 extern int soc_reg32_rawport_set(int unit, soc_reg_t reg, int port, int index, uint32 data); 821 822 extern int soc_reg_egress_cell_count_get(int unit, soc_port_t port, int cos, 823 uint32 *data); 824 /* Read/Write custom registers */ 825 extern int soc_custom_reg32_get(int unit, soc_reg_t reg, int port, int index, uint32 *data); 826 extern int soc_custom_reg32_set(int unit, soc_reg_t reg, int port, int index, uint32 data); 827 828 extern int soc_custom_reg64_get(int unit, soc_reg_t reg, int port, int index, uint64 *data); 829 extern int soc_custom_reg64_set(int unit, soc_reg_t reg, int port, int index, uint64 data); 830 831 extern int soc_custom_reg_above_64_get(int unit, soc_reg_t reg, int port, int index, soc_reg_above_64_val_t data); 832 extern int soc_custom_reg_above_64_set(int unit, soc_reg_t reg, int port, int index, soc_reg_above_64_val_t data); 833 834 /* Write internal register for a group of ports */ 835 extern int soc_reg_write_ports(int unit, soc_reg_t reg, pbmp_t pbmp, 836 uint32 value); 837 838 /* Write internal register for a block or group of blocks */ 839 extern int soc_reg_write_blocks(int unit, soc_reg_t reg, soc_block_t block, 840 uint64 value); 841 842 /* Write internal register for all possible blocks */ 843 extern int soc_reg_write_all_blocks(int unit, soc_reg_t reg, uint32 value); 844 extern int soc_reg64_write_all_blocks(int unit, soc_reg_t reg, uint64 value); 845 /* Read a single copy of the register from any appropriate block */ 846 extern int soc_reg_read_any_block(int unit, soc_reg_t reg, uint32 *datap); 847 extern int soc_reg64_read_any_block(int unit, soc_reg_t reg, uint64 *datap); 848 849 extern int soc_direct_reg_get(int unit, int cmic_block, 850 uint32 addr, uint32 dwc_read, uint32 *data); 851 extern int soc_direct_reg_set(int unit, int cmic_block, 852 uint32 addr, uint32 dwc_write, uint32 *data); 853 extern int soc_direct_memreg_get(int unit, int cmic_block, 854 uint32 addr, uint32 dwc_read, int is_mem, uint32 *data); 855 extern int soc_direct_memreg_set(int unit, int cmic_block, 856 uint32 addr, uint32 dwc_write, int is_mem, uint32 *data); 857 858 /* Set link scanning calls */ 859 860 extern int soc_linkscan_config(int unit, pbmp_t mii_pbm, pbmp_t direct_pbm); 861 extern void soc_linkscan_pause(int unit); 862 extern void soc_linkscan_continue(int unit); 863 extern int soc_linkscan_register(int unit, void (*f)(int)); 864 extern int soc_linkscan_hw_init(int unit); 865 extern int _soc_linkscan_hw_port_init(int unit, soc_port_t port); 866 extern int soc_linkscan_hw_port_update(int unit, soc_port_t port); 867 extern int soc_linkscan_hw_link_get(int unit, soc_pbmp_t *hw_link); 868 extern int _soc_linkscan_phy_flags_test(int unit, int port, int flags); 869 extern int soc_linkscan_hw_link_cache_get(int unit, soc_pbmp_t *hw_link); 870 871 extern int soc_link_fwd_set(int unit, pbmp_t fwd); 872 extern void soc_link_fwd_get(int unit, pbmp_t *fwd); 873 extern int soc_link_mask1_set(int unit, pbmp_t mask); 874 extern void soc_link_mask1_get(int unit, pbmp_t *mask); 875 extern int soc_link_mask2_set(int unit, pbmp_t mask); 876 extern void soc_link_mask2_get(int unit, pbmp_t *mask); 877 878 /* 879 * Read/write from PHY registers. 880 * 881 * On BCM5690, the internal MDIO bus can be accessed by adding 882 * an offset of 0x80 to the PHY ID. 883 */ 884 885 #define SOC_INTERNAL_PHY_ID_OFFSET 0x80 886 887 /* 888 * Identifier of bus type of external PHY access 889 * 890 * 891 * 31 16 15 8 7 0 892 * +--------------------+------ ------+-------------+ 893 * | Reg bus type | addr1 | addr2 | 894 * +--------------------+-------------+-------------+ 895 * 896 * Reg bus type: Bus type identifier 897 * addr1: 898 * For 'Reg bus type=SOC_EXTERNAL_PHY_BUS_CPUMDIO': PHY id. 899 * addr2: 900 * For 'Reg bus type=SOC_EXTERNAL_PHY_BUS_CPUMDIO': PHY reg addr. 901 */ 902 /* Bus type identifier: external PHY bus is CPU's MDIO interface */ 903 #define SOC_EXTERNAL_PHY_BUS_CPUMDIO 0x80000000 904 905 extern int soc_miim_write(int unit, uint16 phy_id, 906 uint8 phy_reg_addr, uint16 phy_wr_data); 907 extern int soc_esw_miim_write(int unit, uint32 phy_id, 908 uint32 phy_reg_addr, uint16 phy_wr_data); 909 extern int soc_dcmn_miim_write(int unit, int clause, uint32 phy_id, 910 uint32 phy_reg_addr, uint16 phy_wr_data); 911 extern int soc_dcmn_miim_cl22_write(int unit, uint32 phy_id, 912 uint32 phy_reg_addr, uint16 phy_wr_data); 913 extern int soc_dcmn_miim_cl45_write(int unit, uint32 phy_id, 914 uint32 phy_reg_addr, uint16 phy_wr_data); 915 extern int soc_miim_read(int unit, uint16 phy_id, 916 uint8 phy_reg_addr, uint16 *phy_rd_data); 917 extern int soc_esw_miim_read(int unit, uint32 phy_id, 918 uint32 phy_reg_addr, uint16 *phy_rd_data); 919 extern int soc_dcmn_miim_read(int unit, int clause, uint32 phy_id, 920 uint32 phy_reg_addr, uint16 *phy_rd_data); 921 extern int soc_dcmn_miim_cl22_read(int unit, uint32 phy_id, 922 uint32 phy_reg_addr, uint16 *phy_rd_data); 923 extern int soc_dcmn_miim_cl45_read(int unit, uint32 phy_id, 924 uint32 phy_reg_addr, uint16 *phy_rd_data); 925 extern int soc_sbus_mdio_write(int unit, uint16 phy_id, 926 uint32 phy_reg_addr, uint32 phy_wr_data); 927 extern int soc_sbus_mdio_read(int unit, uint16 phy_id, 928 uint32 phy_reg_addr, uint32 *phy_rd_data); 929 #ifdef PORTMOD_SUPPORT 930 extern int portmod_ext_phy_mdio_c45_reg_read( void* user_acc, 931 uint32 core_addr, 932 uint32 reg_addr, 933 uint32 *val); 934 935 extern int portmod_ext_phy_mdio_c45_reg_write( void* user_acc, 936 uint32 core_addr, 937 uint32 reg_addr, 938 uint32 val); 939 #endif /* PORTMOD_SUPPORT */ 940 941 942 extern int soc_miim_modify(int unit, uint16 phy_id, 943 uint16 phy_reg_addr, uint16 phy_rd_data, uint16 phy_rd_mask); 944 945 extern int soc_miimc45_write(int unit, uint16 phy_id, uint8 phy_devad, 946 uint16 phy_reg_addr, uint16 phy_wr_data); 947 extern int soc_esw_miimc45_write(int unit, uint32 phy_id, 948 uint32 phy_reg_addr, uint16 phy_wr_data); 949 extern int soc_esw_miimc45_wb_write(int unit, uint32 phy_id, 950 uint32 phy_reg_addr, uint16 phy_wr_data); 951 extern int soc_miimc45_read(int unit, uint16 phy_id, uint8 phy_devad, 952 uint16 phy_reg_addr, uint16 *phy_rd_data); 953 extern int soc_esw_miimc45_read(int unit, uint32 phy_id, 954 uint32 phy_reg_addr, uint16 *phy_rd_data); 955 extern int soc_esw_miimc45_data_write(int unit, uint32 phy_id, 956 uint8 phy_devad, uint16 phy_wr_data); 957 extern int soc_esw_miimc45_data_read(int unit, uint32 phy_id, 958 uint8 phy_devad, uint16 *phy_rd_data); 959 extern int soc_esw_miimc45_addr_write(int unit, uint32 phy_id, 960 uint8 phy_devad, uint16 phy_ad_data); 961 extern int soc_esw_miimc45_post_read(int unit, uint32 phy_id, 962 uint8 phy_devad, uint16 *phy_rd_data); 963 964 extern int soc_miimc45_modify(int unit, uint16 phy_id, uint8 phy_devad, 965 uint16 phy_reg_addr, uint16 phy_rd_data, uint16 phy_rd_mask); 966 967 extern int soc_rcpu_miim_write(int unit, uint16 phy_id, 968 uint8 phy_reg_addr, uint16 phy_wr_data); 969 extern int soc_rcpu_miim_read(int unit, uint16 phy_id, 970 uint8 phy_reg_addr, uint16 *phy_rd_data); 971 extern int soc_rcpu_miimc45_write(int unit, uint16 phy_id, uint8 phy_devad, 972 uint16 phy_reg_addr, uint16 phy_wr_data); 973 extern int soc_rcpu_miimc45_read(int unit, uint16 phy_id, uint8 phy_devad, 974 uint16 phy_reg_addr, uint16 *phy_rd_data); 975 976 #endif /* !_SOC_CMIC_H */