port.h (80545B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * This file defines common network port parameters. 8 * 9 * Its contents are not used directly by applications; it is used only 10 * by header files of parent APIs which need to define port parameters. 11 */ 12 13 #ifndef _SHR_PORT_H 14 #define _SHR_PORT_H 15 16 #define _SHR_PORT_PRD_ETH_MAP_INDICATION 0x1000000 17 #define _SHR_PORT_PRD_TM_MAP_INDICATION 0x2000000 18 #define _SHR_PORT_PRD_IP_MAP_INDICATION 0x3000000 19 #define _SHR_PORT_PRD_MPLS_MAP_INDICATION 0x4000000 20 21 #define _SHR_PORT_PRD_ETH_PCP_KEY_MASK 0x7 22 #define _SHR_PORT_PRD_ETH_DEI_KEY_MASK 0x1 23 #define _SHR_PORT_PRD_TM_TC_KEY_MASK 0xF 24 #define _SHR_PORT_PRD_TM_DP_KEY_MASK 0x3 25 #define _SHR_PORT_PRD_IP_DSCP_KEY_MASK 0x3F 26 #define _SHR_PORT_PRD_MPLS_EXP_KEY_MASK 0x7 27 28 #define _SHR_PORT_PRD_ETH_PCP_KEY_SIZE 3 29 #define _SHR_PORT_PRD_ETH_DEI_KEY_SIZE 1 30 #define _SHR_PORT_PRD_TM_TC_KEY_SIZE 4 /*TC is 4 bit in HiGig and 3 bits in ITMH/FTMH*/ 31 #define _SHR_PORT_PRD_TM_DP_KEY_SIZE 2 32 #define _SHR_PORT_PRD_IP_DSCP_KEY_SIZE 6 33 #define _SHR_PORT_PRD_MPLS_EXP_KEY_SIZE 3 34 35 #define _SHR_PORT_PRD_ETH_KEY_MASK (_SHR_PORT_PRD_ETH_PCP_KEY_MASK << _SHR_PORT_PRD_ETH_DEI_KEY_SIZE) | _SHR_PORT_PRD_ETH_DEI_KEY_MASK 36 #define _SHR_PORT_PRD_TM_KEY_MASK (_SHR_PORT_PRD_TM_TC_KEY_MASK << _SHR_PORT_PRD_TM_DP_KEY_SIZE) | _SHR_PORT_PRD_TM_DP_KEY_MASK 37 #define _SHR_PORT_PRD_IP_KEY_MASK _SHR_PORT_PRD_IP_DSCP_KEY_MASK 38 #define _SHR_PORT_PRD_MPLS_KEY_MASK _SHR_PORT_PRD_MPLS_EXP_KEY_MASK 39 40 #define _SHR_PORT_PRD_ETH_KEY_SIZE _SHR_PORT_PRD_ETH_PCP_KEY_SIZE + _SHR_PORT_PRD_ETH_DEI_KEY_SIZE 41 #define _SHR_PORT_PRD_TM_KEY_SIZE _SHR_PORT_PRD_TM_TC_KEY_SIZE + _SHR_PORT_PRD_TM_DP_KEY_SIZE 42 #define _SHR_PORT_PRD_IP_KEY_SIZE _SHR_PORT_PRD_IP_DSCP_KEY_SIZE 43 #define _SHR_PORT_PRD_MPLS_KEY_SIZE _SHR_PORT_PRD_MPLS_EXP_KEY_SIZE 44 45 /* 46 * Typedef: 47 * _shr_port_t 48 * Purpose: 49 * Port number type for shared definitions 50 * Note: 51 * Currently it is NOT used to define bcm_port_t and soc_port_t, but thus 52 * should be changed 53 */ 54 #include <sal/types.h> 55 56 typedef int _shr_port_t; 57 58 /* 59 * Defines: 60 * _SHR_PORT_DUPLEX_* 61 * Purpose: 62 * Defines duplexity of a port 63 */ 64 65 typedef enum _shr_port_duplex_e { 66 _SHR_PORT_DUPLEX_HALF, 67 _SHR_PORT_DUPLEX_FULL, 68 _SHR_PORT_DUPLEX_COUNT /* last, please */ 69 } _shr_port_duplex_t; 70 71 /* 72 * Defines: 73 * _SHR_PORT_IF_* 74 * Purpose: 75 * Defines interface type between MAC and PHY. 76 */ 77 78 typedef enum _shr_port_if_e { 79 _SHR_PORT_IF_NOCXN, /* No physical connection */ 80 _SHR_PORT_IF_NULL, /* Pass-through connection without PHY */ 81 _SHR_PORT_IF_MII, 82 _SHR_PORT_IF_GMII, 83 _SHR_PORT_IF_SGMII, 84 _SHR_PORT_IF_TBI, 85 _SHR_PORT_IF_XGMII, 86 _SHR_PORT_IF_RGMII, 87 _SHR_PORT_IF_RvMII, 88 _SHR_PORT_IF_SFI, 89 _SHR_PORT_IF_XFI, 90 _SHR_PORT_IF_KR, 91 _SHR_PORT_IF_KR4, 92 _SHR_PORT_IF_CR, 93 _SHR_PORT_IF_CR4, 94 _SHR_PORT_IF_XLAUI, 95 _SHR_PORT_IF_SR, 96 _SHR_PORT_IF_RXAUI, 97 _SHR_PORT_IF_XAUI, 98 _SHR_PORT_IF_SPAUI, 99 _SHR_PORT_IF_QSGMII, 100 _SHR_PORT_IF_ILKN, 101 _SHR_PORT_IF_RCY, 102 _SHR_PORT_IF_FAT_PIPE, 103 _SHR_PORT_IF_CGMII, 104 _SHR_PORT_IF_CAUI, 105 _SHR_PORT_IF_LR, 106 _SHR_PORT_IF_LR4, 107 _SHR_PORT_IF_SR4, 108 _SHR_PORT_IF_KX, 109 _SHR_PORT_IF_ZR, 110 _SHR_PORT_IF_SR10, 111 _SHR_PORT_IF_OTL, 112 _SHR_PORT_IF_CPU, 113 _SHR_PORT_IF_OLP, 114 _SHR_PORT_IF_OAMP, 115 _SHR_PORT_IF_ERP, 116 _SHR_PORT_IF_TM_INTERNAL_PKT, 117 _SHR_PORT_IF_SR2, 118 _SHR_PORT_IF_KR2, 119 _SHR_PORT_IF_CR2, 120 _SHR_PORT_IF_XFI2, 121 _SHR_PORT_IF_XLAUI2, 122 _SHR_PORT_IF_CR10, 123 _SHR_PORT_IF_KR10, 124 _SHR_PORT_IF_LR10, 125 _SHR_PORT_IF_ER, 126 _SHR_PORT_IF_ER2, 127 _SHR_PORT_IF_ER4, 128 _SHR_PORT_IF_CX, 129 _SHR_PORT_IF_CX2, 130 _SHR_PORT_IF_CX4, 131 _SHR_PORT_IF_CAUI_C2C, 132 _SHR_PORT_IF_CAUI_C2M, 133 _SHR_PORT_IF_VSR, 134 _SHR_PORT_IF_LR2, 135 _SHR_PORT_IF_LRM, 136 _SHR_PORT_IF_XLPPI, 137 _SHR_PORT_IF_2500X, 138 _SHR_PORT_IF_SAT, 139 _SHR_PORT_IF_IPSEC, 140 _SHR_PORT_IF_LBG, 141 _SHR_PORT_IF_CAUI4, 142 _SHR_PORT_IF_5000X, 143 _SHR_PORT_IF_EVENTOR, 144 _SHR_PORT_IF_RCY_MIRROR, 145 _SHR_PORT_IF_CPRI, 146 _SHR_PORT_IF_RSVD4, 147 _SHR_PORT_IF_NIF_ETH, 148 _SHR_PORT_IF_COUNT /* last, please */ 149 } _shr_port_if_t; 150 151 /* 152 * Defines: 153 * _SHR_PORT_MS_* 154 * Purpose: 155 * Defines master/slave mode of a port (PHY). 156 */ 157 158 typedef enum _shr_port_ms_e { 159 _SHR_PORT_MS_SLAVE, 160 _SHR_PORT_MS_MASTER, 161 _SHR_PORT_MS_AUTO, 162 _SHR_PORT_MS_NONE, 163 _SHR_PORT_MS_COUNT /* last, please */ 164 } _shr_port_ms_t; 165 166 /* 167 * Defines: 168 * _SHR_PORT_ENCAP_* 169 * Purpose: 170 * Defines various header encapsulation modes. 171 * Notes: 172 * WARNING: values must match MAC_TXCTRL register HDRMODE field. 173 */ 174 175 typedef enum _shr_port_encap_e { 176 _SHR_PORT_ENCAP_IEEE = 0, /* IEEE 802.3 Ethernet-II */ 177 _SHR_PORT_ENCAP_HIGIG = 1, /* HIGIG Header mode */ 178 _SHR_PORT_ENCAP_B5632 = 2, /* BCM5632 Header mode */ 179 _SHR_PORT_ENCAP_HIGIG2 = 3, /* HIGIG2 Header mode */ 180 _SHR_PORT_ENCAP_HIGIG2_LITE = 4, /* HIGIG2 Header mode (Raptor style) */ 181 _SHR_PORT_ENCAP_HIGIG2_L2 = 5, /* HIGIG2 L2 Tunnel mode */ 182 _SHR_PORT_ENCAP_HIGIG2_IP_GRE = 6, /* HIGIG2 L3 (IP-GRE) Tunnel mode */ 183 _SHR_PORT_ENCAP_OBSOLETE = 7, /* Obsolete header mode */ 184 _SHR_PORT_ENCAP_PREAMBLE_SOP_ONLY = 8, /* 1B preamble mode */ 185 _SHR_PORT_ENCAP_HIGIG_OVER_ETHERNET = 9,/* HIGIG over Ethernet */ 186 _SHR_PORT_ENCAP_CPRI = 10 , /* CPRI radio port encap*/ 187 _SHR_PORT_ENCAP_RSVD4 = 11 , /* RSVD4 radio port encap*/ 188 _SHR_PORT_ENCAP_COUNT /* last, please */ 189 } _shr_port_encap_t; 190 191 #define _SHR_PORT_ENCAP_NAMES_INITIALIZER { \ 192 "IEEE", \ 193 "HiGig", \ 194 "B5632", \ 195 "HiGig2", \ 196 "HiGig2-Lite", \ 197 "HiGig2_L2", \ 198 "HiGig2_IP_GRE", \ 199 "Obsolete", \ 200 "SOP_Only", \ 201 "HiGig_over_Ethernet", \ 202 "CPRI", \ 203 "MAX_Count" \ 204 } 205 206 /* 207 * Defines: 208 * _SHR_PORT_STP_* 209 * Purpose: 210 * Defines the spanning tree states of a port. 211 */ 212 213 typedef enum _shr_port_stp_e { 214 _SHR_PORT_STP_DISABLE = 0, 215 _SHR_PORT_STP_BLOCK = 1, 216 _SHR_PORT_STP_LISTEN = 2, 217 _SHR_PORT_STP_LEARN = 3, 218 _SHR_PORT_STP_FORWARD = 4, 219 _SHR_PORT_STP_COUNT = 5 /* last, please */ 220 } _shr_port_stp_t; 221 222 /* 223 * Defines: 224 * _SHR_PORT_MDIX_* 225 * Purpose: 226 * Defines the MDI crossover (MDIX) modes for the port 227 */ 228 typedef enum _shr_port_mdix_e { 229 _SHR_PORT_MDIX_AUTO, 230 _SHR_PORT_MDIX_FORCE_AUTO, 231 _SHR_PORT_MDIX_NORMAL, 232 _SHR_PORT_MDIX_XOVER, 233 _SHR_PORT_MDIX_COUNT /* last, please */ 234 } _shr_port_mdix_t; 235 236 /* 237 * Defines: 238 * _SHR_PORT_MDIX_STATUS_* 239 * Purpose: 240 * Defines the MDI crossover state 241 */ 242 typedef enum _shr_port_mdix_status_e { 243 _SHR_PORT_MDIX_STATUS_NORMAL, 244 _SHR_PORT_MDIX_STATUS_XOVER, 245 _SHR_PORT_MDIX_STATUS_COUNT /* last, please */ 246 } _shr_port_mdix_status_t; 247 248 /* 249 * Defines: 250 * _SHR_PORT_MEDIUM_* 251 * Purpose: 252 * Supported physical mediums 253 */ 254 typedef enum _shr_port_medium_e { 255 _SHR_PORT_MEDIUM_NONE = 0, 256 _SHR_PORT_MEDIUM_COPPER = 1, 257 _SHR_PORT_MEDIUM_FIBER = 2, 258 _SHR_PORT_MEDIUM_BACKPLANE, 259 _SHR_PORT_MEDIUM_ALL, /* this defines mainly for local_ability_get function */ 260 _SHR_PORT_MEDIUM_COUNT /* last, please */ 261 } _shr_port_medium_t; 262 263 /* 264 * Defines: 265 * _SHR_PORT_MCAST_FLOOD_* 266 * Purpose: 267 * Multicast packet flooding mode 268 */ 269 typedef enum _shr_port_mcast_flood_e { 270 _SHR_PORT_MCAST_FLOOD_ALL = 0, 271 _SHR_PORT_MCAST_FLOOD_UNKNOWN = 1, 272 _SHR_PORT_MCAST_FLOOD_NONE = 2, 273 _SHR_PORT_MCAST_FLOOD_COUNT /* last, please */ 274 } _shr_port_mcast_flood_t; 275 276 /* 277 * Defines: 278 * _SHR_PORT_CABLE_STATE_* 279 * Purpose: 280 * Cable diag state (per pair and overall) 281 */ 282 typedef enum { 283 _SHR_PORT_CABLE_STATE_OK, 284 _SHR_PORT_CABLE_STATE_OPEN, 285 _SHR_PORT_CABLE_STATE_SHORT, 286 _SHR_PORT_CABLE_STATE_OPENSHORT, 287 _SHR_PORT_CABLE_STATE_CROSSTALK, 288 _SHR_PORT_CABLE_STATE_UNKNOWN, 289 _SHR_PORT_CABLE_STATE_COUNT /* last, as always */ 290 } _shr_port_cable_state_t; 291 292 #define _SHR_PORT_CABLE_STATE_NAMES_INITIALIZER { \ 293 "Ok", \ 294 "Open", \ 295 "Short", \ 296 "Open/Short", \ 297 "Crosstalk", \ 298 "Unknown", \ 299 } 300 301 /* 302 * Defines: 303 * _shr_port_cable_diag_t 304 * Purpose: 305 * Shared definition of port (phy) cable diag status structure. 306 * Used both in soc/phy layer and in bcm layer. 307 */ 308 typedef struct _shr_port_cable_diag_s { 309 _shr_port_cable_state_t state; /* state of all pairs */ 310 int npairs; /* pair_* elements valid */ 311 _shr_port_cable_state_t pair_state[4]; /* pair state */ 312 int pair_len[4]; /* pair length in metres */ 313 int fuzz_len; /* len values +/- this */ 314 } _shr_port_cable_diag_t; 315 316 /* 317 * Defines: 318 * _SHR_PORT_PHY_INTR_* 319 * Purpose: 320 * Generic PHY interrupt sources for use with: 321 * _SHR_PORT_PHY_CONTROL_INTR_MASK 322 * _SHR_PORT_PHY_CONTROL_INTR_STATUS 323 */ 324 #define _SHR_PORT_PHY_INTR_TIMESYNC_FRAMESYNC 0x1 /* Timesync framesync interrupt */ 325 #define _SHR_PORT_PHY_INTR_TIMESYNC_TIMESTAMP 0x2 /* Timesync timestamp interrupt */ 326 #define _SHR_PORT_PHY_INTR_LINK_EVENT 0x4 /* Link status event interrupt */ 327 #define _SHR_PORT_PHY_INTR_AUTONEG_EVENT 0x8 /* Auto-negotiation event interrupt */ 328 #define _SHR_PORT_PHY_INTR_PLL_EVENT 0x10 /* PLL status event interrupt */ 329 #define _SHR_PORT_PHY_INTR_UC_EVENT 0x20 /* Microcontroller event interrupt */ 330 #define _SHR_PORT_PHY_INTR_EMON_EVENT 0x40 /* Error monitor event interrupt */ 331 #define _SHR_PORT_PHY_INTR_AUX_EVENT 0x80 /* Non-standard PHY event interrupt */ 332 333 /* 334 * Defines: 335 * _SHR_PORT_PHY_CONTROL_* 336 * Purpose: 337 * PHY specific control settings 338 */ 339 typedef enum _shr_port_phy_control_e { 340 _SHR_PORT_PHY_CONTROL_WAN = 0, 341 _SHR_PORT_PHY_CONTROL_PREEMPHASIS = 1, 342 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT = 2, 343 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT = 3, 344 _SHR_PORT_PHY_CONTROL_EQUALIZER_BOOST = 4, 345 _SHR_PORT_PHY_CONTROL_INTERFACE = 5, 346 _SHR_PORT_PHY_CONTROL_INTERFACE_MAX = 6, 347 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED = 7, 348 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_SPEED = 8, 349 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_DUPLEX = 9, 350 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_PAUSE = 10, 351 _SHR_PORT_PHY_CONTROL_MACSEC_PAUSE_RX_FORWARD = 11, 352 _SHR_PORT_PHY_CONTROL_MACSEC_PAUSE_TX_FORWARD = 12, 353 _SHR_PORT_PHY_CONTROL_MACSEC_LINE_IPG = 13, 354 _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_IPG = 14, 355 _SHR_PORT_PHY_CONTROL_LONGREACH_SPEED = 15, 356 _SHR_PORT_PHY_CONTROL_LONGREACH_PAIRS = 16, 357 _SHR_PORT_PHY_CONTROL_LONGREACH_GAIN = 17, 358 _SHR_PORT_PHY_CONTROL_LONGREACH_AUTONEG = 18, 359 _SHR_PORT_PHY_CONTROL_LONGREACH_LOCAL_ABILITY = 19, 360 _SHR_PORT_PHY_CONTROL_LONGREACH_REMOTE_ABILITY = 20, 361 _SHR_PORT_PHY_CONTROL_LONGREACH_CURRENT_ABILITY = 21, 362 _SHR_PORT_PHY_CONTROL_LONGREACH_MASTER = 22, 363 _SHR_PORT_PHY_CONTROL_LONGREACH_ACTIVE = 23, 364 _SHR_PORT_PHY_CONTROL_LONGREACH_ENABLE = 24, 365 _SHR_PORT_PHY_CONTROL_LOOPBACK_EXTERNAL = 25, 366 _SHR_PORT_PHY_CONTROL_CLOCK_ENABLE = 26, 367 _SHR_PORT_PHY_CONTROL_CLOCK_SECONDARY_ENABLE = 27, 368 _SHR_PORT_PHY_CONTROL_CLOCK_FREQUENCY = 28, 369 _SHR_PORT_PHY_CONTROL_PORT_PRIMARY = 29, 370 _SHR_PORT_PHY_CONTROL_PORT_OFFSET = 30, 371 _SHR_PORT_PHY_CONTROL_PRE_PREEMPHASIS = 31, 372 _SHR_PORT_PHY_CONTROL_ENCODING = 32, 373 _SHR_PORT_PHY_CONTROL_SCRAMBLER = 33, 374 _SHR_PORT_PHY_CONTROL_PRBS_POLYNOMIAL = 34, 375 _SHR_PORT_PHY_CONTROL_PRBS_TX_INVERT_DATA = 35, 376 _SHR_PORT_PHY_CONTROL_PRBS_TX_ENABLE = 36, 377 _SHR_PORT_PHY_CONTROL_PRBS_RX_ENABLE = 37, 378 _SHR_PORT_PHY_CONTROL_PRBS_RX_STATUS = 38, 379 _SHR_PORT_PHY_CONTROL_SERDES_DRIVER_TUNE = 39, 380 _SHR_PORT_PHY_CONTROL_SERDES_DRIVER_EQUALIZATION_TUNE_STATUS_FAR_END = 40, 381 _SHR_PORT_PHY_CONTROL_8B10B = 41, 382 _SHR_PORT_PHY_CONTROL_64B66B = 42, 383 _SHR_PORT_PHY_CONTROL_POWER = 43, 384 _SHR_PORT_PHY_CONTROL_POWER_AUTO_SLEEP_TIME = 44, 385 _SHR_PORT_PHY_CONTROL_POWER_AUTO_WAKE_TIME = 45, 386 _SHR_PORT_PHY_CONTROL_LINKDOWN_TRANSMIT = 46, 387 _SHR_PORT_PHY_CONTROL_EDC_CONFIG = 47, 388 _SHR_PORT_PHY_CONTROL_EDC_MODE = 48, 389 _SHR_PORT_PHY_CONTROL_EEE = 49, 390 _SHR_PORT_PHY_CONTROL_EEE_AUTO = 50, 391 _SHR_PORT_PHY_CONTROL_EEE_AUTO_IDLE_THRESHOLD = 51, 392 _SHR_PORT_PHY_CONTROL_EEE_AUTO_BUFFER_LIMIT = 52, 393 _SHR_PORT_PHY_CONTROL_EEE_AUTO_FIXED_LATENCY = 53, 394 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_WAKE_TIME = 54, 395 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_WAKE_TIME = 55, 396 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_SLEEP_TIME = 56, 397 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_SLEEP_TIME = 57, 398 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_QUIET_TIME = 58, 399 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_QUIET_TIME = 59, 400 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_REFRESH_TIME = 60, 401 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_EVENTS = 61, 402 _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_DURATION = 62, 403 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_EVENTS = 63, 404 _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_DURATION = 64, 405 _SHR_PORT_PHY_CONTROL_EEE_STATISTICS_CLEAR = 65, 406 _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MAX = 66, 407 _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MODE = 67, 408 _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_VALUE = 68, 409 _SHR_PORT_PHY_CONTROL_PARALLEL_DETECTION = 69, 410 _SHR_PORT_PHY_CONTROL_PARALLEL_DETECTION_10G = 70, 411 _SHR_PORT_PHY_CONTROL_LOOPBACK_INTERNAL = 71, 412 _SHR_PORT_PHY_CONTROL_LOOPBACK_REMOTE = 72, 413 _SHR_PORT_PHY_CONTROL_LOOPBACK_REMOTE_PCS_BYPASS = 73, 414 _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION = 74, 415 _SHR_PORT_PHY_CONTROL_CUSTOM1 = 75, 416 _SHR_PORT_PHY_CONTROL_BERT_PATTERN = 76, 417 _SHR_PORT_PHY_CONTROL_BERT_RUN = 77, 418 _SHR_PORT_PHY_CONTROL_BERT_PACKET_SIZE = 78, 419 _SHR_PORT_PHY_CONTROL_BERT_IPG = 79, 420 _SHR_PORT_PHY_CONTROL_BERT_TX_PACKETS = 80, 421 _SHR_PORT_PHY_CONTROL_BERT_RX_PACKETS = 81, 422 _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_BITS = 82, 423 _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_BYTES = 83, 424 _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_PACKETS = 84, 425 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE0 = 85, 426 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE1 = 86, 427 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE2 = 87, 428 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE3 = 88, 429 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE0 = 89, 430 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE1 = 90, 431 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE2 = 91, 432 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE3 = 92, 433 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE0 = 93, 434 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE1 = 94, 435 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE2 = 95, 436 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE3 = 96, 437 _SHR_PORT_PHY_CONTROL_TX_LANE_SQUELCH = 97, 438 _SHR_PORT_PHY_CONTROL_DRIVER_POST2_CURRENT = 98, 439 _SHR_PORT_PHY_CONTROL_RX_PPM = 99, 440 _SHR_PORT_PHY_CONTROL_RX_PEAK_FILTER = 100, 441 _SHR_PORT_PHY_CONTROL_RX_LOW_FREQ_PEAK_FILTER = 101, 442 _SHR_PORT_PHY_CONTROL_RX_VGA = 102, 443 _SHR_PORT_PHY_CONTROL_RX_TAP1 = 103, 444 _SHR_PORT_PHY_CONTROL_RX_TAP2 = 104, 445 _SHR_PORT_PHY_CONTROL_RX_TAP3 = 105, 446 _SHR_PORT_PHY_CONTROL_RX_TAP4 = 106, 447 _SHR_PORT_PHY_CONTROL_RX_TAP5 = 107, 448 _SHR_PORT_PHY_CONTROL_RX_VGA_RELEASE = 108, 449 _SHR_PORT_PHY_CONTROL_RX_TAP1_RELEASE = 109, 450 _SHR_PORT_PHY_CONTROL_RX_TAP2_RELEASE = 110, 451 _SHR_PORT_PHY_CONTROL_RX_TAP3_RELEASE = 111, 452 _SHR_PORT_PHY_CONTROL_RX_TAP4_RELEASE = 112, 453 _SHR_PORT_PHY_CONTROL_RX_TAP5_RELEASE = 113, 454 _SHR_PORT_PHY_CONTROL_RX_PLUS1_SLICER = 114, 455 _SHR_PORT_PHY_CONTROL_RX_MINUS1_SLICER = 115, 456 _SHR_PORT_PHY_CONTROL_RX_D_SLICER = 116, 457 _SHR_PORT_PHY_CONTROL_RX_SIGNAL_DETECT = 117, 458 _SHR_PORT_PHY_CONTROL_RX_SEQ_DONE = 118, 459 _SHR_PORT_PHY_CONTROL_RX_POLARITY = 119, 460 _SHR_PORT_PHY_CONTROL_TX_POLARITY = 120, 461 _SHR_PORT_PHY_CONTROL_RX_RESET = 121, 462 _SHR_PORT_PHY_CONTROL_TX_RESET = 122, 463 _SHR_PORT_PHY_CONTROL_CL72 = 123, 464 _SHR_PORT_PHY_CONTROL_CL72_STATUS = 124, 465 _SHR_PORT_PHY_CONTROL_LANE_SWAP = 125, 466 _SHR_PORT_PHY_CONTROL_DUMP = 126, 467 _SHR_PORT_PHY_CONTROL_TX_PATTERN_20BIT = 127, 468 _SHR_PORT_PHY_CONTROL_TX_PATTERN_256BIT = 128, 469 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA0 = 129, 470 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA1 = 130, 471 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA2 = 131, 472 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA3 = 132, 473 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA4 = 133, 474 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA5 = 134, 475 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA6 = 135, 476 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA7 = 136, 477 _SHR_PORT_PHY_CONTROL_PHASE_INTERP = 137, 478 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER_TIME = 138, 479 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER_MODE = 139, 480 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_STATUS = 140, 481 _SHR_PORT_PHY_CONTROL_PON_LASER_RX_STATE = 141, 482 _SHR_PORT_PHY_CONTROL_PON_LASER_TRANCEIVER_TEMP = 142, 483 _SHR_PORT_PHY_CONTROL_PON_LASER_SUPPLY_VOLTAGE = 143, 484 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_BIAS = 144, 485 _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER = 145, 486 _SHR_PORT_PHY_CONTROL_PON_LASER_RX_POWER = 146, 487 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_STATE = 147, 488 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_REPORT_THRESHOLD = 148, 489 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_CLEAR_THRESHOLD = 149, 490 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_STATE = 150, 491 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_REPORT_THRESHOLD = 151, 492 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_CLEAR_THRESHOLD = 152, 493 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_STATE = 153, 494 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_REPORT_THRESHOLD = 154, 495 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_CLEAR_THRESHOLD = 155, 496 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_STATE = 156, 497 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_REPORT_THRESHOLD = 157, 498 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_CLEAR_THRESHOLD = 158, 499 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_STATE = 159, 500 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_REPORT_THRESHOLD = 160, 501 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_CLEAR_THRESHOLD = 161, 502 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_STATE = 162, 503 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_REPORT_THRESHOLD = 163, 504 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_CLEAR_THRESHOLD = 164, 505 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_STATE = 165, 506 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_REPORT_THRESHOLD = 166, 507 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_CLEAR_THRESHOLD = 167, 508 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_STATE = 168, 509 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_REPORT_THRESHOLD = 169, 510 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_CLEAR_THRESHOLD = 170, 511 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_STATE = 171, 512 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_REPORT_THRESHOLD = 172, 513 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_CLEAR_THRESHOLD = 173, 514 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_STATE = 174, 515 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_REPORT_THRESHOLD = 175, 516 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_CLEAR_THRESHOLD = 176, 517 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_STATE = 177, 518 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_REPORT_THRESHOLD = 178, 519 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_CLEAR_THRESHOLD = 179, 520 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_STATE = 180, 521 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_REPORT_THRESHOLD = 181, 522 _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_CLEAR_THRESHOLD = 182, 523 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_STATE = 183, 524 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_REPORT_THRESHOLD = 184, 525 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_CLEAR_THRESHOLD = 185, 526 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_STATE = 186, 527 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_REPORT_THRESHOLD = 187, 528 _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_CLEAR_THRESHOLD = 188, 529 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_STATE = 189, 530 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_REPORT_THRESHOLD = 190, 531 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_CLEAR_THRESHOLD = 191, 532 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_STATE = 192, 533 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_REPORT_THRESHOLD = 193, 534 _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_CLEAR_THRESHOLD = 194, 535 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_STATE = 195, 536 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_REPORT_THRESHOLD = 196, 537 _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_CLEAR_THRESHOLD = 197, 538 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_STATE = 198, 539 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_REPORT_THRESHOLD = 199, 540 _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_CLEAR_THRESHOLD = 200, 541 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_STATE = 201, 542 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_REPORT_THRESHOLD = 202, 543 _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_CLEAR_THRESHOLD = 203, 544 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_STATE = 204, 545 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_REPORT_THRESHOLD = 205, 546 _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_CLEAR_THRESHOLD = 206, 547 _SHR_PORT_PHY_CONTROL_DLL_POWER_AUTO = 207, 548 _SHR_PORT_PHY_CONTROL_TX_PPM_ADJUST = 208, 549 _SHR_PORT_PHY_CONTROL_FIRMWARE_MODE = 209, 550 _SHR_PORT_PHY_CONTROL_VCO_FREQ = 210, 551 _SHR_PORT_PHY_CONTROL_PLL_DIVIDER = 211, 552 _SHR_PORT_PHY_CONTROL_OVERSAMPLE_MODE = 212, 553 _SHR_PORT_PHY_CONTROL_REF_CLK = 213, 554 _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS = 214, 555 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_ENABLE = 215, 556 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_INVERT_DATA = 216, 557 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_POLYNOMIAL = 217, 558 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_ENABLE = 218, 559 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_INVERT_DATA = 219, 560 _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_POLYNOMIAL = 220, 561 _SHR_PORT_PHY_CONTROL_RX_PEAK_FILTER_TEMP_COMP = 221, 562 _SHR_PORT_PHY_CONTROL_CL73_FSM_AUTO_RECOVER = 222, 563 _SHR_PORT_PHY_CONTROL_RX_SEQ_TOGGLE = 223, 564 _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY = 224, 565 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE = 225, 566 _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE = 226, 567 _SHR_PORT_PHY_CONTROL_PRBS_RX_INVERT_DATA = 227, 568 _SHR_PORT_PHY_CONTROL_PRBS_CHECK_MODE = 228, 569 _SHR_PORT_PHY_CONTROL_MOD_AUTO_DETECT_ENABLE = 229, 570 _SHR_PORT_PHY_CONTROL_DIGITAL_TEMP = 230, 571 _SHR_PORT_PHY_CONTROL_ANALOG_TEMP = 231, 572 _SHR_PORT_PHY_CONTROL_TX_FIR_PRE = 232, 573 _SHR_PORT_PHY_CONTROL_TX_FIR_MAIN = 233, 574 _SHR_PORT_PHY_CONTROL_TX_FIR_POST = 234, 575 _SHR_PORT_PHY_CONTROL_TX_FIR_POST2 = 235, 576 _SHR_PORT_PHY_CONTROL_TX_FIR_POST3 = 236, 577 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PMA_OS = 237, 578 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_SCR_MODE = 238, 579 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_ENCODE_MODE = 239, 580 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL48_CHECK_END = 240, 581 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_BLK_SYNC_MODE = 241, 582 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_REORDER_MODE = 242, 583 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL36_EN = 243, 584 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESCR1_MODE = 244, 585 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DEC1_MODE = 245, 586 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESKEW_MODE = 246, 587 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_MODE = 247, 588 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_BYTE_DEL = 248, 589 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_BRCM64B66_DESCR = 249, 590 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_SGMII_MODE = 250, 591 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT0 = 251, 592 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT1 = 252, 593 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT0 = 253, 594 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT1 = 254, 595 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_MAC_CGC = 255, 596 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_REPCNT = 256, 597 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CREDTEN = 257, 598 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CLKCNT = 258, 599 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CGC = 259, 600 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL72_EN = 260, 601 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_ENTRY = 261, 602 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_HCD = 262, 603 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PMA_OS = 263, 604 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_SCR_MODE = 264, 605 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_ENCODE_MODE = 265, 606 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL48_CHECK_END = 266, 607 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_BLK_SYNC_MODE = 267, 608 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_REORDER_MODE = 268, 609 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL36_EN = 269, 610 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESCR1_MODE = 270, 611 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DEC1_MODE = 271, 612 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESKEW_MODE = 272, 613 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_MODE = 273, 614 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_BYTE_DEL = 274, 615 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_BRCM64B66_DESCR = 275, 616 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_SGMII_MODE = 276, 617 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT0 = 277, 618 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT1 = 278, 619 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT0 = 279, 620 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT1 = 280, 621 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_MAC_CGC = 281, 622 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_REPCNT = 282, 623 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CREDTEN = 283, 624 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CLKCNT = 284, 625 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CGC = 285, 626 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL72_EN = 286, 627 _SHR_PORT_PHY_CONTROL_LOOPBACK_PMD = 287, 628 _SHR_PORT_PHY_CONTROL_TX_PATTERN_GEN_ENABLE = 288, 629 _SHR_PORT_PHY_CONTROL_TX_PATTERN_LENGTH = 289, 630 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PLL_DIVIDER = 290, 631 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLEAR = 291, 632 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PLL_DIVIDER = 292, 633 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_NUM_OF_LANES = 293, 634 _SHR_PORT_PHY_CONTROL_CLOCK_MODE_AUTO = 294, 635 _SHR_PORT_PHY_CONTROL_CLOCK_AUTO_SECONDARY = 295, 636 _SHR_PORT_PHY_CONTROL_CLOCK_SOURCE = 296, 637 _SHR_PORT_PHY_CONTROL_DFE = 297, 638 _SHR_PORT_PHY_CONTROL_INTR_MASK = 298, 639 _SHR_PORT_PHY_CONTROL_INTR_STATUS = 299, 640 _SHR_PORT_PHY_CONTROL_XSW_LANE_MAP = 300, 641 _SHR_PORT_PHY_CONTROL_VCO_DISTURBED = 301, 642 _SHR_PORT_PHY_CONTROL_FIRMWARE_DFE_ENABLE = 302, 643 _SHR_PORT_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE = 303, 644 _SHR_PORT_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE = 304, 645 _SHR_PORT_PHY_CONTROL_GPIO_CONFIG = 305, 646 _SHR_PORT_PHY_CONTROL_GPIO_VALUE = 306, 647 _SHR_PORT_PHY_CONTROL_PCS_MODE = 307, 648 _SHR_PORT_PHY_CONTROL_SUPER_ISOLATE = 308, 649 _SHR_PORT_PHY_CONTROL_SOFT_RESET = 309, 650 _SHR_PORT_PHY_CONTROL_AUTONEG_ALLOW_PLL_CHANGE = 310, 651 _SHR_PORT_PHY_CONTROL_FAIL_OVER_MODE = 311, 652 _SHR_PORT_PHY_SHORT_CHANNEL_MODE = 312, 653 _SHR_PORT_PHY_CONTROL_EYE_VAL_HZ_L = 313, 654 _SHR_PORT_PHY_CONTROL_EYE_VAL_HZ_R = 314, 655 _SHR_PORT_PHY_CONTROL_EYE_VAL_VT_U = 315, 656 _SHR_PORT_PHY_CONTROL_EYE_VAL_VT_D = 316, 657 _SHR_PORT_PHY_CONTROL_MEDIUM_TYPE = 317, 658 _SHR_PORT_PHY_CONTROL_FORCED_SPEED_LINE_SIDE = 318, 659 _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL91 = 319, 660 _SHR_PORT_PHY_CONTROL_SHORT_CHANNEL_MODE_STATUS = 320, 661 _SHR_PORT_PHY_EGRESS_FLOW_CONTROL_MODE = 321, 662 _SHR_PORT_PHY_INGRESS_FLOW_CONTROL_MODE = 322, 663 _SHR_PORT_PHY_CONTROL_UNRELIABLE_LOS = 323, 664 _SHR_PORT_PHY_CONTROL_PSM_COS_BMP = 324, 665 _SHR_PORT_PHY_CONTROL_RX_LANE_SQUELCH = 325, 666 _SHR_PORT_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE = 326, 667 _SHR_PORT_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE = 327, 668 _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_LINK_WAIT_TIMER_US = 328, 669 _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_RESTART_TIMER_US = 329, 670 _SHR_PORT_PHY_CONTROL_MGBASET_802P3BZ_PRIORITY = 330, 671 _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE = 331, 672 _SHR_PORT_PHY_CONTROL_AUTONEG_OUI = 332, 673 _SHR_PORT_PHY_CONTROL_AUTONEG_LINE_SIDE =333, 674 _SHR_PORT_PHY_CONTROL_FEC_CORRECTED_BLOCK_COUNT = 334, 675 _SHR_PORT_PHY_CONTROL_FEC_UNCORRECTED_BLOCK_COUNT = 335, 676 _SHR_PORT_PHY_CONTROL_FEC_CORRECTED_CODEWORD_COUNT = 336, 677 _SHR_PORT_PHY_CONTROL_FEC_UNCORRECTED_CODEWORD_COUNT = 337, 678 _SHR_PORT_PHY_CONTROL_RX_TAP6 = 338, 679 _SHR_PORT_PHY_CONTROL_RX_TAP6_RELEASE = 339, 680 _SHR_PORT_PHY_CONTROL_PAM4_TX_PATTERN_ENABLE = 340, 681 _SHR_PORT_PHY_CONTROL_FEC_SYMBOL_ERROR_COUNT = 341, 682 _SHR_PORT_PHY_CONTROL_TX_FIR_MODE = 342, 683 _SHR_PORT_PHY_CONTROL_TX_FIR_PRE2 = 343, 684 _SHR_PORT_PHY_CONTROL_RX_ADAPTATION_RESUME = 344, 685 _SHR_PORT_PHY_CONTROL_BOND_IN_PWRDN_OVERRIDE = 345, 686 _SHR_PORT_PHY_CONTROL_TX_PAM4_PRECODER_ENABLE = 346, 687 _SHR_PORT_PHY_CONTROL_LP_TX_PRECODER_ENABLE = 347, 688 _SHR_PORT_PHY_CONTROL_RX_HIGH_FREQ_PEAK_FILTER = 348, 689 _SHR_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE = 349, 690 _SHR_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE = 350, 691 _SHR_PORT_PHY_CONTROL_FAST_BER_PROJ = 351, 692 _SHR_PORT_PHY_CONTROL_AUTONEG_FEC_OVERRIDE = 352, 693 _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL108 = 353, 694 _SHR_PORT_PHY_CONTROL_CHANNEL_LOSS_HINT = 354, 695 _SHR_PORT_PHY_CONTROL_LINK_TRAINING_INIT_TX_FIR_POST = 355, 696 _SHR_PORT_PHY_CONTROL_MACSEC_ENABLE = 356, 697 _SHR_PORT_PHY_CONTROL_FEC_BYPASS_INDICATION_ENABLE = 357, 698 _SHR_PORT_PHY_CONTROL_PFC_USE_IP_COS = 358, 699 _SHR_PORT_PHY_CONTROL_NUM /* Must be last */ 700 } _shr_port_phy_control_t; 701 702 /* 703 * SyncE recovered clock source 704 * status to indicate primary recovered clock has switched to secondary source 705 * when link failure 706 */ 707 typedef enum _shr__port_phy_clock_source_e { 708 _SHR_PORT_PHY_CLOCK_SOURCE_NONE = 0, 709 _SHR_PORT_PHY_CLOCK_SOURCE_PRIMARY, /* Recovery clock is being derived from *\ 710 \* primary port's recovered clock */ 711 _SHR_PORT_PHY_CLOCK_SOURCE_SECONDARY /* Recovery clock is being derived from *\ 712 \* secondary port's recovered clock */ 713 } _shr_port_phy_clock_source_t; 714 715 /* 716 * Defines: 717 * _SHR_PORT_PHY_CONTROL_FIRMWARE_MODE_* 718 * Purpose: 719 * FIRMWARE MODE 720 */ 721 typedef enum _shr_port_phy_control_firmware_mode_e { 722 _SHR_PORT_PHY_FIRMWARE_DEFAULT = 0, /* default */ 723 _SHR_PORT_PHY_FIRMWARE_SFP_OPT_SR4, /* optical short range */ 724 _SHR_PORT_PHY_FIRMWARE_SFP_DAC, /* direct attach copper */ 725 _SHR_PORT_PHY_FIRMWARE_XLAUI, /* 40G XLAUI mode */ 726 _SHR_PORT_PHY_FIRMWARE_FORCE_OSDFE, /* force over sample digital feedback equalization */ 727 _SHR_PORT_PHY_FIRMWARE_FORCE_BRDFE, /* force baud rate digital feedback equalization */ 728 _SHR_PORT_PHY_FIRMWARE_SW_CL72, /* software cl72 with AN on */ 729 _SHR_PORT_PHY_FIRMWARE_CL72_WITHOUT_AN, /* cl72 without AN */ 730 _SHR_PORT_PHY_FIRMWARE_DFE_ENABLE, /* enable digital feedback equalization */ 731 _SHR_PORT_PHY_FIRMWARE_LP_DFE_ENABLE /* enable digital feedback equalization */ 732 } _shr_port_phy_control_firmware_mode_t; 733 734 /* 735 * Defines: 736 * _SHR_PORT_PHY_CONTROL_DFE_* 737 * Purpose: 738 * DFE MODE 739 */ 740 typedef enum _shr_port_phy_control_dfe_e { 741 _SHR_PORT_PHY_DFE_AUTO = 0, /* default */ 742 _SHR_PORT_PHY_DFE_FREEZE /* Freeze DFE */ 743 } _shr_port_phy_control_dfe_t; 744 745 /* 746 * Defines: 747 * _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_* 748 * Purpose: 749 * Set autoneg mode 750 */ 751 typedef enum _shr_port_phy_control_autoneg_mode_e { 752 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37 = 1, 753 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM, 754 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73, 755 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM, 756 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73, 757 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73_BAM, 758 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73, 759 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73_BAM, 760 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_MSA, 761 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_NONE, /*this flag is for local_ability_ get function indicating forced speed */ 762 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_COUNT 763 } _shr_port_phy_control_autoneg_mode_t; 764 765 766 /* 767 * Defines: 768 * _SHR_PORT_PHY_CONTROL_AUTONEG_OUI_* 769 * Purpose: 770 * Set autoneg oui mode 771 */ 772 typedef enum _shr_port_phy_control_autoneg_oui_value_e { 773 _SHR_PORT_PHY_CONTROL_AUTONEG_OUI_DEFAULT = 0 774 } _shr_port_phy_control_autoneg_oui_value_t; 775 776 777 /* 778 * Defines: 779 * _SHR_PORT_PRBS_POLYNOMIAL_* 780 * Purpose: 781 * PRBS polynomial type 782 */ 783 typedef enum _shr_port_prbs_polynomial_e { 784 _SHR_PORT_PRBS_POLYNOMIAL_X7_X6_1 = 0, 785 _SHR_PORT_PRBS_POLYNOMIAL_X15_X14_1 = 1, 786 _SHR_PORT_PRBS_POLYNOMIAL_X23_X18_1 = 2, 787 _SHR_PORT_PRBS_POLYNOMIAL_X31_X28_1 = 3, 788 _SHR_PORT_PRBS_POLYNOMIAL_X9_X5_1 = 4, 789 _SHR_PORT_PRBS_POLYNOMIAL_X11_X9_1 = 5, 790 _SHR_PORT_PRBS_POLYNOMIAL_X58_X31_1 = 6, 791 _SHR_PORT_PRBS_POLYNOMIAL_X49_X40_1 = 7, 792 _SHR_PORT_PRBS_POLYNOMIAL_X20_X3_1 = 8, 793 _SHR_PORT_PRBS_POLYNOMIAL_X13_X12_X2_1 = 9, 794 _SHR_PORT_PRBS_POLYNOMIAL_X10_X7_1 = 10, 795 _SHR_PORT_PRBS_POLYNOMIAL_PAM4_13Q = 11 796 } _shr_port_prbs_polynomial_t; 797 798 /* 799 * Defines: 800 * _SHR_PHY_PCS_MODE_* 801 * Purpose: 802 * PCS MODE type 803 */ 804 typedef enum _shr_port_phy_pcs_mode_e { 805 _SHR_PORT_PHY_CONTROL_PCS_MODE_IEEE = 0, 806 _SHR_PORT_PHY_CONTROL_PCS_MODE_BRCM = 1, 807 _SHR_PORT_PHY_CONTROL_PCS_MODE_COUNT 808 } _shr_port_phy_pcs_mode_t; 809 810 /* 811 * Defines: 812 * _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_* 813 * Purpose: 814 * PHY specific control settings 815 */ 816 typedef enum _shr_port_phy_control_longreach_ability_e { 817 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_NONE, 818 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_1PAIR=1, 819 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_2PAIR=2, 820 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_1PAIR=4, 821 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_2PAIR=8, 822 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_1PAIR=16, 823 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_2PAIR=32, 824 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_1PAIR=64, 825 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_2PAIR=128, 826 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_1PAIR=256, 827 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_2PAIR=512, 828 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_1PAIR=1024, 829 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_2PAIR=2048, 830 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_4PAIR=4096, 831 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_RX=8192, 832 _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_TX=16384 833 } _shr_port_phy_control_longreach_ability_t; 834 835 /* 836 * Defines: 837 * _SHR_PORT_PHY_CONTROL_POWER_* 838 * Purpose: 839 * PHY specific values for _SHR_PORT_PHY_CONTROL_POWER type 840 */ 841 typedef enum _shr_port_phy_control_power_e { 842 _SHR_PORT_PHY_CONTROL_POWER_FULL, 843 _SHR_PORT_PHY_CONTROL_POWER_LOW, 844 _SHR_PORT_PHY_CONTROL_POWER_AUTO, 845 /* Power mode added(SDK-30895). Requirement is to disable *\ 846 \* Auto Power Down without changing Tx bias current */ 847 _SHR_PORT_PHY_CONTROL_POWER_AUTO_DISABLE, 848 _SHR_PORT_PHY_CONTROL_POWER_AUTO_FULL, 849 _SHR_PORT_PHY_CONTROL_POWER_AUTO_LOW 850 } _shr_port_phy_control_power_t; 851 852 /* 853 * Defines: 854 * _SHR_PORT_PHY_CONTROL_FEC_* 855 * Purpose: 856 * PHY specific values for _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION 857 */ 858 typedef enum _shr_port_phy_control_fec_e { 859 _SHR_PORT_PHY_CONTROL_FEC_OFF, 860 _SHR_PORT_PHY_CONTROL_FEC_ON, 861 _SHR_PORT_PHY_CONTROL_FEC_AUTO 862 } _shr_port_phy_control_fec_t; 863 864 /* 865 * Defines: 866 * _SHR_PORT_PHY_CONTROL_EDC_CONFIG_* 867 * Purpose: 868 * Valid control values for _SHR_PORT_PHY_CONTROL_EDC_CONFIG type 869 */ 870 typedef enum _shr_port_phy_control_edc_config_e { 871 _SHR_PORT_PHY_CONTROL_EDC_CONFIG_NONE, 872 _SHR_PORT_PHY_CONTROL_EDC_CONFIG_HARDWARE, 873 _SHR_PORT_PHY_CONTROL_EDC_CONFIG_SOFTWARE 874 } _shr_port_phy_control_edc_config_t; 875 876 /* 877 * Defines: 878 * _SHR_PORT_PHY_CONTROL_BERT_* 879 * Purpose: 880 * Valid control values for _SHR_PORT_PHY_CONTROL_BERT_PATTERN type 881 */ 882 typedef enum _shr_port_phy_control_bert_pattern_e { 883 _SHR_PORT_PHY_CONTROL_BERT_CRPAT = 1, 884 _SHR_PORT_PHY_CONTROL_BERT_CJPAT = 2 885 } _shr_port_phy_control_bert_pattern_t; 886 887 typedef enum _shr_port_phy_control_pam4_tx_pattern_e { 888 _SHR_PORT_PHY_PAM4_TX_PATTERN_INVALID = 0, 889 _SHR_PORT_PHY_PAM4_TX_PATTERN_OFF, 890 _SHR_PORT_PHY_PAM4_TX_PATTERN_JP03B, 891 _SHR_PORT_PHY_PAM4_TX_PATTERN_LINEAR 892 } _shr_port_phy_control_pam4_tx_pattern_t; 893 894 typedef enum _shr_port_phy_control_driver_supply_e { 895 _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_1_0V, 896 _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_0V_700MV, 897 _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_700MV 898 } _shr_port_phy_control_driver_supply_t; 899 900 901 typedef enum _shr_port_phy_control_tx_fir_drivermode_e { 902 _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_DEFAULT, 903 _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_NOT_SUPPORTED, 904 _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP, 905 _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP_HI_IMPED 906 } _shr_port_phy_control_tx_fir_drivermode_t; 907 908 typedef enum _shr_port_phy_control_hg2_bcm_codec_enable_e { 909 _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF, 910 _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_8BYTE_IPG, 911 _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_9BYTE_IPG 912 } _shr_port_phy_control_hg2_bcm_codec_enable_t; 913 914 typedef enum _shr_port_phy_control_tx_fir_mode_e { 915 _SHR_PORT_PHY_TX_FIR_MODE_INVALID = 0, 916 _SHR_PORT_PHY_TX_FIR_3TAP_MODE, 917 _SHR_PORT_PHY_TX_FIR_6TAP_MODE 918 } _shr_port_phy_control_tx_fir_mode_t; 919 920 typedef enum _shr_port_phy_control_rx_los_e { 921 _SHR_PORT_PHY_CONTROL_RX_LOS_NONE, 922 _SHR_PORT_PHY_CONTROL_RX_LOS_SOFTWARE, 923 _SHR_PORT_PHY_CONTROL_RX_LOS_FIRMWARE 924 } _shr_port_phy_control_rx_los_t; 925 926 typedef enum _shr_port_phy_control_gpio_config_e { 927 _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_DISABLED, 928 _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_OUTPUT, 929 _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_INPUT 930 } _shr_port_phy_control_gpio_config_t; 931 932 #define _SHR_PORT_RESOURCE_DEFAULT_REQUEST (-1) 933 /* 934 * Defines: 935 * _SHR_PORT_RLM_* 936 * Purpose: 937 * Valid values for RLM Status 938 */ 939 typedef enum _shr_port_rlm_status_e { 940 _SHR_PORT_RLM_DISABLED, 941 _SHR_PORT_RLM_BUSY, 942 _SHR_PORT_RLM_DONE, 943 _SHR_PORT_RLM_FAILED, 944 _SHR_PORT_RLM_COUNT 945 } _shr_port_rlm_status_t; 946 947 /* 948 * Defines: 949 * _SHR_PORT_PHY_FEC* 950 * Purpose: 951 * Valid values for fec type 952 */ 953 typedef enum _shr_port_phy_fec_e { 954 _SHR_PORT_PHY_FEC_DEFAULT_REQUEST = _SHR_PORT_RESOURCE_DEFAULT_REQUEST, 955 _SHR_PORT_PHY_FEC_INVALID, 956 _SHR_PORT_PHY_FEC_NONE, 957 _SHR_PORT_PHY_FEC_BASE_R, 958 _SHR_PORT_PHY_FEC_RS_FEC, 959 _SHR_PORT_PHY_FEC_RS_544, 960 _SHR_PORT_PHY_FEC_RS_272, 961 _SHR_PORT_PHY_FEC_RS_206, 962 _SHR_PORT_PHY_FEC_RS_108, 963 _SHR_PORT_PHY_FEC_RS_545, 964 _SHR_PORT_PHY_FEC_RS_304, 965 _SHR_PORT_PHY_FEC_RS_544_2XN, 966 _SHR_PORT_PHY_FEC_RS_272_2XN, 967 _SHR_PORT_PHY_FEC_COUNT 968 } _shr_port_phy_fec_t; 969 970 /* 971 * Defines: 972 * _SHR_PORT_PAUSE_* 973 * Purpose: 974 * Supported port pause 975 */ 976 typedef enum _shr_port_phy_pause_e { 977 _SHR_PORT_PHY_PAUSE_NONE = 1, 978 _SHR_PORT_PHY_PAUSE_TX, 979 _SHR_PORT_PHY_PAUSE_RX, 980 _SHR_PORT_PHY_PAUSE_SYMM, 981 _SHR_PORT_PHY_PAUSE_ALL, /*this mainly for local_ability_get function */ 982 _SHR_PORT_PHY_PAUSE_COUNT /* last, please */ 983 } _shr_port_phy_pause_t; 984 985 /* 986 * Defines: 987 * _SHR_PORT_PHY_CHANNEL* 988 * Purpose: 989 * Supported port phy channel 990 */ 991 typedef enum _shr_port_phy_channel_e { 992 _SHR_PORT_PHY_CHANNEL_SHORT = 1, 993 _SHR_PORT_PHY_CHANNEL_LONG, 994 _SHR_PORT_PHY_CHANNEL_ALL, /*this mainly for local_ability_get function */ 995 _SHR_PORT_PHY_CHANNEL_COUNT /* last, please */ 996 } _shr_port_phy_channel_t; 997 998 /* 999 * Defines: 1000 * _shr_port_autoneg_ability_t 1001 * Purpose: 1002 * For autoneg_ability_set/get 1003 */ 1004 typedef struct _shr_port_autoneg_ability_s { 1005 uint32 speed; /* port speed in mbps */ 1006 uint32 resolved_num_lanes; /* autoneg resolved speed num lane */ 1007 _shr_port_phy_fec_t fec_type; /* fec_type for a port */ 1008 _shr_port_medium_t medium; /* medium type of a port */ 1009 _shr_port_phy_pause_t pause; /* pause */ 1010 _shr_port_phy_channel_t channel; /* short/long channel for a port */ 1011 _shr_port_phy_control_autoneg_mode_t an_mode; /* autoneg mode */ 1012 } _shr_port_autoneg_ability_t; 1013 1014 /* 1015 * IEEE-1588 TimeSync timer mode 1016 */ 1017 typedef enum _shr_port_phy_timesync_timer_mode_e { 1018 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_NONE = 0x00, 1019 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_DEFAULT = 0x01, 1020 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_32BIT = 0x02, 1021 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_48BIT = 0x04, 1022 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_64BIT = 0x08, 1023 _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_80BIT = 0x10 1024 } _shr_port_phy_timesync_timer_mode_t; 1025 1026 typedef enum _shr_port_phy_control_flow_control_mode_e { 1027 _SHR_PORT_PHY_CONTROL_FLOW_CTRL_MODE_NONE = 0x00, 1028 _SHR_PORT_PHY_CONTROL_FLOW_CTRL_LEGACY_PAUSE_EN = 0x01, 1029 _SHR_PORT_PHY_CONTROL_FLOW_CTRL_PFC_PAUSE = 0x02, 1030 _SHR_PORT_PHY_CONTROL_FLOW_CTRL_LLFC = 0x04 1031 } _shr_port_phy_control_flow_control_mode_t; 1032 1033 /* bit shift defines for the lane_config on the serdes PMD side */ 1034 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_SHIFT 2 1035 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_MASK 0x1 1036 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_SHIFT 3 1037 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_MASK 0x1 1038 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_SHIFT 4 1039 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_MASK 0x1 1040 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_SHIFT 5 1041 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_MASK 0x3 1042 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_SHIFT 7 1043 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_MASK 0x1 1044 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_SHIFT 8 1045 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_MASK 0x1 1046 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_SHIFT 9 1047 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_MASK 0x1 1048 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_SHIFT 10 1049 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_MASK 0x1 1050 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_SHIFT 11 1051 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_MASK 0x1 1052 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_SHIFT 12 1053 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_MASK 0x1 1054 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_SHIFT 13 1055 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_MASK 0x1 1056 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_SHIFT 14 1057 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_MASK 0x1 1058 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_SHIFT 15 1059 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_MASK 0x1 1060 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_SHIFT 16 1061 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_MASK 0x3f 1062 1063 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_BACKPLANE 0x0 1064 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_COPPER_CABLE 0x1 1065 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_OPTICS 0x2 1066 1067 1068 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_SET(lane_config) \ 1069 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_MASK << \ 1070 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_SHIFT ) 1071 1072 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_CLEAR(lane_config) \ 1073 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_MASK << \ 1074 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_SHIFT) ) 1075 1076 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_GET(lane_config) \ 1077 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_MASK << \ 1078 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_SHIFT) ? 1 : 0 ) 1079 1080 1081 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_SET(lane_config) \ 1082 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_MASK << \ 1083 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_SHIFT ) 1084 1085 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_CLEAR(lane_config) \ 1086 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_MASK << \ 1087 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_SHIFT) ) 1088 1089 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_GET(lane_config) \ 1090 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_MASK << \ 1091 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_SHIFT) ? 1 : 0 ) 1092 1093 1094 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_SET(lane_config) \ 1095 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_MASK << \ 1096 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_SHIFT ) 1097 1098 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_CLEAR(lane_config) \ 1099 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_MASK << \ 1100 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_SHIFT) ) 1101 1102 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_GET(lane_config) \ 1103 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_MASK << \ 1104 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_SHIFT) ? 1 : 0 ) 1105 1106 1107 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_SET(lane_config, medium_type) \ 1108 ( lane_config |= medium_type << \ 1109 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_SHIFT ) 1110 1111 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_CLEAR(lane_config) \ 1112 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_MASK << \ 1113 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_SHIFT) ) 1114 1115 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_GET(lane_config) \ 1116 ( (lane_config >> _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_SHIFT) & \ 1117 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_MASK ) 1118 1119 1120 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_SET(lane_config) \ 1121 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_MASK << \ 1122 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_SHIFT ) 1123 1124 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_CLEAR(lane_config) \ 1125 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_MASK << \ 1126 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_SHIFT) ) 1127 1128 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_GET(lane_config) \ 1129 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_MASK << \ 1130 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_SHIFT) ? 1 : 0 ) 1131 1132 1133 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_SET(lane_config) \ 1134 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_MASK << \ 1135 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_SHIFT ) 1136 1137 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_CLEAR(lane_config) \ 1138 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_MASK << \ 1139 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_SHIFT) ) 1140 1141 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_GET(lane_config) \ 1142 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_MASK << \ 1143 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_SHIFT) ? 1 : 0 ) 1144 1145 1146 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_SET(lane_config) \ 1147 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_MASK << \ 1148 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_SHIFT ) 1149 1150 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_CLEAR(lane_config) \ 1151 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_MASK << \ 1152 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_SHIFT) ) 1153 1154 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_GET(lane_config) \ 1155 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_MASK << \ 1156 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_SHIFT) ? 1 : 0 ) 1157 1158 1159 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_SET(lane_config) \ 1160 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_MASK << \ 1161 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_SHIFT ) 1162 1163 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_CLEAR(lane_config) \ 1164 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_MASK << \ 1165 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_SHIFT) ) 1166 1167 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_GET(lane_config) \ 1168 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_MASK << \ 1169 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_SHIFT) ? 1 : 0 ) 1170 1171 1172 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_SET(lane_config) \ 1173 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_MASK << \ 1174 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_SHIFT ) 1175 1176 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_CLEAR(lane_config) \ 1177 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_MASK << \ 1178 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_SHIFT) ) 1179 1180 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_GET(lane_config) \ 1181 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_MASK << \ 1182 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_SHIFT) ? 1 : 0 ) 1183 1184 1185 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_SET(lane_config) \ 1186 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_MASK << \ 1187 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_SHIFT ) 1188 1189 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_CLEAR(lane_config) \ 1190 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_MASK << \ 1191 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_SHIFT) ) 1192 1193 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_GET(lane_config) \ 1194 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_MASK << \ 1195 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_SHIFT) ? 1 : 0 ) 1196 1197 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_SET(lane_config) \ 1198 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_MASK << \ 1199 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_SHIFT ) 1200 1201 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_CLEAR(lane_config) \ 1202 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_MASK << \ 1203 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_SHIFT) ) 1204 1205 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_GET(lane_config) \ 1206 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_MASK << \ 1207 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_SHIFT) ? 1 : 0 ) 1208 1209 1210 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_SET(lane_config) \ 1211 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_MASK << \ 1212 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_SHIFT ) 1213 1214 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_CLEAR(lane_config) \ 1215 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_MASK << \ 1216 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_SHIFT) ) 1217 1218 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_GET(lane_config) \ 1219 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_MASK << \ 1220 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_SHIFT) ? 1 : 0 ) 1221 1222 1223 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_SET(lane_config) \ 1224 ( lane_config |= _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_MASK << \ 1225 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_SHIFT ) 1226 1227 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_CLEAR(lane_config) \ 1228 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_MASK << \ 1229 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_SHIFT) ) 1230 1231 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_GET(lane_config) \ 1232 ( lane_config & (_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_MASK << \ 1233 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_SHIFT) ? 1 : 0 ) 1234 1235 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_SET(lane_config, channel_loss) \ 1236 ( lane_config |= channel_loss << \ 1237 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_SHIFT ) 1238 1239 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_GET(lane_config) \ 1240 ( (lane_config >> _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_SHIFT) & \ 1241 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_MASK ) 1242 1243 #define _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_CLEAR(lane_config) \ 1244 ( lane_config &= ~(_SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_MASK << \ 1245 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_SHIFT) ) 1246 1247 /* 1248 * Congestion support (HCFC) 1249 */ 1250 #define _SHR_PORT_CHANNEL_ID_PORT_BASE_SHIFT 8 1251 #define _SHR_PORT_CHANNEL_ID_PORT_BASE_MASK 0xFF 1252 #define _SHR_PORT_CHANNEL_ID_PORT_CH_SHIFT 0 1253 #define _SHR_PORT_CHANNEL_ID_PORT_CH_MASK 0xFF 1254 1255 #define _SHR_PORT_CONGESTION_MAPPING_CLEAR 0x01 1256 #define _SHR_PORT_CONGESTION_MAPPING_RX 0x02 1257 #define _SHR_PORT_CONGESTION_MAPPING_TX 0x04 1258 1259 #define _SHR_PORT_CHANNEL_ID_SET(_channel_id, _port_base, _port_ch) \ 1260 ( _channel_id = \ 1261 ( ((_port_base & _SHR_PORT_CHANNEL_ID_PORT_BASE_MASK) << \ 1262 _SHR_PORT_CHANNEL_ID_PORT_BASE_SHIFT) | \ 1263 ((_port_ch & _SHR_PORT_CHANNEL_ID_PORT_CH_MASK) << \ 1264 _SHR_PORT_CHANNEL_ID_PORT_CH_SHIFT) ) ) 1265 1266 #define _SHR_PORT_CHANNEL_ID_PORT_BASE_GET(_channel_id) \ 1267 ( (_channel_id >> _SHR_PORT_CHANNEL_ID_PORT_BASE_SHIFT) & \ 1268 _SHR_PORT_CHANNEL_ID_PORT_BASE_MASK ) 1269 1270 #define _SHR_PORT_CHANNEL_ID_PORT_CH_GET(_channel_id) \ 1271 ( (_channel_id >> _SHR_PORT_CHANNEL_ID_PORT_CH_SHIFT) & \ 1272 _SHR_PORT_CHANNEL_ID_PORT_CH_MASK ) 1273 1274 #define _SHR_PORT_PHY_TIMESYNC_CAP_MPLS (1U << 0) 1275 #define _SHR_PORT_PHY_TIMESYNC_CAP_ENHANCED_TSFIFO (1U << 1) 1276 #define _SHR_PORT_PHY_TIMESYNC_CAP_INBAND_TS (1U << 2) 1277 #define _SHR_PORT_PHY_TIMESYNC_CAP_FOLLOW_UP_ASSIST (1U << 3) 1278 #define _SHR_PORT_PHY_TIMESYNC_CAP_DELAY_RESP_ASSIST (1U << 4) 1279 #define _SHR_PORT_PHY_TIMESYNC_CAP_CAPTURE_TIMESTAMP_MSG (1U << 5) 1280 1281 #define _SHR_PORT_PHY_TIMESYNC_VALID_FLAGS (1U << 0) 1282 #define _SHR_PORT_PHY_TIMESYNC_VALID_ITPID (1U << 1) 1283 #define _SHR_PORT_PHY_TIMESYNC_VALID_OTPID (1U << 2) 1284 #define _SHR_PORT_PHY_TIMESYNC_VALID_OTPID2 (1U << 3) 1285 #define _SHR_PORT_PHY_TIMESYNC_VALID_GMODE (1U << 4) 1286 #define _SHR_PORT_PHY_TIMESYNC_VALID_FRAMESYNC_MODE (1U << 5) 1287 #define _SHR_PORT_PHY_TIMESYNC_VALID_SYNCOUT_MODE (1U << 6) 1288 #define _SHR_PORT_PHY_TIMESYNC_VALID_TS_DIVIDER (1U << 7) 1289 #define _SHR_PORT_PHY_TIMESYNC_VALID_ORIGINAL_TIMECODE (1U << 8) 1290 #define _SHR_PORT_PHY_TIMESYNC_VALID_TX_TIMESTAMP_OFFSET (1U << 9) 1291 #define _SHR_PORT_PHY_TIMESYNC_VALID_RX_TIMESTAMP_OFFSET (1U << 10) 1292 #define _SHR_PORT_PHY_TIMESYNC_VALID_TX_SYNC_MODE (1U << 11) 1293 #define _SHR_PORT_PHY_TIMESYNC_VALID_TX_DELAY_REQUEST_MODE (1U << 12) 1294 #define _SHR_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_REQUEST_MODE (1U << 13) 1295 #define _SHR_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_RESPONSE_MODE (1U << 14) 1296 #define _SHR_PORT_PHY_TIMESYNC_VALID_RX_SYNC_MODE (1U << 15) 1297 #define _SHR_PORT_PHY_TIMESYNC_VALID_RX_DELAY_REQUEST_MODE (1U << 16) 1298 #define _SHR_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_REQUEST_MODE (1U << 17) 1299 #define _SHR_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_RESPONSE_MODE (1U << 18) 1300 #define _SHR_PORT_PHY_TIMESYNC_VALID_MPLS_CONTROL (1U << 19) 1301 #define _SHR_PORT_PHY_TIMESYNC_VALID_RX_LINK_DELAY (1U << 20) 1302 #define _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_SYNC_FREQ (1U << 21) 1303 #define _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K1 (1U << 22) 1304 #define _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K2 (1U << 23) 1305 #define _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K3 (1U << 24) 1306 #define _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_LOOP_FILTER (1U << 25) 1307 #define _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE (1U << 26) 1308 #define _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE_DELTA (1U << 27) 1309 #define _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_INBAND_CONTROL (1U << 28) 1310 #define _SHR_PORT_PHY_TIMESYNC_VALID_TIMER_ADJUSTMENT (1U << 29) 1311 1312 #define _SHR_PORT_PHY_TIMESYNC_ENABLE (1U<<0) 1313 #define _SHR_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE (1U<<1) /* per port */ 1314 #define _SHR_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE (1U<<2) 1315 #define _SHR_PORT_PHY_TIMESYNC_RX_CRC_ENABLE (1U<<3) 1316 #define _SHR_PORT_PHY_TIMESYNC_8021AS_ENABLE (1U<<4) 1317 #define _SHR_PORT_PHY_TIMESYNC_L2_ENABLE (1U<<5) 1318 #define _SHR_PORT_PHY_TIMESYNC_IP4_ENABLE (1U<<6) 1319 #define _SHR_PORT_PHY_TIMESYNC_IP6_ENABLE (1U<<7) 1320 #define _SHR_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT (1U<<8) /* 0 - NCO FREQ CTRL REG, 1 - DPLL */ 1321 #define _SHR_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT_MODE (1U<<9) /* DPLL 0 - phase, 1 - freq lock */ 1322 #define _SHR_PORT_PHY_TIMESYNC_1588_ENCRYPTED_MODE (1U<<10) 1323 #define _SHR_PORT_PHY_TIMESYNC_FOLLOW_UP_ASSIST_ENABLE (1U<<11) 1324 #define _SHR_PORT_PHY_TIMESYNC_DELAY_RESP_ASSIST_ENABLE (1U<<12) 1325 #define _SHR_PORT_PHY_TIMESYNC_64BIT_TIMESTAMP_ENABLE (1U<<13) 1326 #define _SHR_PORT_PHY_TIMESYNC_1588_OVER_HSR_ENABLE (1U<<14) 1327 1328 #define _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_SYNC (1U<<15) 1329 #define _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_DELAY_REQ (1U<<16) 1330 #define _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_REQ (1U<<17) 1331 #define _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_RESP (1U<<18) 1332 #define _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_SYNC (1U<<19) 1333 #define _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_DELAY_REQ (1U<<20) 1334 #define _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_REQ (1U<<21) 1335 #define _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_RESP (1U<<22) 1336 #define _SHR_PORT_PHY_TIMESYNC_ONE_STEP_ENABLE (1U<<23) 1337 1338 #define _SHR_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_CHECK (1U << 0) 1339 #define _SHR_PORT_PHY_TIMESYNC_INBAND_SYNC_ENABLE (1U << 1) 1340 #define _SHR_PORT_PHY_TIMESYNC_INBAND_DELAY_RQ_ENABLE (1U << 2) 1341 #define _SHR_PORT_PHY_TIMESYNC_INBAND_PDELAY_RQ_ENABLE (1U << 3) 1342 #define _SHR_PORT_PHY_TIMESYNC_INBAND_PDELAY_RESP_ENABLE (1U << 4) 1343 #define _SHR_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_UPDATE (1U << 5) 1344 #define _SHR_PORT_PHY_TIMESYNC_INBAND_CAP_SRC_PORT_CLK_ID (1U << 6) 1345 #define _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_VLAN_ID (1U << 7) 1346 #define _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_SRC_PORT_NUM (1U << 8) 1347 #define _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_MAC_ADDR (1U << 9) 1348 #define _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_IP_ADDR (1U << 10) 1349 #define _SHR_PORT_PHY_TIMESYNC_INBAND_FOLLOW_UP_ASSIST (1U << 11) 1350 #define _SHR_PORT_PHY_TIMESYNC_INBAND_DELAY_RESP_ASSIST (1U << 12) 1351 #define _SHR_PORT_PHY_TIMESYNC_INBAND_TIMER_MODE_SELECT (1U << 13) 1352 1353 /* Base time structure. */ 1354 typedef struct _shr_time_spec_s { 1355 uint8 isnegative; /* Sign identifier. */ 1356 uint64 seconds; /* Seconds absolute value. */ 1357 uint32 nanoseconds; /* Nanoseconds absolute value. */ 1358 } _shr_time_spec_t; 1359 1360 /* Actions on Egress event messages */ 1361 typedef enum _shr_port_phy_timesync_event_message_egress_mode_e { 1362 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_NONE = 0, 1363 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_UPDATE_CORRECTIONFIELD = 1, 1364 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_REPLACE_CORRECTIONFIELD_ORIGIN = 2, 1365 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_CAPTURE_TIMESTAMP = 3 1366 } _shr_port_phy_timesync_event_message_egress_mode_t; 1367 1368 /* Actions on ingress event messages */ 1369 typedef enum _shr_port_phy_timesync_event_message_ingress_mode_e { 1370 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_NONE = 0, 1371 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_UPDATE_CORRECTIONFIELD = 1, 1372 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP = 2, 1373 _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_DELAYTIME = 3 1374 } _shr_port_phy_timesync_event_message_ingress_mode_t; 1375 1376 /* Global mode actions */ 1377 typedef enum _shr_port_phy_timesync_global_mode_e { 1378 _SHR_PORT_PHY_TIMESYNC_MODE_FREE = 0, 1379 _SHR_PORT_PHY_TIMESYNC_MODE_SYNCIN = 1, 1380 _SHR_PORT_PHY_TIMESYNC_MODE_CPU = 2 1381 } _shr_port_phy_timesync_global_mode_t; 1382 1383 1384 typedef enum _shr_port_phy_timesync_framesync_mode_s 1385 { 1386 _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_NONE = 0, 1387 _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN0 = 1, 1388 _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN1 = 2, 1389 _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCOUT = 3, 1390 _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_CPU = 4 1391 } _shr_port_phy_timesync_framesync_mode_t; 1392 1393 typedef enum _shr_port_pcs_e { 1394 _SHR_PORT_PCS_8B9BLFEC = 0, 1395 _SHR_PORT_PCS_8B10B = 1, 1396 _SHR_PORT_PCS_64B66BFEC = 2, 1397 _SHR_PORT_PCS_64B66BBEC = 3, 1398 _SHR_PORT_PCS_64B66B = 4, 1399 _SHR_PORT_PCS_64B66B_RS_FEC = 5, 1400 _SHR_PORT_PCS_64B66B_LOW_LATENCY_RS_FEC = 6, 1401 _SHR_PORT_PCS_64B66B_15T_RS_FEC = 7, 1402 _SHR_PORT_PCS_64B66B_15T_LOW_LATENCY_RS_FEC = 8, 1403 _SHR_PORT_PCS_COUNT = 9, 1404 _SHR_PORT_PCS_UNKNOWN = -1 1405 } _shr_port_pcs_t; 1406 1407 1408 typedef struct _shr_port_phy_framesync_s { 1409 1410 _shr_port_phy_timesync_framesync_mode_t mode; 1411 uint32 length_threshold; 1412 uint32 event_offset; 1413 1414 } _shr_port_phy_timesync_framesync_t; 1415 1416 1417 typedef enum _shr_port_phy_timesync_syncout_mode_s 1418 { 1419 _SHR_PORT_PHY_TIMESYNC_SYNCOUT_DISABLE = 0, 1420 _SHR_PORT_PHY_TIMESYNC_SYNCOUT_ONE_TIME = 1, 1421 _SHR_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN = 2, 1422 _SHR_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN_WITH_SYNC = 3 1423 } _shr_port_phy_timesync_syncout_mode_t; 1424 1425 typedef struct _shr_port_phy_timesync_syncout_s { 1426 1427 _shr_port_phy_timesync_syncout_mode_t mode; 1428 uint16 pulse_1_length; /* in nanoseconds */ 1429 uint16 pulse_2_length; /* in nanoseconds */ 1430 uint32 interval; /* in nanoseconds */ 1431 uint64 syncout_ts; 1432 1433 } _shr_port_phy_timesync_syncout_t; 1434 1435 1436 /* mpls_label_flags */ 1437 #define _SHR_PORT_PHY_TIMESYNC_MPLS_LABEL_IN (1U<<0) 1438 #define _SHR_PORT_PHY_TIMESYNC_MPLS_LABEL_OUT (1U<<1) 1439 1440 typedef struct _shr_port_phy_timesync_mpls_label_s { 1441 1442 uint32 value; /* bits [19:0] */ 1443 uint32 mask; /* bits [19:0] */ 1444 uint32 flags; /* label flags */ 1445 1446 } _shr_port_phy_timesync_mpls_label_t; 1447 1448 1449 /* mpls_flags */ 1450 #define _SHR_PORT_PHY_TIMESYNC_MPLS_ENABLE (1U<<0) 1451 #define _SHR_PORT_PHY_TIMESYNC_MPLS_ENTROPY_ENABLE (1U<<1) 1452 #define _SHR_PORT_PHY_TIMESYNC_MPLS_SPECIAL_LABEL_ENABLE (1U<<2) 1453 #define _SHR_PORT_PHY_TIMESYNC_MPLS_CONTROL_WORD_ENABLE (1U<<3) 1454 1455 typedef struct _shr_port_phy_timesync_mpls_control_s { 1456 uint32 flags; 1457 uint32 special_label; /* bits [19:0] */ 1458 _shr_port_phy_timesync_mpls_label_t labels[10]; /* Timesync MPLS labels */ 1459 int size; /* Number of elements in label array */ 1460 1461 } _shr_port_phy_timesync_mpls_control_t; 1462 1463 #define _SHR_PORT_PHY_TIMESYNC_TN_LOAD (1U<<23) 1464 #define _SHR_PORT_PHY_TIMESYNC_TN_ALWAYS_LOAD (1U<<22) 1465 #define _SHR_PORT_PHY_TIMESYNC_TIMECODE_LOAD (1U<<21) 1466 #define _SHR_PORT_PHY_TIMESYNC_TIMECODE_ALWAYS_LOAD (1U<<20) 1467 #define _SHR_PORT_PHY_TIMESYNC_SYNCOUT_LOAD (1U<<19) 1468 #define _SHR_PORT_PHY_TIMESYNC_SYNCOUT_ALWAYS_LOAD (1U<<18) 1469 #define _SHR_PORT_PHY_TIMESYNC_NCO_DIVIDER_LOAD (1U<<17) 1470 #define _SHR_PORT_PHY_TIMESYNC_NCO_DIVIDER_ALWAYS_LOAD (1U<<16) 1471 #define _SHR_PORT_PHY_TIMESYNC_LOCAL_TIME_LOAD (1U<<15) 1472 #define _SHR_PORT_PHY_TIMESYNC_LOCAL_TIME_ALWAYS_LOAD (1U<<14) 1473 #define _SHR_PORT_PHY_TIMESYNC_NCO_ADDEND_LOAD (1U<<13) 1474 #define _SHR_PORT_PHY_TIMESYNC_NCO_ADDEND_ALWAYS_LOAD (1U<<12) 1475 #define _SHR_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_LOAD (1U<<11) 1476 #define _SHR_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_ALWAYS_LOAD (1U<<10) 1477 #define _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_LOAD (1U<<9) 1478 #define _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_ALWAYS_LOAD (1U<<8) 1479 #define _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_LOAD (1U<<7) 1480 #define _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_ALWAYS_LOAD (1U<<6) 1481 #define _SHR_PORT_PHY_TIMESYNC_DPLL_K3_LOAD (1U<<5) 1482 #define _SHR_PORT_PHY_TIMESYNC_DPLL_K3_ALWAYS_LOAD (1U<<4) 1483 #define _SHR_PORT_PHY_TIMESYNC_DPLL_K2_LOAD (1U<<3) 1484 #define _SHR_PORT_PHY_TIMESYNC_DPLL_K2_ALWAYS_LOAD (1U<<2) 1485 #define _SHR_PORT_PHY_TIMESYNC_DPLL_K1_LOAD (1U<<1) 1486 #define _SHR_PORT_PHY_TIMESYNC_DPLL_K1_ALWAYS_LOAD (1U<<0) 1487 1488 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT (1U<<1) 1489 1490 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_0 COMPILER_64_INIT((1U<<0),0) 1491 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_1 COMPILER_64_INIT((1U<<1),0) 1492 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_2 COMPILER_64_INIT((1U<<2),0) 1493 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_3 COMPILER_64_INIT((1U<<3),0) 1494 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_4 COMPILER_64_INIT((1U<<4),0) 1495 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_5 COMPILER_64_INIT((1U<<5),0) 1496 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_6 COMPILER_64_INIT((1U<<6),0) 1497 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_7 COMPILER_64_INIT((1U<<7),0) 1498 1499 #define _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT (1U<<0) 1500 1501 #define _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_MASK (1U<<1) 1502 #define _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT_MASK (1U<<0) 1503 1504 /* Fast call actions */ 1505 typedef enum _shr_port_control_timesync_e { 1506 _SHR_PORT_CONTROL_PHY_TIMESYNC_CAPTURE_TIMESTAMP = 0, 1507 _SHR_PORT_CONTROL_PHY_TIMESYNC_HEARTBEAT_TIMESTAMP = 1, 1508 _SHR_PORT_CONTROL_PHY_TIMESYNC_NCOADDEND = 2, 1509 _SHR_PORT_CONTROL_PHY_TIMESYNC_FRAMESYNC = 3, 1510 _SHR_PORT_CONTROL_PHY_TIMESYNC_LOCAL_TIME = 4, 1511 _SHR_PORT_CONTROL_PHY_TIMESYNC_LOAD_CONTROL = 5, 1512 _SHR_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT = 6, 1513 _SHR_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT_MASK = 7, 1514 _SHR_PORT_CONTROL_PHY_TIMESYNC_TX_TIMESTAMP_OFFSET = 8, 1515 _SHR_PORT_CONTROL_PHY_TIMESYNC_RX_TIMESTAMP_OFFSET = 9, 1516 _SHR_PORT_CONTROL_PHY_TIMESYNC_NSE_TIME_OFFSET = 10, 1517 _SHR_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_OFFSET = 11, 1518 _SHR_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_ADJUST = 12, 1519 _SHR_PORT_CONTROL_PHY_TIMESYNC_ONE_STEP_ENABLE = 13 1520 } _shr_port_control_phy_timesync_t; 1521 1522 /*AM norm modes for aggregated port speeds*/ 1523 typedef enum _shr_port_phy_timesync_compensation_mode_e { 1524 _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_NONE = 0, 1525 _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_EARLIEST_LANE = 1, 1526 _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_LATEST_LANE = 2 1527 } _shr_port_phy_timesync_compensation_mode_t; 1528 1529 typedef enum _shr_port_phy_timesync_msg_e { 1530 _SHR_PORT_PHY_TIMESYNC_MSG_SYNC = 0, 1531 _SHR_PORT_PHY_TIMESYNC_MSG_DELAY_REQ = 1, 1532 _SHR_PORT_PHY_TIMESYNC_MSG_PDELAY_REQ = 2, 1533 _SHR_PORT_PHY_TIMESYNC_MSG_PDELAY_RESP = 3 1534 } _shr_port_phy_timesync_msg_t; 1535 1536 typedef enum _shr_port_phy_timesync_prot_e { 1537 _SHR_PORT_PHY_TIMESYNC_PROT_LAYER2 = 0, 1538 _SHR_PORT_PHY_TIMESYNC_PROT_IPV4_UDP = 1, 1539 _SHR_PORT_PHY_TIMESYNC_PROT_IPV6_UDP = 2 1540 } _shr_port_phy_timesync_prot_t; 1541 1542 typedef enum _shr_port_phy_timesync_dir_e { 1543 _SHR_PORT_PHY_TIMESYNC_DIR_EGRESS = 0, 1544 _SHR_PORT_PHY_TIMESYNC_DIR_INGRESS = 1 1545 } _shr_port_phy_timesync_dir_t; 1546 1547 typedef struct _shr_port_phy_timesync_timer_adjust_s { 1548 _shr_port_phy_timesync_timer_mode_t mode; 1549 int delta; 1550 } _shr_port_phy_timesync_timer_adjust_t; 1551 1552 typedef struct _shr_port_phy_timesync_inband_control_s { 1553 uint32 flags; 1554 int resv0_id; 1555 _shr_port_phy_timesync_timer_mode_t timer_mode; 1556 } _shr_port_phy_timesync_inband_control_t; 1557 1558 /* Base timesync configuration type. */ 1559 typedef struct _shr_port_phy_timesync_enhanced_capture_s { 1560 _shr_port_phy_timesync_msg_t msg_type; 1561 _shr_port_phy_timesync_prot_t protocol; 1562 _shr_port_phy_timesync_dir_t direction; 1563 int seq_id; 1564 uint32 domain; 1565 uint64 timestamp; 1566 uint64 source_port_identity; 1567 uint16 source_port; 1568 uint16 vlan_id; 1569 } _shr_port_phy_timesync_enhanced_capture_t; 1570 1571 /* Base timesync configuration type. */ 1572 typedef struct _shr_port_phy_timesync_config_s { 1573 uint32 capabilities; /* Flags BCM_PORT_PHY_TIMESYNC_CAP_* */ 1574 uint32 validity_mask; /* Flags BCM_PORT_PHY_TIMESYNC_VALID_* */ 1575 uint32 flags; /* Flags BCM_PORT_PHY_TIMESYNC_* */ 1576 uint16 itpid; /* 1588 inner tag */ 1577 uint16 otpid; /* 1588 outer tag */ 1578 uint16 otpid2; /* 1588 outer tag 2 */ 1579 _shr_port_phy_timesync_timer_adjust_t timer_adjust; 1580 _shr_port_phy_timesync_inband_control_t inband_control; /* Inband TS control */ 1581 _shr_port_phy_timesync_global_mode_t gmode; /* Global mode */ 1582 _shr_port_phy_timesync_framesync_t framesync; 1583 _shr_port_phy_timesync_syncout_t syncout; 1584 uint16 ts_divider; 1585 _shr_time_spec_t original_timecode; /* Original timecode to be inserted */ 1586 uint32 tx_timestamp_offset; /* TX AFE delay in ns - per port */ 1587 uint32 rx_timestamp_offset; /* RX AFE delay in ns - per port */ 1588 uint32 rx_link_delay; 1589 _shr_port_phy_timesync_event_message_egress_mode_t tx_sync_mode; /* sync */ 1590 _shr_port_phy_timesync_event_message_egress_mode_t tx_delay_request_mode; /* delay request */ 1591 _shr_port_phy_timesync_event_message_egress_mode_t tx_pdelay_request_mode; /* pdelay request */ 1592 _shr_port_phy_timesync_event_message_egress_mode_t tx_pdelay_response_mode; /* pdelay response */ 1593 _shr_port_phy_timesync_event_message_ingress_mode_t rx_sync_mode; /* sync */ 1594 _shr_port_phy_timesync_event_message_ingress_mode_t rx_delay_request_mode; /* delay request */ 1595 _shr_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_request_mode; /* pdelay request */ 1596 _shr_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_response_mode; /* pdelay response */ 1597 _shr_port_phy_timesync_mpls_control_t mpls_control; 1598 uint32 sync_freq; /* sync frequency */ 1599 uint16 phy_1588_dpll_k1; 1600 uint16 phy_1588_dpll_k2; 1601 uint16 phy_1588_dpll_k3; 1602 uint64 phy_1588_dpll_loop_filter; /* loop filter */ 1603 uint64 phy_1588_dpll_ref_phase; /* ref phase */ 1604 uint32 phy_1588_dpll_ref_phase_delta; /* ref phase delta */ 1605 } _shr_port_phy_timesync_config_t; 1606 1607 /* timestamp adjust */ 1608 typedef struct _shr_port_timestamp_adjust_s { 1609 uint32 osts_adjust; /* MAC pipeline delay in OSTS */ 1610 uint32 tsts_adjust; /* Delay of TS timer from TS clk to TSC_Clk domain */ 1611 } _shr_port_timestamp_adjust_t; 1612 1613 /* _shr_port_phy_timesync_config_set */ 1614 extern int _shr_port_phy_timesync_config_set( 1615 int unit, 1616 _shr_port_t port, 1617 _shr_port_phy_timesync_config_t *conf); 1618 1619 /* _shr_port_phy_timesync_config_get */ 1620 extern int _shr_port_phy_timesync_config_get( 1621 int unit, 1622 _shr_port_t port, 1623 _shr_port_phy_timesync_config_t *conf); 1624 1625 /* _shr_port_control_phy_timesync_set */ 1626 extern int _shr_port_control_phy_timesync_set( 1627 int unit, 1628 _shr_port_t port, 1629 _shr_port_control_phy_timesync_t type, 1630 uint64 value); 1631 1632 /* _shr_port_control_phy_timesync_get */ 1633 extern int _shr_port_control_phy_timesync_get( 1634 int unit, 1635 _shr_port_t port, 1636 _shr_port_control_phy_timesync_t type, 1637 uint64 *value); 1638 1639 /* _shr_port_control_phy_timesync_enhanced_capture_get */ 1640 extern int _shr_port_control_phy_timesync_enhanced_capture_get( 1641 int unit, 1642 _shr_port_t port, 1643 _shr_port_phy_timesync_enhanced_capture_t *value); 1644 1645 /*************************** 1646 * OAM related definitions 1647 */ 1648 1649 #define _SHR_PORT_PHY_OAM_MAC_CHECK_ENABLE (1U << 0) /* Enable MAC check for 1650 Delay Measurement */ 1651 #define _SHR_PORT_PHY_OAM_CONTROL_WORD_ENABLE (1U << 1) /* Enable Control Word 1652 for Delay Measurement */ 1653 #define _SHR_PORT_PHY_OAM_DM_ENTROPY_ENABLE (1U << 2) /* Enable entropy for 1654 Delay Measurement */ 1655 #define _SHR_PORT_PHY_OAM_DM_TS_FORMAT (1U << 3) /* Select timestamp 1656 format PTP(0)/NTP(1) 1657 for Delay Measurement */ 1658 1659 /* Port controls for phy OAM */ 1660 typedef enum _shr_port_control_phy_oam_e { 1661 _SHR_PORT_CONTROL_PHY_OAM_DM_TX_ETHERTYPE = 1, /* OAM Delay measurement Tx Ethertype */ 1662 _SHR_PORT_CONTROL_PHY_OAM_DM_RX_ETHERTYPE = 2, /* OAM Delay measurement Rx Ethertype */ 1663 _SHR_PORT_CONTROL_PHY_OAM_DM_TX_PORT_MAC_ADDRESS_INDEX = 3, /* Index to select the MAC address. Use 1664 index of 1 to select MacAddress1, 1665 index of 2 for MacAddress2 and so 1666 forth. */ 1667 _SHR_PORT_CONTROL_PHY_OAM_DM_RX_PORT_MAC_ADDRESS_INDEX = 4, /* Index to select the MAC address. Use 1668 index of 1 to select MacAddress1, 1669 index of 2 for MacAddress2 and so 1670 forth. */ 1671 _SHR_PORT_CONTROL_PHY_OAM_DM_MAC_ADDRESS_1 = 5, /* OAM Delay measurement MAC address 1. 1672 There can be multiple MAC address to 1673 choose from in a PHY depending upon 1674 the design */ 1675 _SHR_PORT_CONTROL_PHY_OAM_DM_MAC_ADDRESS_2 = 6, /* OAM Delay measurement MAC address 2. 1676 There can be multiple MAC address to 1677 choose from in a PHY depending upon 1678 the design */ 1679 _SHR_PORT_CONTROL_PHY_OAM_DM_MAC_ADDRESS_3 = 7/* OAM Delay measurement MAC address 3. 1680 There can be multiple MAC address to 1681 choose from in a PHY depending upon 1682 the design */ 1683 } _shr_port_control_phy_oam_t; 1684 1685 /* Phy OAM Delay Measurement Modes */ 1686 typedef enum _shr_port_config_phy_oam_dm_mode_e { 1687 _SHR_PORT_CONFIG_PHY_OAM_DM_Y1731 = 1, /* OAM Delay measurement Y.7131 Mode */ 1688 _SHR_PORT_CONFIG_PHY_OAM_DM_BHH = 2, /* OAM Delay measurement BHH Mode */ 1689 _SHR_PORT_CONFIG_PHY_OAM_DM_IETF = 3 /* OAM Delay measurement IETF Mode */ 1690 } _shr_port_config_phy_oam_dm_mode_t; 1691 1692 /* Phy OAM Delay measurement config type. */ 1693 typedef struct _shr_port_config_phy_oam_dm_s { 1694 uint32 flags; /* OAM Delay Measurement config flags */ 1695 _shr_port_config_phy_oam_dm_mode_t mode; /* OAM Delay Measurement mode Y.1731, 1696 BHH or IETF */ 1697 } _shr_port_config_phy_oam_dm_t; 1698 1699 /* Phy OAM config type. */ 1700 typedef struct _shr_port_config_phy_oam_s { 1701 _shr_port_config_phy_oam_dm_t tx_dm_config; /* OAM delay measurement config for Tx */ 1702 _shr_port_config_phy_oam_dm_t rx_dm_config; /* OAM delay measurement config for Rx */ 1703 } _shr_port_config_phy_oam_t; 1704 1705 #ifndef BCM_HIDE_DISPATCHABLE 1706 1707 /* _shr_port_config_phy_oam_set */ 1708 extern int _shr_port_config_phy_oam_set( 1709 int unit, 1710 _shr_port_t port, 1711 _shr_port_config_phy_oam_t *conf); 1712 1713 /* _shr_port_config_phy_oam_get */ 1714 extern int _shr_port_config_phy_oam_get( 1715 int unit, 1716 _shr_port_t port, 1717 _shr_port_config_phy_oam_t *conf); 1718 1719 /* _shr_port_control_phy_oam_set */ 1720 extern int _shr_port_control_phy_oam_set( 1721 int unit, 1722 _shr_port_t port, 1723 _shr_port_control_phy_oam_t type, 1724 uint64 value); 1725 1726 /* _shr_port_control_phy_oam_get */ 1727 extern int _shr_port_control_phy_oam_get( 1728 int unit, 1729 _shr_port_t port, 1730 _shr_port_control_phy_oam_t type, 1731 uint64 *value); 1732 1733 #endif /* BCM_HIDE_DISPATCHABLE */ 1734 1735 typedef enum _shr_port_phy_tx_tap_mode_e { 1736 _SHR_PORT_PHY_TX_TAP_MODE_3_TAP = 0, 1737 _SHR_PORT_PHY_TX_TAP_MODE_6_TAP = 1 1738 } _shr_port_phy_tx_tap_mode_t; 1739 1740 typedef enum _shr_port_phy_signalling_mode_t { 1741 _SHR_PORT_PHY_SIGNALLING_MODE_NRZ = 0, 1742 _SHR_PORT_PHY_SIGNALLING_MODE_PAM4 = 1 1743 } _shr_port_phy_signalling_mode_t; 1744 1745 typedef struct _shr_port_phy_tx_s { 1746 int pre2; 1747 int pre; 1748 int main; 1749 int post; 1750 int post2; 1751 int post3; 1752 _shr_port_phy_tx_tap_mode_t tx_tap_mode; 1753 _shr_port_phy_signalling_mode_t signalling_mode; 1754 } _shr_port_phy_tx_t; 1755 1756 typedef struct _shr_port_rlm_config_s { 1757 int is_initiator; 1758 uint32 active_lane_bit_map; 1759 } _shr_port_rlm_config_t; 1760 #endif /* !_SHR_PORT_H */