phyreg.h (3158B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * This file defines common PHY register definition. 8 * 9 * Its contents are not used directly by applications; it is used only 10 * by header files of parent APIs which need to define PHY register definition. 11 */ 12 13 #ifndef _SHR_PHYREG_H 14 #define _SHR_PHYREG_H 15 16 #define _SHR_PORT_PHY_PHYMOD_IBLK_FORCE_LANE 0x8000000 17 #define _SHR_PORT_PHY_PHYMOD_ACCESS_FLAGS_SHIFT 24 18 19 #define _SHR_PORT_PHT_PHYMOD_FORCE_LANE_SET(_addr, _lane) \ 20 _addr = ((_addr & ~(0x7 << _SHR_PORT_PHY_PHYMOD_ACCESS_FLAGS_SHIFT)) | \ 21 _SHR_PORT_PHY_PHYMOD_IBLK_FORCE_LANE | \ 22 ((_lane & 0x7) << _SHR_PORT_PHY_PHYMOD_ACCESS_FLAGS_SHIFT)) 23 24 #define _SHR_PORT_PHY_SHAD_RETRY_CNT (50) 25 26 #define _SHR_PORT_PHY_INTERNAL 0x00000001 27 #define _SHR_PORT_PHY_NOMAP 0x00000002 28 #define _SHR_PORT_PHY_CLAUSE45 0x00000004 29 #define _SHR_PORT_PHY_I2C_DATA8 0x00000008 30 #define _SHR_PORT_PHY_I2C_DATA16 0x00000010 31 #define _SHR_PORT_PHY_PVT_DATA 0x00000020 32 #define _SHR_PORT_PHY_REG_RDB 0x02000000 33 #define _SHR_PORT_PHY_REG_MACSEC 0x04000000 34 #define _SHR_PORT_PHY_REG64_DATA_HI32 0x08000000 35 36 #define _SHR_PORT_PHY_CLAUSE45_ADDR(_devad, _regad) \ 37 ((((_devad) & 0x3F) << 16) | \ 38 ((_regad) & 0xFFFF)) 39 #define _SHR_PORT_PHY_CLAUSE45_DEVAD(_reg_addr) \ 40 (((_reg_addr) >> 16) & 0x3F) 41 #define _SHR_PORT_PHY_CLAUSE45_REGAD(_reg_addr) \ 42 ((_reg_addr) & 0xFFFF) 43 #define _SHR_PORT_PHY_I2C_ADDR(_devad, _regad) \ 44 ((((_devad) & 0xFF) << 16) | \ 45 ((_regad) & 0xFFFF)) 46 #define _SHR_PORT_PHY_I2C_DEVAD(_reg_addr) \ 47 (((_reg_addr) >> 16) & 0xFF) 48 #define _SHR_PORT_PHY_I2C_REGAD(_reg_addr) \ 49 ((_reg_addr) & 0xFFFF) 50 51 #define _SHR_PORT_PHY_REG_NO_RETRY_ACCESS 0x08000000 52 #define _SHR_PORT_PHY_REG_RESERVE_ACCESS 0x20000000 53 #define _SHR_PORT_PHY_REG_1000X 0x40000000 54 #define _SHR_PORT_PHY_REG_INDIRECT 0x80000000 55 #define _SHR_PORT_PHY_REG_DUMMY_ACCESS 0x10000000 56 57 #define _SHR_PORT_PHY_REG_FLAGS_MASK 0xFF000000 58 #define _SHR_PORT_PHY_REG_BANK_MASK 0x0000FFFF 59 #define _SHR_PORT_PHY_REG_ADDR_MASK 0x000000FF 60 61 #define _SHR_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_bank, _reg_addr) \ 62 ((((_flags) | _SHR_PORT_PHY_REG_INDIRECT) & \ 63 _SHR_PORT_PHY_REG_FLAGS_MASK) | \ 64 (((_reg_bank) & _SHR_PORT_PHY_REG_BANK_MASK) << 8) | \ 65 ((_reg_addr) & _SHR_PORT_PHY_REG_ADDR_MASK)) 66 #define _SHR_PORT_PHY_REG_FLAGS(_reg_addr) \ 67 ((_reg_addr) & _SHR_PORT_PHY_REG_FLAGS_MASK) 68 #define _SHR_PORT_PHY_REG_BANK(_reg_addr) \ 69 (((_reg_addr) >> 8) & _SHR_PORT_PHY_REG_BANK_MASK) 70 #define _SHR_PORT_PHY_REG_ADDR(_reg_addr) \ 71 ((_reg_addr) & _SHR_PORT_PHY_REG_ADDR_MASK) 72 73 #endif /* !_SHR_PHYREG_H */