fcmap.h (24392B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 */ 7 8 #ifndef _SHR_BFCMAP_H 9 #define _SHR_BFCMAP_H 10 11 #ifdef INCLUDE_FCMAP 12 #include <sal/types.h> 13 #include <bfcmap_types.h> 14 #include <bfcmap_io.h> 15 #include <bfcmap_err.h> 16 17 18 typedef uint32 _shr_bfcmap_dev_addr_t; 19 20 /* 21 * Attach console/debug functions to BFCMAP module. 22 */ 23 typedef bprint_fn _shr_bfcmap_print_fn; 24 25 /* 26 * Enum for traffic direction. 27 * Ingress traffic is defined as the one coming from the Line side. 28 * Egress traffic is defined as coming from the switch/ASIC side. 29 */ 30 typedef enum { 31 _SHR_BFCMAP_DIR_EGRESS = 0, 32 _SHR_BFCMAP_DIR_INGRESS = 1, 33 } _shr_bfcmap_dir_t; 34 35 /* 36 * Identifiers for BFCMAP core type. 37 */ 38 typedef enum { 39 _SHR_BFCMAP_CORE_UNKNOWN = 0, 40 _SHR_BFCMAP_CORE_OCTAL_GIG = 1, /* BCM54580, BCM54584, BCM54585 */ 41 _SHR_BFCMAP_CORE_BCM5458X = 2, 42 _SHR_BFCMAP_CORE_BCM5458X_B0 = 3, 43 _SHR_BFCMAP_CORE_BCM8729 = 4, /* BCM8729 */ 44 _SHR_BFCMAP_CORE_BCM8483X = 5, /* BCM8483X */ 45 _SHR_BFCMAP_CORE_BCM5438X = 6, /* BCM5438X */ 46 _SHR_BFCMAP_CORE_BCM84756 = 7, /* BCM84756 */ 47 _SHR_BFCMAP_CORE_BCM84756_C0 = 8, /* BCM84756_C0 */ 48 _SHR_BFCMAP_CORE_BCM88060_A0 = 9, /* BCM88060_A0 */ 49 _SHR_BFCMAP_CORE_BCM88061_A0 = 10 /* BCM88061_A0 */ 50 } _shr_bfcmap_core_t; 51 52 53 /* Port Mode */ 54 typedef enum { 55 _SHR_BFCMAP_FCOE_TO_FC_MODE = 0, 56 _SHR_BFCMAP_FCOE_TO_FCOE_MODE = 1, 57 } _shr_bfcmap_port_mode_t; 58 59 /* Port Speed */ 60 typedef enum { 61 _SHR_BFCMAP_PORT_SPEED_AN = 0, 62 _SHR_BFCMAP_PORT_SPEED_2GBPS = 1, 63 _SHR_BFCMAP_PORT_SPEED_4GBPS = 2, 64 _SHR_BFCMAP_PORT_SPEED_8GBPS = 3, 65 _SHR_BFCMAP_PORT_SPEED_16GBPS = 4, 66 _SHR_BFCMAP_PORT_SPEED_32GBPS = 5, 67 _SHR_BFCMAP_PORT_SPEED_AN_2GBPS = 6, 68 _SHR_BFCMAP_PORT_SPEED_AN_4GBPS = 7, 69 _SHR_BFCMAP_PORT_SPEED_AN_8GBPS = 8, 70 _SHR_BFCMAP_PORT_SPEED_AN_16GBPS = 9, 71 _SHR_BFCMAP_PORT_SPEED_AN_32GBPS = 10, 72 _SHR_BFCMAP_PORT_SPEED_MAX_COUNT 73 } _shr_bfcmap_port_speed_t; 74 75 /* Port State */ 76 typedef enum { 77 _SHR_BFCMAP_PORT_STATE_INIT = 0, /* INITIALIZATION STATE */ 78 _SHR_BFCMAP_PORT_STATE_RESET = 1, /* PORT IN RESETING STATE */ 79 _SHR_BFCMAP_PORT_STATE_ACTIVE = 2, /* PORT IN ACTIVE(LINK UP) STATE */ 80 _SHR_BFCMAP_PORT_STATE_LINKDOWN = 3, /* PORT IN LINK DOWN STATE */ 81 _SHR_BFCMAP_PORT_STATE_DISABLE = 4, /* PORT IN DISABLED STATE */ 82 _SHR_BFCMAP_PORT_STATE_MAX_COUNT 83 } _shr_bfcmap_port_state_t; 84 85 86 typedef uint8 _shr_bmac_addr_t[6]; 87 88 89 typedef enum { 90 _SHR_BFCMAP_ENCAP_FCOE_FPMA = 0,/* FPMA, use prefix and Node 91 ID to construct FCoE MAC Address */ 92 _SHR_BFCMAP_ENCAP_FCOE_ETH_ADDRESS_NULL = 1,/* Null address for FCOE MAC */ 93 _SHR_BFCMAP_ENCAP_FCOE_ETH_ADDRESS_USER = 2/* User Provided Address */ 94 } _shr_bfcmap_encap_mac_address_t; 95 96 97 typedef enum { 98 _SHR_BFCMAP_8G_FW_ON_ACTIVE_ARBFF = 0, /* Use ARBFF as fillword on 8G Active state */ 99 _SHR_BFCMAP_8G_FW_ON_ACTIVE_IDLE = 1 /* Use IDLE as fillword on 8G Active state */ 100 } _shr_bfcmap_8g_fw_on_active_t; 101 102 typedef enum { 103 _SHR_BFCMAP_MAP_TABLE_INPUT_VID = 0, /* Use VID as input for FCMAPPER */ 104 _SHR_BFCMAP_MAP_TABLE_INPUT_VFID = 1 /* Use VFID as input for FCMAPPER */ 105 } _shr_bfcmap_map_table_input_t; 106 107 typedef enum { 108 _SHR_BFCMAP_FC_CRC_MODE_NORMAL = 0, /* normal mode */ 109 _SHR_BFCMAP_FC_CRC_MODE_NO_CRC_CHECK = 1 /* no CRC check mode */ 110 } _shr_bfcmap_fc_crc_mode_t; 111 112 typedef enum { 113 _SHR_BFCMAP_VFTHDR_PRESERVE = 0, /* preserve vfthdr */ 114 _SHR_BFCMAP_VFTHDR_INSERT = 1, /* insert vfthdr */ 115 _SHR_BFCMAP_VFTHDR_DELETE = 2 /* delete vfthdr */ 116 } _shr_bfcmap_vfthdr_proc_mode_t; 117 118 typedef enum { 119 _SHR_BFCMAP_VLANTAG_PRESERVE = 0, /* preserve vlantag */ 120 _SHR_BFCMAP_VLANTAG_INSERT = 1, /* insert vlantag */ 121 _SHR_BFCMAP_VLANTAG_DELETE = 2 /* delete vlantag */ 122 } _shr_bfcmap_vlantag_proc_mode_t; 123 124 typedef enum { 125 _SHR_BFCMAP_VFID_MACSRC_PASSTHRU = 0, /* passthru the vfid */ 126 _SHR_BFCMAP_VFID_MACSRC_PORT_DEFAULT = 1, /* use port default vfid */ 127 _SHR_BFCMAP_VFID_MACSRC_VID = 2, /* use vid if exists*/ 128 _SHR_BFCMAP_VFID_MACSRC_MAPPER = 3, /* use FCMAPER ouput if exists */ 129 _SHR_BFCMAP_VFID_MACSRC_DISABLE = 4 /* disable processing */ 130 } _shr_bfcmap_vfid_mapsrc_t; 131 132 typedef enum { 133 _SHR_BFCMAP_VID_MACSRC_VFID = 0, /* use vfid if exists*/ 134 _SHR_BFCMAP_VID_MACSRC_PASSTHRU = 1, /* passthru the vid */ 135 _SHR_BFCMAP_VID_MACSRC_PORT_DEFAULT = 2, /* use port default vid */ 136 _SHR_BFCMAP_VID_MACSRC_MAPPER = 3 /* use FCMAPER ouput if exists */ 137 } _shr_bfcmap_vid_mapsrc_t; 138 139 140 typedef enum { 141 _SHR_BFCMAP_VLAN_PRI_MAP_MODE_PORT_DEFAULT = 0, /* use port default priority */ 142 _SHR_BFCMAP_VLAN_PRI_MAP_MODE_PASSTHRU = 1, /* passthru if exists, else use port default priority */ 143 } _shr_bfcmap_vlan_pri_map_mode_t; 144 145 typedef enum { 146 _SHR_BFCMAP_HOPCNT_CHECK_MODE_NO_CHK = 0, /* no check on hop count at ingress */ 147 _SHR_BFCMAP_HOPCNT_CHECK_MODE_FAIL_DROP = 1, /* discard on hop count == 1 */ 148 _SHR_BFCMAP_HOPCNT_CHECK_MODE_FAIL_EOFNI = 2, /* EOFni on hop count == 1 */ 149 } _shr_bfcmap_hopcnt_check_mode_t; 150 typedef struct { 151 uint16 cos; 152 uint16 pri; 153 } _shr_bfcmap_cos_to_pri_t; 154 155 #define _SHR_FCMAP_ATTR_PORT_MODE_MASK (0x1 << 0) 156 #define _SHR_FCMAP_ATTR_SPEED_MASK (0x1 << 1) 157 #define _SHR_FCMAP_ATTR_TX_BB_CREDITS_MASK (0x1 << 2) 158 #define _SHR_FCMAP_ATTR_RX_BB_CREDITS_MASK (0x1 << 3) 159 #define _SHR_FCMAP_ATTR_MAX_FRAME_LENGTH_MASK (0x1 << 4) 160 #define _SHR_FCMAP_ATTR_BB_SC_N_MASK (0x1 << 5) 161 #define _SHR_FCMAP_ATTR_PORT_STATE_MASK (0x1 << 6) 162 #define _SHR_FCMAP_ATTR_R_T_TOV_MASK (0x1 << 7) 163 #define _SHR_FCMAP_ATTR_INTERRUPT_ENABLE_MASK (0x1 << 8) 164 #define _SHR_FCMAP_ATTR_FW_ON_ACTIVE_8G_MASK (0x1 << 9) 165 #define _SHR_FCMAP_ATTR_SRC_MAC_CONSTRUCT_MASK (0x1 << 10) 166 #define _SHR_FCMAP_ATTR_DST_MAC_CONSTRUCT_MASK (0x1 << 11) 167 #define _SHR_FCMAP_ATTR_VLAN_TAG_MASK (0x1 << 12) 168 #define _SHR_FCMAP_ATTR_VFT_TAG_MASK (0x1 << 13) 169 #define _SHR_FCMAP_ATTR_MAPPER_LEN_MASK (0x1 << 14) 170 #define _SHR_FCMAP_ATTR_INGRESS_MAPPER_BYPASS_MASK (0x1 << 15) 171 #define _SHR_FCMAP_ATTR_EGRESS_MAPPER_BYPASS_MASK (0x1 << 16) 172 #define _SHR_FCMAP_ATTR_INGRESS_MAP_TABLE_INPUT_MASK (0x1 << 17) 173 #define _SHR_FCMAP_ATTR_EGRESS_MAP_TABLE_INPUT_MASK (0x1 << 18) 174 #define _SHR_FCMAP_ATTR_INGRESS_FC_CRC_MODE_MASK (0x1 << 19) 175 #define _SHR_FCMAP_ATTR_EGRESS_FC_CRC_MODE_MASK (0x1 << 20) 176 #define _SHR_FCMAP_ATTR_INGRESS_VFTHDR_PROC_MODE_MASK (0x1 << 21) 177 #define _SHR_FCMAP_ATTR_EGRESS_VFTHDR_PROC_MODE_MASK (0x1 << 22) 178 #define _SHR_FCMAP_ATTR_INGRESS_VLANTAG_PROC_MODE_MASK (0x1 << 23) 179 #define _SHR_FCMAP_ATTR_EGRESS_VLANTAG_PROC_MODE_MASK (0x1 << 24) 180 #define _SHR_FCMAP_ATTR_INGRESS_VFID_MAPSRC_MASK (0x1 << 25) 181 #define _SHR_FCMAP_ATTR_EGRESS_VFID_MAPSRC_MASK (0x1 << 26) 182 #define _SHR_FCMAP_ATTR_INGRESS_VID_MAPSRC_MASK (0x1 << 27) 183 #define _SHR_FCMAP_ATTR_EGRESS_VID_MAPSRC_MASK (0x1 << 28) 184 #define _SHR_FCMAP_ATTR_INGRESS_VLAN_PRI_MAP_MODE_MASK (0x1 << 29) 185 #define _SHR_FCMAP_ATTR_EGRESS_VLAN_PRI_MAP_MODE_MASK (0x1 << 30) 186 #define _SHR_FCMAP_ATTR_INGRESS_HOPCNT_CHECK_MODE_MASK (0x1 << 31) 187 #define _SHR_FCMAP_ATTR2_EGRESS_HOPCNT_DEC_ENABLE_MASK (0x1 << 0) 188 #define _SHR_FCMAP_ATTR2_USE_TTS_PCS_16G_MASK (0x1 << 1) 189 #define _SHR_FCMAP_ATTR2_USE_TTS_PCS_32G_MASK (0x1 << 2) 190 #define _SHR_FCMAP_ATTR2_TRAINING_ENABLE_16G_MASK (0x1 << 3) 191 #define _SHR_FCMAP_ATTR2_TRAINING_ENABLE_32G_MASK (0x1 << 4) 192 #define _SHR_FCMAP_ATTR2_FEC_ENABLE_16G_MASK (0x1 << 5) 193 #define _SHR_FCMAP_ATTR2_FEC_ENABLE_32G_MASK (0x1 << 6) 194 #define _SHR_FCMAP_ATTR2_INGRESS_FCS_CRRPT_EOF_ENABLE_MASK (0x1 << 7) 195 #define _SHR_FCMAP_ATTR2_INGRESS_VLANTAG_PRESENCE_ENABLE_MASK (0x1 << 8) 196 #define _SHR_FCMAP_ATTR2_EGRESS_HOPCNT_CHECK_MODE_MASK (0x1 << 9) 197 #define _SHR_FCMAP_ATTR2_EGRESS_PASS_CTRL_FRAME_ENABLE_MASK (0x1 << 10) 198 #define _SHR_FCMAP_ATTR2_EGRESS_PASS_PFC_FRAME_ENABLE_MASK (0x1 << 11) 199 #define _SHR_FCMAP_ATTR2_EGRESS_PASS_PAUSE_FRAME_ENABLE_MASK (0x1 << 12) 200 #define _SHR_FCMAP_ATTR2_EGRESS_FCOE_VER_CHK_DISABLE_MASK (0x1 << 13) 201 #define _SHR_FCMAP_ATTR2_EGRESS_DEFAULT_COS_VALUE_MASK (0x1 << 14) 202 #define _SHR_FCMAP_ATTR2_EGRESS_USE_IP_COS_MAP_MASK (0x1 << 15) 203 #define _SHR_FCMAP_ATTR2_INGRESS_HOPCNT_DEC_ENABLE_MASK (0x1 << 16) 204 #define _SHR_FCMAP_ATTR2_SCRAMBLING_ENABLE_MASK (0x1 << 17) 205 #define _SHR_FCMAP_ATTR2_EGRESS_PAUSE_ENABLE_MASK (0x1 << 18) 206 #define _SHR_FCMAP_ATTR2_EGRESS_PFC_ENABLE_MASK (0x1 << 19) 207 #define _SHR_FCMAP_ATTR2_STAT_INTERVAL_MASK (0x1 << 20) 208 #define _SHR_FCMAP_ATTR2_TRCM_ATTRIBS_MASK (0x1 << 21) 209 #define _SHR_FCMAP_ATTR2_COS_TO_PRI_MASK (0x1 << 22) 210 211 #define _SHR_FCMAP_ATTR_ALL_MASK 0xFFFFFFFF 212 #define _SHR_FCMAP_ATTR2_ALL_MASK 0xFFFFFFFF 213 214 /* 215 * BFCMAP port configuration structure. 216 */ 217 typedef struct _shr_bfcmap_port_config_s { 218 uint32 action_mask; /* _SHR_FCMAP_ATTR_xxx. */ 219 uint32 action_mask2; /* _SHR_FCMAP_ATTR2_xxx. */ 220 _shr_bfcmap_port_mode_t port_mode; /* FC port Mode, FCoE mode */ 221 _shr_bfcmap_port_speed_t speed; /* Speed, 2/4/8/16/32G */ 222 int tx_buffer_to_buffer_credits; /* Transit B2B credits */ 223 int rx_buffer_to_buffer_credits; /* Receive B2B Credits (read only), computed based on max_frame_length */ 224 int max_frame_length; /* maximum FC frame length for ingress and egress (in unit of 32-bit word) */ 225 int bb_sc_n; /* bb credit recovery parameter */ 226 _shr_bfcmap_port_state_t port_state; /* Port state, INIT, Reset, Link Up, Link down (read only) */ 227 int r_t_tov; /* Receive, transmit Timeout, default 100ms */ 228 int interrupt_enable; /* Interrupt enable */ 229 _shr_bfcmap_8g_fw_on_active_t fw_on_active_8g; /* fillword on 8G active state */ 230 231 /* The following three fields should be valid when _SHR_FCMAP_ATTR_SRC_MAC_CONSTRUCT_MASK is set */ 232 _shr_bfcmap_encap_mac_address_t src_mac_construct; /* Encap Source MAC construct mode */ 233 _shr_bmac_addr_t src_mac_addr; /* Src MAC Addr for encapsulated frame */ 234 uint32 src_fcmap_prefix; /* Source FCMAP prefix for the FPMA */ 235 236 /* The following three fields should be valid when _SHR_FCMAP_ATTR_DST_MAC_CONSTRUCT_MASK is set */ 237 _shr_bfcmap_encap_mac_address_t dst_mac_construct; /* Encap Dest MAC construct mode */ 238 _shr_bmac_addr_t dst_mac_addr; /* Dest MAC Addr for encapsulated frame */ 239 uint32 dst_fcmap_prefix; /* Destination FCMAP prefix for the FPMA */ 240 241 /* FC Mapper Configuration */ 242 uint32 vlan_tag; /* default vlan for the mapper */ 243 uint32 vft_tag; /* default VFT tag for the mapper */ 244 int mapper_len; /* Size of VLAN-VSAN Mapper table (read only) */ 245 int ingress_mapper_bypass; /* Bypass Mapper */ 246 int egress_mapper_bypass; /* Bypass Mapper */ 247 _shr_bfcmap_map_table_input_t ingress_map_table_input; /* VID or VFID */ 248 _shr_bfcmap_map_table_input_t egress_map_table_input; /* VID or VFID */ 249 _shr_bfcmap_fc_crc_mode_t ingress_fc_crc_mode; /* Mapper FC-CRC handling */ 250 _shr_bfcmap_fc_crc_mode_t egress_fc_crc_mode; /* Mapper FC-CRC handling */ 251 _shr_bfcmap_vfthdr_proc_mode_t ingress_vfthdr_proc_mode; /* VFT header processing mode */ 252 _shr_bfcmap_vfthdr_proc_mode_t egress_vfthdr_proc_mode; /* VFT header processing mode */ 253 _shr_bfcmap_vlantag_proc_mode_t ingress_vlantag_proc_mode; /* VLAN header processing mode */ 254 _shr_bfcmap_vlantag_proc_mode_t egress_vlantag_proc_mode; /* VLAN header processing mode */ 255 _shr_bfcmap_vfid_mapsrc_t ingress_vfid_mapsrc; /* source of VFID */ 256 _shr_bfcmap_vfid_mapsrc_t egress_vfid_mapsrc; /* source of VFID */ 257 _shr_bfcmap_vid_mapsrc_t ingress_vid_mapsrc; /* source of VID */ 258 _shr_bfcmap_vid_mapsrc_t egress_vid_mapsrc; /* source of VID */ 259 _shr_bfcmap_vlan_pri_map_mode_t ingress_vlan_pri_map_mode; /* processing mode for priority field of vlan tag */ 260 _shr_bfcmap_vlan_pri_map_mode_t egress_vlan_pri_map_mode; /* processing mode for priority field of vlan tag */ 261 _shr_bfcmap_hopcnt_check_mode_t ingress_hopCnt_check_mode; /* mode of VFT hopCnt check on ingress */ 262 int egress_hopCnt_dec_enable; /* enable VFT hopCnt decrement on egress */ 263 264 int use_tts_pcs_16G; /* during 16G speed negotiation, 0 -- Use TTS, 1 -- Use PCS */ 265 int use_tts_pcs_32G; /* during 32G speed negotiation, 0 -- Use TTS, 1 -- Use PCS */ 266 int training_enable_16G; /* enable/disable link training for 16G */ 267 int training_enable_32G; /* enable/disable link training for 32G */ 268 int fec_enable_16G; /* enable/disable FEC for 16G */ 269 int fec_enable_32G; /* enable/disable FEC for 32G */ 270 271 /* Config Parameters for FC Mapper */ 272 int ingress_fcs_crrpt_eof_enable; /* Enable FCS corruption on if FCoE pkt has EOFni or EOFa on ingress */ 273 int ingress_vlantag_presence_enable; /* VLAN header insert enable */ 274 _shr_bfcmap_hopcnt_check_mode_t egress_hopcnt_check_mode; /* mode of VFT hopCnt check on egress */ 275 int ingress_hopcnt_dec_enable; /* enable VFT hopCnt decrement on ingress */ 276 int egress_pass_ctrl_frame_enable; /* enable passing control frame on egress when mapper is in bypass mode */ 277 int egress_pass_pfc_frame_enable; /* enable passing pfc frame on egress when mapper is in bypass mode */ 278 int egress_pass_pause_frame_enable; /* enable passing pause frame on egress when mapper is in bypass mode */ 279 int egress_fcoe_version_chk_disable; /* disable FCOE header version field check on egress */ 280 int egress_default_cos_value; /* specify default CoS value to use on egress */ 281 int egress_use_ip_cos_map; /* use IP CoS map values on egress */ 282 283 /* The following two fields should be valid when _SHR_FCMAP_ATTR2_SCRAMBLING_ENABLE_MASK is set */ 284 uint32 scrambling_enable_mask; /* bitmap to enable/disable scrambling for 2/4/8/16/32G FC speed */ 285 uint32 scrambling_enable_value; /* 0 - disable, 1 - enable: bitmap value for corresponding speed */ 286 287 int egress_pause_enable; /* 0 - disable, 1 - enable; legacy pause on egress */ 288 int egress_pfc_enable; /* 0 - disable, 1 - enable; PFC on egress */ 289 uint32 stat_interval; /* stats collection interval in milliseconds */ 290 uint32 trcm_attribs; /* Tranceiver module configured attributes 291 Configure it when Firmwre does not have access 292 acces to the Transceiver over I2C or the module 293 does not have the MSA compliant memory map 294 describing its attributes (Example Copper). 295 */ 296 _shr_bfcmap_cos_to_pri_t cos_to_pri; /* Specifies the vlan priority the cos maps to. */ 297 } _shr_bfcmap_port_config_t; 298 299 300 /* 301 * Prototype for Port interation callback function. 302 */ 303 typedef int (*_shr_bfcmap_port_traverse_cb)(bfcmap_port_t p, 304 _shr_bfcmap_core_t dev_core, 305 bfcmap_dev_addr_t dev_addr, 306 int dev_port, 307 bfcmap_dev_io_f devio_f, 308 void *user_data); 309 310 311 /* 312 * BFCMAP VLAN - VSAN Mapping 313 */ 314 typedef struct _shr_bfcmap_vlan_vsan_map_s { 315 uint16 vlan_vid; 316 uint16 vsan_vfid; 317 } _shr_bfcmap_vlan_vsan_map_t; 318 319 320 /* 321 * BFCMAP Events that are triggered by the BFCMAP driver. 322 */ 323 typedef enum { 324 _SHR_BFCMAP_EVENT_FC_LINK_INIT = 0, /* LINK Initialized */ 325 _SHR_BFCMAP_EVENT_FC_LINK_RESET = 1, /* Link Reset received */ 326 _SHR_BFCMAP_EVENT_FC_LINK_DOWN = 2, /* Link DOWN */ 327 _SHR_BFCMAP_EVENT_FC_R_T_TIMEOUT = 3, /* R_T_Timeout expired */ 328 _SHR_BFCMAP_EVENT_FC_E_D_TIMEOUT = 4, /* E_D_Timeout expired */ 329 _SHR_BFCMAP_EVENT__COUNT = 5 330 } _shr_bfcmap_event_t; 331 332 333 /* 334 * Prototype for the event callback function. 335 */ 336 typedef int (*_shr_bfcmap_event_cb_fn)(bfcmap_port_t p, /* Port ID */ 337 _shr_bfcmap_event_t event, /* Event */ 338 void *user_data); /* secure assoc ID */ 339 340 341 /* 342 * The following enums define the stats/couter types. 343 */ 344 typedef enum { 345 _shr_fc_rxdebug0 = 0, 346 _shr_fc_rxdebug1 = 1, 347 _shr_fc_rxunicastpkts = 2, 348 _shr_fc_rxgoodframes = 3, 349 _shr_fc_rxbcastpkts = 4, 350 _shr_fc_rxbbcredit0 = 5, 351 _shr_fc_rxinvalidcrc = 6, 352 _shr_fc_rxframetoolong = 7, 353 _shr_fc_rxtruncframes = 8, 354 _shr_fc_rxdelimitererr = 9, 355 _shr_fc_rxothererr = 10, 356 _shr_fc_rxruntframes = 11, 357 _shr_fc_rxlipcount = 12, 358 _shr_fc_rxnoscount = 13, 359 _shr_fc_rxerrframes = 14, 360 _shr_fc_rxdropframes = 15, 361 _shr_fc_rxlinkfail = 16, 362 _shr_fc_rxlosssync = 17, 363 _shr_fc_rxlosssig = 18, 364 _shr_fc_rxprimseqerr = 19, 365 _shr_fc_rxinvalidword = 20, 366 _shr_fc_rxinvalidset = 21, 367 _shr_fc_rxencodedisparity = 22, 368 _shr_fc_rxbyt = 23, 369 _shr_fc_txdebug0 = 24, 370 _shr_fc_txdebug1 = 25, 371 _shr_fc_txunicastpkts = 26, 372 _shr_fc_txbcastpkts = 27, 373 _shr_fc_txbbcredit0 = 28, 374 _shr_fc_txgoodframes = 29, 375 _shr_fc_txfifounderrun = 30, 376 _shr_fc_txdropframes = 31, 377 _shr_fc_txbyt = 32, 378 379 _shr_fc_class2_rxgoodframes = 33, 380 _shr_fc_class2_rxinvalidcrc = 34, 381 _shr_fc_class2_rxframetoolong = 35, 382 _shr_fc_class3_rxgoodframes = 36, 383 _shr_fc_class3_rxinvalidcrc = 37, 384 _shr_fc_class3_rxframetoolong = 38, 385 _shr_fc_classf_rxgoodframes = 39, 386 _shr_fc_classf_rxinvalidcrc = 40, 387 _shr_fc_classf_rxframetoolong = 41, 388 _shr_fc_rxbbc0drop = 42, 389 _shr_fc_rxsyncfail = 43, 390 _shr_fc_rxbadxword = 44, 391 _shr_fc_class2_rxruntframes = 45, 392 _shr_fc_class3_rxruntframes = 46, 393 _shr_fc_classf_rxruntframes = 47, 394 _shr_fc_class2_rxbyt = 48, 395 _shr_fc_class3_rxbyt = 49, 396 _shr_fc_classf_rxbyt = 50, 397 _shr_fc_class2_txframes = 51, 398 _shr_fc_class3_txframes = 52, 399 _shr_fc_classf_txframes = 53, 400 _shr_fc_txframes = 54, 401 _shr_fc_class2_txoversized_frames = 55, 402 _shr_fc_class3_txoversized_frames = 56, 403 _shr_fc_classf_txoversized_frames = 57, 404 _shr_fc_txoversized_frames = 58, 405 _shr_fc_class2_txbyt = 59, 406 _shr_fc_class3_txbyt = 60, 407 _shr_fc_classf_txbyt = 61, 408 409 _shr_bfcmap_stat__count = 62 410 } _shr_bfcmap_stat_t; 411 412 413 /* FC link failure trigger type */ 414 typedef enum { 415 _SHR_BFCMAP_LF_TR_NONE = 0x0, 416 _SHR_BFCMAP_LF_TR_PORT_INIT = 0x1, 417 _SHR_BFCMAP_LF_TR_OPEN_LINK = 0x2, 418 _SHR_BFCMAP_LF_TR_LINK_FAILURE = 0x3, 419 _SHR_BFCMAP_LF_TR_OLS_RCVD = 0x4, 420 _SHR_BFCMAP_LF_TR_NOS_RCVD = 0x5, 421 _SHR_BFCMAP_LF_TR_SYNC_LOSS = 0x6, 422 _SHR_BFCMAP_LF_TR_BOUCELINK_FROM_ADMIN = 0x7, 423 _SHR_BFCMAP_LF_TR_CHGSPEED_FROM_ADMIN = 0x8, 424 _SHR_BFCMAP_LF_TR_DISABLE_FROM_ADMIN = 0x9, 425 _SHR_BFCMAP_LF_TR_RESET_FROM_ADMIN = 0xA, 426 _SHR_BFCMAP_LF_TR_LR_RCVD = 0xB, 427 _SHR_BFCMAP_LF_TR_LRR_RCVD = 0xC, 428 _SHR_BFCMAP_LF_TR_ED_TOV = 0xD, 429 _SHR_BFCMAP_LF_TR_SYS_LNK_FAILURE = 0xE 430 } _shr_bfcmap_lf_tr_t; 431 432 /* FC link failure reason code */ 433 typedef enum { 434 _SHR_BFCMAP_LF_RC_NONE = 0x0, 435 _SHR_BFCMAP_LF_RC_PORT_INIT = 0x1, 436 _SHR_BFCMAP_LF_RC_OPEN_LINK = 0x2, 437 _SHR_BFCMAP_LF_RC_LINK_FAILURE = 0x3, 438 _SHR_BFCMAP_LF_RC_OLS_RCVD = 0x4, 439 _SHR_BFCMAP_LF_RC_NOS_RCVD = 0x5, 440 _SHR_BFCMAP_LF_RC_SYNC_LOSS = 0x6, 441 _SHR_BFCMAP_LF_RC_BOUCELINK_FROM_ADMIN = 0x7, 442 _SHR_BFCMAP_LF_RC_CHGSPEED_FROM_ADMIN = 0x8, 443 _SHR_BFCMAP_LF_RC_DISABLE_FROM_ADMIN = 0x9, 444 _SHR_BFCMAP_LF_RC_RESET_FAILURE = 0xA, 445 _SHR_BFCMAP_LF_RC_SYS_LNK_FAILURE = 0xB 446 } _shr_bfcmap_lf_rc_t; 447 448 449 /* FC link failure diagnostic code */ 450 typedef enum { 451 _SHR_BFCMAP_DIAG_OK = 0x0, 452 _SHR_BFCMAP_DIAG_PORT_INIT = 0x1, 453 _SHR_BFCMAP_DIAG_OPEN_LINK = 0x2, 454 _SHR_BFCMAP_DIAG_LINK_FAILURE = 0x3, 455 _SHR_BFCMAP_DIAG_OLS_RCVD = 0x4, 456 _SHR_BFCMAP_DIAG_NOS_RCVD = 0x5, 457 _SHR_BFCMAP_DIAG_SYNC_LOSS = 0x6, 458 _SHR_BFCMAP_DIAG_BOUCELINK_FROM_ADMIN = 0x7, 459 _SHR_BFCMAP_DIAG_CHGSPEED_FROM_ADMIN = 0x8, 460 _SHR_BFCMAP_DIAG_DISABLE_FROM_ADMIN = 0x9, 461 _SHR_BFCMAP_DIAG_AN_NO_SIGNAL = 0xA, 462 _SHR_BFCMAP_DIAG_AN_TIMEOUT = 0xB, 463 _SHR_BFCMAP_DIAG_PROTO_TIMEOUT = 0xC, 464 _SHR_BFCMAP_DIAG_SYS_LNK_FAILURE = 0xD 465 } _shr_bfcmap_diag_code_t; 466 467 typedef uint32 _shr_bfcmap_pa_speed_t; 468 469 /* 470 * FC Port ability structure for port speeds 471 */ 472 typedef struct _shr_bfcmap_port_ability_s { 473 _shr_bfcmap_pa_speed_t port_ability_speed; 474 } _shr_bfcmap_port_ability_t; 475 476 #define _SHR_FCMAP_PORT_ABILITY_SPEED_AN (0x1 << 0) 477 #define _SHR_FCMAP_PORT_ABILITY_SPEED_2GBPS (0x1 << 1) 478 #define _SHR_FCMAP_PORT_ABILITY_SPEED_4GBPS (0x1 << 2) 479 #define _SHR_FCMAP_PORT_ABILITY_SPEED_8GBPS (0x1 << 3) 480 #define _SHR_FCMAP_PORT_ABILITY_SPEED_16GBPS (0x1 << 4) 481 #define _SHR_FCMAP_PORT_ABILITY_SPEED_32GBPS (0x1 << 5) 482 483 #define _SHR_FCMAP_PORT_SCRAMBLING_SPEED_2GBPS (0x1 << 0) 484 #define _SHR_FCMAP_PORT_SCRAMBLING_SPEED_4GBPS (0x1 << 1) 485 #define _SHR_FCMAP_PORT_SCRAMBLING_SPEED_8GBPS (0x1 << 2) 486 #define _SHR_FCMAP_PORT_SCRAMBLING_SPEED_16GBPS (0x1 << 3) 487 #define _SHR_FCMAP_PORT_SCRAMBLING_SPEED_32GBPS (0x1 << 4) 488 489 #define _SHR_FCMAP_PORT_MODULE_NO_FW_I2C (0x1 << 0) 490 #define _SHR_FCMAP_PORT_MODULE_IS_COPPER (0x1 << 1) 491 #define _SHR_FCMAP_PORT_MODULE_SPEED_CAP32G (0x1 << 2) 492 #define _SHR_FCMAP_PORT_MODULE_SPEED_CAP16G (0x1 << 3) 493 #define _SHR_FCMAP_PORT_MODULE_SPEED_CAP8G (0x1 << 4) 494 #define _SHR_FCMAP_PORT_MODULE_SPEED_CAP4G (0x1 << 5) 495 #define _SHR_FCMAP_PORT_MODULE_FEC_CAP32G (0x1 << 6) 496 #define _SHR_FCMAP_PORT_MODULE_FEC_CAP16G (0x1 << 7) 497 #define _SHR_FCMAP_PORT_MODULE_IS_QSFP (0x1 << 8) 498 #define _SHR_FCMAP_PORT_MODULE_SUPP_RS (0x1 << 9) 499 #define _SHR_FCMAP_PORT_MODULE_RS_HRD_RX_CUTOFF (0x3 << 10) 500 #define _SHR_FCMAP_PORT_MODULE_RS_HRD_TX_CUTOFF (0x3 << 12) 501 502 503 #endif /* INCLUDE_FCMAP */ 504 505 #endif /* _SHR_BFCMAP_H */ 506