cpri.h (18758B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * This file defines commo cpri port parameters. 8 * 9 * Its contents are not used directly by applications; it is used only 10 * by header files of parent APIs which need to define cpri parameters. 11 */ 12 13 #ifndef _SHR_CPRI_H 14 #define _SHR_CPRI_H 15 16 typedef struct _shr_cpri_cw_l1_protocol_info_s{ 17 uint32 protocol_ver; /* */ 18 uint32 hdlc_rate; /* */ 19 int reset; /* DL request, UL ack */ 20 int l1_lof; 21 int l1_los; 22 int l1_sdi; 23 int l1_rai; 24 uint32 eth_pointer; /* Eth control location 010100 - 11111*/ 25 } _shr_cpri_cw_l1_protocol_info_t; 26 27 typedef enum _shr_cpri_hdlc_crc_byte_order_e { 28 _shrCpriHdlcCrcByteOrderNone = 0, /**< Default 15 .. 0 */ 29 _shrCpriHdlcCrcByteOrderSwap = 1, /**< Byte Order Swap [7:0][15:8] */ 30 _shrCpriHdlcCrcByteOrderCount 31 } _shr_cpri_hdlc_crc_byte_order_t; 32 33 typedef enum _shr_cpri_hdlc_fcs_err_check_e { 34 _shrCpriHdlcFcsErrCheck = 0, /**< Check for FCS Error */ 35 _shrCpriHdlcFcsErrNoCheck = 1, /**< No FCS Error Check. Ignore FCS. */ 36 _shrCpriHdlcFcsErrCount 37 } _shr_cpri_hdlc_fcs_err_check_t; 38 39 typedef enum _shr_cpri_hdlc_fcs_size_e { 40 _shrCpriHdlcFcsSize8Bits = 0, /**< FCS Size 8 bits */ 41 _shrCpriHdlcFcsSize16Bits = 1, /**< FCS Size 16 bits */ 42 _shrCpriHdlcFcsSize32Bits = 2, /**< FCS Size 32 bits */ 43 _shrCpriHdlcFcsSizeCount 44 } _shr_cpri_hdlc_fcs_size_t; 45 46 typedef enum _shr_cpri_hdlc_filling_flag_pattern_e { 47 _shrCpriHdlcFillingFlagPattern7E = 0, /**< Fill 7E */ 48 _shrCpriHdlcFillingFlagPattern7F = 1, /**< Fill 7F */ 49 _shrCpriHdlcFillingFlagPatternFF = 2, /**< Fill FF */ 50 _shrCpriHdlcFillingFlagPatternCount 51 } _shr_cpri_hdlc_filling_flag_pattern_t; 52 53 typedef enum _shr_cpri_hdlc_flag_size_e { 54 _shrCpriHdlcNumFlagSizeOneByte = 0, /**< Min 1 Flag Byte */ 55 _shrCpriHdlcNumFlagSizeTwoByte = 1, /**< Min 2 Flag Bytes */ 56 _shrCpriHdlcNumFlagByteCount 57 } _shr_cpri_hdlc_flag_size_t; 58 59 typedef enum _shr_cpri_hdlc_crc_mode_e { 60 _shrCpriHdlcCrcAppend = 0, /**< Append CRC */ 61 _shrCpriHdlcCrcReplace = 1, /**< Replace CRC */ 62 _shrCpriHdlcCrcNoUpdate = 2, /**< Keep existing CRC. */ 63 _shrCpriHdlcCrcCount 64 } _shr_cpri_hdlc_crc_mode_t; 65 66 typedef enum _shr_cpri_hdlc_crc_init_val_e { 67 _shrCpriHdlcCrcInitValAll0 = 0, /**< ALL 0s */ 68 _shrCpriHdlcCrcInitValAll1 = 1, /**< All 1s */ 69 _shrCpriHdlcCrcInitValCount 70 } _shr_cpri_hdlc_crc_init_val_t; 71 72 typedef enum _shr_cpri_vsd_control_subchan_num_bytes_e { 73 _shrVsdCtrlSubchanNumBytes1 = 0, /**< Sub Channel Num of Bytes 1. */ 74 _shrVsdCtrlSubchanNumBytes2 = 1, /**< Sub Channel Num of Bytes 2. */ 75 _shrVsdCtrlSubchanNumBytes4 = 2, /**< Sub Channel Num of Bytes 4. */ 76 _shrVsdCtrlSubchanNumBytesCount 77 } _shr_cpri_vsd_control_subchan_num_bytes_t; 78 79 typedef enum _shr_cpri_vsd_control_flow_num_bytes_e { 80 _shrVsdCtrlFlowNumBytes2 = 0, /**< VSD control flow num of Bytes 2. */ 81 _shrVsdCtrlFlowNumBytes4 = 1, /**< VSD control flow num of Bytes 4. */ 82 _shrVsdCtrlFlowNumBytesCount 83 } _shr_cpri_vsd_control_flow_num_bytes_t; 84 85 typedef enum _shr_cpri_vsd_control_subchan_size_e { 86 _shrVsdCtrlSubchanSize2 = 0, /**< VSD control Sub Chan Size 2 bytes. */ 87 _shrVsdCtrlSubchanSize4 = 1, /**< VSD control Sub Chan Size 4 bytes. */ 88 _shrVsdCtrlSubchanSizeCount 89 } _shr_cpri_vsd_control_subchan_size_t; 90 91 typedef struct _shr_cpri_rx_vsd_flow_info_s{ 92 uint32 hyper_frame_number; /**< Hyper Frame Number */ 93 uint32 hyper_frame_modulo; /**< Hyper Frame Modulo */ 94 int filter_zero_data; /**< Filer all 0's Data. */ 95 uint32 section_num[4]; /**< VSD Section in this group in Order 0-127. */ 96 uint32 num_sector; /**< Number of Sectors. */ 97 uint32 tag_id; /**< Tag Id */ 98 } _shr_cpri_rx_vsd_flow_info_t; 99 100 typedef struct _shr_cpri_tx_vsd_flow_info_s { 101 uint32 hyper_frame_number; /**< Hyper Frame Number */ 102 uint32 hyper_frame_modulo; /**< Hyper Frame Number */ 103 int repeat_mode; /**< Filer all 0's Data. */ 104 uint32 section_num[4]; /**< VSD Sector in this group in Order. */ 105 uint32 num_sector; /**< Number of Sectors. */ 106 uint32 roe_flow_id; /**< Roe Flow ID. */ 107 } _shr_cpri_tx_vsd_flow_info_t; 108 109 typedef enum _shr_cpri_cw_filter_mode_e { 110 _shrCpriFilterDisable = 0, /**< Disable Filter */ 111 _shrCpriFilterNonZero = 1, /**< Non-Zero Data only */ 112 _shrCpriFilterPeriodic = 2, /**< Periodic Generation */ 113 _shrCpriFilterChange = 3, /**< Content Change Only */ 114 _shrCpriFilterPatternMatch = 4, /**< Pattern Match */ 115 _shrCpriFilterCount 116 } _shr_cpri_cw_filter_mode_t; 117 118 typedef enum _shr_vsd_raw_map_mode_e { 119 _shrVsdRawMapModePeriodic = 0, /**< Peridic insert data using Modulo */ 120 _shrVsdRawMapModeRoeFrame = 1, /**< Use Frame Number from ROE frame. */ 121 _shrVsdRawMapModeCount 122 } _shr_vsd_raw_map_mode_t; 123 124 typedef enum _shr_cpri_gcw_mask_e { 125 _shrCpriGcwMaskNone = 0, /**< None of the Byte are extracted. */ 126 _shrCpriGcwMaskLSB = 1, /**< LSB Byte is extracted. */ 127 _shrCpriGcwMaskMSB = 2, /**< MSB Byte is extracted. */ 128 _shrCpriGcwMaskBOTH = 3, /**< Both Byte are extracted. */ 129 _shrCpriGcwMaskCount 130 } _shr_cpri_gcw_mask_t; 131 132 typedef struct _shr_cpri_cw_l1_config_info_s{ 133 uint32 enet_ptr; /**< Z.194.0 Ethernet pointer p. */ 134 uint32 l1_fun; /**< Z.130.0 l1 function */ 135 uint32 hdlc_rate; /**< hdlc rate */ 136 uint32 protocol_ver; /**< Byte Z.2.0 version 1 or 2 */ 137 } _shr_cpri_cw_l1_config_info_t; 138 139 /* BRCM_RSVD4 */ 140 typedef enum _shr_rsvd4_control_msg_proc_type_e { 141 _shrRsvd4CtrlMsgProcFE = 0, /**< Multi Message Fast Ethernet. */ 142 _shrRsvd4CtrlMsgProcFCB = 1, /**< FCB . */ 143 _shrRsvd4CtrlMsgProcPayload = 2, /**< Message Payload Extraction. */ 144 _shrRsvd4CtrlMsgProcFull = 3, /**< Full Message. */ 145 _shrRsvd4CtrlMsgProcFullWithTag = 4, /**< Full Message with Tag. */ 146 _shrRsvd4CtrlMsgProcCount 147 } _shr_rsvd4_control_msg_proc_type_t; 148 149 typedef enum _shr_cpri_tag_option_e { 150 _shrCpriTagUseDefault= 0, /**< Tag Use default. */ 151 _shrCpriTagUseLookup = 1, /**< Tag Use Look up table. */ 152 _shrCpriTagOptionCount 153 } _shr_cpri_tag_option_t; 154 155 typedef enum _shr_cpri_interrupt_type_e{ 156 _shrCpriIntrRx1588CapturedTs, /* RX 1588 Fifo intr */ 157 _shrCpriIntrRx1588TsFifo, /* RX 1588 Fifo intr - Fifo full, */ 158 _shrCpriIntrRxEncapCtrlQOverflow, /* Encap Ctrl Queue(0-15) FIFO Over-Flow */ 159 _shrCpriIntrRxEncapDataQOverflow, /* Encap Data Queue(0-63) FIFO Over-Flow */ 160 _shrCpriIntrRxEncapGsmTsQErr, /* Encap Per Queue GSM(0-63) Time-Slot Error */ 161 _shrCpriIntrRxEncapIpsmCdcFifoErr, /* Encap IPSM CDC FIFO Error */ 162 _shrCpriIntrRxEncapRxFrmInFifoOverflow, /* Encap RX-framer Input-buffer FIFO Over Error */ 163 _shrCpriIntrRxEncapWqFiFoOverflow, /* Encap Per Work-Queue FIFO Over Error */ 164 _shrCpriIntrRxFrmL1SigChange, /* L1 signal change */ 165 _shrCpriIntrRxFrmRsvd4SingleTsErr, /*Per Axc(0-63) Single Timestamp Error in RSVD4 mode */ 166 _shrCpriIntrRxFrmRsvd4Ts, /* Per Axc(0-63) Timestamp interrupt in RSVD4 mode */ 167 _shrCpriIntrRxGcw, /* Interrupt for RX GCW Word(0-15) is loaded */ 168 _shrCpriIntrRxPcs64B66BBlkLckLh, /* RX PCS Block lock status - latch high version */ 169 _shrCpriIntrRxPcs64B66BBlkLckLl, /* RX PCS Block lock status - latch low version */ 170 _shrCpriIntrRxPcs64B66BHiBerLh, /* RX PCS BER - latch high version */ 171 _shrCpriIntrRxPcs64B66BHiBerLl, /* RX PCS BER - latch low version */ 172 _shrCpriIntrRxPcsExtractFifoOvrFlow, /* RX PCS extract FIFO overflow intr */ 173 _shrCpriIntrRxPcsFecCsCwBad, /* cw_bad during CW_SYNC state */ 174 _shrCpriIntrRxPcsLinkStatusLh, /* RX PCS link status - latch high version */ 175 _shrCpriIntrRxPcsLinkStatusLl, /* RX PCS link status - latch low version */ 176 _shrCpriIntrRxPcsLosLh, /* RX PCS LOS - latch high version */ 177 _shrCpriIntrRxPcsLosLl, /* RX PCS LOS - latch low version */ 178 _shrCpriIntrTx1588CapturedTs, /* TX 1588 Sw capture interrupt */ 179 _shrCpriIntrTx1588TsFifo, /* "TX 1588 Fifo capture interrupt. */ 180 _shrCpriIntrTxDecapAgModePktMiss, /* Agnostic mode missing packet */ 181 _shrCpriIntrTxDecapDataQBufSizeErr,/* Decap Per Queue Decap Data Queue BUFF SIZE Error */ 182 _shrCpriIntrTxDecapDataQOvflErr,/* Decap Per Queue Decap Data Queue FIFO Over-Flow Error */ 183 _shrCpriIntrTxDecapDataQUdflErr,/* Decap Per Queue Decap Data Queue FIFO underflow Error */ 184 _shrCpriIntrTxFrmArbCpriAckMismatch, /* arbiter cpri ack mismatch */ 185 _shrCpriIntrTxFrmArbPsizeZero, /* decap sop control word packet size = 0 */ 186 _shrCpriIntrTxFrmArbRsvd4AckMisalign, /* arbiter RSVD4 ack misaligned */ 187 _shrCpriIntrTxFrmArbRsvd4ReqConflict, /* arbiter RSVD4 req conflict */ 188 _shrCpriIntrTxFrmBfaHfStartMisalign, /* BFA hf start misalign */ 189 _shrCpriIntrTxFrmCwaCtrlPktFlowIdErr, /* CWA ctrl flow packet flow id error */ 190 _shrCpriIntrTxFrmCwaFastEthBufferOverflow, /* CPRI control asm fast ethernet (fast cm) buffer overflow */ 191 _shrCpriIntrTxFrmCwaHdlcBufferOverflow, /* CPRI control asm hdlc (slow cm) buffer overflow */ 192 _shrCpriIntrTxFrmCwaMultipleValids, /* CPRI control asm valids from multiple engines are asserted at same time */ 193 _shrCpriIntrTxFrmCwaSdvmBufferOverflow, /* CPRI control asm Rsvd5 buffer overflow */ 194 _shrCpriIntrTxFrmCwaSdvmProcOverflow, /* CPRI control asm RSVD5 proc buffer overflow */ 195 _shrCpriIntrTxFrmCwaVsdRawBufferOverflow, /* CPRI control asm vsd raw buffer overflow */ 196 _shrCpriIntrTxFrmDrAckMisalign,/* RSVD4 control proc decap req - decap ack and delayed req misalign */ 197 _shrCpriIntrTxFrmDrMultiEthPsizeUndersize, /* RSVD4 control proc decap req multi eth - packet undersize */ 198 _shrCpriIntrTxFrmMultiEthBufferOverflow, /* RSVD4 control multi-msg eth buffer overflow */ 199 _shrCpriIntrTxFrmMultiEthBufferUnderflow, /* RSVD4 control multi-msg eth buffer underflow */ 200 _shrCpriIntrTxGcw, /* Interrupt for TX GCW Word(0-15) is loaded */ 201 _shrCpriIntrTxPcsFifoOverflow, /* TX assembly FIFO overflow */ 202 _shrCpriIntrTxPcsFifoUnderflow, /* TX assembly FIFO underflow */ 203 _shrCpriIntrTxPcsGboxOverflow,/* gearbox buffer overflow */ 204 _shrCpriIntrTxPcsGboxUnderflow, /* gearbox buffer underflow */ 205 _shrCpriIntrCount /* Should be last */ 206 } _shr_cpri_interrupt_type_t; 207 208 typedef struct _shr_cpri_fast_eth_config_s { 209 uint32 queue_num; 210 int no_fcs_err_check; 211 uint32 min_packet_size; 212 uint32 max_packet_size; 213 int min_packet_drop; 214 int max_packet_drop; 215 int strip_crc; 216 } _shr_cpri_fast_eth_config_t; 217 218 typedef enum _shr_rsvd4_sync_count_cycle_e { 219 _shrRsvd4SyncCountCycleEveryMF = 0, /**< Every Frame. */ 220 _shrRsvd4SyncCountCycleUpToSixMF = 1, /**< Up to 6 MF . */ 221 _shrRsvd4SyncCountCycleCount 222 } _shr_rsvd4_sync_count_cycle_t; 223 224 typedef struct _shr_cpri_tag_gen_entry_s { 225 uint32 tag_id; /**< Tag ID */ 226 uint32 mask; /**< Mask */ 227 uint32 header; /**< Header Info */ 228 uint32 word_count; /**< Word Count, only for RTWP */ 229 } _shr_cpri_tag_gen_entry_t; 230 231 typedef enum _shr_rsvd4_crc_option_e { 232 _shrRsvd4CrcOptionUseRoe = 0, /**< Use CRC from ROE packet. */ 233 _shrRsvd4CrcOptionRegenerate = 1, /**< Regenerate New One . */ 234 _shrRsvd4CrcOptionCount 235 } _shr_rsvd4_crc_option_t; 236 237 /* RSVD4 TS MSG modes */ 238 typedef enum _shr_rsvd4_msg_ts_mode_e { 239 _shrRsvd4MsgTsModeWCDMA = 0, /* */ 240 _shrRsvd4MsgTsModeLTE = 1, /* */ 241 _shrRsvd4MsgTsModeGSMDL = 2, /* */ 242 _shrRsvd4MsgTsModeGSMUL = 3, /* */ 243 _shrRsvd4MsgTsModeCount = 4 /* */ 244 } _shr_rsvd4_msg_ts_mode_t; 245 246 247 typedef enum _shr_cpri_1588_capture_mode_e { 248 _shrCpri1588CaptureModeMatchBfnHfn = 0, 249 _shrCpri1588CaptureModeMatchHfnOnly = 1, 250 _shrCpri1588CaptureModeCount 251 } _shr_cpri_1588_capture_mode_t; 252 253 typedef enum _shr_cpri_frame_sync_mode_e { 254 _shrCpriFrameSyncModeHyper, 255 _shrCpriFrameSyncModeRadio, 256 _shrCpriFrameSyncModeBasic, 257 _shrCpriFrameSyncModeTunnel, /* Frame sync mode for tunnel */ 258 _shrCpriFrameSyncModeCount 259 } _shr_cpri_frame_sync_mode_t; 260 261 typedef enum _shr_rsvd4_sync_mode_e { 262 _shrRsvd4SyncModeNoSync, 263 _shrRsvd4SyncModeMsgOffset, 264 _shrRsvd4SyncModeMsgAndMasterFrameOffset, 265 _shrRsvd4SyncModeTsNoSync, 266 _shrRsvd4SyncModeTsMsgOffset, 267 _shrRsvd4SyncModeTsMsgAndMasterFrameOffset, 268 _shrRsvd4SyncModeCount 269 } _shr_rsvd4_sync_mode_t; 270 271 typedef enum _shr_cpri_roe_payload_multiple_e { 272 _shrCpriPayloadMultiple1X, 273 _shrCpriPayloadMultiple1p5X, 274 _shrCpriPayloadMultiple2X, 275 _shrCpriPayloadMultiple4X, 276 _shrCpriPayloadMultiple8X, 277 _shrCpriPayloadMultipleCount 278 } _shr_cpri_roe_payload_multiple_t; 279 280 typedef enum _shr_cpri_dir_e { 281 _shrCpriDirTx, 282 _shrCpriDirRx, 283 _shrCpriDirCount 284 } _shr_cpri_dir_t; 285 286 typedef struct _shr_cpri_presentation_time_s { 287 uint32 time; /* 29 bits only, sign bit | 24 bits ns | 4 bits sub ns */ 288 }_shr_cpri_presentation_time_t; 289 290 typedef enum _shr_cpri_presentation_ts_attribute_e { 291 _shrCpriEncapPresentationTsAdjust, 292 _shrCpriEncapPresentationApproxInc 293 }_shr_cpri_presentation_ts_attribute_t; 294 295 typedef struct _shr_cpri_decap_presentation_config_s { 296 uint32 time_mod_offset; /* 20 bits only */ 297 uint32 mod_count; 298 }_shr_cpri_decap_presentation_config_t; 299 300 typedef enum _shr_cpri_1588_ts_type_e { 301 _shrCpri1588TsTypeFifo, 302 _shrCpri1588TsTypeCMIC, 303 _shrCpri1588TsTypeSw, 304 _shrCpri1588TsTypeCount 305 } _shr_cpri_1588_ts_type_t; 306 307 typedef struct _shr_cpri_1588_timestamp_ts_config_s { 308 int enable; /* Enable/Disable */ 309 uint32 modulo_count; /* modulo count */ 310 }_shr_cpri_1588_timestamp_ts_config_t; 311 312 #define _shrIntrDataNumOfData64 8 313 typedef struct _shr_cpri_intr_info_s { 314 _shr_cpri_interrupt_type_t cpri_intr_type; /**< cpri interrupt type */ 315 int axc_id; /**< AxC Id */ 316 int queue_num; /**< queu num */ 317 int data; /**< reserved */ 318 uint64 data64[_shrIntrDataNumOfData64]; /**< reserved */ 319 } _shr_cpri_intr_info_t; 320 321 /* sync up with bcm_cpri_port_interrupt_callback_t */ 322 typedef void 323 (*_shr_cpri_port_interrupt_callback_t)(int unit, int port, 324 _shr_cpri_intr_info_t *data, 325 void *userdata); 326 327 typedef enum _shr_cpri_fec_ts_source_e { 328 _shrCpriFecTsSource66b, 329 _shrCpriFecTsSource257b 330 } _shr_cpri_fec_ts_source_t; 331 332 typedef enum _shr_cpri_fec_aux_config_e { 333 _shrCpriFecAuxConfigScrambleBypassTx, 334 _shrCpriFecAuxConfigDescrambleBypassRx, 335 _shrCpriFecAuxConfigBypassIndicationEnable, 336 _shrCpriFecAuxConfigBypassCorrectionEnable, 337 _shrCpriFecAuxConfigCorruptAlternateBlocksEnable, 338 _shrCpriFecAuxConfigSymbolErrorCorruptEnable, 339 _shrCpriFecAuxConfigSymbolErrorTmrPeriod, 340 _shrCpriFecAuxConfigSymbolErrCntThreshold, 341 _shrCpriFecAuxConfigSetSymbErrWindow128, 342 _shrCpriFecAuxConfigGboxTickDenominator, 343 _shrCpriFecAuxConfigGboxTickNumerator, 344 _shrCpriFecAuxConfigSoftReset 345 } _shr_cpri_fec_aux_config_t; 346 347 typedef struct _shr_cpri_fec_timestamp_config_e{ 348 int enable; 349 _shr_cpri_fec_ts_source_t fec_fifo_ts_source_select; /* 66 or 257 */ 350 _shr_cpri_fec_ts_source_t fec_cmic_ts_source_select; /* 66 or 257 */ 351 uint32 control_bit_offset_0; 352 uint32 control_bit_offset_1; 353 uint32 control_bit_offset_2; 354 uint32 control_bit_offset_3; 355 } _shr_cpri_fec_timestamp_config_t; 356 357 /* ECC related enums */ 358 typedef enum _shr_cpri_ecc_err_type_s { 359 _shrCpriEccErrTypeNone, 360 _shrCpriEccErrType1Bit, 361 _shrCpriEccErrType2Bit, 362 _shrCpriEccErrTypeMultiBit, 363 _shrCpriEccErrTypeCount 364 }_shr_cpri_ecc_err_type_t; 365 366 /* RoE frame format */ 367 typedef enum _shr_cpri_roe_frame_format_s { 368 _shrCpriRoeFrameFormatIEEE1914, 369 _shrCpriRoeFrameFormatRsvd3, 370 _shrCpriRoeFrameFormatEcpri8, 371 _shrCpriRoeFrameFormatEcpri12, 372 _shrCpriRoeFrameFormatCount 373 }_shr_cpri_roe_frame_format_t; 374 375 /* RoE Order Info Type .orderInfoType */ 376 typedef enum _shr_cpri_roe_ordering_info_option_s { 377 _shrCpriRoeOrderingInfoOptionSeqNum, 378 _shrCpriRoeOrderingInfoOptionTimestamp, 379 _shrCpriRoeOrderingInfoOptionCount 380 }_shr_cpri_roe_ordering_info_option_t; 381 382 /* Field IDs for CPRI_ENCAP_HDR_FLD_MAPPING */ 383 #define CPRIF_ENCAP_HEADER_FIELD_ID_SUBTYPE 0 384 #define CPRIF_ENCAP_HEADER_FIELD_ID_FLOW_ID 1 385 #define CPRIF_ENCAP_HEADER_FIELD_ID_LENGTH_15_8 2 386 #define CPRIF_ENCAP_HEADER_FIELD_ID_LENGTH_7_0 3 387 #define CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_32_24 4 388 #define CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_23_16 5 389 #define CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_15_8 6 390 #define CPRIF_ENCAP_HEADER_FIELD_ID_ORDER_INFO_7_0 7 391 #define CPRIF_ENCAP_HEADER_FIELD_ID_OPCODE 8 392 #define CPRIF_ENCAP_HEADER_FIELD_ID_UNMAPPED 0xf 393 394 /* Encap RoE Header Field. */ 395 typedef enum _shr_cpri_roe_header_field_e { 396 _shrCpriRoeHeaderFieldSubType, /* Subtype */ 397 _shrCpriRoeHeaderFieldFlowID, /* Flow ID */ 398 _shrCpriRoeHeaderFieldLength_15_8, /* Length 15:8 */ 399 _shrCpriRoeHeaderFieldLength_7_0, /* Length 7:0 */ 400 _shrCpriRoeHeaderFieldOrderInfo_32_24, /* OrderInfo 32:24 */ 401 _shrCpriRoeHeaderFieldOrderInfo_23_16, /* OrderInfo 23:16 */ 402 _shrCpriRoeHeaderFieldOrderInfo_15_8, /* OrderInfo 15:8 */ 403 _shrCpriRoeHeaderFieldOrderInfo_7_0, /* OrderInfo 7:0 */ 404 _shrCpriRoeHeaderFieldOpcode, /* Opcode */ 405 _shrCpriRoeHeaderFieldUnmapped /* Unmapped */ 406 } _shr_cpri_roe_header_field_t; 407 408 /* Decap RoE Header Field. */ 409 typedef enum _shr_cpri_ecpri_header_field_e { 410 _shrCpriEcpriHeaderFieldByte0, /* Header Byte 0 */ 411 _shrCpriEcpriHeaderFieldByte1, /* Header Byte 1 */ 412 _shrCpriEcpriHeaderFieldByte2, /* Header Byte 2 */ 413 _shrCpriEcpriHeaderFieldByte3, /* Header Byte 3 */ 414 _shrCpriEcpriHeaderFieldByte4, /* Header Byte 4 */ 415 _shrCpriEcpriHeaderFieldByte5, /* Header Byte 5 */ 416 _shrCpriEcpriHeaderFieldByte6, /* Header Byte 6 */ 417 _shrCpriEcpriHeaderFieldByte7, /* Header Byte 7 */ 418 _shrCpriEcpriHeaderFieldByte8, /* Header Byte 8 */ 419 _shrCpriEcpriHeaderFieldByte9, /* Header Byte 9 */ 420 _shrCpriEcpriHeaderFieldByte10, /* Header Byte 10 */ 421 _shrCpriEcpriHeaderFieldByte11, /* Header Byte 11 */ 422 423 _shrCpriEcpriHeaderFieldVlan0Byte0, /* VLAN0 Byte 0 */ 424 _shrCpriEcpriHeaderFieldVlan0Byte1, /* VLAN0 Byte 1 */ 425 _shrCpriEcpriHeaderFieldVlan1Byte0, /* VLAN1 Byte 0 */ 426 _shrCpriEcpriHeaderFieldVlan1Byte1 /* VLAN1 Byte 1 */ 427 } _shr_cpri_ecpri_header_field_t; 428 #endif /* !_SHR_CPRI_H */ 429