iproc_m0ssq.h (4982B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: iproc_m0ssq.h 8 * Purpose: iproc M0SSQ read and write tcam and sram from M0 and host. 9 */ 10 #ifndef __IPROC_M0SSQ_H__ 11 #define __IPROC_M0SSQ_H__ 12 #ifndef CMICX_FW_BUILD 13 #include <soc/iproc.h> 14 #include <sal/core/thread.h> 15 #endif 16 #if defined(BCM_CMICX_SUPPORT) || defined(CMICX_FW_BUILD) 17 18 #define IPROC_MDIO_SYS_BASE_HX5 0x10019000 19 #define MIIM_PHY_LINK_STATUS0_OFFSET_HX5 0x174 20 #define IPROC_MDIO_SYS_BASE 0x1319000 21 #define MIIM_PHY_LINK_STATUS0_OFFSET 0x174 22 #define M0SSQ_RESET_ENABLE 1 23 #ifdef CMICX_FW_BUILD 24 #define IPROC_M0SSQ_SRAM_BASE 0x1340000 25 #define IPROC_M0SSQ_SRAM_SIZE (128 * 1024) 26 #define IPROC_M0SSQ_SRAM_BASE_HX5 0x10040000 27 #define IPROC_M0SSQ_SRAM_SIZE_HX5 (128 * 1024) 28 #define IPROC_M0SSQ_TCAM_BASE_HX5 0x10000000 29 #define IPROC_M0SSQ_TCAM_SIZE_HX5 (32 * 1024) 30 #define IPROC_M0SSQ_TCAM_BASE 0x0000 31 #define IPROC_M0SSQ_TCAM_SIZE (32 * 1024) 32 #define IPROC_M0SSQ_CORE_OFFSET 0x10000 33 #define IPROC_M0SSQ_PERCORE_REGBASE 0x8000 34 #define IPROC_M0SSQ_PERCORE_PRIPORT_BASE 0x9000 35 #else 36 #define IPROC_M0SSQ_SRAM_BASE_HX5 0x10040000 37 #define IPROC_M0SSQ_SRAM_SIZE_HX5 (128 * 1024) 38 #define IPROC_M0SSQ_SRAM_BASE 0x1340000 39 #define IPROC_M0SSQ_SRAM_SIZE (128 * 1024) 40 #define IPROC_M0SSQ_TCAM_BASE_HX5 0x10000000 41 #define IPROC_M0SSQ_TCAM_SIZE_HX5 (32 * 1024) 42 #define IPROC_M0SSQ_TCAM_BASE 0x1300000 43 #define IPROC_M0SSQ_TCAM_SIZE (32 * 1024) 44 #define IPROC_M0SSQ_PERCORE_OFFSET 0x10000 45 #define IPROC_M0SSQ_PERCORE_REGBASE 0x1380000 46 #define IPROC_M0SSQ_PERCORE_PRIPORT_BASE 0x1390000 47 #endif /* CMICX_FW_BUILD */ 48 49 #define MAX_UCORES 4 50 51 typedef struct { 52 53 /* Device unit number. */ 54 int unit; 55 56 /* Base address of shared memory. */ 57 uint32 base; 58 59 /* Size of shared memory. */ 60 uint32 size; 61 62 } soc_iproc_m0ssq_shmem_t; 63 64 65 #ifndef CMICX_FW_BUILD 66 extern uint32 soc_iproc_percore_membase_get(int unit, int ucnum); 67 extern uint32 soc_iproc_sram_membase_get(int unit); 68 69 typedef struct { 70 VOL sal_thread_t thread_pid; /* Cortex-M0 pid */ 71 char thread_name[16]; 72 VOL sal_usecs_t thread_interval; 73 uint32 flags; 74 sal_sem_t event_sema; 75 } soc_iproc_m0ssq_control_t; 76 77 #define IPROC_M0SSQ_THREAD_INTERVAL 150 78 #define IPROC_M0SSQ_THREAD_PRI 50 79 80 /* Macros for passing unit + ucore numbers to the threads */ 81 #define M0SSQ_ENCODE_UNIT_UCORE(unit, ucore) INT_TO_PTR((unit) << 16 | (ucore)) 82 #define M0SSQ_DECODE_UNIT(val) ((int)(PTR_TO_INT(val) >> 16)) 83 #define M0SSQ_DECODE_UCORE(val) ((int)(PTR_TO_INT(val) & 0xffff)) 84 85 86 static __inline__ void soc_m0ssq_tcam_write32(int unit, int ucnum, int offset, uint32 val) 87 { 88 uint32 base; 89 90 base = soc_iproc_percore_membase_get(unit, ucnum); 91 soc_iproc_setreg(unit, (base + offset), val); 92 } 93 94 static __inline__ uint32 soc_m0ssq_tcam_read32(int unit, int ucnum, int offset) 95 { 96 uint32 base; 97 uint32 val; 98 99 base = soc_iproc_percore_membase_get(unit, ucnum); 100 soc_iproc_getreg(unit, (base + offset), &val); 101 return val; 102 } 103 104 static __inline__ void soc_m0ssq_sram_write32(int unit, int offset, uint32 val) 105 { 106 uint32 base; 107 108 base = soc_iproc_sram_membase_get(unit); 109 soc_iproc_setreg(unit, (base + offset), val); 110 } 111 112 static __inline__ uint32 soc_m0ssq_sram_read32(int unit, int offset) 113 { 114 uint32 base; 115 uint32 val; 116 117 base = soc_iproc_sram_membase_get(unit); 118 soc_iproc_getreg(unit, (base + offset), &val); 119 return val; 120 } 121 /* APIs */ 122 extern int soc_iproc_m0ssq_init(int unit); 123 extern int soc_iproc_m0ssq_exit(int unit); 124 extern void soc_iproc_m0ssq_reset(int unit, int enable); 125 extern int soc_iproc_m0_init(int unit); 126 extern int soc_iproc_m0_exit(int unit); 127 extern int soc_iproc_m0ssq_shmem_get(int unit, char *name, soc_iproc_m0ssq_shmem_t **shmem); 128 extern int soc_iproc_m0ssq_shmem_write32(soc_iproc_m0ssq_shmem_t *shmem, 129 uint32 offset, uint32 value); 130 extern int soc_iproc_m0ssq_shmem_read32(soc_iproc_m0ssq_shmem_t *shmem, 131 uint32 offset, uint32 *value); 132 extern int soc_iproc_m0ssq_shmem_clear(soc_iproc_m0ssq_shmem_t *shmem); 133 #else 134 extern int soc_iproc_m0ssq_shmem_get(char *name, soc_iproc_m0ssq_shmem_t **shmem); 135 extern int soc_iproc_m0ssq_shmem_write32(soc_iproc_m0ssq_shmem_t *shmem, 136 uint32 offset, uint32 value); 137 extern int soc_iproc_m0ssq_shmem_read32(soc_iproc_m0ssq_shmem_t *shmem, 138 uint32 offset, uint32 *value); 139 #endif /* !CMICX_FW_BUILD */ 140 #endif /*defined(BCM_CMICX_SUPPORT) | defined(CMICX_FW_BUILD)*/ 141 #endif /*__IPROC_M0SSQ_H__ */