iproc_fwconfig.h (4862B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: iproc_fwconfig.h 8 * Purpose: iproc M0SSQ resource configuration to run application on M0SSQ 9 */ 10 #ifndef __IPROC_FWCONFIG_H__ 11 #define __IPROC_FWCONFIG_H__ 12 13 /*Per ucore register offsets*/ 14 /* Store ucnum for each ucore at last 15 * 4 bytes of Code segment 16 */ 17 #define CPU_ID_OFFSET 0x3FFC 18 #define DEVID_ID_OFFSET 0x37F0 19 20 /*Registers defined in M0SSQ shmem*/ 21 #define U0_MBOX_BASE_OFFSET 0x0 22 #define U0_MBOX_SIZE_OFFSET 0x4 23 #define U1_MBOX_BASE_OFFSET 0x8 24 #define U1_MBOX_SIZE_OFFSET 0xc 25 #define U2_MBOX_BASE_OFFSET 0x10 26 #define U2_MBOX_SIZE_OFFSET 0x14 27 #define U3_MBOX_BASE_OFFSET 0x18 28 #define U3_MBOX_SIZE_OFFSET 0x1c 29 #define MBOX_INTERRUPT_MODE_OFFSET 0x20 30 #define MAX_IPROC_MBOX_PER_CORE_OFFSET 0x24 31 32 #define MAX_IPROC_MBOX_TYPES 2 33 #define M0SSQ_SHMEM_SIZE (128 * 1024) 34 #define M0SSQ_SRAM_FWREG_SIZE 256 35 #define M0SSQ_SHMEM_MBOX_BASE (IPROC_M0SSQ_SRAM_BASE + M0SSQ_SRAM_FWREG_SIZE) 36 37 /******************************************************************************/ 38 /* Following are the configurable per unit parameters based on application requirement */ 39 #define M0SSQ_SHMEM_MBOX_SIZE (4096*4) 40 #define MAX_UCORES_ENABLED 1 41 #define MAX_IPROC_MBOX_SHIFT 2 42 #define NUM_MBOX_PER_UCORE (1 << MAX_IPROC_MBOX_SHIFT) 43 #define MAX_IPROC_MBOX_MASK ((1 << MAX_IPROC_MBOX_SHIFT) - 1) 44 #define U0_MAX_MBOXS 2 45 #define U1_MAX_MBOXS 0 46 #define U2_MAX_MBOXS 0 47 #define U3_MAX_MBOXS 0 48 #define MBOX_INTERRUPT_ENABLE 0 49 50 #if (U0_MAX_MBOXS > NUM_MBOX_PER_UCORE) 51 #error "IPROC Mbox Configuration Error : U0_MAX_MBOXS > NUM_MBOX_PER_UCORE" 52 #endif /* (U0_MAX_MBOXS > NUM_MBOX_PER_UCORE) */ 53 54 #if (U1_MAX_MBOXS > NUM_MBOX_PER_UCORE) 55 #error "IPROC Mbox Configuration Error : U0_MAX_MBOXS > NUM_MBOX_PER_UCORE" 56 #endif /* (U1_MAX_MBOXS > NUM_MBOX_PER_UCORE) */ 57 58 #if ((M0SSQ_SHMEM_MBOX_SIZE * MAX_UCORES_ENABLED * MAX_IPROC_MBOX_TYPES) > (M0SSQ_SHMEM_SIZE - M0SSQ_SRAM_FWREG_SIZE)) 59 #error "IPROC Mbox Configuration Error : Mailbox size exceeding the total SRAM size" 60 #endif /* M0SSQ_SHMEM_MBOX_SIZE */ 61 /******************************************************************************/ 62 63 #ifndef CMICX_FW_BUILD 64 #define MAX_IPROC_MBOXS (NUM_MBOX_PER_UCORE * MAX_UCORES) 65 #define HOST_TO_LE32(data) htol32(data) 66 #define LE32_TO_HOST(data) ltoh32(data) 67 68 #define LOCK_FOREVER sal_mutex_FOREVER 69 #define RESOURCE_LOCK(lock, timeout) sal_mutex_take(lock, timeout) 70 #define RESOURCE_UNLOCK(lock) sal_mutex_give(lock) 71 #define soc_iproc_alloc(size) sal_alloc(size, "Iproc buffer") 72 #define soc_iproc_free(ptr) sal_free(ptr) 73 #define soc_iproc_memcpy memcpy 74 75 #else 76 #ifdef SOC_MAX_NUM_DEVICES 77 #undef SOC_MAX_NUM_DEVICES 78 #define SOC_MAX_NUM_DEVICES 1 79 #endif 80 81 #define MAX_IPROC_MBOXS (NUM_MBOX_PER_UCORE * MAX_UCORES) 82 #define HOST_TO_LE32(data) (data) 83 #define LE32_TO_HOST(data) (data) 84 85 #define LOCK_FOREVER 1 86 #define RESOURCE_LOCK(lock, timeout) { } 87 #define RESOURCE_UNLOCK(lock) { } 88 #define soc_iproc_alloc malloc 89 #define soc_iproc_free free 90 #define soc_iproc_memcpy memcpy 91 92 #define WRITE_UCORE_NUM(ucnum) soc_m0ssq_tcam_write32(CPU_ID_OFFSET, ucnum) 93 #define WRITE_MBOX_BASE(ucnum, val) soc_m0ssq_sram_write32((U0_MBOX_BASE_OFFSET + (ucnum * 8)), val) 94 #define WRITE_MBOX_SIZE(ucnum, val) soc_m0ssq_sram_write32((U0_MBOX_SIZE_OFFSET + (ucnum * 8)), val) 95 #define GET_UCORE_NUM() soc_m0ssq_tcam_read32(CPU_ID_OFFSET) 96 #define GET_MBOX_BASE(ucnum) soc_m0ssq_sram_read32(U0_MBOX_BASE_OFFSET + (ucnum * 8)) 97 #define GET_MBOX_SIZE(ucnum) soc_m0ssq_sram_read32(U0_MBOX_SIZE_OFFSET + (ucnum * 8)) 98 #endif /* !CMICX_FW_BUILD */ 99 100 #define UC_APPID_SHIFT 8 101 #define UC_APPID_MASK MAX_IPROC_MBOX_MASK 102 #define UC_APPID(ucnum, app_id) ((ucnum << UC_APPLICATION_ID_SHIFT) | (app_id & UC_APPLICATION_ID_MASK)) 103 #define UC_APPID_TO_UCNUM(uc_app_id) (uc_app_id >> UC_APPID_SHIFT) 104 #define UC_APPID_TO_MBOX(uc_app_id) (uc_app_id & UC_APPID_MASK) 105 106 /* Application IDs */ 107 typedef enum soc_iproc_u0m0_apps_e { 108 U0_LED_APP = 0, 109 U0_LINKSCAN_APP = 1 110 } soc_iproc_u0m0_apps_t; 111 112 typedef enum soc_iproc_u1m0_apps_e { 113 U1_LINKSCAN_APP = 0 114 } soc_iproc_u1m0_apps_t; 115 #endif /* __IPROC_FWCONFIG_H__ */