gdpll_shared.h (5897B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: gdpll_shared.h 8 * Purpose: Shared GDPLL header file between M7 and the host 9 */ 10 11 #ifndef __BCM_INT_GDPLL_SHARED_H__ 12 #define __BCM_INT_GDPLL_SHARED_H__ 13 14 #if defined(INCLUDE_GDPLL) 15 16 /* M7 DTCM region references */ 17 #define DPLL_ALIVE_SIZE 4 /* This is the M7 Alive Indication */ 18 #define DPLL_FW_VERSION_SIZE 40 /* This is the M7 version size */ 19 #define DPLL_DEBUG_ENABLE_SIZE 4 /* This is the M7 switch for debug push */ 20 #define DPLL_PARAM_SIZE 236 /* This size is given to accomodate max 3 states */ 21 #define DPLL_GENERIC_SIZE (1024*2) 22 23 /* For any offset that gets added for versioning, etc */ 24 #define DPLL_ALIVE_OFFSET 0 /* This is the M7 Alive Indication */ 25 #define DPLL_FW_VERSION_OFFSET (DPLL_ALIVE_OFFSET + DPLL_ALIVE_SIZE) /* This is the M7 version start */ 26 #define DPLL_BCN_UPDATE_LOC (DPLL_FW_VERSION_OFFSET + DPLL_FW_VERSION_SIZE) /* Location used by R5 and Host for BCN counter */ 27 #define DPLL_NTPTOD_UPDATE_LOC (DPLL_BCN_UPDATE_LOC + 4) /* Location used by R5 and Host for NTPTOD counter updates */ 28 #define DPLL_PTPTOD_UPDATE_LOC (DPLL_NTPTOD_UPDATE_LOC + 4) /* Location used by R5 and Host for PTPTOD counter updates */ 29 30 #define DPLL_DEBUG_ENABLE_OFFSET (DPLL_GENERIC_SIZE)/*200*/ /* This is the M7 switch for debug push */ 31 #define DPLL_PARAM_START_OFFSET (DPLL_DEBUG_ENABLE_OFFSET + DPLL_DEBUG_ENABLE_SIZE) 32 #define DPLL_CHAN_PARAM_ADDR(base, chan) \ 33 ((base + DPLL_PARAM_START_OFFSET) + (DPLL_PARAM_SIZE * chan)) 34 35 #define DPLL_VERSION_02 36 37 #if defined(DPLL_VERSION_01) 38 39 #define DPLL_DEBUG_MODE (0) /* Channel debug flag offset, start */ 40 /********************************************************** 41 * Following are per channel data structure offsets 42 * Refer dpllWrapper.h from the M7 firmware 43 */ 44 #define SIZEOF_DEBUGMODE (4) 45 #define SIZEOF_DPLLNUMSTATE (1) 46 #define SIZEOF_K1 (2) 47 #define SIZEOF_K1SHIFT (1) 48 #define SIZEOF_K1K2 (2) 49 #define SIZEOF_K1K2SHIFT (1) 50 #define SIZEOF_K1K3 (2) 51 #define SIZEOF_K1K3SHIFT (1) 52 #define SIZEOF_LOCKTHETHRE (4) 53 #define SIZEOF_DWELLCNT (1) 54 #define SIZEOF_PELTHR (8) 55 #define SIZEOF_FLLDEC (1) 56 #define SIZEOF_NCOBITS (1) 57 #define SIZEOF_PHASECNTREF (1) 58 #define SIZEOF_DUALLOOPFLAG (1) 59 #define SIZEOF_PHASECNTDELTA (8) 60 61 #define SIZEOF_STATE (1) 62 #define SIZEOF_LOOPF (8) 63 #define SIZEOF_DWELLCOUNTER (4) 64 #define SIZEOF_LOCKDETF (4) 65 #define SIZEOF_PERROR (8) 66 #define SIZEOF_FERROR (8) 67 #define SIZEOF_FLLCNT (1) 68 #define SIZEOF_1STLOOP (1) 69 #define SIZEOF_INITFLAG (1) 70 #define SIZEOF_PHASECNT (8) 71 72 /* DPLL Channel config offsets */ 73 #define DPLL_CONFIG_BASE_DPLLNUMSTATE (DPLL_DEBUG_MODE + SIZEOF_DEBUGMODE) 74 #define DPLL_CONFIG_BASE_K1 (DPLL_CONFIG_BASE_DPLLNUMSTATE + SIZEOF_DPLLNUMSTATE) 75 #define DPLL_CONFIG_BASE_K1SHIFT (DPLL_CONFIG_BASE_K1 + SIZEOF_K1 * BCM_GDPLL_NUM_STATES) 76 #define DPLL_CONFIG_BASE_K1K2 (DPLL_CONFIG_BASE_K1SHIFT + SIZEOF_K1SHIFT * BCM_GDPLL_NUM_STATES) 77 #define DPLL_CONFIG_BASE_K1K2SHIFT (DPLL_CONFIG_BASE_K1K2 + SIZEOF_K1K2 * BCM_GDPLL_NUM_STATES) 78 #define DPLL_CONFIG_BASE_K1K3 (DPLL_CONFIG_BASE_K1K2SHIFT + SIZEOF_K1K2SHIFT * BCM_GDPLL_NUM_STATES) 79 #define DPLL_CONFIG_BASE_K1K3SHIFT (DPLL_CONFIG_BASE_K1K3 + SIZEOF_K1K3 * BCM_GDPLL_NUM_STATES) 80 #define DPLL_CONFIG_BASE_LOCKTHETHRE (DPLL_CONFIG_BASE_K1K3SHIFT + SIZEOF_K1K3SHIFT * BCM_GDPLL_NUM_STATES) 81 #define DPLL_CONFIG_BASE_DWELLCNT (DPLL_CONFIG_BASE_LOCKTHETHRE + SIZEOF_LOCKTHETHRE * BCM_GDPLL_NUM_STATES) 82 #define DPLL_CONFIG_BASE_PELTHR_LOW (DPLL_CONFIG_BASE_DWELLCNT + SIZEOF_DWELLCNT * BCM_GDPLL_NUM_STATES) 83 #define DPLL_CONFIG_BASE_PELTHR_HIGH (DPLL_CONFIG_BASE_PELTHR_LOW + 4) 84 #define DPLL_CONFIG_BASE_FLLDEC (DPLL_CONFIG_BASE_PELTHR_LOW + SIZEOF_PELTHR * BCM_GDPLL_NUM_STATES) 85 #define DPLL_CONFIG_BASE_NCOBITS (DPLL_CONFIG_BASE_FLLDEC + SIZEOF_FLLDEC) 86 #define DPLL_CONFIG_BASE_PHASECNTREF (DPLL_CONFIG_BASE_NCOBITS + SIZEOF_NCOBITS) 87 #define DPLL_CONFIG_BASE_DUALLOOPFLAG (DPLL_CONFIG_BASE_PHASECNTREF + SIZEOF_PHASECNTREF) 88 #define DPLL_CONFIG_BASE_PHASECNTDELTA_LOW (DPLL_CONFIG_BASE_DUALLOOPFLAG + SIZEOF_DUALLOOPFLAG) 89 #define DPLL_CONFIG_BASE_PHASECNTDELTA_HIGH (DPLL_CONFIG_BASE_PHASECNTDELTA_LOW + 4) 90 91 /* DPLL Channel state offsets */ 92 #define DPLL_STATE_BASE_STATE (DPLL_CONFIG_BASE_PHASECNTDELTA_LOW + SIZEOF_PHASECNTDELTA) 93 #define DPLL_STATE_BASE_LOOPF_LOW (DPLL_STATE_BASE_STATE + SIZEOF_STATE) 94 #define DPLL_STATE_BASE_LOOPF_HIGH (DPLL_STATE_BASE_LOOPF_LOW + 4) 95 #define DPLL_STATE_BASE_DWELLCNT (DPLL_STATE_BASE_LOOPF_LOW + SIZEOF_LOOPF) 96 #define DPLL_STATE_BASE_LOCKDETF (DPLL_STATE_BASE_DWELLCNT + SIZEOF_DWELLCOUNTER) 97 #define DPLL_STATE_BASE_PERROR_LOW (DPLL_STATE_BASE_LOCKDETF + SIZEOF_LOCKDETF) 98 #define DPLL_STATE_BASE_PERROR_HIGH (DPLL_STATE_BASE_PERROR_LOW + 4) 99 #define DPLL_STATE_BASE_FERROR_LOW (DPLL_STATE_BASE_PERROR_LOW + SIZEOF_PERROR) 100 #define DPLL_STATE_BASE_FERROR_HIGH (DPLL_STATE_BASE_FERROR_LOW + 4) 101 #define DPLL_STATE_BASE_FLLCNT (DPLL_STATE_BASE_FERROR_LOW + SIZEOF_FERROR) 102 #define DPLL_STATE_BASE_1STLOOP (DPLL_STATE_BASE_FLLCNT + SIZEOF_FLLCNT) 103 #define DPLL_STATE_BASE_INITFLAG (DPLL_STATE_BASE_1STLOOP + SIZEOF_1STLOOP) 104 #define DPLL_STATE_BASE_PHASECNT_LOW (DPLL_STATE_BASE_INITFLAG + SIZEOF_INITFLAG) 105 #define DPLL_STATE_BASE_PHASECNT_HIGH (DPLL_STATE_BASE_PHASECNT_LOW + 4) 106 107 #endif /* DPLL_VERSION_01 */ 108 #endif /* INCLUDE_GDPLL */ 109 #endif /* __BCM_INT_GDPLL_SHARED_H__ */