gdpll.h (5421B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: gdpll.h 8 * Purpose: Internal GDPLL header 9 */ 10 11 #ifndef __BCM_INT_GDPLL_H__ 12 #define __BCM_INT_GDPLL_H__ 13 14 #if defined(INCLUDE_GDPLL) 15 16 #include <bcm/gdpll.h> 17 #include <bcm_int/esw/gdpll_shared.h> 18 19 /* Number of GDPLL input array locations */ 20 #define BCM_GDPLL_NUM_IA_ENTRIES 256 21 22 /* TBD - As per section 6.6, port events are from 0 to 191 and misc events 23 * start from 192 24 */ 25 #define BCM_GDPLL_NUM_INPUT_EVENTS 256 26 #define BCM_GDPLL_IA_START_TXPI_TXSOF 128 27 #define BCM_GDPLL_IA_START_MISC 192 28 #define BCM_GDPLL_IA_START_R5 214 29 30 #define GDPLL_DEBUGBUFF_LOCAL_COPY 31 #ifdef GDPLL_DEBUGBUFF_LOCAL_COPY 32 #define GDPLL_NUM_DEBUG_BUFFERS 2 33 #endif 34 35 36 #define bcmGdpllInputEventR5 23 37 #define bcmGdpllInputEventMax 24 38 39 /* M7 TCM region references 40 */ 41 #define BCM_M7_ITCM_BASE (0x3260000) 42 #define BCM_M7_DTCM_BASE (0x3264000) 43 44 /* Internal datastructure for event destination config */ 45 typedef struct gdpll_event_dest_cfg_s { 46 bcm_gdpll_event_dest_t event_dest; 47 int ts_counter; /* 0: TS0 1:TS1*/ 48 int ppm_check_enable; /* PPM check enable */ 49 } gdpll_event_dest_cfg_t; 50 51 /* Internal datastructure for gdpll channel */ 52 typedef struct dpll_chan_s { 53 uint32 flag; /* Channel flags */ 54 uint32 eventId_ref; /* Channel reference event */ 55 uint32 eventId_fb; /* Channel feedback event */ 56 int phaseConterRef; 57 }dpll_chan_t; 58 59 /* Internal datastructure for gdpll context */ 60 typedef struct gdpll_context_s { 61 /* Per dpll channel parameters */ 62 dpll_chan_t dpll_chan[BCM_GDPLL_NUM_CHANNELS]; 63 64 /* event_id array holds the Input array location for that event */ 65 int eventId[BCM_GDPLL_NUM_INPUT_EVENTS]; 66 sal_mutex_t mutex; 67 68 /* User callback for debug registry */ 69 bcm_gdpll_debug_cb debug_cb; 70 void *pUserData; 71 bcm_gdpll_cb gdpll_cb; 72 void *pGdpll_cb_data; 73 int gdpll_cb_type; 74 sal_sem_t debug_sem; 75 uint32 debugRdIdx; 76 77 }gdpll_context_t; 78 79 #if defined(DPLL_VERSION_02) 80 /* Per DPLL Configuration variables stored in state memory */ 81 typedef struct COMPILER_ATTRIBUTE((__packed__)) m7_gdpll_chan_dpll_config_s { 82 int32 K1[BCM_GDPLL_NUM_STATES]; 83 int8 K1Shift[BCM_GDPLL_NUM_STATES]; 84 int32 K1K2[BCM_GDPLL_NUM_STATES]; 85 int8 K1K2Shift[BCM_GDPLL_NUM_STATES]; 86 uint32 LockDetThres[BCM_GDPLL_NUM_STATES]; 87 uint32 LockIndicatorThresholdLo; 88 uint32 LockIndicatorThresholdHi; 89 uint16 DwellCount[BCM_GDPLL_NUM_STATES]; 90 uint64 PhaseErrorLimiterThres[BCM_GDPLL_NUM_STATES]; 91 uint8 NCObits; /* How many bits in NCO */ 92 uint8 PhaseCounterRef; /* use the phase counter instead of timestamp as reference input */ 93 uint8 DPLLNumOfStates; 94 uint16 IdumpMod[BCM_GDPLL_NUM_STATES]; 95 uint8 PhaseErrorShift; 96 int64 NominalLoopFilter; /* Nominal value of loop filter */ 97 uint8 InvertPhaseError; 98 uint8 NormalizePhaseError; /* remove full cycles of phase error */ 99 int32 NormPhaseErrorThres0; 100 int32 NormPhaseErrorThres1; 101 } m7_gdpll_chan_dpll_config_t; 102 103 /* Per DPLL state variables stored in state memory */ 104 typedef struct COMPILER_ATTRIBUTE((__packed__)) m7_gdpll_chan_dpll_state_s { 105 int64 Offset; 106 uint8 LockIndicator; /* Initialize to FALSE */ 107 uint8 LossOfLockIndicator; /* Initialize to FALSE */ 108 uint8 LargeErrorIndicator; /* Initialize to FALSE */ 109 uint8 PadByte1; /* Pad for aligned 32b access */ 110 uint8 HoldoverFlag; /* Initialize to FALSE. Used to get the DPLL into holdover */ 111 uint8 InitPhaseCounterFlag; /* Initialize to FALSE */ 112 uint8 InitOffsetFlag; /* Initialize to FALSE */ 113 uint8 PadByte2; /* Pad for aligned 32b access */ 114 uint8 DPLLState; 115 int64 LoopFilter; 116 uint32 DwellCounter; 117 uint32 LockDetFilter; 118 uint64 PhaseCounter; 119 uint64 PhaseCounterDelta; 120 uint16 PhaseCounterN; /* Initialize to 1 */ 121 uint16 PhaseCounterM; /* Initialize to 0 */ 122 uint16 PhaseCounterFrac; /* Initialize to 0 */ 123 uint16 IdumpCounter; /* Initialize to 0 */ 124 int64 AccumPhaseError; /* Initialize to 0 */ 125 int64 PrevIn0[2]; /* Initialize to 0 */ 126 int64 PrevIn1[2]; /* Initialize to 0 */ 127 uint8 LargeErrorCounter; 128 } m7_gdpll_chan_dpll_state_t; 129 130 /* Internal datastructure for dpll config */ 131 typedef struct COMPILER_ATTRIBUTE((__packed__)) m7_dpll_param_s { 132 int debugMode; 133 m7_gdpll_chan_dpll_state_t m7_dpll_state; 134 m7_gdpll_chan_dpll_config_t m7_dpll_config; 135 } m7_dpll_param_t; 136 #endif /* DPLL_VERSION_02 */ 137 138 /* Internal datastructure for dpll config */ 139 typedef struct dpll_param_s { 140 int debugMode; 141 bcm_gdpll_chan_dpll_config_t dpll_config; 142 bcm_gdpll_chan_dpll_state_t dpll_state; 143 } dpll_param_t; 144 145 #endif /* INCLUDE_GDPLL */ 146 #endif /* __BCM_INT_GDPLL_H__ */