port.h (332711B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 7 * 8 * DO NOT EDIT THIS FILE! 9 * This file is auto-generated. 10 * Edits to this file will be lost when it is regenerated. 11 */ 12 13 #ifndef __BCM_PORT_H__ 14 #define __BCM_PORT_H__ 15 16 #include <shared/portmode.h> 17 #include <shared/port.h> 18 #include <shared/phyconfig.h> 19 #include <shared/phyreg.h> 20 #include <shared/switch.h> 21 #include <bcm/types.h> 22 #include <bcm/stat.h> 23 #include <shared/port_ability.h> 24 25 #define BCM_PIPES_MAX _SHR_SWITCH_MAX_PIPES 26 27 #define BCM_PORT_WIDE_DATA_WIDTH 57 28 29 #define BCM_PORT_WIDE_DATA_STRENGTH_SET(_data, _strength) \ 30 COMPILER_64_SET(_data,( (_strength ) ? ( COMPILER_64_HI(_data) | (1 << ((BCM_PORT_WIDE_DATA_WIDTH -1) -32))) : (COMPILER_64_HI(_data) & ~( 1 << ((BCM_PORT_WIDE_DATA_WIDTH -1) -32)))) ,COMPILER_64_LO(_data)) 31 32 #define BCM_PORT_WIDE_DATA_STRENGTH_GET(_data) \ 33 (COMPILER_64_HI(_data) >> ((BCM_PORT_WIDE_DATA_WIDTH -1) -32) ) 34 35 /* Port Configuration structure. */ 36 typedef struct bcm_port_config_s { 37 bcm_pbmp_t fe; /* Mask of FE ports. */ 38 bcm_pbmp_t ge; /* Mask of GE ports. */ 39 bcm_pbmp_t xe; /* Mask of 10gig ports. */ 40 bcm_pbmp_t ce; /* Mask of 100gig ports. */ 41 bcm_pbmp_t le; /* Mask of 50gig ports. */ 42 bcm_pbmp_t cc; /* Mask of 200gig ports. */ 43 bcm_pbmp_t cd; /* Mask of 400gig ports. */ 44 bcm_pbmp_t e; /* Mask of eth ports. */ 45 bcm_pbmp_t hg; /* Mask of Higig ports. */ 46 bcm_pbmp_t sci; /* Mask of SCI ports. */ 47 bcm_pbmp_t sfi; /* Mask of SFI ports. */ 48 bcm_pbmp_t spi; /* Mask of SPI ports. */ 49 bcm_pbmp_t spi_subport; /* Mask of SPI subports. */ 50 bcm_pbmp_t port; /* Mask of all front panel ports. */ 51 bcm_pbmp_t cpu; /* Mask of CPU ports. */ 52 bcm_pbmp_t all; /* Mask of all ports. */ 53 bcm_pbmp_t stack_int; /* Deprecated - unused. */ 54 bcm_pbmp_t stack_ext; /* Mask of Stack ports. */ 55 bcm_pbmp_t tdm; /* Mask of TDM ports. */ 56 bcm_pbmp_t pon; /* Mask of PON ports. */ 57 bcm_pbmp_t llid; /* Mask of LLID ports. */ 58 bcm_pbmp_t il; /* Mask of ILKN ports. */ 59 bcm_pbmp_t xl; /* Mask of XLAUI ports. */ 60 bcm_pbmp_t rcy; /* Mask of RECYCLE ports. */ 61 bcm_pbmp_t sat; /* Mask of SAT ports. */ 62 bcm_pbmp_t ipsec; /* Mask of IPSEC ports. */ 63 bcm_pbmp_t per_pipe[BCM_PIPES_MAX]; /* Mask of ports per pipe. The number of 64 pipes per device can be obtained via 65 num_pipes field of bcm_info_t. */ 66 bcm_pbmp_t nif; /* Mask of Network Interfaces ports. */ 67 bcm_pbmp_t control; /* Mask of hot swap controlling ports. */ 68 bcm_pbmp_t eventor; /* Mask of Eventor ports. */ 69 bcm_pbmp_t olp; /* Mask of OLP ports. */ 70 bcm_pbmp_t oamp; /* Mask of OAMP ports. */ 71 bcm_pbmp_t erp; /* Mask of ERP ports. */ 72 bcm_pbmp_t roe; /* Mask of ROE ports. */ 73 bcm_pbmp_t rcy_mirror; /* Mask of mirror recycle ports (sniff) */ 74 } bcm_port_config_t; 75 76 /* Port destination info structure. */ 77 typedef struct bcm_port_dest_info_s { 78 uint32 flags; /* Future expansion. */ 79 bcm_gport_t gport; /* e.g. sysport gport, unicast gport, multicast gport, 80 etc... */ 81 bcm_cos_t priority; /* Traffic class (0-7). */ 82 bcm_color_t dp; /* Drop precedence (0-3). */ 83 } bcm_port_dest_info_t; 84 85 /* Port ability */ 86 typedef _shr_port_ability_t bcm_port_ability_t; 87 88 #define BCM_PORT_ABILITY_10MB _SHR_PA_SPEED_10MB 89 #define BCM_PORT_ABILITY_100MB _SHR_PA_SPEED_100MB 90 #define BCM_PORT_ABILITY_1000MB _SHR_PA_SPEED_1000MB 91 #define BCM_PORT_ABILITY_2500MB _SHR_PA_SPEED_2500MB 92 #define BCM_PORT_ABILITY_3000MB _SHR_PA_SPEED_3000MB 93 #define BCM_PORT_ABILITY_5000MB _SHR_PA_SPEED_5000MB 94 #define BCM_PORT_ABILITY_6000MB _SHR_PA_SPEED_6000MB 95 #define BCM_PORT_ABILITY_10GB _SHR_PA_SPEED_10GB 96 #define BCM_PORT_ABILITY_11GB _SHR_PA_SPEED_11GB 97 #define BCM_PORT_ABILITY_12GB _SHR_PA_SPEED_12GB 98 #define BCM_PORT_ABILITY_12P5GB _SHR_PA_SPEED_12P5GB 99 #define BCM_PORT_ABILITY_13GB _SHR_PA_SPEED_13GB 100 #define BCM_PORT_ABILITY_15GB _SHR_PA_SPEED_15GB 101 #define BCM_PORT_ABILITY_16GB _SHR_PA_SPEED_16GB 102 #define BCM_PORT_ABILITY_20GB _SHR_PA_SPEED_20GB 103 #define BCM_PORT_ABILITY_21GB _SHR_PA_SPEED_21GB 104 #define BCM_PORT_ABILITY_23GB _SHR_PA_SPEED_23GB 105 #define BCM_PORT_ABILITY_24GB _SHR_PA_SPEED_24GB 106 #define BCM_PORT_ABILITY_25GB _SHR_PA_SPEED_25GB 107 #define BCM_PORT_ABILITY_27GB _SHR_PA_SPEED_27GB 108 #define BCM_PORT_ABILITY_30GB _SHR_PA_SPEED_30GB 109 #define BCM_PORT_ABILITY_32GB _SHR_PA_SPEED_32GB 110 #define BCM_PORT_ABILITY_40GB _SHR_PA_SPEED_40GB 111 #define BCM_PORT_ABILITY_42GB _SHR_PA_SPEED_42GB 112 #define BCM_PORT_ABILITY_48GB _SHR_PA_SPEED_48GB 113 #define BCM_PORT_ABILITY_50GB _SHR_PA_SPEED_50GB 114 #define BCM_PORT_ABILITY_53GB _SHR_PA_SPEED_53GB 115 #define BCM_PORT_ABILITY_100GB _SHR_PA_SPEED_100GB 116 #define BCM_PORT_ABILITY_106GB _SHR_PA_SPEED_106GB 117 #define BCM_PORT_ABILITY_120GB _SHR_PA_SPEED_120GB 118 #define BCM_PORT_ABILITY_127GB _SHR_PA_SPEED_127GB 119 #define BCM_PORT_ABILITY_INTERFACE_TBI _SHR_PA_INTF_TBI 120 #define BCM_PORT_ABILITY_INTERFACE_MII _SHR_PA_INTF_MII 121 #define BCM_PORT_ABILITY_INTERFACE_GMII _SHR_PA_INTF_GMII 122 #define BCM_PORT_ABILITY_INTERFACE_SGMII _SHR_PA_INTF_SGMII 123 #define BCM_PORT_ABILITY_INTERFACE_XGMII _SHR_PA_INTF_XGMII 124 #define BCM_PORT_ABILITY_INTERFACE_QSGMII _SHR_PA_INTF_QSGMII 125 #define BCM_PORT_ABILITY_INTERFACE_CGMII _SHR_PA_INTF_CGMII 126 #define BCM_PORT_ABILITY_MEDIUM_COPPER _SHR_PA_MEDIUM_COPPER 127 #define BCM_PORT_ABILITY_MEDIUM_FIBER _SHR_PA_MEDIUM_FIBER 128 #define BCM_PORT_ABILITY_MEDIUM_BACKPLANE _SHR_PA_MEDIUM_BACKPLANE 129 #define BCM_PORT_ABILITY_LB_NONE _SHR_PA_LB_NONE 130 #define BCM_PORT_ABILITY_LB_MAC _SHR_PA_LB_MAC 131 #define BCM_PORT_ABILITY_LB_PHY _SHR_PA_LB_PHY 132 #define BCM_PORT_ABILITY_LB_LINE _SHR_PA_LB_LINE 133 #define BCM_PORT_ABILITY_AUTONEG _SHR_PA_AUTONEG 134 #define BCM_PORT_ABILITY_COMBO _SHR_PA_COMBO 135 #define BCM_PORT_ABILITY_PAUSE_TX _SHR_PA_PAUSE_TX 136 #define BCM_PORT_ABILITY_PAUSE_RX _SHR_PA_PAUSE_RX 137 #define BCM_PORT_ABILITY_PAUSE _SHR_PA_PAUSE /* Both TX and RX. */ 138 #define BCM_PORT_ABILITY_PAUSE_ASYMM _SHR_PA_PAUSE_ASYMM /* The following is used 139 only by 140 bcm_port_ability_get, 141 and indicates that a 142 port can support 143 having PAUSE_TX be 144 different than 145 PAUSE_RX. */ 146 #define BCM_PORT_ABILITY_FEC_NONE _SHR_PA_FEC_NONE /* No FEC request */ 147 #define BCM_PORT_ABILITY_FEC_CL74 _SHR_PA_FEC_CL74 /* FEC CL74 request. */ 148 #define BCM_PORT_ABILITY_FEC_CL91 _SHR_PA_FEC_CL91 /* FEC CL91 request. */ 149 #define BCM_PORT_ABILITY_EEE_100MB_BASETX _SHR_PA_EEE_100MB_BASETX /* EEE ability at 150 100M-BaseTX. */ 151 #define BCM_PORT_ABILITY_EEE_1GB_BASET _SHR_PA_EEE_1GB_BASET /* EEE ability at 152 1G-BaseT. */ 153 #define BCM_PORT_ABILITY_EEE_10GB_BASET _SHR_PA_EEE_10GB_BASET /* EEE ability at 154 10G-BaseT. */ 155 #define BCM_PORT_ABILITY_EEE_10GB_KX _SHR_PA_EEE_10GB_KX /* EEE ability at 156 10GB-KX. */ 157 #define BCM_PORT_ABILITY_EEE_10GB_KX4 _SHR_PA_EEE_10GB_KX4 /* EEE ability at 158 10GB-KX4. */ 159 #define BCM_PORT_ABILITY_EEE_10GB_KR _SHR_PA_EEE_10GB_KR /* EEE ability at 160 10GB-KR. */ 161 #define BCM_PORT_ABILITY_CHANNEL_LONG _SHR_PA_CHANNEL_LONG /* port is long channel. */ 162 #define BCM_PORT_ABILITY_CHANNEL_SHORT _SHR_PA_CHANNEL_SHORT /* port is short channel. */ 163 164 /* 165 * Port ability mask. 166 * 167 * The following flags are used to indicate which set of capabilities are 168 * provided by a PHY or MAC when retrieving the ability of a port, 169 * setting or getting the local advertisement, getting the remote 170 * advertisement, or setting the MAC encapsulation and/or CRC modes. 171 */ 172 typedef _shr_port_mode_t bcm_port_abil_t; 173 174 #define BCM_PORT_ABIL_10MB_HD _SHR_PM_10MB_HD 175 #define BCM_PORT_ABIL_10MB_FD _SHR_PM_10MB_FD 176 #define BCM_PORT_ABIL_100MB_HD _SHR_PM_100MB_HD 177 #define BCM_PORT_ABIL_100MB_FD _SHR_PM_100MB_FD 178 #define BCM_PORT_ABIL_1000MB_HD _SHR_PM_1000MB_HD 179 #define BCM_PORT_ABIL_1000MB_FD _SHR_PM_1000MB_FD 180 #define BCM_PORT_ABIL_2500MB_HD _SHR_PM_2500MB_HD 181 #define BCM_PORT_ABIL_2500MB_FD _SHR_PM_2500MB_FD 182 #define BCM_PORT_ABIL_3000MB_HD _SHR_PM_3000MB_HD 183 #define BCM_PORT_ABIL_3000MB_FD _SHR_PM_3000MB_FD 184 #define BCM_PORT_ABIL_10GB_HD _SHR_PM_10GB_HD 185 #define BCM_PORT_ABIL_10GB_FD _SHR_PM_10GB_FD 186 #define BCM_PORT_ABIL_12GB_HD _SHR_PM_12GB_HD 187 #define BCM_PORT_ABIL_12GB_FD _SHR_PM_12GB_FD 188 #define BCM_PORT_ABIL_13GB_HD _SHR_PM_13GB_HD 189 #define BCM_PORT_ABIL_13GB_FD _SHR_PM_13GB_FD 190 #define BCM_PORT_ABIL_16GB_HD _SHR_PM_16GB_HD 191 #define BCM_PORT_ABIL_16GB_FD _SHR_PM_16GB_FD 192 #define BCM_PORT_ABIL_TBI _SHR_PM_TBI 193 #define BCM_PORT_ABIL_MII _SHR_PM_MII 194 #define BCM_PORT_ABIL_GMII _SHR_PM_GMII 195 #define BCM_PORT_ABIL_SGMII _SHR_PM_SGMII 196 #define BCM_PORT_ABIL_XGMII _SHR_PM_XGMII 197 #define BCM_PORT_ABIL_LB_MAC _SHR_PM_LB_MAC 198 #define BCM_PORT_ABIL_LB_PHY _SHR_PM_LB_PHY 199 #define BCM_PORT_ABIL_LB_NONE _SHR_PM_LB_NONE 200 #define BCM_PORT_ABIL_AN _SHR_PM_AN 201 #define BCM_PORT_ABIL_COMBO _SHR_PM_COMBO 202 #define BCM_PORT_ABIL_PAUSE_TX _SHR_PM_PAUSE_TX 203 #define BCM_PORT_ABIL_PAUSE_RX _SHR_PM_PAUSE_RX 204 #define BCM_PORT_ABIL_PAUSE _SHR_PM_PAUSE /* Both TX and RX. */ 205 #define BCM_PORT_ABIL_10B BCM_PORT_ABIL_TBI /* Deprecated */ 206 #define BCM_PORT_ABIL_PAUSE_ASYMM _SHR_PM_PAUSE_ASYMM /* The following is used only by 207 bcm_port_ability_get, and 208 indicates that a port can 209 support having PAUSE_TX be 210 different than PAUSE_RX. */ 211 #define BCM_PORT_ABIL_10MB _SHR_PM_10MB 212 #define BCM_PORT_ABIL_100MB _SHR_PM_100MB 213 #define BCM_PORT_ABIL_1000MB _SHR_PM_1000MB 214 #define BCM_PORT_ABIL_2500MB _SHR_PM_2500MB 215 #define BCM_PORT_ABIL_3000MB _SHR_PM_3000MB 216 #define BCM_PORT_ABIL_10GB _SHR_PM_10GB 217 #define BCM_PORT_ABIL_12GB _SHR_PM_12GB 218 #define BCM_PORT_ABIL_13GB _SHR_PM_13GB 219 #define BCM_PORT_ABIL_16GB _SHR_PM_16GB 220 #define BCM_PORT_ABIL_HD _SHR_PM_HD 221 #define BCM_PORT_ABIL_FD _SHR_PM_FD 222 #define BCM_PORT_ABIL_SPD_ANY _SHR_PM_SPEED_ALL 223 224 #define BCM_PORT_ABIL_SPD_MAX(abil) \ 225 _SHR_PM_SPEED_MAX(abil) 226 227 #define BCM_PORT_ABILITY_SPEED_MAX(abil) _SHR_PA_SPEED_MAX(abil) 228 229 #define BCM_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_0 _SHR_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_0 230 #define BCM_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_1 _SHR_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_1 231 #define BCM_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_2 _SHR_PORT_CONTROL_FABRIC_HEADER_OBSOLETE_2 232 #define BCM_PORT_CONTROL_FABRIC_HEADER_CUSTOM _SHR_PORT_CONTROL_FABRIC_HEADER_CUSTOM 233 #define BCM_PORT_CONTROL_FABRIC_HEADER_88640_TM _SHR_PORT_CONTROL_FABRIC_HEADER_88640_TM 234 #define BCM_PORT_CONTROL_FABRIC_HEADER_88640_RAW _SHR_PORT_CONTROL_FABRIC_HEADER_88640_RAW 235 236 /* Port Management packet Classification flags. */ 237 #define BCM_PORT_MANAGEMENT_PACKET_ETHERTYPE 0x01 /* If set, ether type is 238 valid in the 239 configuration 240 structure. */ 241 #define BCM_PORT_MANAGEMENT_PACKET_DEST_MAC 0x02 /* If set, Destination 242 MAC is valid in the 243 configuration 244 structure. */ 245 #define BCM_PORT_MANAGEMENT_PACKET_CLEAR 0x80 /* If set, Destination 246 MAC and or Ethertype 247 to be cleared from 248 Management packet 249 classification. */ 250 251 /* Port Management Packet Classification Configuration structure. */ 252 typedef struct bcm_port_management_packet_config_s { 253 uint32 flags; /* See BCM_PORT_MANAGEMENT_XXX flag definitions. */ 254 bcm_ethertype_t ethertype; /* Ether Type for packet classification. */ 255 bcm_mac_t dest_mac; /* Destination mac address for packet 256 classification */ 257 } bcm_port_management_packet_config_t; 258 259 #ifndef BCM_HIDE_DISPATCHABLE 260 261 /* Initialize the port subsystem. */ 262 extern int bcm_port_init( 263 int unit); 264 265 /* 266 * Initialize the port subsystem without affecting the current state of 267 * stack ports. 268 */ 269 extern int bcm_port_clear( 270 int unit); 271 272 /* Probe the port to determine the proper MAC and PHY drivers. */ 273 extern int bcm_port_probe( 274 int unit, 275 bcm_pbmp_t pbmp, 276 bcm_pbmp_t *okay_pbmp); 277 278 /* Detach ports from the BCM API. */ 279 extern int bcm_port_detach( 280 int unit, 281 bcm_pbmp_t pbmp, 282 bcm_pbmp_t *detached); 283 284 /* 285 * Retrieved the port configuration for the specified device or for all 286 * ports known to bcmx. 287 */ 288 extern int bcm_port_config_get( 289 int unit, 290 bcm_port_config_t *config); 291 292 /* Enable or disable a port. */ 293 extern int bcm_port_enable_set( 294 int unit, 295 bcm_port_t port, 296 int enable); 297 298 /* Enable or disable a port. */ 299 extern int bcm_port_enable_get( 300 int unit, 301 bcm_port_t port, 302 int *enable); 303 304 /* Set or retrieve autonegotiation settings for a port. */ 305 extern int bcm_port_advert_set( 306 int unit, 307 bcm_port_t port, 308 bcm_port_abil_t ability_mask); 309 310 /* Set or retrieve autonegotiation settings for a port. */ 311 extern int bcm_port_ability_advert_set( 312 int unit, 313 bcm_port_t port, 314 bcm_port_ability_t *ability_mask); 315 316 /* Set or retrieve autonegotiation settings for a port. */ 317 extern int bcm_port_advert_get( 318 int unit, 319 bcm_port_t port, 320 bcm_port_abil_t *ability_mask); 321 322 /* Set or retrieve autonegotiation settings for a port. */ 323 extern int bcm_port_ability_advert_get( 324 int unit, 325 bcm_port_t port, 326 bcm_port_ability_t *ability_mask); 327 328 /* Set or retrieve autonegotiation settings for a port. */ 329 extern int bcm_port_advert_remote_get( 330 int unit, 331 bcm_port_t port, 332 bcm_port_abil_t *ability_mask); 333 334 /* Set or retrieve autonegotiation settings for a port. */ 335 extern int bcm_port_ability_remote_get( 336 int unit, 337 bcm_port_t port, 338 bcm_port_ability_t *ability_mask); 339 340 /* 341 * Retrieve the valid operating modes of a port including speed and 342 * duplex. 343 */ 344 extern int bcm_port_ability_get( 345 int unit, 346 bcm_port_t port, 347 bcm_port_abil_t *local_ability_mask); 348 349 /* 350 * Retrieve the valid operating modes of a port including speed and 351 * duplex. 352 */ 353 extern int bcm_port_ability_local_get( 354 int unit, 355 bcm_port_t port, 356 bcm_port_ability_t *local_ability_mask); 357 358 #endif /* BCM_HIDE_DISPATCHABLE */ 359 360 /* Backward compatibility. */ 361 #define bcm_port_remote_advert_get bcm_port_advert_remote_get 362 363 #ifndef BCM_HIDE_DISPATCHABLE 364 365 /* Set the Management Packet Classification properties. */ 366 extern int bcm_port_management_packet_config_set( 367 int unit, 368 bcm_port_t port, 369 bcm_port_management_packet_config_t *config); 370 371 /* Get Management Packet Classification properties. */ 372 extern int bcm_port_management_packet_config_get( 373 int unit, 374 bcm_port_t port, 375 bcm_port_management_packet_config_t *config_array, 376 int max_config, 377 int *config_count); 378 379 /* Get or set the default vlan for packets that ingress untagged. */ 380 extern int bcm_port_untagged_vlan_set( 381 int unit, 382 bcm_port_t port, 383 bcm_vlan_t vid); 384 385 /* Get or set the default vlan for packets that ingress untagged. */ 386 extern int bcm_port_untagged_vlan_get( 387 int unit, 388 bcm_port_t port, 389 bcm_vlan_t *vid_ptr); 390 391 /* Get or set the default priority for packets that ingress untagged. */ 392 extern int bcm_port_untagged_priority_set( 393 int unit, 394 bcm_port_t port, 395 int priority); 396 397 /* Get or set the default priority for packets that ingress untagged. */ 398 extern int bcm_port_untagged_priority_get( 399 int unit, 400 bcm_port_t port, 401 int *priority); 402 403 #endif /* BCM_HIDE_DISPATCHABLE */ 404 405 #define BCM_PORT_DSCP_MAP_NONE 0 /* Disable DSCP mapping */ 406 #define BCM_PORT_DSCP_MAP_ZERO 1 /* Map only if incoming DSCP 407 = 0. */ 408 #define BCM_PORT_DSCP_MAP_ALL 2 /* Map all. */ 409 #define BCM_PORT_DSCP_MAP_UNTAGGED_ONLY 3 /* Map only when packet is 410 untagged. */ 411 #define BCM_PORT_DSCP_MAP_DEFAULT 4 /* Map according to default 412 mapping,Not looking at PCP 413 or TOS. */ 414 #define BCM_PORT_DSCP_MAP_IPV4_ONLY (1 << 3) /* Map DSCP only for IPv4 415 packets. */ 416 #define BCM_PORT_DSCP_MAP_IPV6_ONLY (1 << 4) /* Map DSCP only for IPv6 417 packets. */ 418 #define BCM_PORT_DSCP_MAP_IPV4_NONE (1 << 5) /* Disable DSCP mapping for 419 IPv4 packets. */ 420 #define BCM_PORT_DSCP_MAP_IPV6_NONE (1 << 6) /* Disable DSCP mapping for 421 IPv6 packets. */ 422 423 #ifndef BCM_HIDE_DISPATCHABLE 424 425 /* Control mapping of Differentiated Services Code Points (DSCP). */ 426 extern int bcm_port_dscp_map_mode_set( 427 int unit, 428 bcm_port_t port, 429 int mode); 430 431 /* Control mapping of Differentiated Services Code Points (DSCP). */ 432 extern int bcm_port_dscp_map_mode_get( 433 int unit, 434 bcm_port_t port, 435 int *mode); 436 437 /* Control mapping of Differentiated Services Code Points (DSCP). */ 438 extern int bcm_port_dscp_map_set( 439 int unit, 440 bcm_port_t port, 441 int srccp, 442 int mapcp, 443 int prio); 444 445 /* Control mapping of Differentiated Services Code Points (DSCP). */ 446 extern int bcm_port_dscp_map_get( 447 int unit, 448 bcm_port_t port, 449 int srccp, 450 int *mapcp, 451 int *prio); 452 453 /* Get or set the current linkscan mode for the specified port. */ 454 extern int bcm_port_linkscan_set( 455 int unit, 456 bcm_port_t port, 457 int linkscan); 458 459 /* Get or set the current linkscan mode for the specified port. */ 460 extern int bcm_port_linkscan_get( 461 int unit, 462 bcm_port_t port, 463 int *linkscan); 464 465 /* 466 * Configure or retrieve the current autonegotiation settings for a port, 467 * or restart autonegotiation if already enabled. 468 */ 469 extern int bcm_port_autoneg_set( 470 int unit, 471 bcm_port_t port, 472 int autoneg); 473 474 /* 475 * Configure or retrieve the current autonegotiation settings for a port, 476 * or restart autonegotiation if already enabled. 477 */ 478 extern int bcm_port_autoneg_get( 479 int unit, 480 bcm_port_t port, 481 int *autoneg); 482 483 /* Get or set the current operating speed of a port. */ 484 extern int bcm_port_speed_max( 485 int unit, 486 bcm_port_t port, 487 int *speed); 488 489 /* Get or set the current operating speed of a port. */ 490 extern int bcm_port_speed_set( 491 int unit, 492 bcm_port_t port, 493 int speed); 494 495 /* Get or set the current operating speed of a port. */ 496 extern int bcm_port_speed_get( 497 int unit, 498 bcm_port_t port, 499 int *speed); 500 501 #endif /* BCM_HIDE_DISPATCHABLE */ 502 503 /* bcm_port_ms_t */ 504 typedef _shr_port_ms_t bcm_port_ms_t; 505 506 #define BCM_PORT_MS_SLAVE _SHR_PORT_MS_SLAVE 507 #define BCM_PORT_MS_MASTER _SHR_PORT_MS_MASTER 508 #define BCM_PORT_MS_AUTO _SHR_PORT_MS_AUTO 509 #define BCM_PORT_MS_NONE _SHR_PORT_MS_NONE 510 #define BCM_PORT_MS_COUNT _SHR_PORT_MS_COUNT 511 512 #ifndef BCM_HIDE_DISPATCHABLE 513 514 /* Set or get the Master mode on the PHY attached to the specified port. */ 515 extern int bcm_port_master_set( 516 int unit, 517 bcm_port_t port, 518 int ms); 519 520 /* Set or get the Master mode on the PHY attached to the specified port. */ 521 extern int bcm_port_master_get( 522 int unit, 523 bcm_port_t port, 524 int *ms); 525 526 #endif /* BCM_HIDE_DISPATCHABLE */ 527 528 /* bcm_port_if_t */ 529 typedef _shr_port_if_t bcm_port_if_t; 530 531 /* Port properties structure. */ 532 typedef struct bcm_port_interface_config_s { 533 uint32 flags; /* flags of port. */ 534 uint32 channel; /* channel of port. */ 535 uint32 phy_port; /* related phy port. */ 536 bcm_port_if_t interface; /* interface of port. */ 537 } bcm_port_interface_config_t; 538 539 /* physical port properties structure. */ 540 typedef struct bcm_port_interface_info_s { 541 uint32 phy_port; /* related phy port. */ 542 bcm_port_if_t interface; /* interface of port. */ 543 uint32 num_lanes; /* number of lanes the interface uses. */ 544 bcm_pbmp_t phy_pbmp; /* bitmap of phy lanes the interface occupies. */ 545 uint32 interface_id; /* should be indicated in case the id can't be 546 derived from phy_port. */ 547 } bcm_port_interface_info_t; 548 549 /* port mapping properties structure. */ 550 typedef struct bcm_port_mapping_info_s { 551 uint32 channel; /* logical port channel. */ 552 int core; /* core id */ 553 uint32 tm_port; /* tm port id */ 554 uint32 pp_port; /* pp port id */ 555 uint32 base_q_pair; /* base queue pair id */ 556 uint32 num_priorities; /* number of port priorities */ 557 } bcm_port_mapping_info_t; 558 559 /* Initialize structure bcm_port_mapping_info_t */ 560 extern void bcm_port_mapping_info_t_init( 561 bcm_port_mapping_info_t *mapping); 562 563 /* Port link state structure. */ 564 typedef struct bcm_port_link_state_s { 565 int status; /* link status, one of BCM_PORT_LINK_STATUS_* */ 566 int latch_down; /* indicates whether link latch has been down since last 567 call to API. */ 568 } bcm_port_link_state_t; 569 570 #define BCM_PORT_IF_NOCXN _SHR_PORT_IF_NOCXN 571 #define BCM_PORT_IF_NULL _SHR_PORT_IF_NULL 572 #define BCM_PORT_IF_MII _SHR_PORT_IF_MII /* MII Operating mode, not supported 573 on all ports */ 574 #define BCM_PORT_IF_GMII _SHR_PORT_IF_GMII /* GMII Operating mode, not supported 575 on all ports */ 576 #define BCM_PORT_IF_SGMII _SHR_PORT_IF_SGMII 577 #define BCM_PORT_IF_TBI _SHR_PORT_IF_TBI /* TBI interface supported on Gigabit 578 Ethernet ports operating at 579 gigabit speeds */ 580 #define BCM_PORT_IF_XGMII _SHR_PORT_IF_XGMII /* 10-Gigabit interface */ 581 #define BCM_PORT_IF_RGMII _SHR_PORT_IF_RGMII /* Reduced Gigabit Media Independent 582 Interface */ 583 #define BCM_PORT_IF_SFI _SHR_PORT_IF_SFI /* SFI 10-Gigabit serial electrical 584 interface */ 585 #define BCM_PORT_IF_XFI _SHR_PORT_IF_XFI /* XFI 10-Gigabit serial electrical 586 interface */ 587 #define BCM_PORT_IF_KR _SHR_PORT_IF_KR /* Backplane 10 GbE 64B/66B interface */ 588 #define BCM_PORT_IF_KR2 _SHR_PORT_IF_KR2 /* Backplane 2x10GbE 64B/66B 589 interface */ 590 #define BCM_PORT_IF_KR4 _SHR_PORT_IF_KR4 /* Backplane 4x10 GbE 64B/66B 591 interface */ 592 #define BCM_PORT_IF_CR _SHR_PORT_IF_CR /* Copper 10 GbE 64B/66B interface */ 593 #define BCM_PORT_IF_CR2 _SHR_PORT_IF_CR2 /* Copper 2x10GbE 64B/66B interface */ 594 #define BCM_PORT_IF_CR4 _SHR_PORT_IF_CR4 /* Copper 4x10 GbE 64B/66B interface. */ 595 #define BCM_PORT_IF_XLAUI _SHR_PORT_IF_XLAUI /* 40 Gigabit Attachment Unit 596 Interface */ 597 #define BCM_PORT_IF_XLAUI2 _SHR_PORT_IF_XLAUI2 /* 40 Gigabit Attachment Unit 598 Interface over 2 lanes */ 599 #define BCM_PORT_IF_RXAUI _SHR_PORT_IF_RXAUI 600 #define BCM_PORT_IF_XAUI _SHR_PORT_IF_XAUI 601 #define BCM_PORT_IF_SPAUI _SHR_PORT_IF_SPAUI 602 #define BCM_PORT_IF_QSGMII _SHR_PORT_IF_QSGMII 603 #define BCM_PORT_IF_ILKN _SHR_PORT_IF_ILKN 604 #define BCM_PORT_IF_RCY _SHR_PORT_IF_RCY 605 #define BCM_PORT_IF_FAT_PIPE _SHR_PORT_IF_FAT_PIPE 606 #define BCM_PORT_IF_SR _SHR_PORT_IF_SR /* Fiber SR/LR 64B/66B interface */ 607 #define BCM_PORT_IF_SR2 _SHR_PORT_IF_SR2 /* Fiber 2x10GbE 64B/66B interface. */ 608 #define BCM_PORT_IF_CAUI _SHR_PORT_IF_CAUI 609 #define BCM_PORT_IF_LR _SHR_PORT_IF_LR /* Fiber LR 64B/66B interface */ 610 #define BCM_PORT_IF_LR4 _SHR_PORT_IF_LR4 /* Fiber LR4 64B/66B interface */ 611 #define BCM_PORT_IF_SR4 _SHR_PORT_IF_SR4 /* Fiber SR4 64B/66B interface */ 612 #define BCM_PORT_IF_KX _SHR_PORT_IF_KX 613 #define BCM_PORT_IF_ZR _SHR_PORT_IF_ZR /* Fiber ZR 64B/66B interface */ 614 #define BCM_PORT_IF_SR10 _SHR_PORT_IF_SR10 /* Fiber SR10 64B/66B interface. */ 615 #define BCM_PORT_IF_CR10 _SHR_PORT_IF_CR10 /* Copper CR10 64B/66B interface. */ 616 #define BCM_PORT_IF_KR10 _SHR_PORT_IF_KR10 /* Backplane KR10 64B/66B interface. */ 617 #define BCM_PORT_IF_LR10 _SHR_PORT_IF_LR10 /* Fiber LR10 64B/66B interface. */ 618 #define BCM_PORT_IF_OTL _SHR_PORT_IF_OTL /* Fiber 4x25 GbE OTL interface */ 619 #define BCM_PORT_IF_CPU _SHR_PORT_IF_CPU 620 #define BCM_PORT_IF_ER _SHR_PORT_IF_ER /* Fiber ER 64B/66B interface */ 621 #define BCM_PORT_IF_ER2 _SHR_PORT_IF_ER2 /* Fiber ER2 2x10G 64B/66B interface */ 622 #define BCM_PORT_IF_ER4 _SHR_PORT_IF_ER4 /* Fiber ER4 4x10G 64B/66B interface */ 623 #define BCM_PORT_IF_CX _SHR_PORT_IF_CX /* Copper 10G 10B/8B interface */ 624 #define BCM_PORT_IF_CX2 _SHR_PORT_IF_CX2 /* Copper 2x10G 10B/8B interface. */ 625 #define BCM_PORT_IF_CX4 _SHR_PORT_IF_CX4 /* Copper 4x10G 10B/8B interface */ 626 #define BCM_PORT_IF_CAUI_C2C _SHR_PORT_IF_CAUI_C2C /* CAUI 100G C2C interface */ 627 #define BCM_PORT_IF_CAUI_C2M _SHR_PORT_IF_CAUI_C2M /* CAUI 100G C2M interface */ 628 #define BCM_PORT_IF_VSR _SHR_PORT_IF_VSR /* Fiber VSR 10G 64B/66B interface */ 629 #define BCM_PORT_IF_LR2 _SHR_PORT_IF_LR2 /* Fiber 2x10Gbe LR 64B/66B interface */ 630 #define BCM_PORT_IF_LRM _SHR_PORT_IF_LRM /* Fiber LRM multipoint 64B/66B 631 interface */ 632 #define BCM_PORT_IF_XLPPI _SHR_PORT_IF_XLPPI /* 40G parallel physical interface */ 633 #define BCM_PORT_IF_LBG _SHR_PORT_IF_LBG /* Link bonding interface */ 634 #define BCM_PORT_IF_CAUI4 _SHR_PORT_IF_CAUI4 /* CAUI4 100G interface */ 635 #define BCM_PORT_IF_OAMP _SHR_PORT_IF_OAMP 636 #define BCM_PORT_IF_OLP _SHR_PORT_IF_OLP 637 #define BCM_PORT_IF_ERP _SHR_PORT_IF_ERP 638 #define BCM_PORT_IF_SAT _SHR_PORT_IF_SAT 639 #define BCM_PORT_IF_RCY_MIRROR _SHR_PORT_IF_RCY_MIRROR 640 #define BCM_PORT_IF_EVENTOR _SHR_PORT_IF_EVENTOR 641 #define BCM_PORT_IF_NIF_ETH _SHR_PORT_IF_NIF_ETH /* NIF interface */ 642 #define BCM_PORT_IF_COUNT _SHR_PORT_IF_COUNT 643 644 #define BCM_PORT_IF_10B BCM_PORT_IF_TBI /* Deprecated */ 645 646 #ifndef BCM_HIDE_DISPATCHABLE 647 648 /* 649 * Configure the physical interface between the MAC and the PHY for the 650 * specified port. 651 */ 652 extern int bcm_port_interface_set( 653 int unit, 654 bcm_port_t port, 655 bcm_port_if_t intf); 656 657 /* 658 * Configure the physical interface between the MAC and the PHY for the 659 * specified port. 660 */ 661 extern int bcm_port_interface_get( 662 int unit, 663 bcm_port_t port, 664 bcm_port_if_t *intf); 665 666 /* 667 * Add a new port interface configuration. If BCM_PORT_IF_NULL remove 668 * port configuration 669 */ 670 extern int bcm_port_interface_config_set( 671 int unit, 672 bcm_port_t port, 673 bcm_port_interface_config_t *config); 674 675 /* Get port interface configuration. */ 676 extern int bcm_port_interface_config_get( 677 int unit, 678 bcm_port_t port, 679 bcm_port_interface_config_t *config); 680 681 /* Add a new port */ 682 extern int bcm_port_add( 683 int unit, 684 bcm_port_t port, 685 uint32 flags, 686 bcm_port_interface_info_t *interface_info, 687 bcm_port_mapping_info_t *mapping_info); 688 689 /* Add a new port */ 690 extern int bcm_port_get( 691 int unit, 692 bcm_port_t port, 693 uint32 *flags, 694 bcm_port_interface_info_t *interface_info, 695 bcm_port_mapping_info_t *mapping_info); 696 697 /* Add a new port */ 698 extern int bcm_port_remove( 699 int unit, 700 bcm_port_t port, 701 uint32 flags); 702 703 #endif /* BCM_HIDE_DISPATCHABLE */ 704 705 /* Port add flags. */ 706 #define BCM_PORT_ADD_BASE_Q_PAIR_WITH_ID 0x0001 /* Static base queue pair 707 configuration, should 708 be passed in API */ 709 #define BCM_PORT_ADD_CONFIG_CHANNELIZED 0x0002 /* Indicate a channelized 710 interface */ 711 #define BCM_PORT_ADD_CGM_AUTO_ADJUST_DISABLE 0x0004 /* Disable CGM 712 adjustments */ 713 #define BCM_PORT_ADD_HIGH_GIG 0x0008 /* Indicate a High Gig 714 port */ 715 #define BCM_PORT_ADD_DONT_PROBE 0x0010 /* Don't initialize the 716 physical port */ 717 #define BCM_PORT_ADD_USE_PHY_PBMP 0x0020 /* The phy pots occupided 718 by the interface are 719 indicated by phy_pbmp 720 in interface_info 721 struct */ 722 #define BCM_PORT_ADD_TDM_QUEUING_ON 0x0040 /* TDM queuing is on for 723 this port, it's 724 handled as a TDM 725 interleaved port */ 726 #define BCM_PORT_ADD_TDM_PORT 0x0080 /* Indicate a new TDM 727 port */ 728 #define BCM_PORT_ADD_KBP_PORT 0x0100 /* Indicate it is a port 729 for KBP */ 730 #define BCM_PORT_ADD_STIF_PORT 0x0200 /* Indicate it is a port 731 for statistics 732 interface */ 733 #define BCM_PORT_ADD_MODEM_PORT 0x0400 /* Indicate it is a port 734 used for Link bonding 735 modem */ 736 #define BCM_PORT_ADD_BICAST_PORT 0x0800 /* Indicate it is a port 737 used for Bicast */ 738 #define BCM_PORT_ADD_ILKN_OVER_FABRIC_PORT 0x1000 /* Indicate it is an over 739 fabric port */ 740 741 /* bcm_port_duplex_t */ 742 typedef _shr_port_duplex_t bcm_port_duplex_t; 743 744 #define BCM_PORT_DUPLEX_HALF _SHR_PORT_DUPLEX_HALF 745 #define BCM_PORT_DUPLEX_FULL _SHR_PORT_DUPLEX_FULL 746 #define BCM_PORT_DUPLEX_COUNT _SHR_PORT_DUPLEX_COUNT 747 748 /* Port pause modes (mainly used by the BCMX layer). */ 749 typedef enum bcm_port_pause_e { 750 BCM_PORT_PAUSE_NONE = 0, 751 BCM_PORT_PAUSE_ASYM_RX = 1, 752 BCM_PORT_PAUSE_ASYM_TX = 2, 753 BCM_PORT_PAUSE_SYM = 3 754 } bcm_port_pause_t; 755 756 /* Port PCS modes */ 757 typedef enum bcm_port_pcs_e { 758 bcmPortPCS8b9bLFec = 0, 759 bcmPortPCS8b10b = 1, 760 bcmPortPCS64b66bFec = 2, 761 bcmPortPCS64b66bBec = 3, 762 bcmPortPCS64b66b = 4, 763 bcmPortPCS64b66bRsFec = 5, 764 bcmPortPCS64b66bLowLatencyRsFec = 6, 765 bcmPortPCS64b66b15TRsFec = 7, 766 bcmPortPCS64b66b15TLowLatencyRsFec = 8 767 } bcm_port_pcs_t; 768 769 /* Set NIV Port type. */ 770 typedef enum bcm_port_niv_type_e { 771 BCM_PORT_NIV_TYPE_UPLINK = 0, /* NIV Uplink port */ 772 BCM_PORT_NIV_TYPE_RESERVED_1 = 1, /* Reserved */ 773 BCM_PORT_NIV_TYPE_RESERVED_2 = 2, /* Reserved */ 774 BCM_PORT_NIV_TYPE_UPLINK_ACCESS = BCM_PORT_NIV_TYPE_UPLINK, /* NIV uplink port */ 775 BCM_PORT_NIV_TYPE_UPLINK_TRANSIT = BCM_PORT_NIV_TYPE_UPLINK, /* NIV uplink port */ 776 BCM_PORT_NIV_TYPE_DOWNLINK_ACCESS = 3, /* NIV Downlink access port */ 777 BCM_PORT_NIV_TYPE_DOWNLINK_TRANSIT = 4, /* NIV downlink transit port */ 778 BCM_PORT_NIV_TYPE_SWITCH = 5, /* NIV switch port */ 779 BCM_PORT_NIV_TYPE_NONE = 6 780 } bcm_port_niv_type_t; 781 782 /* Set Extender Port type. */ 783 typedef enum bcm_port_extender_type_e { 784 BCM_PORT_EXTENDER_TYPE_UPLINK = 0, 785 BCM_PORT_EXTENDER_TYPE_DOWNLINK_ACCESS = 1, 786 BCM_PORT_EXTENDER_TYPE_DOWNLINK_TRANSIT= 2, 787 BCM_PORT_EXTENDER_TYPE_SWITCH = 3, 788 BCM_PORT_EXTENDER_TYPE_NONE 789 } bcm_port_extender_type_t; 790 791 /* Set Egress Port QoS Resolution Type. */ 792 typedef enum bcm_qos_resolution_type_e { 793 BCM_PORT_QOS_SERIAL_RESOLUTION = 0, 794 BCM_PORT_QOS_LAYERED_RESOLUTION = 1, 795 BCM_PORT_QOS_RESOLUTION_TYPE_NONE 796 } bcm_qos_resolution_type_t; 797 798 /* Port COS remap Selection. */ 799 typedef enum bcm_port_cos_remap_e { 800 BCM_PORT_COS_REMAP_VLAN_PRI = 0, 801 BCM_PORT_COS_REMAP_DSCP = 1, 802 BCM_PORT_COS_REMAP_EXP = 2 803 } bcm_port_cos_remap_t; 804 805 /* Port TPID source Selection. */ 806 typedef enum bcm_port_tpid_src_e { 807 bcmPortTpidSrcVp = 0, 808 bcmPortTpidSrcVpn = 1, 809 bcmPortTpidSrcPort = 2, 810 bcmPortTpidSrcTrillPayload = 3, 811 bcmPortTpidSrcCount = 4 812 } bcm_port_tpid_src_t; 813 814 #ifndef BCM_HIDE_DISPATCHABLE 815 816 /* Get or set the current duplex mode of a port. */ 817 extern int bcm_port_duplex_set( 818 int unit, 819 bcm_port_t port, 820 int duplex); 821 822 /* Get or set the current duplex mode of a port. */ 823 extern int bcm_port_duplex_get( 824 int unit, 825 bcm_port_t port, 826 int *duplex); 827 828 /* 829 * Enable or disable transmission of pause frames and honoring received 830 * pause frames on a port. 831 */ 832 extern int bcm_port_pause_set( 833 int unit, 834 bcm_port_t port, 835 int pause_tx, 836 int pause_rx); 837 838 /* 839 * Enable or disable transmission of pause frames and honoring received 840 * pause frames on a port. 841 */ 842 extern int bcm_port_pause_get( 843 int unit, 844 bcm_port_t port, 845 int *pause_tx, 846 int *pause_rx); 847 848 /* 849 * Get or set the source MAC address transmitted in MAC control pause 850 * frames. 851 */ 852 extern int bcm_port_pause_addr_set( 853 int unit, 854 bcm_port_t port, 855 bcm_mac_t mac); 856 857 /* 858 * Get or set the source MAC address transmitted in MAC control pause 859 * frames. 860 */ 861 extern int bcm_port_pause_addr_get( 862 int unit, 863 bcm_port_t port, 864 bcm_mac_t mac); 865 866 /* Configure or retrieve asymmetric pause setting for a port. */ 867 extern int bcm_port_pause_sym_set( 868 int unit, 869 bcm_port_t port, 870 int pause); 871 872 /* Configure or retrieve asymmetric pause setting for a port. */ 873 extern int bcm_port_pause_sym_get( 874 int unit, 875 bcm_port_t port, 876 int *pause); 877 878 #endif /* BCM_HIDE_DISPATCHABLE */ 879 880 /* Backward compatibility. */ 881 #define bcm_port_sym_pause_set bcm_port_pause_sym_set 882 #define bcm_port_sym_pause_get bcm_port_pause_sym_get 883 884 #ifndef BCM_HIDE_DISPATCHABLE 885 886 /* Process a link change event and perform required device configuration. */ 887 extern int bcm_port_update( 888 int unit, 889 bcm_port_t port, 890 int link); 891 892 /* Set or retrieve the current maximum packet size permitted on a port. */ 893 extern int bcm_port_frame_max_set( 894 int unit, 895 bcm_port_t port, 896 int size); 897 898 /* Set or retrieve the current maximum packet size permitted on a port. */ 899 extern int bcm_port_frame_max_get( 900 int unit, 901 bcm_port_t port, 902 int *size); 903 904 /* 905 * Set or retrieve the current maximum L3 packet size permitted on a 906 * port. 907 */ 908 extern int bcm_port_l3_mtu_set( 909 int unit, 910 bcm_port_t port, 911 int size); 912 913 /* 914 * Set or retrieve the current maximum L3 packet size permitted on a 915 * port. 916 */ 917 extern int bcm_port_l3_mtu_get( 918 int unit, 919 bcm_port_t port, 920 int *size); 921 922 /* 923 * Set or retrieve the current maximum encapsulated L3 packet size 924 * permitted on a port. 925 */ 926 extern int bcm_port_l3_encapsulated_mtu_set( 927 int unit, 928 bcm_port_t port, 929 int size); 930 931 /* 932 * Set or retrieve the current maximum encapsulated L3 packet size 933 * permitted on a port. 934 */ 935 extern int bcm_port_l3_encapsulated_mtu_get( 936 int unit, 937 bcm_port_t port, 938 int *size); 939 940 /* Get or set half duplex flow control (jam) for a port. */ 941 extern int bcm_port_jam_set( 942 int unit, 943 bcm_port_t port, 944 int enable); 945 946 /* Get or set half duplex flow control (jam) for a port. */ 947 extern int bcm_port_jam_get( 948 int unit, 949 bcm_port_t port, 950 int *enable); 951 952 /* Get or set the interframe gap settings for the specified port. */ 953 extern int bcm_port_ifg_set( 954 int unit, 955 bcm_port_t port, 956 int speed, 957 bcm_port_duplex_t duplex, 958 int bit_times); 959 960 /* Get or set the interframe gap settings for the specified port. */ 961 extern int bcm_port_ifg_get( 962 int unit, 963 bcm_port_t port, 964 int speed, 965 bcm_port_duplex_t duplex, 966 int *bit_times); 967 968 #endif /* BCM_HIDE_DISPATCHABLE */ 969 970 /* Values for flags parameter of bcm_port_force_vlan_set/get. */ 971 #define BCM_PORT_FORCE_VLAN_ENABLE 0x01 /* Enable force VLAN on 972 this port. */ 973 #define BCM_PORT_FORCE_VLAN_UNTAG 0x02 /* Egress untagged when 974 force VLAN is enabled 975 on this port. */ 976 #define BCM_PORT_FORCE_VLAN_PROMISCUOUS_PORT 0x04 /* Promiscuous port type. */ 977 #define BCM_PORT_FORCE_VLAN_ISOLATED_PORT 0x08 /* isolated port type. */ 978 #define BCM_PORT_FORCE_VLAN_COMMUNITY_PORT 0x0c /* community port type. */ 979 #define BCM_PORT_FORCE_VLAN_PORT_TYPE_MASK 0x0c /* port type mask. */ 980 981 #ifndef BCM_HIDE_DISPATCHABLE 982 983 /* Set/Get force vlan attribute of a port. */ 984 extern int bcm_port_force_vlan_set( 985 int unit, 986 bcm_port_t port, 987 bcm_vlan_t vlan, 988 int pkt_prio, 989 uint32 flags); 990 991 /* Set/Get force vlan attribute of a port. */ 992 extern int bcm_port_force_vlan_get( 993 int unit, 994 bcm_port_t port, 995 bcm_vlan_t *vlan, 996 int *pkt_prio, 997 uint32 *flags); 998 999 #endif /* BCM_HIDE_DISPATCHABLE */ 1000 1001 /* Flags for direct PHY register access. */ 1002 #define BCM_PORT_PHY_INTERNAL _SHR_PORT_PHY_INTERNAL 1003 #define BCM_PORT_PHY_NOMAP _SHR_PORT_PHY_NOMAP 1004 #define BCM_PORT_PHY_CLAUSE45 _SHR_PORT_PHY_CLAUSE45 1005 #define BCM_PORT_PHY_I2C_DATA8 _SHR_PORT_PHY_I2C_DATA8 1006 #define BCM_PORT_PHY_I2C_DATA16 _SHR_PORT_PHY_I2C_DATA16 1007 #define BCM_PORT_PHY_PVT_DATA _SHR_PORT_PHY_PVT_DATA 1008 #define BCM_PORT_PHY_REG_RDB _SHR_PORT_PHY_REG_RDB 1009 #define BCM_PORT_PHY_REG_MACSEC _SHR_PORT_PHY_REG_MACSEC 1010 #define BCM_PORT_PHY_REG64_DATA_HI32 _SHR_PORT_PHY_REG64_DATA_HI32 1011 1012 #define BCM_PORT_PHY_CLAUSE45_ADDR(_devad, _regad) \ 1013 _SHR_PORT_PHY_CLAUSE45_ADDR(_devad, _regad) 1014 1015 #define BCM_PORT_PHY_CLAUSE45_DEVAD(_reg_addr) \ 1016 _SHR_PORT_PHY_CLAUSE45_DEVAD(_reg_addr) 1017 1018 #define BCM_PORT_PHY_CLAUSE45_REGAD(_reg_addr) \ 1019 _SHR_PORT_PHY_CLAUSE45_REGAD(_reg_addr) 1020 1021 #define BCM_PORT_PHY_I2C_ADDR(_devad, _regad) \ 1022 _SHR_PORT_PHY_I2C_ADDR(_devad, _regad) 1023 1024 #define BCM_PORT_PHY_I2C_DEVAD(_reg_addr) \ 1025 _SHR_PORT_PHY_I2C_DEVAD(_reg_addr) 1026 1027 #define BCM_PORT_PHY_I2C_REGAD(_reg_addr) \ 1028 _SHR_PORT_PHY_I2C_REGAD(_reg_addr) 1029 1030 /* Flags for indirect PHY register access. */ 1031 #define BCM_PORT_PHY_REG_1000X _SHR_PORT_PHY_REG_1000X 1032 1033 #define BCM_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_type, _reg_selector) \ 1034 _SHR_PORT_PHY_REG_INDIRECT_ADDR(_flags, _reg_type, _reg_selector) 1035 1036 #define BCM_PORT_PHY_REG_FLAGS(_reg_addr) _SHR_PORT_PHY_REG_FLAGS(_reg_addr) 1037 1038 #define BCM_PORT_PHY_REG_BANK(_reg_addr) _SHR_PORT_PHY_REG_BANK(_reg_addr) 1039 1040 #define BCM_PORT_PHY_REG_ADDR(_reg_addr) _SHR_PORT_PHY_REG_ADDR(_reg_addr) 1041 1042 #ifndef BCM_HIDE_DISPATCHABLE 1043 1044 /* Write phy registers associated with a port. */ 1045 extern int bcm_port_phy_set( 1046 int unit, 1047 bcm_port_t port, 1048 uint32 flags, 1049 uint32 phy_reg_addr, 1050 uint32 phy_data); 1051 1052 /* Read phy registers associated with a port. */ 1053 extern int bcm_port_phy_get( 1054 int unit, 1055 bcm_port_t port, 1056 uint32 flags, 1057 uint32 phy_reg_addr, 1058 uint32 *phy_data); 1059 1060 /* Modify phy registers associated with a port. */ 1061 extern int bcm_port_phy_modify( 1062 int unit, 1063 bcm_port_t port, 1064 uint32 flags, 1065 uint32 phy_reg_addr, 1066 uint32 phy_data, 1067 uint32 phy_mask); 1068 1069 /* Read phy ROM data associated with a port. */ 1070 extern int bcm_port_phy_multi_get( 1071 int unit, 1072 bcm_port_t port, 1073 uint32 flags, 1074 uint32 dev_addr, 1075 uint32 offset, 1076 int max_size, 1077 uint8 *data, 1078 int *actual_size); 1079 1080 #endif /* BCM_HIDE_DISPATCHABLE */ 1081 1082 /* PHY reset callback function prototype. */ 1083 typedef _shr_port_phy_reset_cb_t bcm_port_phy_reset_cb_t; 1084 1085 #ifndef BCM_HIDE_DISPATCHABLE 1086 1087 /* Register or unregister a callout to post process PHY resets. */ 1088 extern int bcm_port_phy_reset_register( 1089 int unit, 1090 bcm_port_t port, 1091 bcm_port_phy_reset_cb_t callback, 1092 void *user_data); 1093 1094 /* Register or unregister a callout to post process PHY resets. */ 1095 extern int bcm_port_phy_reset_unregister( 1096 int unit, 1097 bcm_port_t port, 1098 bcm_port_phy_reset_cb_t callback, 1099 void *user_data); 1100 1101 /* Perform low level PHY reset. */ 1102 extern int bcm_port_phy_reset( 1103 int unit, 1104 bcm_port_t port); 1105 1106 #endif /* BCM_HIDE_DISPATCHABLE */ 1107 1108 /* MDI crossover control. */ 1109 typedef _shr_port_mdix_t bcm_port_mdix_t; 1110 1111 /* MDI crossover control values. */ 1112 #define BCM_PORT_MDIX_AUTO _SHR_PORT_MDIX_AUTO 1113 #define BCM_PORT_MDIX_FORCE_AUTO _SHR_PORT_MDIX_FORCE_AUTO 1114 #define BCM_PORT_MDIX_NORMAL _SHR_PORT_MDIX_NORMAL 1115 #define BCM_PORT_MDIX_XOVER _SHR_PORT_MDIX_XOVER 1116 #define BCM_PORT_MDIX_COUNT _SHR_PORT_MDIX_COUNT 1117 1118 /* MDI crossover status. */ 1119 typedef _shr_port_mdix_status_t bcm_port_mdix_status_t; 1120 1121 /* MDI crossover status values. */ 1122 #define BCM_PORT_MDIX_STATUS_NORMAL _SHR_PORT_MDIX_STATUS_NORMAL 1123 #define BCM_PORT_MDIX_STATUS_XOVER _SHR_PORT_MDIX_STATUS_XOVER 1124 #define BCM_PORT_MDIX_STATUS_COUNT _SHR_PORT_MDIX_STATUS_COUNT 1125 1126 #ifndef BCM_HIDE_DISPATCHABLE 1127 1128 /* Get or set the Auto MDIX mode for a port. */ 1129 extern int bcm_port_mdix_set( 1130 int unit, 1131 bcm_port_t port, 1132 bcm_port_mdix_t mode); 1133 1134 /* Get or set the Auto MDIX mode for a port. */ 1135 extern int bcm_port_mdix_get( 1136 int unit, 1137 bcm_port_t port, 1138 bcm_port_mdix_t *mode); 1139 1140 /* Get or set the Auto MDIX mode for a port. */ 1141 extern int bcm_port_mdix_status_get( 1142 int unit, 1143 bcm_port_t port, 1144 bcm_port_mdix_status_t *status); 1145 1146 #endif /* BCM_HIDE_DISPATCHABLE */ 1147 1148 /* Combo port control/status. */ 1149 typedef _shr_port_medium_t bcm_port_medium_t; 1150 1151 /* Combo port control/status values. */ 1152 #define BCM_PORT_MEDIUM_NONE _SHR_PORT_MEDIUM_NONE 1153 #define BCM_PORT_MEDIUM_COPPER _SHR_PORT_MEDIUM_COPPER 1154 #define BCM_PORT_MEDIUM_FIBER _SHR_PORT_MEDIUM_FIBER 1155 #define BCM_PORT_MEDIUM_BACKPLANE _SHR_PORT_MEDIUM_BACKPLANE 1156 #define BCM_PORT_MEDIUM_ALL _SHR_PORT_MEDIUM_ALL 1157 #define BCM_PORT_MEDIUM_COUNT _SHR_PORT_MEDIUM_COUNT 1158 1159 /* Call back function prototype for media status changes. */ 1160 typedef _shr_port_medium_status_cb_t bcm_port_medium_status_cb_t; 1161 1162 /* bcm_phy_config_t */ 1163 typedef _shr_phy_config_t bcm_phy_config_t; 1164 1165 #ifndef BCM_HIDE_DISPATCHABLE 1166 1167 /* Get or set medium preferences for combination ports. */ 1168 extern int bcm_port_medium_config_set( 1169 int unit, 1170 bcm_port_t port, 1171 bcm_port_medium_t medium, 1172 bcm_phy_config_t *config); 1173 1174 /* Get or set medium preferences for combination ports. */ 1175 extern int bcm_port_medium_config_get( 1176 int unit, 1177 bcm_port_t port, 1178 bcm_port_medium_t medium, 1179 bcm_phy_config_t *config); 1180 1181 /* Get or set medium preferences for combination ports. */ 1182 extern int bcm_port_medium_get( 1183 int unit, 1184 bcm_port_t port, 1185 bcm_port_medium_t *medium); 1186 1187 /* Register or unregister a call back function on media status changes. */ 1188 extern int bcm_port_medium_status_register( 1189 int unit, 1190 bcm_port_t port, 1191 bcm_port_medium_status_cb_t callback, 1192 void *user_data); 1193 1194 /* Register or unregister a call back function on media status changes. */ 1195 extern int bcm_port_medium_status_unregister( 1196 int unit, 1197 bcm_port_t port, 1198 bcm_port_medium_status_cb_t callback, 1199 void *user_data); 1200 1201 #endif /* BCM_HIDE_DISPATCHABLE */ 1202 1203 /* Port loopback modes. */ 1204 typedef enum bcm_port_loopback_e { 1205 BCM_PORT_LOOPBACK_NONE = 0, 1206 BCM_PORT_LOOPBACK_MAC = 1, 1207 BCM_PORT_LOOPBACK_PHY = 2, 1208 BCM_PORT_LOOPBACK_PHY_REMOTE = 3, 1209 BCM_PORT_LOOPBACK_MAC_REMOTE = 4, 1210 BCM_PORT_LOOPBACK_COUNT = 5 1211 } bcm_port_loopback_t; 1212 1213 #ifndef BCM_HIDE_DISPATCHABLE 1214 1215 /* Set the current loopback mode of a port. */ 1216 extern int bcm_port_loopback_set( 1217 int unit, 1218 bcm_port_t port, 1219 int loopback); 1220 1221 /* Retrieve the current loopback mode of a port. */ 1222 extern int bcm_port_loopback_get( 1223 int unit, 1224 bcm_port_t port, 1225 int *loopback); 1226 1227 /* 1228 * Set the spanning tree state for a port (single instance spanning tree 1229 * only). 1230 */ 1231 extern int bcm_port_stp_set( 1232 int unit, 1233 bcm_port_t port, 1234 int state); 1235 1236 /* 1237 * Get the spanning tree state for a port (single instance spanning tree 1238 * only). 1239 */ 1240 extern int bcm_port_stp_get( 1241 int unit, 1242 bcm_port_t port, 1243 int *state); 1244 1245 #endif /* BCM_HIDE_DISPATCHABLE */ 1246 1247 /* bcm_port_discard_e */ 1248 typedef enum bcm_port_discard_e { 1249 BCM_PORT_DISCARD_NONE = 0, 1250 BCM_PORT_DISCARD_ALL = 1, 1251 BCM_PORT_DISCARD_UNTAG = 2, 1252 BCM_PORT_DISCARD_TAG = 3, 1253 BCM_PORT_DISCARD_INGRESS = 4, 1254 BCM_PORT_DISCARD_EGRESS = 5, 1255 BCM_PORT_DISCARD_COUNT = 6 1256 } bcm_port_discard_t; 1257 1258 #define BCM_PORT_DISCARD_MODE_INGRESS_ONLY (1 << 15) /* Discard state should 1259 be set for ingress 1260 only */ 1261 #define BCM_PORT_DISCARD_MODE_EGRESS_ONLY (1 << 14) /* Discard state should 1262 be set for egress only */ 1263 1264 #ifndef BCM_HIDE_DISPATCHABLE 1265 1266 /* 1267 * Configure port discard mode for packets ingressing tagged and 1268 * untagged. 1269 */ 1270 extern int bcm_port_discard_set( 1271 int unit, 1272 bcm_port_t port, 1273 int mode); 1274 1275 /* Get the port discard mode for packets ingressing tagged and untagged. */ 1276 extern int bcm_port_discard_get( 1277 int unit, 1278 bcm_port_t port, 1279 int *mode); 1280 1281 #endif /* BCM_HIDE_DISPATCHABLE */ 1282 1283 /* 1284 * Flags for learn mode 1285 * 1286 * This call takes flags to turn on and off mutually-independent actions 1287 * that should be taken when a packet is received with an unknown source 1288 * address, or source lookup failure (SLF). 1289 * 1290 * The set call returns BCM_E_UNAVAIL for flag combinations that are not 1291 * supported by the hardware. 1292 */ 1293 #define BCM_PORT_LEARN_ARL 0x01 /* Learn SLF address. */ 1294 #define BCM_PORT_LEARN_CPU 0x02 /* Copy SLF packet to CPU. */ 1295 #define BCM_PORT_LEARN_FWD 0x04 /* Forward SLF packet */ 1296 #define BCM_PORT_LEARN_PENDING 0x08 /* Mark learned SLF as pending */ 1297 #define BCM_PORT_LEARN_ON 0x01 /* Deprecated name */ 1298 #define BCM_PORT_LEARN_SWITCH 0x04 /* Deprecated name */ 1299 1300 #ifndef BCM_HIDE_DISPATCHABLE 1301 1302 /* Control the hardware and software learning support on a port. */ 1303 extern int bcm_port_learn_set( 1304 int unit, 1305 bcm_port_t port, 1306 uint32 flags); 1307 1308 /* Get the hardware and software learning support on a port. */ 1309 extern int bcm_port_learn_get( 1310 int unit, 1311 bcm_port_t port, 1312 uint32 *flags); 1313 1314 /* Control the hardware and software learning support on a port. */ 1315 extern int bcm_port_learn_modify( 1316 int unit, 1317 bcm_port_t port, 1318 uint32 add, 1319 uint32 remove); 1320 1321 #endif /* BCM_HIDE_DISPATCHABLE */ 1322 1323 #define BCM_PORT_LINK_STATUS_DOWN 0 1324 #define BCM_PORT_LINK_STATUS_UP 1 1325 #define BCM_PORT_LINK_STATUS_FAILED 2 1326 #define BCM_PORT_LINK_STATUS_REMOTE_FAULT 3 1327 #define BCM_PORT_LINK_STATUS_LOCAL_FAULT 4 1328 #define BCM_PORT_LINK_STATUS_LOCAL_AND_REMOTE_FAULT 5 1329 1330 #ifndef BCM_HIDE_DISPATCHABLE 1331 1332 /* Retrieve the current link status of a port. */ 1333 extern int bcm_port_link_status_get( 1334 int unit, 1335 bcm_port_t port, 1336 int *status); 1337 1338 /* Retrieve the current link state of a port. */ 1339 extern int bcm_port_link_state_get( 1340 int unit, 1341 bcm_port_t port, 1342 uint32 flags, 1343 bcm_port_link_state_t *state); 1344 1345 /* 1346 * Clear failed link status from a port which has undergone LAG failover. 1347 * The port is moved to down status. The application is responsible for 1348 * removing the port from all trunk memberships before calling this 1349 * function. 1350 */ 1351 extern int bcm_port_link_failed_clear( 1352 int unit, 1353 bcm_port_t port); 1354 1355 #endif /* BCM_HIDE_DISPATCHABLE */ 1356 1357 /* 1358 * Modes for VLAN input filtering. 1359 * 1360 * Superceded APIs: use bcm_port_vlan_member_[get|set] instead. 1361 */ 1362 #define BCM_PORT_IFILTER_OFF 0 1363 #define BCM_PORT_IFILTER_ON 1 1364 1365 #ifndef BCM_HIDE_DISPATCHABLE 1366 1367 /* 1368 * Set current behavior of tagged packets arriving on a port not a member 1369 * of the specified VLAN. 1370 */ 1371 extern int bcm_port_ifilter_set( 1372 int unit, 1373 bcm_port_t port, 1374 int mode); 1375 1376 /* 1377 * Retrieve current behavior of tagged packets arriving on a port not a 1378 * member of the specified VLAN. 1379 */ 1380 extern int bcm_port_ifilter_get( 1381 int unit, 1382 bcm_port_t port, 1383 int *mode); 1384 1385 #endif /* BCM_HIDE_DISPATCHABLE */ 1386 1387 /* Modes for VLAN ingress/egress filtering. */ 1388 #define BCM_PORT_VLAN_MEMBER_INGRESS 0x00000001 1389 #define BCM_PORT_VLAN_MEMBER_EGRESS 0x00000002 1390 1391 /* Table method for VLAN ingress/egress filtering. */ 1392 #define BCM_PORT_VLAN_MEMBER_VP_VLAN_MEMBERSHIP 0x00000004 1393 1394 /* 1395 * Do not perform a VFI membership check on VP, instead do a VLAN check 1396 * on physical port. 1397 */ 1398 #define BCM_PORT_VLAN_MEMBER_VP_DO_NOT_CHECK 0x00000008 1399 1400 #ifndef BCM_HIDE_DISPATCHABLE 1401 1402 /* 1403 * Set current behavior of tagged packets arriving/leaving on a port not 1404 * a member of the specified VLAN. 1405 */ 1406 extern int bcm_port_vlan_member_set( 1407 int unit, 1408 bcm_port_t port, 1409 uint32 flags); 1410 1411 /* 1412 * Retrieve current behavior of tagged packets arriving/leaving on a port 1413 * not a member of the specified VLAN. 1414 */ 1415 extern int bcm_port_vlan_member_get( 1416 int unit, 1417 bcm_port_t port, 1418 uint32 *flags); 1419 1420 /* Enable or disable BPDU processing on a port. */ 1421 extern int bcm_port_bpdu_enable_set( 1422 int unit, 1423 bcm_port_t port, 1424 int enable); 1425 1426 /* Enable or disable BPDU processing on a port. */ 1427 extern int bcm_port_bpdu_enable_get( 1428 int unit, 1429 bcm_port_t port, 1430 int *enable); 1431 1432 /* Enable or disable l3 switching on an ingress port. */ 1433 extern int bcm_port_l3_enable_set( 1434 int unit, 1435 bcm_port_t port, 1436 int enable); 1437 1438 /* Enable or disable l3 switching on an ingress port. */ 1439 extern int bcm_port_l3_enable_get( 1440 int unit, 1441 bcm_port_t port, 1442 int *enable); 1443 1444 /* bcm_port_tgid_set */ 1445 extern int bcm_port_tgid_set( 1446 int unit, 1447 bcm_port_t port, 1448 int tgid, 1449 int psc); 1450 1451 /* bcm_port_tgid_get */ 1452 extern int bcm_port_tgid_get( 1453 int unit, 1454 bcm_port_t port, 1455 int *tgid, 1456 int *psc); 1457 1458 #endif /* BCM_HIDE_DISPATCHABLE */ 1459 1460 /* bcm_port_mcast_flood_t */ 1461 typedef _shr_port_mcast_flood_t bcm_port_mcast_flood_t; 1462 1463 #define BCM_PORT_MCAST_FLOOD_ALL _SHR_PORT_MCAST_FLOOD_ALL 1464 #define BCM_PORT_MCAST_FLOOD_UNKNOWN _SHR_PORT_MCAST_FLOOD_UNKNOWN 1465 #define BCM_PORT_MCAST_FLOOD_NONE _SHR_PORT_MCAST_FLOOD_NONE 1466 #define BCM_PORT_MCAST_FLOOD_COUNT _SHR_PORT_MCAST_FLOOD_COUNT 1467 1468 /* Backward compatibility. */ 1469 #define BCM_PORT_PFM_MODEA BCM_PORT_MCAST_FLOOD_ALL 1470 #define BCM_PORT_PFM_MODEB BCM_PORT_MCAST_FLOOD_UNKNOWN 1471 #define BCM_PORT_PFM_MODEC BCM_PORT_MCAST_FLOOD_NONE 1472 1473 #ifndef BCM_HIDE_DISPATCHABLE 1474 1475 /* Set or retrieve the current unknown multicast behavior. */ 1476 extern int bcm_port_pfm_set( 1477 int unit, 1478 bcm_port_t port, 1479 int mode); 1480 1481 /* Set or retrieve the current unknown multicast behavior. */ 1482 extern int bcm_port_pfm_get( 1483 int unit, 1484 bcm_port_t port, 1485 int *mode); 1486 1487 #endif /* BCM_HIDE_DISPATCHABLE */ 1488 1489 /* 1490 * Port Encapsulation modes 1491 * 1492 * Members of the XGS family of switches support multiple frame 1493 * (link-level) encapsulation modes (HIGIG, BCM5632, Ethernet). 1494 */ 1495 typedef _shr_port_encap_t bcm_port_encap_t; 1496 1497 #define BCM_PORT_ENCAP_IEEE _SHR_PORT_ENCAP_IEEE 1498 #define BCM_PORT_ENCAP_HIGIG _SHR_PORT_ENCAP_HIGIG 1499 #define BCM_PORT_ENCAP_B5632 _SHR_PORT_ENCAP_B5632 1500 #define BCM_PORT_ENCAP_HIGIG2 _SHR_PORT_ENCAP_HIGIG2 1501 #define BCM_PORT_ENCAP_HIGIG2_LITE _SHR_PORT_ENCAP_HIGIG2_LITE 1502 #define BCM_PORT_ENCAP_HIGIG2_L2 _SHR_PORT_ENCAP_HIGIG2_L2 1503 #define BCM_PORT_ENCAP_HIGIG2_IP_GRE _SHR_PORT_ENCAP_HIGIG2_IP_GRE 1504 #define BCM_PORT_ENCAP_OBSOLETE _SHR_PORT_ENCAP_OBSOLETE 1505 #define BCM_PORT_ENCAP_PREAMBLE_SOP_ONLY _SHR_PORT_ENCAP_PREAMBLE_SOP_ONLY 1506 #define BCM_PORT_ENCAP_HIGIG_OVER_ETHERNET _SHR_PORT_ENCAP_HIGIG_OVER_ETHERNET 1507 #define BCM_PORT_ENCAP_CPRI _SHR_PORT_ENCAP_CPRI 1508 #define BCM_PORT_ENCAP_RSVD4 _SHR_PORT_ENCAP_RSVD4 1509 #define BCM_PORT_ENCAP_COUNT _SHR_PORT_ENCAP_COUNT 1510 1511 /* Port Encapsulation abilities */ 1512 typedef _shr_pa_encap_t bcm_pa_encap_t; 1513 1514 #define BCM_PA_ENCAP_IEEE _SHR_PA_ENCAP_IEEE 1515 #define BCM_PA_ENCAP_HIGIG _SHR_PA_ENCAP_HIGIG 1516 #define BCM_PA_ENCAP_B5632 _SHR_PA_ENCAP_B5632 1517 #define BCM_PA_ENCAP_HIGIG2 _SHR_PA_ENCAP_HIGIG2 1518 #define BCM_PA_ENCAP_HIGIG2_LITE _SHR_PA_ENCAP_HIGIG2_LITE 1519 #define BCM_PA_ENCAP_HIGIG2_L2 _SHR_PA_ENCAP_HIGIG2_L2 1520 #define BCM_PA_ENCAP_HIGIG2_IP_GRE _SHR_PA_ENCAP_HIGIG2_IP_GRE 1521 #define BCM_PA_ENCAP_OBSOLETE _SHR_PA_ENCAP_OBSOLETE 1522 #define BCM_PA_ENCAP_HIGIG_OVER_ETHERNET _SHR_PA_ENCAP_HIGIG_OVER_ETHERNET 1523 #define BCM_PA_ENCAP_CPRI _SHR_PA_ENCAP_CPRI 1524 #define BCM_PA_ENCAP_RSVD4 _SHR_PA_ENCAP_RSVD4 1525 1526 /* bcm_port_encap_config_s */ 1527 typedef struct bcm_port_encap_config_s { 1528 bcm_port_encap_t encap; /* Port encapsulation one of the BCM_PORT_ENCAP_* */ 1529 uint16 oui_ethertype; /* Vendor specific ether type. */ 1530 uint16 higig_ethertype; /* Higig ether type */ 1531 uint8 oui[3]; /* Vendor specific value */ 1532 uint16 hgoe_reserved; /* Value for reserved field in HGoE header */ 1533 bcm_mac_t dst_mac; /* Destination MAC address */ 1534 bcm_mac_t src_mac; /* Source MAC address */ 1535 uint16 tpid; /* Outer L2 header TPID */ 1536 uint16 vlan; /* Outer L2 header VLAN tag */ 1537 uint8 ttl; /* Hop limit. */ 1538 uint8 tos; /* Traffic Class/Tos byte */ 1539 bcm_ip_t src_addr; /* Tunnel source ip address (IPv4) */ 1540 bcm_ip_t dst_addr; /* Tunnel destination ip address (IPv4) */ 1541 } bcm_port_encap_config_t; 1542 1543 #ifndef BCM_HIDE_DISPATCHABLE 1544 1545 /* Set the encapsulation of the given port. */ 1546 extern int bcm_port_encap_config_set( 1547 int unit, 1548 bcm_gport_t gport, 1549 bcm_port_encap_config_t *encap_config); 1550 1551 /* Get the encapsulation of the given port. */ 1552 extern int bcm_port_encap_config_get( 1553 int unit, 1554 bcm_gport_t gport, 1555 bcm_port_encap_config_t *encap_config); 1556 1557 /* Set or get the link level encapsulation mode. */ 1558 extern int bcm_port_encap_set( 1559 int unit, 1560 bcm_port_t port, 1561 int mode); 1562 1563 /* Set or get the link level encapsulation mode. */ 1564 extern int bcm_port_encap_get( 1565 int unit, 1566 bcm_port_t port, 1567 int *mode); 1568 1569 /* 1570 * Get the current count of cells or packets queued on a port for 1571 * transmission. 1572 */ 1573 extern int bcm_port_queued_count_get( 1574 int unit, 1575 bcm_port_t port, 1576 uint32 *count); 1577 1578 #endif /* BCM_HIDE_DISPATCHABLE */ 1579 1580 /* bcm_port_frametype_t */ 1581 typedef int bcm_port_frametype_t; 1582 1583 /* Protocol based VLAN support. */ 1584 #define BCM_PORT_FRAMETYPE_ETHER2 0x1 1585 #define BCM_PORT_FRAMETYPE_8023 0x2 1586 #define BCM_PORT_FRAMETYPE_SNAP BCM_PORT_FRAMETYPE_8023 1587 #define BCM_PORT_FRAMETYPE_LLC 0x4 1588 #define BCM_PORT_FRAMETYPE_SNAP_PRIVATE 0x8 1589 1590 /* bcm_port_ethertype_t */ 1591 typedef bcm_ethertype_t bcm_port_ethertype_t; 1592 1593 /* Backplane multiplexing type */ 1594 typedef enum bcm_port_control_ability_e { 1595 BCM_PORT_ABILITY_SFI = 1, 1596 BCM_PORT_ABILITY_DUAL_SFI = 2, 1597 BCM_PORT_ABILITY_SCI = 3, 1598 BCM_PORT_ABILITY_SFI_SCI = 4, 1599 BCM_PORT_ABILITY_DUAL_SFI_LOCAL = 5, 1600 BCM_PORT_ABILITY_DUAL_SFI_LOOPBACK=BCM_PORT_ABILITY_DUAL_SFI_LOCAL, 1601 BCM_PORT_ABILITY_SFI_LOOPBACK = 6 1602 } bcm_port_control_ability_t; 1603 1604 /* PRBS Polynomial type */ 1605 typedef _shr_port_prbs_polynomial_t bcm_port_prbs_t; 1606 1607 #define BCM_PORT_PRBS_POLYNOMIAL_X7_X6_1 _SHR_PORT_PRBS_POLYNOMIAL_X7_X6_1 1608 #define BCM_PORT_PRBS_POLYNOMIAL_X15_X14_1 _SHR_PORT_PRBS_POLYNOMIAL_X15_X14_1 1609 #define BCM_PORT_PRBS_POLYNOMIAL_X23_X18_1 _SHR_PORT_PRBS_POLYNOMIAL_X23_X18_1 1610 #define BCM_PORT_PRBS_POLYNOMIAL_X31_X28_1 _SHR_PORT_PRBS_POLYNOMIAL_X31_X28_1 1611 #define BCM_PORT_PRBS_POLYNOMIAL_X9_X5_1 _SHR_PORT_PRBS_POLYNOMIAL_X9_X5_1 1612 #define BCM_PORT_PRBS_POLYNOMIAL_X11_X9_1 _SHR_PORT_PRBS_POLYNOMIAL_X11_X9_1 1613 #define BCM_PORT_PRBS_POLYNOMIAL_X58_X31_1 _SHR_PORT_PRBS_POLYNOMIAL_X58_X31_1 1614 #define BCM_PORT_PRBS_POLYNOMIAL_X49_X40_1 _SHR_PORT_PRBS_POLYNOMIAL_X49_X40_1 1615 #define BCM_PORT_PRBS_POLYNOMIAL_X20_X3_1 _SHR_PORT_PRBS_POLYNOMIAL_X20_X3_1 1616 #define BCM_PORT_PRBS_POLYNOMIAL_X13_X12_X2_1 _SHR_PORT_PRBS_POLYNOMIAL_X13_X12_X2_1 1617 #define BCM_PORT_PRBS_POLYNOMIAL_X20_X3_1 _SHR_PORT_PRBS_POLYNOMIAL_X20_X3_1 1618 #define BCM_PORT_PRBS_POLYNOMIAL_X10_X7_1 _SHR_PORT_PRBS_POLYNOMIAL_X10_X7_1 1619 #define BCM_PORT_PRBS_POLYNOMIAL_PAM4_13Q _SHR_PORT_PRBS_POLYNOMIAL_PAM4_13Q 1620 1621 /* PHY PCS mode */ 1622 typedef _shr_port_phy_pcs_mode_t bcm_port_phy_pcs_mode_t; 1623 1624 #define BCM_PORT_PHY_CONTROL_PCS_MODE_IEEE _SHR_PORT_PHY_CONTROL_PCS_MODE_IEEE 1625 #define BCM_PORT_PHY_CONTROL_PCS_MODE_BRCM _SHR_PORT_PHY_CONTROL_PCS_MODE_BRCM 1626 1627 /* Backward compatibility. */ 1628 #define bcm_port_untagged_protocol_vlan_add \ 1629 bcm_port_protocol_vlan_add 1630 #define bcm_port_untagged_protocol_vlan_delete \ 1631 bcm_port_protocol_vlan_delete 1632 #define bcm_port_untagged_protocol_vlan_delete_all \ 1633 bcm_port_protocol_vlan_delete_all 1634 1635 #ifndef BCM_HIDE_DISPATCHABLE 1636 1637 /* Add or delete a protocol based vlan. */ 1638 extern int bcm_port_protocol_vlan_add( 1639 int unit, 1640 bcm_port_t port, 1641 bcm_port_frametype_t frame, 1642 bcm_port_ethertype_t ether, 1643 bcm_vlan_t vid); 1644 1645 /* Add or delete a protocol based vlan. */ 1646 extern int bcm_port_protocol_vlan_delete( 1647 int unit, 1648 bcm_port_t port, 1649 bcm_port_frametype_t frame, 1650 bcm_port_ethertype_t ether); 1651 1652 /* Add or delete a protocol based vlan. */ 1653 extern int bcm_port_protocol_vlan_delete_all( 1654 int unit, 1655 bcm_port_t port); 1656 1657 /* 1658 * Configure a port to block or allow packets from a given ingress port 1659 * for egressing. 1660 */ 1661 extern int bcm_port_egress_set( 1662 int unit, 1663 bcm_port_t port, 1664 int modid, 1665 bcm_pbmp_t pbmp); 1666 1667 /* 1668 * Configure a port to block or allow packets from a given ingress port 1669 * for egressing. 1670 */ 1671 extern int bcm_port_egress_get( 1672 int unit, 1673 bcm_port_t port, 1674 int modid, 1675 bcm_pbmp_t *pbmp); 1676 1677 /* 1678 * Configure which egress ports an ingress port is permitted to forward 1679 * packets to. 1680 */ 1681 extern int bcm_port_modid_enable_set( 1682 int unit, 1683 bcm_port_t port, 1684 int modid, 1685 int enable); 1686 1687 /* 1688 * Configure which egress ports an ingress port is permitted to forward 1689 * packets to. 1690 */ 1691 extern int bcm_port_modid_enable_get( 1692 int unit, 1693 bcm_port_t port, 1694 int modid, 1695 int *enable); 1696 1697 /* 1698 * Configure which egress ports an ingress port is permitted to forward 1699 * packets to. 1700 */ 1701 extern int bcm_port_modid_egress_set( 1702 int unit, 1703 bcm_port_t port, 1704 bcm_module_t modid, 1705 bcm_pbmp_t pbmp); 1706 1707 /* 1708 * Configure which egress ports an ingress port is permitted to forward 1709 * packets to. 1710 */ 1711 extern int bcm_port_modid_egress_get( 1712 int unit, 1713 bcm_port_t port, 1714 bcm_module_t modid, 1715 bcm_pbmp_t *pbmp); 1716 1717 #endif /* BCM_HIDE_DISPATCHABLE */ 1718 1719 /* Flood blocking modes. */ 1720 #define BCM_PORT_FLOOD_BLOCK_BCAST 0x1 1721 #define BCM_PORT_FLOOD_BLOCK_UNKNOWN_UCAST 0x2 1722 #define BCM_PORT_FLOOD_BLOCK_UNKNOWN_MCAST 0x4 1723 #define BCM_PORT_FLOOD_BLOCK_ALL 0x8 1724 #define BCM_PORT_FLOOD_BLOCK_UNKNOWN_IP_MCAST 0x10 1725 #define BCM_PORT_FLOOD_BLOCK_UNKNOWN_NONIP_MCAST 0x20 1726 #define BCM_PORT_FLOOD_BLOCK_KNOWN_MCAST 0x40 1727 1728 #ifndef BCM_HIDE_DISPATCHABLE 1729 1730 /* Selectively block flooding traffic. */ 1731 extern int bcm_port_flood_block_set( 1732 int unit, 1733 bcm_port_t ingress_port, 1734 bcm_port_t egress_port, 1735 uint32 flags); 1736 1737 /* Selectively block flooding traffic. */ 1738 extern int bcm_port_flood_block_get( 1739 int unit, 1740 bcm_port_t ingress_port, 1741 bcm_port_t egress_port, 1742 uint32 *flags); 1743 1744 /* Configure a port for egress rate shaping. */ 1745 extern int bcm_port_rate_egress_set( 1746 int unit, 1747 bcm_port_t port, 1748 uint32 kbits_sec, 1749 uint32 kbits_burst); 1750 1751 /* Configure a port for egress rate shaping in packet mode. */ 1752 extern int bcm_port_rate_egress_pps_set( 1753 int unit, 1754 bcm_port_t port, 1755 uint32 pps, 1756 uint32 burst); 1757 1758 /* Get a port's egress rate shaping parameters. */ 1759 extern int bcm_port_rate_egress_get( 1760 int unit, 1761 bcm_port_t port, 1762 uint32 *kbits_sec, 1763 uint32 *kbits_burst); 1764 1765 /* Get port's egress rate shaping parameters in packet mode. */ 1766 extern int bcm_port_rate_egress_pps_get( 1767 int unit, 1768 bcm_port_t port, 1769 uint32 *pps, 1770 uint32 *burst); 1771 1772 /* Configure a port for ingress rate policing. */ 1773 extern int bcm_port_rate_ingress_set( 1774 int unit, 1775 bcm_port_t port, 1776 uint32 kbits_sec, 1777 uint32 kbits_burst); 1778 1779 /* Configure a port for ingress rate policing. */ 1780 extern int bcm_port_rate_ingress_get( 1781 int unit, 1782 bcm_port_t port, 1783 uint32 *kbits_sec, 1784 uint32 *kbits_burst); 1785 1786 /* 1787 * Configure a port's ingress rate limiting pause frame control 1788 * parameters. 1789 */ 1790 extern int bcm_port_rate_pause_set( 1791 int unit, 1792 bcm_port_t port, 1793 uint32 kbits_pause, 1794 uint32 kbits_resume); 1795 1796 /* 1797 * Configure a port's ingress rate limiting pause frame control 1798 * parameters. 1799 */ 1800 extern int bcm_port_rate_pause_get( 1801 int unit, 1802 bcm_port_t port, 1803 uint32 *kbits_pause, 1804 uint32 *kbits_resume); 1805 1806 /* Control the sampling of packets ingressing or egressing a port. */ 1807 extern int bcm_port_sample_rate_set( 1808 int unit, 1809 bcm_port_t port, 1810 int ingress_rate, 1811 int egress_rate); 1812 1813 /* Control the sampling of packets ingressing or egressing a port. */ 1814 extern int bcm_port_sample_rate_get( 1815 int unit, 1816 bcm_port_t port, 1817 int *ingress_rate, 1818 int *egress_rate); 1819 1820 #endif /* BCM_HIDE_DISPATCHABLE */ 1821 1822 /* Double tagging modes. */ 1823 #define BCM_PORT_DTAG_MODE_NONE 0 /* No double tagging. */ 1824 #define BCM_PORT_DTAG_MODE_INTERNAL 1 /* Service Provider port. */ 1825 #define BCM_PORT_DTAG_MODE_EXTERNAL 2 /* Customer port. */ 1826 #define BCM_PORT_DTAG_REMOVE_EXTERNAL_TAG 4 /* Remove customer tag. */ 1827 #define BCM_PORT_DTAG_ADD_EXTERNAL_TAG 8 /* Add customer tag. */ 1828 #define BCM_PORT_DTAG_MODE_TRANSPARENT 16 /* Transparent port, all 1829 packets assume port's 1830 default VID. */ 1831 1832 #ifndef BCM_HIDE_DISPATCHABLE 1833 1834 /* Set or retrieve the current double tagging mode for a port. */ 1835 extern int bcm_port_dtag_mode_set( 1836 int unit, 1837 bcm_port_t port, 1838 int mode); 1839 1840 /* Set or retrieve the current double tagging mode for a port. */ 1841 extern int bcm_port_dtag_mode_get( 1842 int unit, 1843 bcm_port_t port, 1844 int *mode); 1845 1846 /* Set the default tag protocol ID (TPID) for the specified port. */ 1847 extern int bcm_port_tpid_set( 1848 int unit, 1849 bcm_port_t port, 1850 uint16 tpid); 1851 1852 /* Set the default tag protocol ID (TPID) for the specified port. */ 1853 extern int bcm_port_tpid_get( 1854 int unit, 1855 bcm_port_t port, 1856 uint16 *tpid); 1857 1858 /* Add an allowed outer tag protocol ID (TPID) for the specified port. */ 1859 extern int bcm_port_tpid_add( 1860 int unit, 1861 bcm_port_t port, 1862 uint16 tpid, 1863 int color_select); 1864 1865 /* Delete allowed outer tag protocol ID (TPID) for the specified port. */ 1866 extern int bcm_port_tpid_delete( 1867 int unit, 1868 bcm_port_t port, 1869 uint16 tpid); 1870 1871 /* Delete allowed outer tag protocol ID (TPID) for the specified port. */ 1872 extern int bcm_port_tpid_delete_all( 1873 int unit, 1874 bcm_port_t port); 1875 1876 /* Set the default tag protocol ID (TPID) for the specified port. */ 1877 extern int bcm_port_inner_tpid_set( 1878 int unit, 1879 bcm_port_t port, 1880 uint16 tpid); 1881 1882 /* Set the default tag protocol ID (TPID) for the specified port. */ 1883 extern int bcm_port_inner_tpid_get( 1884 int unit, 1885 bcm_port_t port, 1886 uint16 *tpid); 1887 1888 #endif /* BCM_HIDE_DISPATCHABLE */ 1889 1890 /* Port TPID class flags. */ 1891 #define BCM_PORT_TPID_CLASS_OUTER_IS_PRIO 0x0001 /* Outer identified TPID 1892 is priority i.e, VLAN 1893 ID equals to zero */ 1894 #define BCM_PORT_TPID_CLASS_DISCARD 0x0002 /* Discard packet */ 1895 #define BCM_PORT_TPID_CLASS_OUTER_C 0x0004 /* Outer tag is customer 1896 tag */ 1897 #define BCM_PORT_TPID_CLASS_INNER_C 0x0008 /* Inner tag is customer 1898 tag */ 1899 #define BCM_PORT_TPID_CLASS_INGRESS_ONLY 0x0010 /* Ingress only */ 1900 #define BCM_PORT_TPID_CLASS_EGRESS_ONLY 0x0020 /* Egress only */ 1901 #define BCM_PORT_TPID_CLASS_OUTER_NOT_PRIO 0x0040 /* Outer identified TPID 1902 is not priority i.e, 1903 VLAN ID different than 1904 zero */ 1905 #define BCM_PORT_TPID_CLASS_NATIVE_EVE 0x0080 /* Native Egress vlan 1906 classification. */ 1907 #define BCM_PORT_TPID_CLASS_NATIVE_IVE 0x0100 /* Native Ingress vlan 1908 classification. */ 1909 #define BCM_PORT_TPID_CLASS_WITH_ID 0x0200 /* Create specified 1910 TAG-STRUCT SW-ID. */ 1911 #define BCM_PORT_TPID_CLASS_EGRESS_IP_TUNNEL 0x0400 /* Egress IP Tunnel vlan 1912 classification. */ 1913 1914 /* Special TPID values for Port TPID class configuration */ 1915 #define BCM_PORT_TPID_CLASS_TPID_INVALID 0xFFFFFFFF /* Value for invalid TPID 1916 in port TPID class 1917 configuration */ 1918 #define BCM_PORT_TPID_CLASS_TPID_ANY 0xFFFFFFFE /* Value for any TPID in 1919 port TPID class 1920 configuration */ 1921 1922 /* bcm_port_tag_format_class_t */ 1923 typedef uint16 bcm_port_tag_format_class_t; 1924 1925 /* VLAN tag structure type */ 1926 typedef enum bcm_port_tag_struct_type_e { 1927 bcmTagStructTypeUntag = 0, /* Type Untagged */ 1928 bcmTagStructTypeSTag = 1, /* Type S tag */ 1929 bcmTagStructTypeCTag = 2, /* Type C tag */ 1930 bcmTagStructTypeSCTag = 3, /* Type S C tag */ 1931 bcmTagStructTypeSPrioCTag = 4, /* Type S prio C tag */ 1932 bcmTagStructTypeSSTag = 5, /* Type S S tag */ 1933 bcmTagStructTypeCCTag = 6, /* Type C C tag */ 1934 bcmNofTagStructType = 7 /* Number of tag structure types */ 1935 } bcm_port_tag_struct_type_t; 1936 1937 /* bcm_port_tpid_class_s */ 1938 typedef struct bcm_port_tpid_class_s { 1939 uint32 flags; /* BCM_PORT_TPID_CLASS_XXX */ 1940 bcm_gport_t port; /* Port ID */ 1941 uint32 tpid1; /* First TPID value, -1 for invalid */ 1942 uint32 tpid2; /* Second TPID value, -1 for invalid */ 1943 bcm_port_tag_format_class_t tag_format_class_id; /* VLAN tag format ID */ 1944 int vlan_translation_action_id; /* Default translation action ID */ 1945 uint32 vlan_translation_qos_map_id; /* Default translation QoS map ID */ 1946 uint32 tpid_class_id; /* TPID profile. */ 1947 } bcm_port_tpid_class_t; 1948 1949 /* Initialize the port TPID class structure */ 1950 extern void bcm_port_tpid_class_t_init( 1951 bcm_port_tpid_class_t *tpid_class); 1952 1953 #ifndef BCM_HIDE_DISPATCHABLE 1954 1955 /* 1956 * Set VLAN tag classification for a port. Given identified TPIDs on 1957 * packet set tag-classifier 1958 */ 1959 extern int bcm_port_tpid_class_set( 1960 int unit, 1961 bcm_port_tpid_class_t *tpid_class); 1962 1963 /* Get VLAN tag classification from a port */ 1964 extern int bcm_port_tpid_class_get( 1965 int unit, 1966 bcm_port_tpid_class_t *tpid_class); 1967 1968 /* Create VLAN tag classification */ 1969 extern int bcm_port_tpid_class_create( 1970 int unit, 1971 uint32 flags, 1972 bcm_port_tag_struct_type_t tag_struct_type, 1973 bcm_port_tag_format_class_t *tag_format_class_id); 1974 1975 /* Delete VLAN tag classification */ 1976 extern int bcm_port_tpid_class_destroy( 1977 int unit, 1978 uint32 flags, 1979 bcm_port_tag_format_class_t tag_format_class_id); 1980 1981 #endif /* BCM_HIDE_DISPATCHABLE */ 1982 1983 /* bcm_port_cable_state_t */ 1984 typedef _shr_port_cable_state_t bcm_port_cable_state_t; 1985 1986 #define BCM_PORT_CABLE_STATE_OK _SHR_PORT_CABLE_STATE_OK 1987 #define BCM_PORT_CABLE_STATE_OPEN _SHR_PORT_CABLE_STATE_OPEN 1988 #define BCM_PORT_CABLE_STATE_SHORT _SHR_PORT_CABLE_STATE_SHORT 1989 #define BCM_PORT_CABLE_STATE_OPENSHORT _SHR_PORT_CABLE_STATE_OPENSHORT 1990 #define BCM_PORT_CABLE_STATE_CROSSTALK _SHR_PORT_CABLE_STATE_CROSSTALK 1991 #define BCM_PORT_CABLE_STATE_UNKNOWN _SHR_PORT_CABLE_STATE_UNKNOWN 1992 #define BCM_PORT_CABLE_STATE_COUNT _SHR_PORT_CABLE_STATE_COUNT 1993 1994 /* bcm_port_cable_diag_t */ 1995 typedef _shr_port_cable_diag_t bcm_port_cable_diag_t; 1996 1997 #ifndef BCM_HIDE_DISPATCHABLE 1998 1999 /* Perform cable diagnostics on the specified port. */ 2000 extern int bcm_port_cable_diag( 2001 int unit, 2002 bcm_port_t port, 2003 bcm_port_cable_diag_t *status); 2004 2005 #endif /* BCM_HIDE_DISPATCHABLE */ 2006 2007 #define BCM_PORT_L3_MODIFY_NO_SRCMAC 0x0001 2008 #define BCM_PORT_L3_MODIFY_NO_DSTMAC 0x0002 2009 #define BCM_PORT_L3_MODIFY_NO_TTL 0x0004 2010 #define BCM_PORT_L3_MODIFY_NO_VLAN 0x0008 2011 2012 #ifndef BCM_HIDE_DISPATCHABLE 2013 2014 /* Get or set the L3 unicast packet modification operations of a port. */ 2015 extern int bcm_port_l3_modify_set( 2016 int unit, 2017 bcm_port_t port, 2018 uint32 flags); 2019 2020 /* Get or set the L3 unicast packet modification operations of a port. */ 2021 extern int bcm_port_l3_modify_get( 2022 int unit, 2023 bcm_port_t port, 2024 uint32 *flags); 2025 2026 #endif /* BCM_HIDE_DISPATCHABLE */ 2027 2028 #define BCM_PORT_IPMC_MODIFY_NO_SRCMAC 0x0001 2029 #define BCM_PORT_IPMC_MODIFY_NO_TTL 0x0004 2030 #define BCM_PORT_IPMC_CHECK_NO_TTL 0x0008 2031 2032 #ifndef BCM_HIDE_DISPATCHABLE 2033 2034 /* Get or set the L3 multicast packet modification operations of a port. */ 2035 extern int bcm_port_ipmc_modify_set( 2036 int unit, 2037 bcm_port_t port, 2038 uint32 flags); 2039 2040 /* Get or set the L3 multicast packet modification operations of a port. */ 2041 extern int bcm_port_ipmc_modify_get( 2042 int unit, 2043 bcm_port_t port, 2044 uint32 *flags); 2045 2046 #endif /* BCM_HIDE_DISPATCHABLE */ 2047 2048 /* 2049 * Port information valid fields 2050 * 2051 * Each field in the bcm_port_info_t structure has a corresponding mask 2052 * bit to control whether to get or set that value during the execution 2053 * of the bcm_port_selective_get/_set functions. The OR of all requested 2054 * ATTR masks should be stored in the action_mask field and the OR of all 2055 * requested ATTR2 masks should be stored in the action_mask2 field of 2056 * the bcm_port_info_t before calling the functions. 2057 */ 2058 #define BCM_PORT_ATTR_ENABLE_MASK 0x00000001 2059 #define BCM_PORT_ATTR_LINKSTAT_MASK 0x00000002 /* Get only. */ 2060 #define BCM_PORT_ATTR_AUTONEG_MASK 0x00000004 2061 #define BCM_PORT_ATTR_SPEED_MASK 0x00000008 2062 #define BCM_PORT_ATTR_DUPLEX_MASK 0x00000010 2063 #define BCM_PORT_ATTR_LINKSCAN_MASK 0x00000020 2064 #define BCM_PORT_ATTR_LEARN_MASK 0x00000040 2065 #define BCM_PORT_ATTR_DISCARD_MASK 0x00000080 2066 #define BCM_PORT_ATTR_VLANFILTER_MASK 0x00000100 2067 #define BCM_PORT_ATTR_UNTAG_PRI_MASK 0x00000200 2068 #define BCM_PORT_ATTR_UNTAG_VLAN_MASK 0x00000400 2069 #define BCM_PORT_ATTR_STP_STATE_MASK 0x00000800 2070 #define BCM_PORT_ATTR_PFM_MASK 0x00001000 2071 #define BCM_PORT_ATTR_LOOPBACK_MASK 0x00002000 2072 #define BCM_PORT_ATTR_PHY_MASTER_MASK 0x00004000 2073 #define BCM_PORT_ATTR_INTERFACE_MASK 0x00008000 2074 #define BCM_PORT_ATTR_PAUSE_TX_MASK 0x00010000 2075 #define BCM_PORT_ATTR_PAUSE_RX_MASK 0x00020000 2076 #define BCM_PORT_ATTR_PAUSE_MAC_MASK 0x00040000 2077 #define BCM_PORT_ATTR_LOCAL_ADVERT_MASK 0x00080000 2078 #define BCM_PORT_ATTR_REMOTE_ADVERT_MASK 0x00100000 /* Get only. */ 2079 #define BCM_PORT_ATTR_ENCAP_MASK 0x00200000 2080 #define BCM_PORT_ATTR_RATE_MCAST_MASK 0x00400000 2081 #define BCM_PORT_ATTR_RATE_BCAST_MASK 0x00800000 2082 #define BCM_PORT_ATTR_RATE_DLFBC_MASK 0x01000000 2083 #define BCM_PORT_ATTR_SPEED_MAX_MASK 0x02000000 /* Get only. */ 2084 #define BCM_PORT_ATTR_ABILITY_MASK 0x04000000 /* Get only. */ 2085 #define BCM_PORT_ATTR_FRAME_MAX_MASK 0x08000000 2086 #define BCM_PORT_ATTR_MDIX_MASK 0x10000000 2087 #define BCM_PORT_ATTR_MDIX_STATUS_MASK 0x20000000 2088 #define BCM_PORT_ATTR_MEDIUM_MASK 0x40000000 2089 #define BCM_PORT_ATTR_FAULT_MASK 0x80000000 /* Get only. */ 2090 #define BCM_PORT_ATTR2_PORT_ABILITY 0x00000001 2091 2092 /* Backward compatibility. */ 2093 #define BCM_PORT_ATTR_SPEED_MAX BCM_PORT_ATTR_SPEED_MAX_MASK 2094 #define BCM_PORT_ATTR_ABILITY BCM_PORT_ATTR_ABILITY_MASK 2095 2096 #define BCM_PORT_ATTR_ALL_MASK 0xffffffff 2097 #define BCM_PORT_ATTR_PAUSE_MASK \ 2098 (BCM_PORT_ATTR_PAUSE_TX_MASK | \ 2099 BCM_PORT_ATTR_PAUSE_RX_MASK) 2100 #define BCM_PORT_ATTR_RATE_MASK \ 2101 (BCM_PORT_ATTR_RATE_MCAST_MASK | \ 2102 BCM_PORT_ATTR_RATE_BCAST_MASK | \ 2103 BCM_PORT_ATTR_RATE_DLFBC_MASK) 2104 2105 /* Attributes that can be controlled on BCM5670/75. */ 2106 #define BCM_PORT_HERC_ATTRS \ 2107 (BCM_PORT_ATTR_ENABLE_MASK | \ 2108 BCM_PORT_ATTR_LINKSTAT_MASK | \ 2109 BCM_PORT_ATTR_SPEED_MASK | \ 2110 BCM_PORT_ATTR_DUPLEX_MASK | \ 2111 BCM_PORT_ATTR_LINKSCAN_MASK | \ 2112 BCM_PORT_ATTR_INTERFACE_MASK | \ 2113 BCM_PORT_ATTR_LOOPBACK_MASK | \ 2114 BCM_PORT_ATTR_PAUSE_TX_MASK | \ 2115 BCM_PORT_ATTR_PAUSE_RX_MASK | \ 2116 BCM_PORT_ATTR_PAUSE_MAC_MASK | \ 2117 BCM_PORT_ATTR_FRAME_MAX_MASK | \ 2118 BCM_PORT_ATTR_ENCAP_MASK) 2119 2120 /* Attributes specific to XGS devices. */ 2121 #define BCM_PORT_XGS_ATTRS (BCM_PORT_ATTR_ENCAP_MASK) 2122 2123 /* Auto-negotiated values. */ 2124 #define BCM_PORT_AN_ATTRS \ 2125 (BCM_PORT_ATTR_SPEED_MASK | \ 2126 BCM_PORT_ATTR_DUPLEX_MASK | \ 2127 BCM_PORT_ATTR_PAUSE_MASK) 2128 2129 /* bcm_port_info_s */ 2130 typedef struct bcm_port_info_s { 2131 uint32 action_mask; /* BCM_PORT_ATTR_xxx. */ 2132 uint32 action_mask2; /* BCM_PORT_ATTR2_xxx. */ 2133 int enable; 2134 int linkstatus; 2135 int autoneg; 2136 int speed; 2137 int duplex; 2138 int linkscan; 2139 uint32 learn; 2140 int discard; 2141 uint32 vlanfilter; 2142 int untagged_priority; 2143 bcm_vlan_t untagged_vlan; 2144 int stp_state; 2145 int pfm; 2146 int loopback; 2147 int phy_master; 2148 bcm_port_if_t interface; 2149 int pause_tx; 2150 int pause_rx; 2151 int encap_mode; 2152 bcm_mac_t pause_mac; 2153 bcm_port_abil_t local_advert; 2154 bcm_port_ability_t local_ability; 2155 int remote_advert_valid; 2156 bcm_port_abil_t remote_advert; 2157 bcm_port_ability_t remote_ability; 2158 int mcast_limit; 2159 int mcast_limit_enable; 2160 int bcast_limit; 2161 int bcast_limit_enable; 2162 int dlfbc_limit; 2163 int dlfbc_limit_enable; 2164 int speed_max; 2165 bcm_port_abil_t ability; 2166 bcm_port_ability_t port_ability; 2167 int frame_max; 2168 bcm_port_mdix_t mdix; 2169 bcm_port_mdix_status_t mdix_status; 2170 bcm_port_medium_t medium; 2171 uint32 fault; 2172 } bcm_port_info_t; 2173 2174 #ifndef BCM_HIDE_DISPATCHABLE 2175 2176 /* Get or set multiple port characteristics. */ 2177 extern int bcm_port_info_get( 2178 int unit, 2179 bcm_port_t port, 2180 bcm_port_info_t *info); 2181 2182 /* Get or set multiple port characteristics. */ 2183 extern int bcm_port_info_set( 2184 int unit, 2185 bcm_port_t port, 2186 bcm_port_info_t *info); 2187 2188 /* Get or set multiple port characteristics. */ 2189 extern int bcm_port_selective_get( 2190 int unit, 2191 bcm_port_t port, 2192 bcm_port_info_t *info); 2193 2194 /* Get or set multiple port characteristics. */ 2195 extern int bcm_port_selective_set( 2196 int unit, 2197 bcm_port_t port, 2198 bcm_port_info_t *info); 2199 2200 /* Get or set multiple port characteristics. */ 2201 extern int bcm_port_info_restore( 2202 int unit, 2203 bcm_port_t port, 2204 bcm_port_info_t *info); 2205 2206 /* Get or set multiple port characteristics. */ 2207 extern int bcm_port_info_save( 2208 int unit, 2209 bcm_port_t port, 2210 bcm_port_info_t *info); 2211 2212 /* Gets the physical driver name. */ 2213 extern int bcm_port_phy_drv_name_get( 2214 int unit, 2215 bcm_port_t port, 2216 char *name, 2217 int len); 2218 2219 #endif /* BCM_HIDE_DISPATCHABLE */ 2220 2221 /* Values for EPON port DBA Polling Intervals. */ 2222 #define BCM_PORT_PON_POLLING_INTERVALS 8 /* Number of DBA Polling 2223 Intervals. */ 2224 2225 /* bcm_port_pon_info_s */ 2226 typedef struct bcm_port_pon_info_s { 2227 int llid; 2228 int enable; 2229 int linkstatus; 2230 int oam_discovery_status; 2231 int loopback; 2232 bcm_mac_t olt_mac_addr; 2233 int polling_intervals[BCM_PORT_PON_POLLING_INTERVALS]; 2234 } bcm_port_pon_info_t; 2235 2236 #ifndef BCM_HIDE_DISPATCHABLE 2237 2238 /* Get or set multiple characteristics for PON port and logical link. */ 2239 extern int bcm_port_pon_info_get( 2240 int unit, 2241 bcm_port_t pon_port, 2242 bcm_port_pon_info_t *info); 2243 2244 /* Get or set multiple characteristics for PON port and logical link. */ 2245 extern int bcm_port_pon_info_set( 2246 int unit, 2247 bcm_port_t pon_port, 2248 bcm_port_pon_info_t *info); 2249 2250 #endif /* BCM_HIDE_DISPATCHABLE */ 2251 2252 /* Port link fault signalling. */ 2253 #define BCM_PORT_FAULT_LOCAL _SHR_PORT_FAULT_LOCAL 2254 #define BCM_PORT_FAULT_REMOTE _SHR_PORT_FAULT_REMOTE 2255 2256 /* 2257 * Port Rate Egress Traffic identifiers for QE Fifo Selectors into 2258 * Shapers. 2259 */ 2260 #define BCM_PORT_RATE_TRAFFIC_UC_EF 0x0001 2261 #define BCM_PORT_RATE_TRAFFIC_UC_NON_EF 0x0002 2262 #define BCM_PORT_RATE_TRAFFIC_NON_UC_EF 0x0200 2263 #define BCM_PORT_RATE_TRAFFIC_NON_UC_NON_EF 0x0100 2264 #define BCM_PORT_RATE_TRAFFIC_ALL 0x0303 2265 2266 #ifndef BCM_HIDE_DISPATCHABLE 2267 2268 /* Get link fault type. */ 2269 extern int bcm_port_fault_get( 2270 int unit, 2271 bcm_port_t port, 2272 uint32 *flags); 2273 2274 /* 2275 * Set or get port index of a trunk for ingress port that is used to 2276 * select the egress port in the trunk. 2277 */ 2278 extern int bcm_port_trunk_index_set( 2279 int unit, 2280 bcm_port_t port, 2281 int port_index); 2282 2283 /* 2284 * Set or get port index of a trunk for ingress port that is used to 2285 * select the egress port in the trunk. 2286 */ 2287 extern int bcm_port_trunk_index_get( 2288 int unit, 2289 bcm_port_t port, 2290 int *port_index); 2291 2292 /* Set or retrieve color assignment for a given port and priority. */ 2293 extern int bcm_port_priority_color_set( 2294 int unit, 2295 bcm_port_t port, 2296 int prio, 2297 bcm_color_t color); 2298 2299 /* Set or retrieve color assignment for a given port and priority. */ 2300 extern int bcm_port_priority_color_get( 2301 int unit, 2302 bcm_port_t port, 2303 int prio, 2304 bcm_color_t *color); 2305 2306 /* Set or retrieve color assignment for a given port and CFI. */ 2307 extern int bcm_port_cfi_color_set( 2308 int unit, 2309 bcm_port_t port, 2310 int cfi, 2311 bcm_color_t color); 2312 2313 /* Set or retrieve color assignment for a given port and CFI. */ 2314 extern int bcm_port_cfi_color_get( 2315 int unit, 2316 bcm_port_t port, 2317 int cfi, 2318 bcm_color_t *color); 2319 2320 /* 2321 * Map the incoming packet priority and CFI to internal priority and 2322 * color. 2323 */ 2324 extern int bcm_port_vlan_priority_map_set( 2325 int unit, 2326 bcm_port_t port, 2327 int pkt_pri, 2328 int cfi, 2329 int internal_pri, 2330 bcm_color_t color); 2331 2332 /* 2333 * Map the incoming packet priority and CFI to internal priority and 2334 * color. 2335 */ 2336 extern int bcm_port_vlan_priority_map_get( 2337 int unit, 2338 bcm_port_t port, 2339 int pkt_pri, 2340 int cfi, 2341 int *internal_pri, 2342 bcm_color_t *color); 2343 2344 /* 2345 * Map the internal priority and color to outgoing packet priority and 2346 * CFI. 2347 */ 2348 extern int bcm_port_vlan_priority_unmap_set( 2349 int unit, 2350 bcm_port_t port, 2351 int internal_pri, 2352 bcm_color_t color, 2353 int pkt_pri, 2354 int cfi); 2355 2356 /* 2357 * Map the internal priority and color to outgoing packet priority and 2358 * CFI. 2359 */ 2360 extern int bcm_port_vlan_priority_unmap_get( 2361 int unit, 2362 bcm_port_t port, 2363 int internal_pri, 2364 bcm_color_t color, 2365 int *pkt_pri, 2366 int *cfi); 2367 2368 /* 2369 * Map the incoming packet priority and CFI to internal priority and 2370 * color on a per-port per-vlan basis. 2371 */ 2372 extern int bcm_port_vlan_pri_map_set( 2373 int unit, 2374 bcm_port_t port, 2375 bcm_vlan_t vlan, 2376 int pkt_pri, 2377 int cfi, 2378 int internal_pri, 2379 bcm_color_t color); 2380 2381 /* 2382 * Get the mapping of incoming packet priority and CFI to internal 2383 * priority and color. 2384 */ 2385 extern int bcm_port_vlan_pri_map_get( 2386 int unit, 2387 bcm_port_t port, 2388 bcm_vlan_t vlan, 2389 int pkt_pri, 2390 int cfi, 2391 int *internal_pri, 2392 bcm_color_t *color); 2393 2394 /* Map the incoming IP packet DSCP to internal priority and color. */ 2395 extern int bcm_port_vlan_dscp_map_set( 2396 int unit, 2397 bcm_port_t port, 2398 bcm_vlan_t vlan, 2399 int dscp, 2400 int internal_pri, 2401 bcm_color_t color); 2402 2403 /* 2404 * Get the mapping of incoming IP packet DSCP to internal priority and 2405 * color. 2406 */ 2407 extern int bcm_port_vlan_dscp_map_get( 2408 int unit, 2409 bcm_port_t port, 2410 bcm_vlan_t vlan, 2411 int dscp, 2412 int *internal_pri, 2413 bcm_color_t *color); 2414 2415 /* Map the internal priority and color to outgoing packet dscp. */ 2416 extern int bcm_port_dscp_unmap_set( 2417 int unit, 2418 bcm_port_t port, 2419 int internal_pri, 2420 bcm_color_t color, 2421 int pkt_dscp); 2422 2423 /* 2424 * Get the mapping of internal priority and color to outgoing packet 2425 * dscp. 2426 */ 2427 extern int bcm_port_dscp_unmap_get( 2428 int unit, 2429 bcm_port_t port, 2430 int internal_pri, 2431 bcm_color_t color, 2432 int *pkt_dscp); 2433 2434 #endif /* BCM_HIDE_DISPATCHABLE */ 2435 2436 /* bcm_priority_mapping_t_init */ 2437 extern void bcm_priority_mapping_t_init( 2438 bcm_priority_mapping_t *pri_map); 2439 2440 #ifndef BCM_HIDE_DISPATCHABLE 2441 2442 /* 2443 * Set the mapping of wire/packet pri and cfi to internal priority and 2444 * color. 2445 */ 2446 extern int bcm_port_vlan_priority_mapping_set( 2447 int unit, 2448 bcm_port_t port, 2449 bcm_vlan_t vid, 2450 int pkt_pri, 2451 int cfi, 2452 bcm_priority_mapping_t *pri_map); 2453 2454 /* 2455 * Get the mapping of wire/packet pri and cfi to internal priority and 2456 * color. 2457 */ 2458 extern int bcm_port_vlan_priority_mapping_get( 2459 int unit, 2460 bcm_port_t port, 2461 bcm_vlan_t vid, 2462 int pkt_pri, 2463 int cfi, 2464 bcm_priority_mapping_t *pri_map); 2465 2466 /* Set the inner tag value to be added to the outgoing packet. */ 2467 extern int bcm_port_vlan_inner_tag_set( 2468 int unit, 2469 bcm_port_t port, 2470 uint16 inner_tag); 2471 2472 /* Set the inner tag value to be added to the outgoing packet. */ 2473 extern int bcm_port_vlan_inner_tag_get( 2474 int unit, 2475 bcm_port_t port, 2476 uint16 *inner_tag); 2477 2478 /* Set or get egress override port. */ 2479 extern int bcm_port_force_forward_set( 2480 int unit, 2481 bcm_port_t port, 2482 bcm_port_t egr_port, 2483 int enable); 2484 2485 /* Set or get egress override port. */ 2486 extern int bcm_port_force_forward_get( 2487 int unit, 2488 bcm_port_t port, 2489 bcm_port_t *egr_port, 2490 int *enabled); 2491 2492 #endif /* BCM_HIDE_DISPATCHABLE */ 2493 2494 #define BCM_PORT_FORCE_FORWARD_DISABLE 0x0 /* Normal switching */ 2495 #define BCM_PORT_FORCE_FORWARD_ALL 0x1 /* Redirect all ingress port 2496 traffic to specified port */ 2497 #define BCM_PORT_FORCE_FORWARD_LOCAL 0x2 /* Redirect all ingress port 2498 traffic which would 2499 otherwise go to a local 2500 port to the specified port */ 2501 2502 #ifndef BCM_HIDE_DISPATCHABLE 2503 2504 /* Set egress override port mode. */ 2505 extern int bcm_port_force_forward_mode_set( 2506 int unit, 2507 bcm_port_t port, 2508 bcm_port_t egr_port, 2509 uint32 flags); 2510 2511 /* Get egress override port. */ 2512 extern int bcm_port_force_forward_mode_get( 2513 int unit, 2514 bcm_port_t port, 2515 bcm_port_t *egr_port, 2516 uint32 *flags); 2517 2518 /* Set forwarding destination. */ 2519 extern int bcm_port_force_dest_set( 2520 int unit, 2521 bcm_gport_t gport, 2522 bcm_port_dest_info_t *dest_info); 2523 2524 /* Get forwarding destination. */ 2525 extern int bcm_port_force_dest_get( 2526 int unit, 2527 bcm_gport_t gport, 2528 bcm_port_dest_info_t *dest_info); 2529 2530 #endif /* BCM_HIDE_DISPATCHABLE */ 2531 2532 /* bcm_port_class_e */ 2533 typedef enum bcm_port_class_e { 2534 bcmPortClassFieldLookup = 0, /* Class for field stage Lookup */ 2535 bcmPortClassFieldIngress = 1, /* Class for field stage Ingress */ 2536 bcmPortClassFieldEgress = 2, /* Class for field stage Egress */ 2537 bcmPortClassVlanTranslateEgress = 3, /* Class for egress VLAN translation */ 2538 bcmPortClassIngress = 4, /* Class for ingress basis grouping */ 2539 bcmPortClassId = 5, /* Class for mapping local-port to 2540 vlan-domain. vlan domain is used in 2541 mapping packet VID to Vlan */ 2542 bcmPortClassFieldIngressPacketProcessing = 6, /* Packet processing port Class lower 32 2543 bits for field stage Ingress */ 2544 bcmPortClassFieldEgressPacketProcessing = 7, /* Packet processing port Class for 2545 field stage Egress */ 2546 bcmPortClassL2Lookup = 8, /* Class for L2 lookup */ 2547 bcmPortClassForwardIngress = 9, /* Class for ingress forwarding */ 2548 bcmPortClassForwardEgress = 10, /* Class for egress forwarding */ 2549 bcmPortClassFieldIngressVlanTranslation = 11, /* Class for field stage Ingress Vlan 2550 Translation */ 2551 bcmPortClassFieldIngressTunnelTerminated = 12, /* Class for field stage Ingress Tunnel 2552 Terminated */ 2553 bcmPortClassProgramEditorEgressPacketProcessing = 13, /* Class for Egress Programmable Editor 2554 properties */ 2555 bcmPortClassEgress = 14, /* EGR_PORT class ID field for field 2556 stage Egress */ 2557 bcmPortClassFieldIngressGroupSel = 15, /* Per port Class ID for field stage 2558 Ingress group selection */ 2559 bcmPortClassFieldIngressSystemPort = 16, /* virtual port instance of SGLP in IFP 2560 IPBM key */ 2561 bcmPortClassFieldIngressSourceGport = 17, /* virtual port instance of SVP in IFP 2562 IPBM key */ 2563 bcmPortClassFieldIngressDevicePort = 18, /* virtual port instance of device port 2564 in IFP IPBM key */ 2565 bcmPortClassVlanTranslateIngress = 19, /* Class for ingress VLAN translation */ 2566 bcmPortClassProgramEditorEgressTrafficManagement = 20, /* Traffic management port Class for 2567 field stage Egress */ 2568 bcmPortClassFieldIngressPacketProcessingHigh = 21, /* Packet processing port Class high 32 2569 bits for field stage Ingress */ 2570 bcmPortClassVlanMember = 22, /* Class for VLAN Membership */ 2571 bcmPortClassFieldIngressVport = 23, /* Class for LIF encoded as Gport in the 2572 Field Ingres stages */ 2573 bcmPortClassFieldEgressVport = 24, /* Class for LIF encoded as Gport in the 2574 Field stage ePMF */ 2575 bcmPortClassFieldIngressPMF1PacketProcessingPort = 25, /* Class for packet processing port in 2576 Field stage iPMF1 */ 2577 bcmPortClassFieldIngressPMF1PacketProcessingPortCs = 26, /* Context selection class for packet 2578 processing port in Field stage iPMF1 */ 2579 bcmPortClassFieldIngressPMF3PacketProcessingPort = 27, /* Class for packet processing port in 2580 Field stage iPMF3 */ 2581 bcmPortClassFieldIngressPMF3PacketProcessingPortCs = 28, /* Context selection class for packet 2582 processing port in Field stage iPMF3 */ 2583 bcmPortClassFieldEgressPacketProcessingPort = 29, /* Class for packet processing port in 2584 Field stage ePMF */ 2585 bcmPortClassFieldEgressPacketProcessingPortCs = 30, /* Context selection class for packet 2586 processing port in Field stage ePMF */ 2587 bcmPortClassFieldExternalPacketProcessingPortCs = 31, /* Context selection class for packet 2588 processing port in Field stage 2589 external */ 2590 bcmPortClassFieldIngressPMF1TrafficManagementPort = 32, /* Class for traffic management port in 2591 Field stage iPMF1 */ 2592 bcmPortClassFieldIngressPMF1TrafficManagementPortCs = 33, /* Context selection class for traffic 2593 management port in Field stage iPMF1 */ 2594 bcmPortClassFieldIngressPMF3TrafficManagementPort = 34, /* Class for traffic management port in 2595 Field stage iPMF3 */ 2596 bcmPortClassFieldIngressPMF3TrafficManagementPortCs = 35, /* Context selection class for traffic 2597 management port in Field stage iPMF3 */ 2598 bcmPortClassFieldEgressTrafficManagementPort = 36, /* Class for traffic management 2599 processing port in Field stage ePMF */ 2600 bcmPortClassFieldExternalTrafficManagementPortCs = 37, /* Context selection class for traffic 2601 management port in Field stage 2602 external */ 2603 bcmPortClassFieldIngressPMF1PacketProcessingPortGeneralData = 38, /* Extra constant to assign to a packet 2604 processing port, up to 32lsb. Field 2605 stage iPMF1. */ 2606 bcmPortClassFieldIngressPMF1PacketProcessingPortGeneralDataHigh = 39, /* Extra constant to assign to a packet 2607 processing port, beyond the first 32 2608 bits. Field stage iPMF1. */ 2609 bcmPortClassFieldIngressPMF3PacketProcessingPortGeneralData = 40, /* Extra constant to assign to a packet 2610 processing port, first 32 bits. Field 2611 stage iPMF3. */ 2612 bcmPortClassFieldIngressPMF3PacketProcessingPortGeneralDataHigh = 41, /* Extra constant to assign to a packet 2613 processing port, beyond the first 32 2614 bits. Field stage iPMF3. */ 2615 bcmPortClassCount = 42 /* Last enum value. */ 2616 } bcm_port_class_t; 2617 2618 #ifndef BCM_HIDE_DISPATCHABLE 2619 2620 /* 2621 * Set or get port classification ID to aggregate a group of ports for 2622 * further processing such as Vlan translation and field processing. 2623 */ 2624 extern int bcm_port_class_set( 2625 int unit, 2626 bcm_port_t port, 2627 bcm_port_class_t pclass, 2628 uint32 class_id); 2629 2630 /* 2631 * Set or get port classification ID to aggregate a group of ports for 2632 * further processing such as Vlan translation and field processing. 2633 */ 2634 extern int bcm_port_class_get( 2635 int unit, 2636 bcm_port_t port, 2637 bcm_port_class_t pclass, 2638 uint32 *class_id); 2639 2640 #endif /* BCM_HIDE_DISPATCHABLE */ 2641 2642 /* Features that can be controlled on a per-port basis. */ 2643 typedef enum bcm_port_control_e { 2644 bcmPortControlBridge = 0, /* Enable local port bridging. */ 2645 bcmPortControlTrunkHashSet = 1, /* Select one of the two sets of hash 2646 bits selection configuration for 2647 trunking. */ 2648 bcmPortControlFabricTrunkHashSet = 2, /* Select one of the two sets of hash 2649 bits selection configuration for 2650 fabric trunking. */ 2651 bcmPortControlECMPHashSet = 3, /* Select one of the two sets of hash 2652 bits selection configuration for 2653 ECMP. */ 2654 bcmPortControlLoadBalanceHashSet = 4, /* Select one of the two sets of hash 2655 bits selection configuration for LBID 2656 to be populated in HiGig2 header. */ 2657 bcmPortControlLoadBalancingNumber = 5, /* Assigns the Load Balancing Number of 2658 this port for HiGig2 headers. */ 2659 bcmPortControlErrorSymbolDetect = 6, /* Enable or disable XAUI |E| monitoring 2660 feature for port's XAUI lanes. */ 2661 bcmPortControlErrorSymbolCount = 7, /* Get the number of XAUI |E| symbol 2662 occured since last read. Setting any 2663 value to the count will set it to 2664 zero. */ 2665 bcmPortControlIP4 = 8, /* Enable IPv4 Routing on port. */ 2666 bcmPortControlIP6 = 9, /* Enable IPv6 Routing on port. */ 2667 bcmPortControlIP4Mcast = 10, /* Enable IPv4 Multicast on port. */ 2668 bcmPortControlIP6Mcast = 11, /* Enable IPv6 Multicast on port. */ 2669 bcmPortControlIP4McastL2 = 12, /* Enable L2 switching on IPv4 IPMC 2670 packets based on (SG,*G) instead of 2671 (DMAC,VLAN). */ 2672 bcmPortControlIP6McastL2 = 13, /* Enable L2 switching on IPv6 IPMC 2673 packets based on (SG,*G) instead of 2674 (DMAC,VLAN). */ 2675 bcmPortControlMpls = 14, /* Enable MPLS on the port ingress. */ 2676 bcmPortControlPassControlFrames = 15, /* Enable controls frames on port. */ 2677 bcmPortControlFilterLookup = 16, /* Enable port lookup Field Processor. */ 2678 bcmPortControlFilterIngress = 17, /* Enable ingress Field Processor on 2679 port. */ 2680 bcmPortControlFilterEgress = 18, /* Enable egress Field Processor on 2681 port. */ 2682 bcmPortControlFrameSpacingStretch = 19, /* One byte of inter packet gap is added 2683 for specified number of packet data 2684 bytes. If the value is 10, one byte 2685 of IPG is added for each 10 byte of 2686 packet data. */ 2687 bcmPortControlPreservePacketPriority = 20, /* Preserve packet original IEEE 802.1p 2688 priority. */ 2689 bcmPortControlLearnClassEnable = 21, /* Enable class based station movement 2690 checks. */ 2691 bcmPortControlTrustIncomingVlan = 22, /* Trust incoming packet's Vlan tag */ 2692 bcmPortControlDoNotCheckVlan = 23, /* Enable/disable spanning tree and Vlan 2693 membership checks on ingress ethernet 2694 and higig packets. For cpu port 2695 configuration is applied only for 2696 higig packets. To configure these 2697 settings for ethernet packets 2698 bcmPortControlDoNotCheckVlanFromCpu 2699 port control can be used. */ 2700 bcmPortControlDoNotCheckVlanFromCpu = 24, /* Enable/disable spanning tree and Vlan 2701 membership checks on ethernet packets 2702 that are ingressed from cpu port. */ 2703 bcmPortControlIEEE8021ASEnableIngress = 25, /* Enable/disable ingress processing of 2704 IEEE 802.1AS protocol packets. */ 2705 bcmPortControlIEEE8021ASEnableEgress = 26, /* Enable/disable egress processing of 2706 IEEE 802.1AS protocol packets. */ 2707 bcmPortControlPrbsMode = 27, /* PRBS location - 0=>Phy PRBS 1=>MAC/SI 2708 Port */ 2709 bcmPortControlPrbsPolynomial = 28, /* Assigns PRBS polynomial, 2710 BCM_PORT_PRBS_POLYNOMIAL_ */ 2711 bcmPortControlPrbsTxInvertData = 29, /* Configure inversion of Tx data */ 2712 bcmPortControlPrbsForceTxError = 30, /* Configure insertion of Tx errors */ 2713 bcmPortControlPrbsTxEnable = 31, /* Enable Tx PRBS */ 2714 bcmPortControlPrbsRxEnable = 32, /* Enable Rx PRBS */ 2715 bcmPortControlPrbsRxStatus = 33, /* PRBS Rx status */ 2716 bcmPortControlSerdesDriverStrength = 34, /* Assigns Driver Strength */ 2717 bcmPortControlSerdesDriverEqualization = 35, /* Assigns Driver Equalization */ 2718 bcmPortControlSerdesDriverEqualizationFarEnd = 36, /* Informs software of far end transmit 2719 driver equalization setting for 2720 tuning */ 2721 bcmPortControlSerdesDriverTune = 37, /* Start hardware receive equalization 2722 tuning */ 2723 bcmPortControlSerdesDriverEqualizationTuneStatusFarEnd = 38, /* Get results of tune operation which 2724 include suggested far end 2725 equalization update */ 2726 bcmPortControlAbility = 39, /* Assigns Port ability, 2727 BCM_PORT_ABILITY_ */ 2728 bcmPortControlMacInMac = 40, /* Enable/Disable MiM frame processing */ 2729 bcmPortControlSrcBmacMissToCpu = 41, /* Mac-in-Mac Source BMAC lookup miss, 2730 Send to CPU (value = TRUE/FALSE) */ 2731 bcmPortControlOamLoopback = 42, /* Enable/Disable 802.3 Clause 57 Oam 2732 Loopback */ 2733 bcmPortControlEgressVlanPriUsesPktPri = 43, /* If set, outgoing packets derive their 2734 priority from the incoming priority */ 2735 bcmPortControlPacketFlowMode = 45, /* Enable/Disable requeue for hybrid 2736 mode */ 2737 bcmPortControlTrain = 46, /* Start/stop training sequence */ 2738 bcmPortControlRxEnable = 47, /* Rx enable/disable */ 2739 bcmPortControlTxEnable = 48, /* Tx enable/disable */ 2740 bcmPortControlRxLink = 49, /* Retreives Rx Status */ 2741 bcmPortControlTxLink = 50, /* Retreives Tx Status */ 2742 bcmPortControlIpfixRate = 51, /* Set IPFIX flow rate meter id */ 2743 bcmPortControlOAMEnable = 52, /* Enable reception of OAM messages */ 2744 bcmPortControlCustomerQueuing = 53, /* Enable customer domain queuing */ 2745 bcmPortControlFabricKnockoutId = 54, /* sets port identifier, used for source 2746 knockout functionality */ 2747 bcmPortControlLanes = 55, /* Sets the number of active lanes for a 2748 port that can be dynamically 2749 hot-swapped. */ 2750 bcmPortControlEgressNonUnicastLossless = 56, /* Enable/Disable multicast Lossless 2751 operation */ 2752 bcmPortControlPFCEthertype = 57, /* Priority Flow Control packet 2753 Ethertype */ 2754 bcmPortControlPFCOpcode = 58, /* Priority Flow Control packet opcode */ 2755 bcmPortControlPFCReceive = 59, /* Priority Flow Control packet receive 2756 enable */ 2757 bcmPortControlPFCTransmit = 60, /* Priority Flow Control packet transmit 2758 enable */ 2759 bcmPortControlPFCClasses = 61, /* Priority Flow Control number of 2760 classes */ 2761 bcmPortControlPFCPassFrames = 62, /* Allow Priority Flow Control packets 2762 into switch device */ 2763 bcmPortControlPFCDestMacOui = 63, /* Priority Flow Control packet 2764 destination MAC address, upper three 2765 bytes */ 2766 bcmPortControlPFCDestMacNonOui = 64, /* Priority Flow Control packet 2767 destination MAC address, lower three 2768 bytes */ 2769 bcmPortControlPFCRefreshTime = 65, /* Priority Flow Control refresh time */ 2770 bcmPortControlVrf = 66, /* Enable per-port VRF to override 2771 per-Vlan VRF */ 2772 bcmPortControlL3Ingress = 67, /* Enable per-port L3-IIF for IP traffic */ 2773 bcmPortControlL2Learn = 69, /* Configure L2 learning behavior using 2774 BCM_PORT_LEARN_xxx flags */ 2775 bcmPortControlL2Move = 70, /* Configure L2 station movement 2776 behavior using BCM_PORT_LEARN_xxx 2777 flags */ 2778 bcmPortControlForwardStaticL2MovePkt = 71, /* Allow forwarding L2 packet even if L2 2779 movement is detected against an 2780 existing static entry in L2 table */ 2781 bcmPortControlLinkFaultLocalEnable = 72, /* Enable local LSS message processing */ 2782 bcmPortControlLinkFaultRemoteEnable = 73, /* Enable remote LSS message processing */ 2783 bcmPortControlLinkFaultLocal = 74, /* Read local LSS message processing 2784 status */ 2785 bcmPortControlLinkFaultRemote = 75, /* Read remote LSS message processing 2786 status */ 2787 bcmPortControlTimestampTransmit = 76, /* Read the timestamp value assigned to 2788 TX packet */ 2789 bcmPortControlTimestampEnable = 77, /* Set the port to be capable of 2790 timestamping TX packet */ 2791 bcmPortControlTCPriority = 78, /* Indicates the default Traffic Class 2792 attributes assoiated with the port */ 2793 bcmPortControlDropPrecedence = 79, /* Indicates the default Drop Precedence 2794 attributes assoiated with the port */ 2795 bcmPortControlFabricQueue = 80, /* Enable ext header on Higig port. */ 2796 bcmPortControlLinkdownTransmit = 81, /* Enable transmission when linkdown */ 2797 bcmPortControlEEETransmitWakeTime = 82, /* Time(in microsecs) to wait before 2798 transmitter can begin transmitting 2799 leaving Low Power Idle State */ 2800 bcmPortControlEEEReceiveWakeTime = 83, /* Time(in microsecs) Receiver counts 2801 for SLEEP or IDLE symbols to move to 2802 Active from Low Power Idle State */ 2803 bcmPortControlEEETransmitSleepTime = 84, /* Time(in microsecs) Tranmitter sends 2804 SLEEP symbols before going to QUIET 2805 state */ 2806 bcmPortControlEEEReceiveSleepTime = 85, /* Time(in microsecs) Receiver is in 2807 SLEEP state before entering QUIET 2808 state */ 2809 bcmPortControlEEETransmitQuietTime = 86, /* Time(in microsecs) transmit stays in 2810 Quiet state before entering REFRESH 2811 state */ 2812 bcmPortControlEEEReceiveQuietTime = 87, /* Time(in microsecs) Receiver stays in 2813 Quiet state before it expects REFRESH 2814 signal */ 2815 bcmPortControlEEETransmitRefreshTime = 88, /* Time(in microsecs) transmitter stays 2816 in Refresh state */ 2817 bcmPortControlSerdesTuneMarginMax = 89, /* SerDes max tune margin value */ 2818 bcmPortControlSerdesTuneMarginMode = 90, /* SerDes in tune margin mode */ 2819 bcmPortControlSerdesTuneMarginValue = 91, /* Value used to measure tune margin */ 2820 bcmPortControlStatOversize = 92, /* Threshold above which packet will be 2821 counted as oversized */ 2822 bcmPortControlStatOversizeIsError = 93, /* Oversize Threshold flag to control 2823 oversize packets as error counts */ 2824 bcmPortControlEEEEnable = 94, /* Enable/Disable Energy Efficient 2825 Ethernet */ 2826 bcmPortControlEEEStatisticsClear = 95, /* Clear Energy Efficient Ethernet Low 2827 Power Idle Statistics */ 2828 bcmPortControlEEETransmitIdleTime = 96, /* Time (in microsecs) for which 2829 condition to move to LPI state is 2830 satisfied, at the end of which MAC 2831 transitions to LPI state */ 2832 bcmPortControlEEETransmitEventCount = 97, /* Number of time MAC TX enters LPI 2833 state for a given measurement 2834 interval */ 2835 bcmPortControlEEETransmitDuration = 98, /* Time (in microseconds) for which MAC 2836 TX is in LPI state during a 2837 measurement interval */ 2838 bcmPortControlEEEReceiveEventCount = 99, /* Number of time MAC RX enters LPI 2839 state for a given measurement 2840 interval */ 2841 bcmPortControlEEEReceiveDuration = 100, /* Time (in microseconds) for which MAC 2842 RX is in LPI state during a 2843 measurement interval */ 2844 bcmPortControlEEETransmitIdleTimeHund = 101, /* The same as 2845 PortControlEEETransmitIdleTime for 2846 the link speed at 100MB data rate */ 2847 bcmPortControlEEETransmitWakeTimeHund = 102, /* The same as 2848 PortControlEEETransmitWakeTime for 2849 the link speed at 100MB data rate */ 2850 bcmPortControlEEETransmitMinLPITime = 103, /* Time (in microseconds) MAC stay in 2851 LPI state before leaving it */ 2852 bcmPortControlEEETransmitMinLPITimeHund = 104, /* The same as 2853 PortControlEEETransmitMinLPITime for 2854 the link speed at 100MB data rate */ 2855 bcmPortControlNivAccessVirtualInterfaceId = 105, /* Source virtual interface identifier 2856 (value range 0-0xfff) */ 2857 bcmPortControlNivNonVntagDrop = 106, /* Set Ingress drop control, if VNTAG is 2858 not present (value = TRUE/FALSE) */ 2859 bcmPortControlNivVntagDrop = 107, /* Set Ingress drop control, if VNTAG is 2860 present (value = TRUE/FALSE) */ 2861 bcmPortControlNivNonVntagAdd = 108, /* Set ADD tag action, when VNTAG is not 2862 present(value = TRUE/FALSE) */ 2863 bcmPortControlNivVntagIngressReplace = 109, /* Set REPLACE Ingress tag action, when 2864 VNTAG is present (value = TRUE/FALSE) */ 2865 bcmPortControlNivVntagEgressReplace = 110, /* Set REPLACE Egress tag action, when 2866 VNTAG is present (value = TRUE/FALSE) */ 2867 bcmPortControlNivVntagIngressDelete = 111, /* Set DELETE Ingress tag action, when 2868 VNTAG is present (value = TRUE/FALSE) */ 2869 bcmPortControlNivVntagEgressDelete = 112, /* Set DELETE Egress tag action, when 2870 VNTAG is present (value = TRUE/FALSE) */ 2871 bcmPortControlNivRpfCheck = 113, /* Set incoming packet VNTAG.SRC_VIF RPF 2872 check control (value = TRUE/FALSE) */ 2873 bcmPortControlNivSourceKnockout = 114, /* Set outgoing packet NIV pruning check 2874 control (value = TRUE/FALSE) */ 2875 bcmPortControlNivForwardPort = 115, /* Set destination port for forwarding - 2876 mainly for upstream traffic only, but 2877 use -1 as special to flag the port as 2878 uplink port (value = local port 2879 number or -1) */ 2880 bcmPortControlNivType = 116, /* Set NIV port type (enumerated value 2881 within bcm_port_niv_type_t) */ 2882 bcmPortControlNivNameSpace = 117, /* Set namespace value (value range 2883 0-0xfff) */ 2884 bcmPortControlRemoteCpuEnable = 118, /* Enables the port to accept packets 2885 from Remote CPU */ 2886 bcmPortControlRemoteCpuTcMapping = 119, /* Enable/Disable the mapping between TC 2887 and COS queue for received ToCPU 2888 packets */ 2889 bcmPortControlArbiterActive = 120, /* Indicates if the SCI link is active 2890 and its arbiter association. -1 2891 indicates disabled, 0 indicates 2892 active and associted with Arbiter 0, 2893 1 indicates active and associated 2894 with Arbiter 1 */ 2895 bcmPortControlArbiterForceDown = 121, /* Status to be indicated to arbiter. 2896 TRUE forces Down, FALSE does not 2897 force down */ 2898 bcmPortControlTrill = 123, /* Enable/Disable TRILL frame processing 2899 (value = TRUE/FALSE) */ 2900 bcmPortControlTrillAllow = 124, /* Allow TRILL frames (value = 2901 TRUE/FALSE) */ 2902 bcmPortControlNonTrillAllow = 125, /* Allow Non-TRILL frames (value = 2903 TRUE/FALSE) */ 2904 bcmPortControlTrillCoreISISToCPU = 126, /* Core IS-IS frames received, Send to 2905 CPU (value = TRUE/FALSE) */ 2906 bcmPortControlTrillHashSelect = 127, /* Select one of 2 sets of configuration 2907 for TRILL ECMP hashing (value = 1/0 ) */ 2908 bcmPortControlFabricHeaderFormat = 128, /* Select appropriate fabric header 2909 type. */ 2910 bcmPortControlFabricSourceKnockout = 130, /* Disables packet forwarding to 2911 non-trunk port on local modid */ 2912 bcmPortControlFaultResponseLocalDataAndIdle = 131, /* If Local Fault indicated, continue 2913 sending data, send Idles */ 2914 bcmPortControlFaultResponseLocalDataAndRf = 132, /* If Local Fault indicated, continue 2915 sending data, send Remote Fault 2916 Indication */ 2917 bcmPortControlFaultResponseLocalDataAndLf = 133, /* If Local Fault indicated, continue 2918 sending data, send Local Fault 2919 Indication */ 2920 bcmPortControlFaultResponseLocalNoDataIdle = 134, /* If Local Fault indicated, stop 2921 sending data, send Idles */ 2922 bcmPortControlFaultResponseLocalNoDataRf = 135, /* If Local Fault indicated, stop 2923 sending data, send Remote Fault 2924 Indication */ 2925 bcmPortControlFaultResponseLocalNoDataLf = 136, /* If Local Fault indicated, stop 2926 sending data, send Local Fault 2927 Indication */ 2928 bcmPortControlFaultResponseRemoteDataAndIdle = 137, /* If Remote Fault indicated, continue 2929 sending data, send Idles */ 2930 bcmPortControlFaultResponseRemoteDataAndRf = 138, /* If Remote Fault indicated, continue 2931 sending data, send Remote Fault 2932 Indication */ 2933 bcmPortControlFaultResponseRemoteDataAndLf = 139, /* If Remote Fault indicated, continue 2934 sending data, send Remote Fault 2935 Indication */ 2936 bcmPortControlFaultResponseRemoteNoDataIdle = 140, /* If Remote Fault indicated, stop 2937 sending data, send Idles */ 2938 bcmPortControlFaultResponseRemoteNoDataRf = 141, /* If Remote Fault indicated, stop 2939 sending data, send Remote Fault 2940 Indication */ 2941 bcmPortControlFaultResponseRemoteNoDataLf = 142, /* If Remote Fault indicated, stop 2942 sending data, send Remote Fault 2943 Indication */ 2944 bcmPortControlPCS = 143, /* The Physical Coding Sub-layer of the 2945 port */ 2946 bcmPortControlLinkDownPowerOn = 144, /* 0: The Link is disabled on the MAC 2947 level, the SerDes power-state is not 2948 changed 1: Activate the link on the 2949 MAC level, the SerDes power-state is 2950 not changed */ 2951 bcmPortControlRegex = 145, /* Enable/Disable tracking of IPv4 flows */ 2952 bcmPortControlRegexTcp = 146, /* Enable/Disable tracking of IPv6 flows */ 2953 bcmPortControlRegexUdp = 147, /* Enable/Disable tracking of IPv4 UDP 2954 flows */ 2955 bcmPortControlPonEncryptKeyExpiryTime = 148, /* Set timeout value for encryption keys 2956 (s) */ 2957 bcmPortControlPonHoldoverState = 149, /* Enable holdover state */ 2958 bcmPortControlPonHoldoverTime = 150, /* Set holdover time (ms) */ 2959 bcmPortControlPonMultiLlid = 151, /* Set LLID number */ 2960 bcmPortControlPonFecMode = 152, /* Set FEC mode on Rx and Tx together, 2961 Rx/Tx off (value = 0), Rx on and Tx 2962 off (value = 1), Rx off and Tx on 2963 (value = 2), Rx/Tx on (value = 3) or 2964 FEC is settable per link (value = 4) */ 2965 bcmPortControlPonUserTraffic = 153, /* Enable user traffic */ 2966 bcmPortControlEthPortAutoNegFailureAlarmState = 154, /* Alarm on/off state of the 2967 EthPortAutoNegFailure */ 2968 bcmPortControlEthPortLosAlarmState = 155, /* Alarm on/off state of the EthPortLos */ 2969 bcmPortControlEthPortFailureAlarmState = 156, /* Alarm on/off state of the 2970 EthPortFailure */ 2971 bcmPortControlEthPortLoopbackAlarmState = 157, /* Alarm on/off state of the 2972 EthPortLoopback */ 2973 bcmPortControlEthPortCongestionAlarmState = 158, /* Alarm on/off state of the 2974 EthPortCongestion */ 2975 bcmPortControlMplsEntropyHashSet = 159, /* Select one of 2 sets of configuration 2976 for MPLS Entropy hashing (value = 2977 1/0) */ 2978 bcmPortControlStripCRC = 160, /* If set no cell CRC is calculated, 2979 else 8-bit CRC will be added to each 2980 data cell. Relevant for VSC256 mode 2981 only. */ 2982 bcmPortControlPrivateVlanIsolate = 161, /* Argument = 1/0. Enable, disable 2983 system port being port isolate type. 2984 By default port will be community. */ 2985 bcmPortControlPrivateVlanModeSet = bcmPortControlPrivateVlanIsolate, /* Argument = 2/1/0. Set system port 2986 private vlan mode (0 : community, 1 : 2987 isolate, 2 : promiscuous). By 2988 default it is community. */ 2989 bcmPortControlFloodUnknownUcastGroup = 162, /* Override the per-vsi settings. */ 2990 bcmPortControlFloodUnknownMcastGroup = 163, /* Override the per-vsi settings. */ 2991 bcmPortControlFloodBroadcastGroup = 164, /* Override the per-vsi settings. */ 2992 bcmPortControlDefaultQueue = 165, /* Specify default queue ID for use with 2993 the port */ 2994 bcmPortControlL2GreEnable = 166, /* Set per port enable for L2-GRE 2995 (Value=TRUE/FALSE) */ 2996 bcmPortControlL2GreTunnelbasedVpnId = 167, /* Set per port VPNID lookup key 2997 (Value=TRUE/FALSE) */ 2998 bcmPortControlL2GreDefaultTunnelEnable = 168, /* Set per port dafult-SVP for Tunnel 2999 lookup failure(Value=TRUE/FALSE) */ 3000 bcmPortControlL2SaAuthenticaion = 169, /* to enable SA authentication check on 3001 a port */ 3002 bcmPortControlUnknownMacDaAction = 170, /* Per port configures set of actions 3003 that are taken by the device when an 3004 unknown destination address is 3005 recognized on an ingressing packet */ 3006 bcmPortControlDiscardMacSaAction = 171, /* Per port configures set of actions 3007 that are taken by the device upon SA 3008 lookup when L2 entry flag with 3009 SA-discard */ 3010 bcmPortControlManagementPacketIp6Reserved = 172, /* Classify Packets with IPV6 multicast 3011 reserved address FF0X:0:0:0:0:0:0:0 3012 on a port as management frames */ 3013 bcmPortControlManagementPacketIp4Reserved = 173, /* Classify Packets with IPV4 multicast 3014 reserved address 224.0.0.x on a port 3015 as management frames */ 3016 bcmPortControlManagementPacketLinkConstrained = 174, /* Classify Packets with 3017 link-constrained multicast range 3018 DMAC=01-80-C2-00-00-0x as management 3019 frames */ 3020 bcmPortControlManagementPacketGarp = 175, /* Classify Packets with DA range 3021 0x0180c2000020 through 0x0180c200002f 3022 as management frames */ 3023 bcmPortControlManagementPacketCos = 176, /* COS assignment for Management Packets */ 3024 bcmPortControlManagementPacketColor = 177, /* Drop Precedence for Management 3025 Packets */ 3026 bcmPortControlTaggedL3PacketPktPri = 178, /* Set packet Priority source for tagged 3027 L3 packets (enumerated value within 3028 bcm_port_cos_remap_t) */ 3029 bcmPortControlTaggedMPLSPacketPktPri = 179, /* Set packet Priority source for tagged 3030 MPLS packets (enumerated value within 3031 bcm_port_cos_remap_t) */ 3032 bcmPortControlTaggedMPLSL3PacketPktPri = 180, /* Set packet Priority source for tagged 3033 MPLS L3 packets (enumerated value 3034 within bcm_port_cos_remap_t) */ 3035 bcmPortControlEEEEventCountSymmetric = 181, /* Operate EEE counter in symmetric 3036 mode, where TX and RX counters 3037 increment together */ 3038 bcmPortControlEEELinkActiveDuration = 182, /* Time(in microsecs) to wait before EEE 3039 transitions to Active state after 3040 link status becomes active */ 3041 bcmPortControlEsmEligibility = 183, /* Indicates if ESM search is enabled 3042 for packets coming in on this port */ 3043 bcmPortControlTrillDesignatedVlan = 184, /* VLAN which carries Trill packets 3044 between RBridges */ 3045 bcmPortControlMplsFRREnable = 185, /* Enable or disable FRR on MPLS 3046 packets. */ 3047 bcmPortControlMplsContextSpecificLabelEnable = 186, /* Enable or disable Upstream assignment 3048 label on MPLS packets. */ 3049 bcmPortControlVxlanEnable = 187, /* Set per port enable for VXLAN 3050 (Value=TRUE/FALSE) */ 3051 bcmPortControlVxlanTunnelbasedVnId = 188, /* Set per port VNID lookup key 3052 (Value=TRUE/FALSE) */ 3053 bcmPortControlVxlanDefaultTunnelEnable = 189, /* Set per port dafult-SVP for Tunnel 3054 lookup failure(Value=TRUE/FALSE) */ 3055 bcmPortControlFieldEgressClassSelect = 190, /* Select Class Id to pass to EFP */ 3056 bcmPortControlPonMpcpDiscoveryRate = 191, /* EPON Port MPCP Discovery rate in 3057 miliseconds. */ 3058 bcmPortControlPonMpcpDiscoveryGrantLength = 192, /* EPON Port MPCP Discovery Grant length 3059 in bytes. */ 3060 bcmPortControlPonMpcpOneRegistrationPerGrant = 193, /* Allow only one registration per grant */ 3061 bcmPortControlPonOamHeartbeatRate = 194, /* EPON port OAM heartbeat rate in 3062 seconds */ 3063 bcmPortControlPonMaxLinks = 195, /* EPON port maximum number of links */ 3064 bcmPortControlPonRamanMitigationMode = 196, /* EPON port Raman Mitigation mode */ 3065 bcmPortControlPonLoopTimeMinPropDelay = 197, /* Epon Loop Timing Minimum Propagation 3066 Delay */ 3067 bcmPortControlPonLoopTimeMaxPropDelay = 198, /* Epon Loop Timing Maximum Propagation 3068 Delay */ 3069 bcmPortControlPonLoopTimeOnuDelay = 199, /* Epon Loop Timing Onu Delay */ 3070 bcmPortControlPonLoopTimeNullGrantSize = 200, /* Epon Loop Timing Null Grant size */ 3071 bcmPortControlPonLoopTimeOltDelay = 201, /* Epon Loop Timing OLT delay */ 3072 bcmPortControlPonSfecAllowedBitErrors = 202, /* Epon SFEC Allowed bit errors */ 3073 bcmPortControlPonTfecAllowedBitErrors = 203, /* Epon TFEC Allowed bit errors */ 3074 bcmPortControlPonFecRxBypass = 204, /* Rx FEC Bypass mode */ 3075 bcmPortControlPonSyncTime = 205, /* Epon Sync Time in 16ns(TQ) unit */ 3076 bcmPortControlPonEncryptionMode = 206, /* Epon encryption mode (0 : None, 1 : 3077 AE, 2 : CTC, 3 : Zero-overhead AE). */ 3078 bcmPortControlPonEncryptionDirection = 207, /* Epon encryption direction (1 : 3079 downstream only, 2 : bi-direction). */ 3080 bcmPortControlPonOamKeyExchangeMsgBypass = 208, /* Bypass processing Key Exchange OAM 3081 from Pon port */ 3082 bcmPortControlTunnelIdIngressSource = 209, /* Move outermost VLAN tag to Tunnel ID 3083 on ingress */ 3084 bcmPortControlTunnelIdEgressAdd = 210, /* Add outermost VLAN tag as Tunnel ID 3085 on egress */ 3086 bcmPortControlPonOamHeartbeatTimeout = 211, /* Epon Oam heartbeat timeout in sec 3087 unit */ 3088 bcmPortControlPonMpcpReportTimeout = 212, /* Epon report timeout in ms unit */ 3089 bcmPortControlPon1GDiscoveryWindow = 213, /* Enable 1G discovery window */ 3090 bcmPortControlPon10GDiscoveryWindow = 214, /* Enable 10G discovery window */ 3091 bcmPortControlExtendedPortVid = 215, /* Extended port VID (value range 3092 0-0xfff) */ 3093 bcmPortControlNonEtagDrop = 216, /* Set Ingress drop control, if ETAG is 3094 not present (value = TRUE/FALSE) */ 3095 bcmPortControlEtagDrop = 217, /* Set Ingress drop control, if ETAG is 3096 present (value = TRUE/FALSE) */ 3097 bcmPortControlNonEtagAdd = 218, /* Set ADD tag action, when ETAG is not 3098 present (value = TRUE/FALSE) */ 3099 bcmPortControlEtagIngressReplace = 219, /* Set REPLACE Ingress tag action, when 3100 ETAG is present (value = TRUE/FALSE) */ 3101 bcmPortControlEtagEgressReplace = 220, /* Set REPLACE Egress tag action, when 3102 ETAG is present (value = TRUE/FALSE) */ 3103 bcmPortControlEtagIngressDelete = 221, /* Set DELETE Ingress tag action, when 3104 ETAG is present (value = TRUE/FALSE) */ 3105 bcmPortControlEtagEgressDelete = 222, /* Set DELETE Egress tag action, when 3106 ETAG is present (value = TRUE/FALSE) */ 3107 bcmPortControlExtenderRpfCheck = 223, /* Set incoming packet ETAG.SVID RPF 3108 check control (value = TRUE/FALSE) */ 3109 bcmPortControlExtenderSourceKnockout = 224, /* Set source extended port VID pruning 3110 control (value = TRUE/FALSE) */ 3111 bcmPortControlExtenderForwardPort = 225, /* Set destination port for upstream 3112 Extender forwarding (value = local 3113 port number) */ 3114 bcmPortControlExtenderType = 226, /* Set Extender port type (enumerated 3115 value within 3116 bcm_port_extender_type_t) */ 3117 bcmPortControlExtenderNameSpace = 227, /* Set namespace value (value range 3118 0-0xfff) */ 3119 bcmPortControlEtagPcpDeSelect = 228, /* Set source of PCP and DE fields when 3120 adding an ETAG to an ingress packet 3121 (value = 3122 bcm_extender_pcp_de_select_t) */ 3123 bcmPortControlEtagPcp = 229, /* Set default PCP field when adding an 3124 ETAG to an ingress packet (value = 3125 0-7) */ 3126 bcmPortControlEtagDe = 230, /* Set default DE field when adding an 3127 ETAG to an ingress packet (value = 3128 0-1) */ 3129 bcmPortControlUseEtagPri = 231, /* Use ETAG PCP and DE fields to derive 3130 internal priority and color */ 3131 bcmPortControlProhibitedDot1p = 232, /* Set prohibited 802.1p values */ 3132 bcmPortControlEgressFilterDisable = 233, /* Enable/ disable Egress Filtering */ 3133 bcmPortControlLLFCReceive = 234, /* Link Level Flow Control packet 3134 receive enable */ 3135 bcmPortControlLLFCTransmit = 235, /* Link Level Flow Control packet 3136 transmit enable */ 3137 bcmPortControlSAFCReceive = 236, /* Service Aware Flow Control packet 3138 receive enable */ 3139 bcmPortControlSAFCTransmit = 237, /* Service Aware Flow Control packet 3140 transmit enable */ 3141 bcmPortControlMacSwap = 238, /* Enable or Disable MAC swapping on the 3142 port for incoming packet */ 3143 bcmPortControlOverlayRecycle = 241, /* Set port as recycle port for overlay 3144 packets second pass */ 3145 bcmPortControlEvbType = 242, /* Set EVB port type (enumerated value 3146 within bcm_port_evb_type_t) */ 3147 bcmPortControlOamLookupWithDvp = 243, /* Use DVP as one of the keys for OAM 3148 lookup */ 3149 bcmPortControlSubportTagEnable = 244, /* Enable/disable 'third VLAN tag' 3150 (subport tag) channelization over 3151 Ethernet */ 3152 bcmPortControlVMac = 247, /* Enable/Disable VMAC function. */ 3153 bcmPortControlEgressModifyDscp = 248, /* Enable DSCP/EXP marking. In simple 3154 mode enable on port. In advanced mode 3155 enable on inlif profile. */ 3156 bcmPortControlFcoeRouteEnable = 249, /* Enables FCOE routing */ 3157 bcmPortControlFcoeVftEnable = 250, /* Controls VFT header expected on port */ 3158 bcmPortControlFcoeZoneCheckEnable = 251, /* Enables zone check */ 3159 bcmPortControlFcoeSourceBindCheckEnable = 252, /* Enables source bind check */ 3160 bcmPortControlFcoeFpmaPrefixCheckEnable = 253, /* Enables FPMA prefix check */ 3161 bcmPortControlFcoeDoNotLearn = 254, /* Disables learning for packets with 3162 FCOE ethertype */ 3163 bcmPortControlFcoeNetworkPort = 255, /* Sets whether the port is network 3164 (uplink) or not (downfacing) */ 3165 bcmPortControlFcoeFabricSel = 256, /* Selects the source of fabric Id and 3166 priority */ 3167 bcmPortControlFcoeFabricId = 257, /* Sets the port default 12-bit fabric 3168 Id */ 3169 bcmPortControlFcoeFabricPri = 258, /* Sets the port default fabric priority */ 3170 bcmPortControlFcoeFcCrcAction = 259, /* Sets the FC CRC action to take */ 3171 bcmPortControlFcoeFcCrcRecompute = 260, /* Sets the re-compute CRC options */ 3172 bcmPortControlFcoeFcEofIgnore = 261, /* Sets the control to Ignore EOF */ 3173 bcmPortControlMcastGroupRemap = 262, /* Enable remapping of multicast group 3174 index. */ 3175 bcmPortControlLocalSwitching = 263, /* to enable Local route switching on a 3176 port */ 3177 bcmPortControlFecErrorDetectEnable = 264, /* Enables marking of failed error 3178 correction on the cells */ 3179 bcmPortControlLowLatencyLLFCEnable = 265, /* Enables an improvment in latency on 3180 the expense of bandwidth */ 3181 bcmPortControlErspanEnable = 266, /* Enable/Disable ERSPAN mirroring */ 3182 bcmPortControlPFCXOffTime = 267, /* Priority Flow Control xoff time */ 3183 bcmPortControlOamDefaultProfile = 268, /* OAM default profile */ 3184 bcmPortControlSubportPktTagDrop = 269, /* Set Ingress drop control, if LLTAG is 3185 present (value = TRUE/FALSE) */ 3186 bcmPortControlNoSubportPktTagDrop = 270, /* Set Ingress drop control, if LLTAG is 3187 not present (value = TRUE/FALSE) */ 3188 bcmPortControlUseSubportPktTagPri = 271, /* Use LLTAG PCP and DE fields to derive 3189 internal priority and color */ 3190 bcmPortControlVlanVpGroupEgress = 272, /* VP group for egress vlan membership */ 3191 bcmPortControlVlanVpGroupIngress = 273, /* VP group for ingress vlan membership */ 3192 bcmPortControlEEEMode = 274, /* Select Energy Efficient Ethernet mode */ 3193 bcmPortControlProbeSerdesReset = 275, /* Request to reset SerDes on next probe 3194 to the SerDes */ 3195 bcmPortControlFcoeVsanSel = bcmPortControlFcoeFabricSel, /* Selects the source of VSAN ID and 3196 priority */ 3197 bcmPortControlFcoeVsanId = bcmPortControlFcoeFabricId, /* Sets the port default 12-bit VSAN ID */ 3198 bcmPortControlFcoeVsanPri = bcmPortControlFcoeFabricPri, /* Sets the port default VSAN priority */ 3199 bcmPortControlIPMC4Ucast = 276, /* Enable IPMCv4 Unicast MACDA feature 3200 on port. */ 3201 bcmPortControlIPMC6Ucast = 277, /* Enable IPMCv6 Unicast MACDA feature 3202 on port. */ 3203 bcmPortControlWredDropCountUpdateEnableQueueMask = 278, /* Set the queue mask to enable the WRED 3204 dropped counter increase. */ 3205 bcmPortControlWredDropCountUpdateEnableColorMask = 279, /* Set the color mask to enable the WRED 3206 dropped counter increase. */ 3207 bcmPortControlReserved280 = 280, /* Reserved. */ 3208 bcmPortControlReserved281 = 281, /* Reserved. */ 3209 bcmPortControlRxFastLOS = 282, /* Enable/disable accelerated linkscan 3210 capability on port */ 3211 bcmPortControlFcoeTranslateKeyFirst = 283, /* The key to use for the first VLAN 3212 translate search if the Ethertype is 3213 FCOE */ 3214 bcmPortControlFcoeTranslateKeySecond = 284, /* The key to use for the second VLAN 3215 translate search if the Ethertype is 3216 FCOE */ 3217 bcmPortControlMmuDrain = 285, /* Draining the cells of the port */ 3218 bcmPortControlMmuTrafficEnable = 286, /* Enable/disable enqueing the packets 3219 to the port */ 3220 bcmPortControlStatCollectionEnable = 287, /* Enable/disable the gathering of MIB 3221 statistics on the port */ 3222 bcmPortControlLlfcCellsCongestionIndEnable = 288, /* EnableDisable extracting cells 3223 congestion indication from LLFC cells */ 3224 bcmPortControlTrunkLoadBalancingRandomizer = 289, /* Assigns the Load Balancing 3225 Randomizer-value for LAGs(value = 3226 integer between 0 and 15) */ 3227 bcmPortControlECMPLevel1LoadBalancingRandomizer = 290, /* Assigns the Load Balancing 3228 Randomizer-value for ECMP (at Level 1 3229 in Two level ECMP)(value = integer 3230 between 0 and 15) */ 3231 bcmPortControlECMPLevel2LoadBalancingRandomizer = 291, /* Assigns the Load Balancing 3232 Randomizer-value for ECMP at Level 2 3233 in Two Level ECMP(value = integer 3234 between 0 and 15) */ 3235 bcmPortControlMplsExplicitNullEnable = 292, /* Enable or disable Explicit NULL 3236 termination database */ 3237 bcmPortControlExtenderEnable = 293, /* Enable/disable port extender 3238 capability on the port */ 3239 bcmPortControlSubportTagSize = 294, /* Set the CoE egress subport tag size. 3240 When set inserts a wide subport tag, 3241 else inserts a regular subport tag */ 3242 bcmPortControlSystemPortOverride = 295, /* When set, port group id used for 3243 egress VLAN translation is replaced 3244 with destination global logical port */ 3245 bcmPortControlOamDefaultProfileEgress = 296, /* OAM default profile for Egress */ 3246 bcmPortControlPadToSize = 297, /* Min packet size in bytes, packets 3247 smaller than this value are padded 3248 with '0' */ 3249 bcmPortControlVxlanVpnAssignmentCriteria = 298, /* VxLAN vpn assignment criteria */ 3250 bcmPortControlVxlanTerminationMatchCriteria = 299, /* VxLAN termination match criteria */ 3251 bcmPortControlVxlanGportAssignmentCriteria = 300, /* VxLAN virtual port assignment 3252 criteria */ 3253 bcmPortControlOOBFCTxReportIngEnable = 301, /* OOB FC Tx Ingress Congestion 3254 Notification Enable */ 3255 bcmPortControlOOBFCTxReportEgrEnable = 302, /* OOB FC Tx Egress Congestion 3256 Notification Enable */ 3257 bcmPortControlMplsEncapsulateExtendedLabel = 303, /* Encapsulate additional MPLS tunnel on 3258 a given outlif */ 3259 bcmPortControlSampleIngressDest = 304, /* Set Ingress sFlow sample destination */ 3260 bcmPortControlSampleFlexDest = 305, /* Set Flex sFlow sample destination */ 3261 bcmPortControlSampleFlexRate = 306, /* Set Flex sFlow sampling rate */ 3262 bcmPortControlExternalBufferEnable = 307, /* Enable/disable the MMU External 3263 Buffer on the port */ 3264 bcmPortControlTrustMimlPri = 308, /* If set, use packet priority from MiML 3265 header for internal priority mapping */ 3266 bcmPortControlTrustCustomHeaderPri = 309, /* If set, determine internal Priority 3267 based on custom header */ 3268 bcmPortControlCustomHeaderEncapEnable = 310, /* If set, enable the capability of 3269 custom header encapsulation */ 3270 bcmPortControlLinkPhyEnable = 311, /* Enable LinkPhy on a Port */ 3271 bcmPortControlOlpEnable = 312, /* Enable/disable OLP 3272 encapsulation/Decapsulation on a 3273 given port */ 3274 bcmPortControlPortMacOui = 313, /* OUI field of PORT specific MAC. Used 3275 for OAM and SAT */ 3276 bcmPortControlPortMacNonOui = 314, /* NON OUI field of PORT specific MAC. 3277 Used for OAM and SAT */ 3278 bcmPortControlSatEnable = 315, /* Enable/Disable SAT feature. */ 3279 bcmPortControl1588P2PDelay = 316, /* Update path delay in 1588 p2p 3280 mechanism. */ 3281 bcmPortControlSampleIngressEnable = 317, /* Enable/Disable ingress port-based 3282 sflow. */ 3283 bcmPortControlSampleEgressEnable = 318, /* Enable/Disable egress port-based 3284 sflow. */ 3285 bcmPortControlSampleIngressRate = 319, /* Set Ingress sFlow sample rate. */ 3286 bcmPortControlSampleEgressRate = 320, /* Set Egress sFlow sample rate. */ 3287 bcmPortControlMplsSpeculativeParse = 321, /* Enable the speculative parsing of 3288 headers over MPLS. */ 3289 bcmPortControlFieldHiGigClassSelect = 322, /* Control classid selection into HG 3290 header. */ 3291 bcmPortControlDvpGroupId = 323, /* Configure DVP group value which will 3292 be used to compare against SVP for 3293 pruning decision */ 3294 bcmPortControlDvpGroupKnockoutEnable = 324, /* Enable/Disable DVP group based 3295 pruning. Supported values are 3296 0-Disable, 1-Enable */ 3297 bcmPortControlUntaggedVlanMember = 325, /* Set the VLAN-Membership state per 3298 port for packets classified as 3299 untagged */ 3300 bcmPortControlMPLSEncapsulateAdditionalLabel = 326, /* Set additional label enable on 3301 outgoing LIF */ 3302 bcmPortControlPreserveDscpIngress = 327, /* Preserve DSCP after routing, ingress 3303 logical port configuration */ 3304 bcmPortControlPreserveDscpEgress = 328, /* Preserve DSCP after routing, egress 3305 logical port configuration */ 3306 bcmPortControlPWETerminationPortModeEnable = 329, /* Enable PWE termination port mode on a 3307 port, if enabled, PWE label 3308 termination lookup key will be 3309 <port+label> */ 3310 bcmPortControlOuterPolicerRemark = 330, /* set/get in-lif profile or map DP 3311 profile mapping in-lif profile to 3312 remark outer PCP-DEI. */ 3313 bcmPortControlInnerPolicerRemark = 331, /* set/get in-lif profile or map DP 3314 profile mapping in-lif profile to 3315 remark inner PCP-DEI. */ 3316 bcmPortControlAllowTtlInheritance = 332, /* Enabling Ingress inheritance of TTL 3317 per Outgoing Logical interface 3318 (consume Out-LIF profile) */ 3319 bcmPortControlAllowQosInheritance = 333, /* Enabling Ingress inheritance DSCP-EXP 3320 per Outgoing Logical interface 3321 (consume Out-LIF profile) */ 3322 bcmPortControlPacketTimeStampInsertRx = 334, /* Insert rx packet timestamp for 3323 packets arriving on the port. */ 3324 bcmPortControlPacketTimeStampInsertTx = 335, /* Insert rx packet timestamp for 3325 packets exiting the port. */ 3326 bcmPortControlPacketTimeStampSrcPortInsertCancel = 336, /* Cancel/override both rx and tx time 3327 stamp insertions for the packets 3328 arriving on the port. */ 3329 bcmPortControlPacketTimeStampDestPortInsertCancel = 337, /* Cancel/override both rx and tx time 3330 stamp insertions for the packets 3331 exiting the port. */ 3332 bcmPortControlPacketTimeStampRxId = 338, /* Set Source identifier of Rx (Ingress) 3333 Packet Time Stamp record header. */ 3334 bcmPortControlPacketTimeStampTxId = 339, /* Set Source identifier of Tx (Egress) 3335 Packet Time Stamp record header. */ 3336 bcmPortControlPacketTimeStampByteMeterAdjust = 340, /* Set if need to adjust meter for 3337 packet timestamp. */ 3338 bcmPortControlDoNotCheckVlanEgress = 341, /* Enable/Disable egress VLAN checks for 3339 VP port. */ 3340 bcmPortControlE2EFCTransmitEnable = 342, /* Enable E2EFC message transmit. */ 3341 bcmPortControlE2EFCReceiveEnable = 343, /* Enable E2EFC message receive. */ 3342 bcmPortControlE2EFCCopyToCpuEnable = 344, /* Enable E2EFC message copy-to-CPU. */ 3343 bcmPortControlE2EFCDestMacOui = 345, /* E2EFC message destination MAC upper 3 3344 bytes, only for E2EFC TX. */ 3345 bcmPortControlE2EFCDestMacNonOui = 346, /* E2EFC message destination MAC lower 3 3346 bytes, only for E2EFC TX. */ 3347 bcmPortControlE2EFCSrcMacOui = 347, /* E2EFC message source MAC upper 3 3348 bytes, only for E2EFC TX. */ 3349 bcmPortControlE2EFCSrcMacNonOui = 348, /* E2EFC message source MAC lower 3 3350 bytes, only for E2EFC TX. */ 3351 bcmPortControlE2EFCEtherType = 349, /* E2EFC message EtherType/length, only 3352 for E2EFC TX. */ 3353 bcmPortControlE2EFCOpcode = 350, /* E2EFC message opcode, only for E2EFC 3354 TX. */ 3355 bcmPortControlForceBridgeForwarding = 351, /* Set port to Force Bridge Forwarding. */ 3356 bcmPortControlIlknRxPathEnable = 352, /* Enable/Disable rx path on Ilkn port. 3357 Only use with no linkscan */ 3358 bcmPortControlEgressAclTwoPassEditing = 353, /* Enable/Disable egress ACL two pass 3359 editing on a recycle port */ 3360 bcmPortControlLLFCAfterFecEnable = 354, /* Enable/Disable FEC on LLFC and 3361 congestion indication */ 3362 bcmPortControlResetSerdes = 355, /* Apply reset and relesase reset to 3363 SerDes core. Hard resets PCS and PMD */ 3364 bcmPortControlPONEnable = 356, /* Enable or disable pon capability on 3365 the port */ 3366 bcmPortControlLogicalInterfaceSameFilter = 357, /* Set or unset Same-interface filtering 3367 according to logical-interface ID 3368 while incoming and outgoing port-ID 3369 will be ignored. */ 3370 bcmPortControlIPv6TerminationCascadedModeEnable = 358, /* Enable per port cascading lookup of 3371 IPv6 tunnel termination */ 3372 bcmPortControlMimUcastTermEnable = 359, /* Enable/Disable MiM UC Termination 3373 Mode */ 3374 bcmPortControlMimMcastTermEnable = 360, /* Enable/Disable MiM MC and BC 3375 Termination Mode */ 3376 bcmPortControlTXPISDMOverride = 361, /* Override TXPI SDM value */ 3377 bcmPortControlTXPISDMStatus = 362, /* The final result value of TXPI SDM */ 3378 bcmPortControlBicastPort = 363, /* Sets the Bicast mapping for port */ 3379 bcmPortControlObmClassifierPriority = 364, /* Indicates the default OBM Traffic 3380 class for port */ 3381 bcmPortControlObmClassifierEnableDscp = 365, /* Enable OBM DSCP Classifier on port */ 3382 bcmPortControlObmClassifierEnableMpls = 366, /* Enable OBM MPLS Classifier on port */ 3383 bcmPortControlObmClassifierEnableEtag = 367, /* Enable OBM ETAG Classifier on port */ 3384 bcmPortControlObmClassifierEtagEthertype = 368, /* Configure Ethertype for OBM ETAG 3385 Classifier */ 3386 bcmPortControlObmClassifierVntagEthertype = 369, /* Configure Ethertype for OBM VNTAG 3387 Classifier */ 3388 bcmPortControlControlCellsFecBypassEnable = 370, /* Determine if FEC is bypassed by two 3389 control cells types: credit cells and 3390 flow status cells. 3391 3392 Enable FEC bypass means to NOT do FEC 3393 on these controls cells.Disable FEC 3394 bypass means to do FEC on these 3395 controls cells. 3396 This 3397 configuration is relevant for RS FEC 3398 types only. */ 3399 bcmPortControlPrbsRxInvertData = 371, /* Configure inversion of Rx data */ 3400 bcmPortControlFcoeTranslateKeyFirstEgress = 372, /* The key to use for the first Egress 3401 VLAN translate search if the 3402 Ethertype is FCOE */ 3403 bcmPortControlFcoeTranslateKeySecondEgress = 373, /* The key to use for the second Egress 3404 VLAN translate search if the 3405 Ethertype is FCOE */ 3406 bcmPortControlIntEnable = 374, /* Enable INT at port level */ 3407 bcmPortControlIntPortMetaData = 375, /* Enable per port Metadata inserstion */ 3408 bcmPortControlIntTurnaround = 376, /* Program a egress port as INT 3409 turnaround port */ 3410 bcmPortControlQosRemarkResolution = 377, /* Program a egress port QoS 3411 resolution(enumerated value within 3412 bcm_port_qos_resolution_type_t) */ 3413 bcmPortControlObmClassifierInternal = 378, /* Used to enable/disable internal OBM 3414 classification. By default external 3415 OBM classification is enabled. Once 3416 internal OBM classification is 3417 disabled, external OBM classification 3418 becomes active. */ 3419 bcmPortControlWirelessCosMapSelect = 379, /* Used to select the wireless cos map 3420 for the traffic for a port. */ 3421 bcmPortControlHiGigCosSelect = 380, /* Used to select the Higig cos for a 3422 port. */ 3423 bcmPortControlTpidSrc = 381, /* Used to configure TPID source on VP */ 3424 bcmPortControlInternalLoopback = 382, /* Enable/Disable the port's internal 3425 loopback mode */ 3426 bcmPortConrolEgressVlanPortArpPointed = 383, /* Used to configure the index to vlan 3427 port per ARP. */ 3428 bcmPortControlVrrpScalingPort = 384, /* Used to enable/disable VRRP scaling 3429 per port. */ 3430 bcmPortControlObmInterruptTypeDropPreempt = 385, /* Used to enable obm interrupt for 3431 preempt drop. */ 3432 bcmPortControlObmInterruptTypeDropExpress = 386, /* Used to enable obm interrupt for 3433 express drop. */ 3434 bcmPortControlObmInterruptTypeOverflowPreempt = 387, /* Used to enable interrupt for preempt 3435 overflow */ 3436 bcmPortControlObmInterruptTypeOverflowExpress = 388, /* Used to enable interrupt for express 3437 overflow. */ 3438 bcmPortControlForwardNetworkGroup = 389, /* Enable/Disable Forward network group 3439 functionality. */ 3440 bcmPortControlIngressQosModelRemark = 390, /* Used to configure Ingress remark QOS 3441 model */ 3442 bcmPortControlIngressQosModelPhb = 391, /* Used to configure Ingress PHB QOS 3443 model */ 3444 bcmPortControlIngressQosModelTtl = 392, /* Used to configure Ingress TTL QOS 3445 model */ 3446 bcmPortControlMetadata = 393, /* Used to configure egress port 3447 metadata */ 3448 bcmPortControlFirstHeaderSize = 394, /* Used to configure the size of the 3449 first header to skip. */ 3450 bcmPortControlDistributeLearnMessageMode = 395, /* Used to configure distribute learn 3451 message mode. */ 3452 bcmPortControlDiscardEgress = 396, /* enable/disable to discard all traffic 3453 on that outgoing port. */ 3454 bcmPortControlngressEnable = 397 /* enable/disable single ingress port. */ 3455 } bcm_port_control_t; 3456 3457 /* EEE modes. */ 3458 typedef enum bcm_port_eee_mode_e { 3459 bcmPortEEENativeMode = 0, /* EEE native mode */ 3460 bcmPortEEEBurstAndBatchMode = 1 /* EEE burst and batch mode */ 3461 } bcm_port_eee_mode_t; 3462 3463 /* Types of Tunnel ID. */ 3464 typedef enum bcm_port_tunnel_id_e { 3465 BCM_PORT_TUNNEL_ID_NONE = 0, /* No Tunnel ID */ 3466 BCM_PORT_TUNNEL_ID_VLAN = 1 /* VLAN tag as Tunnel ID */ 3467 } bcm_port_tunnel_id_t; 3468 3469 #ifndef BCM_HIDE_DISPATCHABLE 3470 3471 /* Get or set various features at the port level. */ 3472 extern int bcm_port_control_set( 3473 int unit, 3474 bcm_port_t port, 3475 bcm_port_control_t type, 3476 int value); 3477 3478 /* Get or set various features at the port level. */ 3479 extern int bcm_port_control_get( 3480 int unit, 3481 bcm_port_t port, 3482 bcm_port_control_t type, 3483 int *value); 3484 3485 /* 3486 * Given a controlling port, this API returns the set of ancillary 3487 * ports belonging to the group (port block) that can be configured to 3488 * operate 3489 * either as a single high-speed port or multiple GE ports. If the input 3490 * port is 3491 * not a controlling port BCM_E_PORT error will be returned. 3492 */ 3493 extern int bcm_port_subsidiary_ports_get( 3494 int unit, 3495 bcm_port_t port, 3496 bcm_pbmp_t *pbmp); 3497 3498 #endif /* BCM_HIDE_DISPATCHABLE */ 3499 3500 /* bcm_port_info_t_init */ 3501 extern void bcm_port_info_t_init( 3502 bcm_port_info_t *info); 3503 3504 /* bcm_port_ability_t_init */ 3505 extern void bcm_port_ability_t_init( 3506 bcm_port_ability_t *ability); 3507 3508 /* bcm_phy_config_t_init */ 3509 extern void bcm_phy_config_t_init( 3510 bcm_phy_config_t *config); 3511 3512 /* bcm_port_interface_config_t_init */ 3513 extern void bcm_port_interface_config_t_init( 3514 bcm_port_interface_config_t *config); 3515 3516 /* Initialize a Port Configuration structure. */ 3517 extern void bcm_port_config_t_init( 3518 bcm_port_config_t *pconfig); 3519 3520 /* Initialize a Port Encapsulation Configuration structure. */ 3521 extern void bcm_port_encap_config_t_init( 3522 bcm_port_encap_config_t *encap_config); 3523 3524 #define BCM_PORT_CONGESTION_CONFIG_E2ECC 0x00000001 3525 #define BCM_PORT_CONGESTION_CONFIG_HCFC 0x00000002 3526 #define BCM_PORT_CONGESTION_CONFIG_DESTMOD_FLOW_CONTROL 0x00000004 3527 #define BCM_PORT_CONGESTION_CONFIG_MAX_SPLIT4 0x00000008 3528 #define BCM_PORT_CONGESTION_CONFIG_TX 0x00000010 3529 #define BCM_PORT_CONGESTION_CONFIG_RX 0x00000020 3530 #define BCM_PORT_CONGESTION_CONFIG_SAFC 0x00000040 3531 #define BCM_PORT_CONGESTION_CONFIG_QCN 0x00000080 3532 #define BCM_PORT_CONGESTION_CONFIG_DEST_PORT_VALID 0x00000100 3533 #define BCM_PORT_CONGESTION_CONFIG_DESTMODPORT_FLOW_CONTROL 0x00000200 3534 #define BCM_PORT_CONGESTION_CONFIG_E2ECC_COE_STRICT_MODE 0x00000400 3535 #define BCM_PORT_CONGESTION_CONFIG_E2ECC_COE_FLEX_MODE 0x00000800 3536 #define BCM_PORT_CONGESTION_CONFIG_VLAN_PAUSE_COE 0x00001000 3537 #define BCM_PORT_CONGESTION_CONFIG_COPY_TO_CPU 0x00002000 3538 3539 /* bcm_port_congestion_config_s */ 3540 typedef struct bcm_port_congestion_config_s { 3541 uint32 flags; /* congestion mode. */ 3542 uint8 port_bits; /* Higig format for port status */ 3543 int packets_per_sec; /* frequency of sending congestion messages */ 3544 bcm_gport_t src_port; /* gport of type mmodid:port, wildcard on 3545 receive */ 3546 uint16 multicast_id; /* Multicast Identifier */ 3547 bcm_cos_t traffic_class; /* Traffic Class */ 3548 bcm_color_t color; /* Color */ 3549 bcm_vlan_t vlan; /* Vlan */ 3550 uint8 pri; /* Packet priority */ 3551 uint8 cfi; /* CFI */ 3552 bcm_mac_t src_mac; /* Source MAC address */ 3553 bcm_mac_t dest_mac; /* Destination MAC address */ 3554 uint16 ethertype; /* Ethernet Type */ 3555 uint16 opcode; /* Opcode */ 3556 uint8 version; /* QCN PDU version */ 3557 uint8 reserved_v; /* QCN PDU reserved_v */ 3558 bcm_gport_t dst_port; /* gport of type mmodid:port */ 3559 } bcm_port_congestion_config_t; 3560 3561 /* Initialize a Port Congestion Configuration structure. */ 3562 extern void bcm_port_congestion_config_t_init( 3563 bcm_port_congestion_config_t *config); 3564 3565 #ifndef BCM_HIDE_DISPATCHABLE 3566 3567 /* Set congestion mode. */ 3568 extern int bcm_port_congestion_config_set( 3569 int unit, 3570 bcm_gport_t port, 3571 bcm_port_congestion_config_t *config); 3572 3573 /* Get congestion mode. */ 3574 extern int bcm_port_congestion_config_get( 3575 int unit, 3576 bcm_gport_t port, 3577 bcm_port_congestion_config_t *config); 3578 3579 #endif /* BCM_HIDE_DISPATCHABLE */ 3580 3581 /* bcm_port_phy_control_t */ 3582 typedef _shr_port_phy_control_t bcm_port_phy_control_t; 3583 3584 /* 3585 * PHY interrupts sources for use with PORT_PHY_CONTROL_INTR_MASK and 3586 * PORT_PHY_CONTROL_INTR_STATUS. 3587 */ 3588 #define BCM_PORT_PHY_INTR_TIMESYNC_FRAMESYNC _SHR_PORT_PHY_INTR_TIMESYNC_FRAMESYNC 3589 #define BCM_PORT_PHY_INTR_TIMESYNC_TIMESTAMP _SHR_PORT_PHY_INTR_TIMESYNC_TIMESTAMP 3590 #define BCM_PORT_PHY_INTR_LINK_EVENT _SHR_PORT_PHY_INTR_LINK_EVENT 3591 #define BCM_PORT_PHY_INTR_AUTONEG_EVENT _SHR_PORT_PHY_INTR_AUTONEG_EVENT 3592 #define BCM_PORT_PHY_INTR_PLL_EVENT _SHR_PORT_PHY_INTR_PLL_EVENT 3593 #define BCM_PORT_PHY_INTR_UC_EVENT _SHR_PORT_PHY_INTR_UC_EVENT 3594 #define BCM_PORT_PHY_INTR_EMON_EVENT _SHR_PORT_PHY_INTR_EMON_EVENT 3595 #define BCM_PORT_PHY_INTR_AUX_EVENT _SHR_PORT_PHY_INTR_AUX_EVENT 3596 3597 /* Controls for changing PHY settings. */ 3598 #define BCM_PORT_PHY_CONTROL_WAN _SHR_PORT_PHY_CONTROL_WAN 3599 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS _SHR_PORT_PHY_CONTROL_PREEMPHASIS 3600 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS_LANE0 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE0 3601 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS_LANE1 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE1 3602 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS_LANE2 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE2 3603 #define BCM_PORT_PHY_CONTROL_PREEMPHASIS_LANE3 _SHR_PORT_PHY_CONTROL_PREEMPHASIS_LANE3 3604 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT 3605 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE0 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE0 3606 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE1 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE1 3607 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE2 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE2 3608 #define BCM_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE3 _SHR_PORT_PHY_CONTROL_DRIVER_CURRENT_LANE3 3609 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT 3610 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE0 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE0 3611 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE1 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE1 3612 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE2 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE2 3613 #define BCM_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE3 _SHR_PORT_PHY_CONTROL_PRE_DRIVER_CURRENT_LANE3 3614 #define BCM_PORT_PHY_CONTROL_EQUALIZER_BOOST _SHR_PORT_PHY_CONTROL_EQUALIZER_BOOST 3615 #define BCM_PORT_PHY_CONTROL_INTERFACE _SHR_PORT_PHY_CONTROL_INTERFACE 3616 #define BCM_PORT_PHY_CONTROL_MACSEC_ENABLE _SHR_PORT_PHY_CONTROL_MACSEC_ENABLE 3617 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED 3618 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_SPEED _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_SPEED 3619 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_DUPLEX _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_DUPLEX 3620 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_PAUSE _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_FIXED_PAUSE 3621 #define BCM_PORT_PHY_CONTROL_MACSEC_PAUSE_RX_FORWARD _SHR_PORT_PHY_CONTROL_MACSEC_PAUSE_RX_FORWARD 3622 #define BCM_PORT_PHY_CONTROL_MACSEC_PAUSE_TX_FORWARD _SHR_PORT_PHY_CONTROL_MACSEC_PAUSE_TX_FORWARD 3623 #define BCM_PORT_PHY_CONTROL_MACSEC_LINE_IPG _SHR_PORT_PHY_CONTROL_MACSEC_LINE_IPG 3624 #define BCM_PORT_PHY_CONTROL_MACSEC_SWITCH_IPG _SHR_PORT_PHY_CONTROL_MACSEC_SWITCH_IPG 3625 #define BCM_PORT_PHY_CONTROL_LONGREACH_SPEED _SHR_PORT_PHY_CONTROL_LONGREACH_SPEED 3626 #define BCM_PORT_PHY_CONTROL_LONGREACH_PAIRS _SHR_PORT_PHY_CONTROL_LONGREACH_PAIRS 3627 #define BCM_PORT_PHY_CONTROL_LONGREACH_GAIN _SHR_PORT_PHY_CONTROL_LONGREACH_GAIN 3628 #define BCM_PORT_PHY_CONTROL_LONGREACH_AUTONEG _SHR_PORT_PHY_CONTROL_LONGREACH_AUTONEG 3629 #define BCM_PORT_PHY_CONTROL_LONGREACH_LOCAL_ABILITY _SHR_PORT_PHY_CONTROL_LONGREACH_LOCAL_ABILITY 3630 #define BCM_PORT_PHY_CONTROL_LONGREACH_REMOTE_ABILITY _SHR_PORT_PHY_CONTROL_LONGREACH_REMOTE_ABILITY 3631 #define BCM_PORT_PHY_CONTROL_LONGREACH_CURRENT_ABILITY _SHR_PORT_PHY_CONTROL_LONGREACH_CURRENT_ABILITY 3632 #define BCM_PORT_PHY_CONTROL_LONGREACH_MASTER _SHR_PORT_PHY_CONTROL_LONGREACH_MASTER 3633 #define BCM_PORT_PHY_CONTROL_LONGREACH_ACTIVE _SHR_PORT_PHY_CONTROL_LONGREACH_ACTIVE 3634 #define BCM_PORT_PHY_CONTROL_LONGREACH_ENABLE _SHR_PORT_PHY_CONTROL_LONGREACH_ENABLE 3635 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_NONE _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_NONE 3636 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_1PAIR 3637 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_10M_2PAIR 3638 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_1PAIR 3639 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_20M_2PAIR 3640 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_1PAIR 3641 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_25M_2PAIR 3642 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_1PAIR 3643 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_33M_2PAIR 3644 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_1PAIR 3645 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_50M_2PAIR 3646 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_1PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_1PAIR 3647 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_2PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_2PAIR 3648 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_4PAIR _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_100M_4PAIR 3649 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_RX _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_RX 3650 #define BCM_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_TX _SHR_PORT_PHY_CONTROL_LONGREACH_ABILITY_PAUSE_TX 3651 #define BCM_PORT_PHY_CONTROL_POWER _SHR_PORT_PHY_CONTROL_POWER 3652 #define BCM_PORT_PHY_CONTROL_POWER_FULL _SHR_PORT_PHY_CONTROL_POWER_FULL 3653 #define BCM_PORT_PHY_CONTROL_POWER_LOW _SHR_PORT_PHY_CONTROL_POWER_LOW 3654 #define BCM_PORT_PHY_CONTROL_POWER_AUTO _SHR_PORT_PHY_CONTROL_POWER_AUTO 3655 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_DISABLE _SHR_PORT_PHY_CONTROL_POWER_AUTO_DISABLE 3656 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_FULL _SHR_PORT_PHY_CONTROL_POWER_AUTO_FULL 3657 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_LOW _SHR_PORT_PHY_CONTROL_POWER_AUTO_LOW 3658 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_SLEEP_TIME _SHR_PORT_PHY_CONTROL_POWER_AUTO_SLEEP_TIME 3659 #define BCM_PORT_PHY_CONTROL_POWER_AUTO_WAKE_TIME _SHR_PORT_PHY_CONTROL_POWER_AUTO_WAKE_TIME 3660 #define BCM_PORT_PHY_CONTROL_LOOPBACK_EXTERNAL _SHR_PORT_PHY_CONTROL_LOOPBACK_EXTERNAL 3661 #define BCM_PORT_PHY_CONTROL_EDC_CONFIG_NONE _SHR_PORT_PHY_CONTROL_EDC_CONFIG_NONE 3662 #define BCM_PORT_PHY_CONTROL_EDC_CONFIG_HARDWARE _SHR_PORT_PHY_CONTROL_EDC_CONFIG_HARDWARE 3663 #define BCM_PORT_PHY_CONTROL_EDC_CONFIG_SOFTWARE _SHR_PORT_PHY_CONTROL_EDC_CONFIG_SOFTWARE 3664 #define BCM_PORT_PHY_CONTROL_EDC_MODE _SHR_PORT_PHY_CONTROL_EDC_MODE 3665 #define BCM_PORT_PHY_CONTROL_CLOCK_ENABLE _SHR_PORT_PHY_CONTROL_CLOCK_ENABLE 3666 #define BCM_PORT_PHY_CONTROL_CLOCK_SECONDARY_ENABLE _SHR_PORT_PHY_CONTROL_CLOCK_SECONDARY_ENABLE 3667 #define BCM_PORT_PHY_CONTROL_CLOCK_FREQUENCY _SHR_PORT_PHY_CONTROL_CLOCK_FREQUENCY 3668 #define BCM_PORT_PHY_CONTROL_CLOCK_MODE_AUTO _SHR_PORT_PHY_CONTROL_CLOCK_MODE_AUTO 3669 #define BCM_PORT_PHY_CONTROL_CLOCK_AUTO_SECONDARY _SHR_PORT_PHY_CONTROL_CLOCK_AUTO_SECONDARY 3670 #define BCM_PORT_PHY_CONTROL_CLOCK_SOURCE _SHR_PORT_PHY_CONTROL_CLOCK_SOURCE 3671 #define BCM_PORT_PHY_CONTROL_PORT_PRIMARY _SHR_PORT_PHY_CONTROL_PORT_PRIMARY 3672 #define BCM_PORT_PHY_CONTROL_PORT_OFFSET _SHR_PORT_PHY_CONTROL_PORT_OFFSET 3673 #define BCM_PORT_PHY_CONTROL_LINKDOWN_TRANSMIT _SHR_PORT_PHY_CONTROL_LINKDOWN_TRANSMIT 3674 #define BCM_PORT_PHY_CONTROL_EDC_CONFIG _SHR_PORT_PHY_CONTROL_EDC_CONFIG 3675 #define BCM_PORT_PHY_CONTROL_SUPER_ISOLATE _SHR_PORT_PHY_CONTROL_SUPER_ISOLATE 3676 #define BCM_PORT_PHY_CONTROL_SOFT_RESET _SHR_PORT_PHY_CONTROL_SOFT_RESET 3677 #define BCM_PORT_PHY_CONTROL_EEE _SHR_PORT_PHY_CONTROL_EEE 3678 #define BCM_PORT_PHY_CONTROL_EEE_AUTO _SHR_PORT_PHY_CONTROL_EEE_AUTO 3679 #define BCM_PORT_PHY_CONTROL_EEE_AUTO_IDLE_THRESHOLD _SHR_PORT_PHY_CONTROL_EEE_AUTO_IDLE_THRESHOLD 3680 #define BCM_PORT_PHY_CONTROL_EEE_AUTO_BUFFER_LIMIT _SHR_PORT_PHY_CONTROL_EEE_AUTO_BUFFER_LIMIT 3681 #define BCM_PORT_PHY_CONTROL_EEE_AUTO_FIXED_LATENCY _SHR_PORT_PHY_CONTROL_EEE_AUTO_FIXED_LATENCY 3682 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_WAKE_TIME _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_WAKE_TIME 3683 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_WAKE_TIME _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_WAKE_TIME 3684 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_SLEEP_TIME _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_SLEEP_TIME 3685 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_SLEEP_TIME _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_SLEEP_TIME 3686 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_QUIET_TIME _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_QUIET_TIME 3687 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_QUIET_TIME _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_QUIET_TIME 3688 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_REFRESH_TIME _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_REFRESH_TIME 3689 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_EVENTS _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_EVENTS 3690 #define BCM_PORT_PHY_CONTROL_EEE_TRANSMIT_DURATION _SHR_PORT_PHY_CONTROL_EEE_TRANSMIT_DURATION 3691 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_EVENTS _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_EVENTS 3692 #define BCM_PORT_PHY_CONTROL_EEE_RECEIVE_DURATION _SHR_PORT_PHY_CONTROL_EEE_RECEIVE_DURATION 3693 #define BCM_PORT_PHY_CONTROL_EEE_STATISTICS_CLEAR _SHR_PORT_PHY_CONTROL_EEE_STATISTICS_CLEAR 3694 #define BCM_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MAX _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MAX 3695 #define BCM_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MODE _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_MODE 3696 #define BCM_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_VALUE _SHR_PORT_PHY_CONTROL_SERDES_TUNE_MARGIN_VALUE 3697 #define BCM_PORT_PHY_CONTROL_PARALLEL_DETECTION _SHR_PORT_PHY_CONTROL_PARALLEL_DETECTION 3698 #define BCM_PORT_PHY_CONTROL_PARALLEL_DETECTION_10G _SHR_PORT_PHY_CONTROL_PARALLEL_DETECTION_10G 3699 #define BCM_PORT_PHY_CONTROL_LOOPBACK_INTERNAL _SHR_PORT_PHY_CONTROL_LOOPBACK_INTERNAL 3700 #define BCM_PORT_PHY_CONTROL_LOOPBACK_REMOTE _SHR_PORT_PHY_CONTROL_LOOPBACK_REMOTE 3701 #define BCM_PORT_PHY_CONTROL_LOOPBACK_REMOTE_PCS_BYPASS _SHR_PORT_PHY_CONTROL_LOOPBACK_REMOTE_PCS_BYPASS 3702 #define BCM_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION 3703 #define BCM_PORT_PHY_CONTROL_FEC_OFF _SHR_PORT_PHY_CONTROL_FEC_OFF 3704 #define BCM_PORT_PHY_CONTROL_FEC_ON _SHR_PORT_PHY_CONTROL_FEC_ON 3705 #define BCM_PORT_PHY_CONTROL_FEC_AUTO _SHR_PORT_PHY_CONTROL_FEC_AUTO 3706 #define BCM_PORT_PHY_CONTROL_SCRAMBLER _SHR_PORT_PHY_CONTROL_SCRAMBLER 3707 #define BCM_PORT_PHY_CONTROL_CUSTOM1 _SHR_PORT_PHY_CONTROL_CUSTOM1 3708 #define BCM_PORT_PHY_CONTROL_BERT_PATTERN _SHR_PORT_PHY_CONTROL_BERT_PATTERN 3709 #define BCM_PORT_PHY_CONTROL_BERT_RUN _SHR_PORT_PHY_CONTROL_BERT_RUN 3710 #define BCM_PORT_PHY_CONTROL_BERT_CRPAT _SHR_PORT_PHY_CONTROL_BERT_CRPAT 3711 #define BCM_PORT_PHY_CONTROL_BERT_CJPAT _SHR_PORT_PHY_CONTROL_BERT_CJPAT 3712 #define BCM_PORT_PHY_CONTROL_BERT_PACKET_SIZE _SHR_PORT_PHY_CONTROL_BERT_PACKET_SIZE 3713 #define BCM_PORT_PHY_CONTROL_BERT_IPG _SHR_PORT_PHY_CONTROL_BERT_IPG 3714 #define BCM_PORT_PHY_CONTROL_BERT_TX_PACKETS _SHR_PORT_PHY_CONTROL_BERT_TX_PACKETS 3715 #define BCM_PORT_PHY_CONTROL_BERT_RX_PACKETS _SHR_PORT_PHY_CONTROL_BERT_RX_PACKETS 3716 #define BCM_PORT_PHY_CONTROL_BERT_RX_ERROR_BITS _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_BITS 3717 #define BCM_PORT_PHY_CONTROL_BERT_RX_ERROR_BYTES _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_BYTES 3718 #define BCM_PORT_PHY_CONTROL_BERT_RX_ERROR_PACKETS _SHR_PORT_PHY_CONTROL_BERT_RX_ERROR_PACKETS 3719 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_POWER_TIME _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER_TIME 3720 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_POWER_MODE _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER_MODE 3721 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_STATUS _SHR_PORT_PHY_CONTROL_PON_LASER_TX_STATUS 3722 #define BCM_PORT_PHY_CONTROL_PON_LASER_RX_STATE _SHR_PORT_PHY_CONTROL_PON_LASER_RX_STATE 3723 #define BCM_PORT_PHY_CONTROL_PON_LASER_TRANCEIVER_TEMP _SHR_PORT_PHY_CONTROL_PON_LASER_TRANCEIVER_TEMP 3724 #define BCM_PORT_PHY_CONTROL_PON_LASER_SUPPLY_VOLTAGE _SHR_PORT_PHY_CONTROL_PON_LASER_SUPPLY_VOLTAGE 3725 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_BIAS _SHR_PORT_PHY_CONTROL_PON_LASER_TX_BIAS 3726 #define BCM_PORT_PHY_CONTROL_PON_LASER_TX_POWER _SHR_PORT_PHY_CONTROL_PON_LASER_TX_POWER 3727 #define BCM_PORT_PHY_CONTROL_PON_LASER_RX_POWER _SHR_PORT_PHY_CONTROL_PON_LASER_RX_POWER 3728 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_STATE 3729 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_REPORT_THRESHOLD 3730 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_ALARM_CLEAR_THRESHOLD 3731 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_STATE 3732 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_REPORT_THRESHOLD 3733 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_ALARM_CLEAR_THRESHOLD 3734 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_STATE 3735 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_REPORT_THRESHOLD 3736 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_ALARM_CLEAR_THRESHOLD 3737 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_STATE 3738 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_REPORT_THRESHOLD 3739 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_ALARM_CLEAR_THRESHOLD 3740 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_STATE 3741 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_REPORT_THRESHOLD 3742 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_ALARM_CLEAR_THRESHOLD 3743 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_STATE 3744 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_REPORT_THRESHOLD 3745 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_ALARM_CLEAR_THRESHOLD 3746 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_STATE 3747 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_REPORT_THRESHOLD 3748 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_ALARM_CLEAR_THRESHOLD 3749 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_STATE 3750 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_REPORT_THRESHOLD 3751 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_ALARM_CLEAR_THRESHOLD 3752 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_STATE 3753 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_REPORT_THRESHOLD 3754 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_ALARM_CLEAR_THRESHOLD 3755 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_STATE _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_STATE 3756 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_REPORT_THRESHOLD 3757 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_ALARM_CLEAR_THRESHOLD 3758 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_STATE 3759 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_REPORT_THRESHOLD 3760 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_HIGH_WARNING_CLEAR_THRESHOLD 3761 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_STATE 3762 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_REPORT_THRESHOLD 3763 #define BCM_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_RX_POWER_LOW_WARNING_CLEAR_THRESHOLD 3764 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_STATE 3765 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_REPORT_THRESHOLD 3766 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_HIGH_WARNING_CLEAR_THRESHOLD 3767 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_STATE 3768 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_REPORT_THRESHOLD 3769 #define BCM_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_POWER_LOW_WARNING_CLEAR_THRESHOLD 3770 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_STATE 3771 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_REPORT_THRESHOLD 3772 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_HIGH_WARNING_CLEAR_THRESHOLD 3773 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_STATE 3774 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_REPORT_THRESHOLD 3775 #define BCM_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TX_BIAS_LOW_WARNING_CLEAR_THRESHOLD 3776 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_STATE 3777 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_REPORT_THRESHOLD 3778 #define BCM_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_HIGH_WARNING_CLEAR_THRESHOLD 3779 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_STATE 3780 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_REPORT_THRESHOLD 3781 #define BCM_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_VCC_LOW_WARNING_CLEAR_THRESHOLD 3782 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_STATE 3783 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_REPORT_THRESHOLD 3784 #define BCM_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_HIGH_WARNING_CLEAR_THRESHOLD 3785 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_STATE _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_STATE 3786 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_REPORT_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_REPORT_THRESHOLD 3787 #define BCM_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_CLEAR_THRESHOLD _SHR_PORT_PHY_CONTROL_PON_TEMP_LOW_WARNING_CLEAR_THRESHOLD 3788 #define BCM_PORT_PHY_CONTROL_DLL_POWER_AUTO _SHR_PORT_PHY_CONTROL_DLL_POWER_AUTO 3789 #define BCM_PORT_PHY_CONTROL_TX_LANE_SQUELCH _SHR_PORT_PHY_CONTROL_TX_LANE_SQUELCH 3790 #define BCM_PORT_PHY_CONTROL_RX_LANE_SQUELCH _SHR_PORT_PHY_CONTROL_RX_LANE_SQUELCH 3791 #define BCM_PORT_PHY_CONTROL_DRIVER_POST2_CURRENT _SHR_PORT_PHY_CONTROL_DRIVER_POST2_CURRENT 3792 #define BCM_PORT_PHY_CONTROL_RX_PPM _SHR_PORT_PHY_CONTROL_RX_PPM 3793 #define BCM_PORT_PHY_CONTROL_RX_POLARITY _SHR_PORT_PHY_CONTROL_RX_POLARITY 3794 #define BCM_PORT_PHY_CONTROL_TX_POLARITY _SHR_PORT_PHY_CONTROL_TX_POLARITY 3795 #define BCM_PORT_PHY_CONTROL_RX_RESET _SHR_PORT_PHY_CONTROL_RX_RESET 3796 #define BCM_PORT_PHY_CONTROL_TX_RESET _SHR_PORT_PHY_CONTROL_TX_RESET 3797 #define BCM_PORT_PHY_CONTROL_CL72 _SHR_PORT_PHY_CONTROL_CL72 3798 #define BCM_PORT_PHY_CONTROL_CL72_STATUS _SHR_PORT_PHY_CONTROL_CL72_STATUS 3799 #define BCM_PORT_PHY_CONTROL_LANE_SWAP _SHR_PORT_PHY_CONTROL_LANE_SWAP 3800 #define BCM_PORT_PHY_CONTROL_RX_PEAK_FILTER _SHR_PORT_PHY_CONTROL_RX_PEAK_FILTER 3801 #define BCM_PORT_PHY_CONTROL_RX_LOW_FREQ_PEAK_FILTER _SHR_PORT_PHY_CONTROL_RX_LOW_FREQ_PEAK_FILTER 3802 #define BCM_PORT_PHY_CONTROL_RX_VGA _SHR_PORT_PHY_CONTROL_RX_VGA 3803 #define BCM_PORT_PHY_CONTROL_RX_TAP1 _SHR_PORT_PHY_CONTROL_RX_TAP1 3804 #define BCM_PORT_PHY_CONTROL_RX_TAP2 _SHR_PORT_PHY_CONTROL_RX_TAP2 3805 #define BCM_PORT_PHY_CONTROL_RX_TAP3 _SHR_PORT_PHY_CONTROL_RX_TAP3 3806 #define BCM_PORT_PHY_CONTROL_RX_TAP4 _SHR_PORT_PHY_CONTROL_RX_TAP4 3807 #define BCM_PORT_PHY_CONTROL_RX_TAP5 _SHR_PORT_PHY_CONTROL_RX_TAP5 3808 #define BCM_PORT_PHY_CONTROL_RX_TAP6 _SHR_PORT_PHY_CONTROL_RX_TAP6 3809 #define BCM_PORT_PHY_CONTROL_RX_VGA_RELEASE _SHR_PORT_PHY_CONTROL_RX_VGA_RELEASE 3810 #define BCM_PORT_PHY_CONTROL_RX_TAP1_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP1_RELEASE 3811 #define BCM_PORT_PHY_CONTROL_RX_TAP2_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP2_RELEASE 3812 #define BCM_PORT_PHY_CONTROL_RX_TAP3_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP3_RELEASE 3813 #define BCM_PORT_PHY_CONTROL_RX_TAP4_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP4_RELEASE 3814 #define BCM_PORT_PHY_CONTROL_RX_TAP5_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP5_RELEASE 3815 #define BCM_PORT_PHY_CONTROL_RX_TAP6_RELEASE _SHR_PORT_PHY_CONTROL_RX_TAP6_RELEASE 3816 #define BCM_PORT_PHY_CONTROL_RX_ADAPTATION_RESUME _SHR_PORT_PHY_CONTROL_RX_ADAPTATION_RESUME 3817 #define BCM_PORT_PHY_CONTROL_RX_PLUS1_SLICER _SHR_PORT_PHY_CONTROL_RX_PLUS1_SLICER 3818 #define BCM_PORT_PHY_CONTROL_RX_MINUS1_SLICER _SHR_PORT_PHY_CONTROL_RX_MINUS1_SLICER 3819 #define BCM_PORT_PHY_CONTROL_RX_D_SLICER _SHR_PORT_PHY_CONTROL_RX_D_SLICER 3820 #define BCM_PORT_PHY_CONTROL_RX_SIGNAL_DETECT _SHR_PORT_PHY_CONTROL_RX_SIGNAL_DETECT 3821 #define BCM_PORT_PHY_CONTROL_RX_SEQ_DONE _SHR_PORT_PHY_CONTROL_RX_SEQ_DONE 3822 #define BCM_PORT_PHY_CONTROL_RX_SEQ_TOGGLE _SHR_PORT_PHY_CONTROL_RX_SEQ_TOGGLE 3823 #define BCM_PORT_PHY_CONTROL_DUMP _SHR_PORT_PHY_CONTROL_DUMP 3824 #define BCM_PORT_PHY_CONTROL_FIRMWARE_MODE _SHR_PORT_PHY_CONTROL_FIRMWARE_MODE 3825 #define BCM_PORT_PHY_CONTROL_DFE _SHR_PORT_PHY_CONTROL_DFE 3826 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_20BIT _SHR_PORT_PHY_CONTROL_TX_PATTERN_20BIT 3827 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_256BIT _SHR_PORT_PHY_CONTROL_TX_PATTERN_256BIT 3828 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA0 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA0 3829 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA1 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA1 3830 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA2 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA2 3831 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA3 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA3 3832 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA4 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA4 3833 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA5 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA5 3834 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA6 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA6 3835 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_DATA7 _SHR_PORT_PHY_CONTROL_TX_PATTERN_DATA7 3836 #define BCM_PORT_PHY_CONTROL_PHASE_INTERP _SHR_PORT_PHY_CONTROL_PHASE_INTERP 3837 #define BCM_PORT_PHY_CONTROL_TX_PPM_ADJUST _SHR_PORT_PHY_CONTROL_TX_PPM_ADJUST 3838 #define BCM_PORT_PHY_CONTROL_SOFTWARE_RX_LOS _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS 3839 #define BCM_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_LINK_WAIT_TIMER_US _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_LINK_WAIT_TIMER_US 3840 #define BCM_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_RESTART_TIMER_US _SHR_PORT_PHY_CONTROL_SOFTWARE_RX_LOS_RESTART_TIMER_US 3841 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_ENABLE _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_ENABLE 3842 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_INVERT_DATA _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_INVERT_DATA 3843 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_POLYNOMIAL _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_TX_POLYNOMIAL 3844 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_ENABLE _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_ENABLE 3845 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_INVERT_DATA _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_INVERT_DATA 3846 #define BCM_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_POLYNOMIAL _SHR_PORT_PHY_CONTROL_PRBS_DECOUPLED_RX_POLYNOMIAL 3847 #define BCM_PORT_PHY_CONTROL_RX_PEAK_FILTER_TEMP_COMP _SHR_PORT_PHY_CONTROL_RX_PEAK_FILTER_TEMP_COMP 3848 #define BCM_PORT_PHY_CONTROL_CL73_FSM_AUTO_RECOVER _SHR_PORT_PHY_CONTROL_CL73_FSM_AUTO_RECOVER 3849 #define BCM_PORT_PHY_CONTROL_DRIVER_SUPPLY _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY 3850 #define BCM_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_1_0V _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_1_0V 3851 #define BCM_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_0V_700MV _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_0V_700MV 3852 #define BCM_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_700MV _SHR_PORT_PHY_CONTROL_DRIVER_SUPPLY_1_5V_700MV 3853 #define BCM_PORT_PHY_CONTROL_DIGITAL_TEMP _SHR_PORT_PHY_CONTROL_DIGITAL_TEMP 3854 #define BCM_PORT_PHY_CONTROL_ANALOG_TEMP _SHR_PORT_PHY_CONTROL_ANALOG_TEMP 3855 #define BCM_PORT_PHY_CONTROL_MGBASET_802P3BZ_PRIORITY _SHR_PORT_PHY_CONTROL_MGBASET_802P3BZ_PRIORITY 3856 #define BCM_PORT_PHY_CONTROL_RX_LOS_NONE _SHR_PORT_PHY_CONTROL_RX_LOS_NONE 3857 #define BCM_PORT_PHY_CONTROL_RX_LOS_SOFTWARE _SHR_PORT_PHY_CONTROL_RX_LOS_SOFTWARE 3858 #define BCM_PORT_PHY_CONTROL_RX_LOS_FIRMWARE _SHR_PORT_PHY_CONTROL_RX_LOS_FIRMWARE 3859 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE _SHR_PORT_PHY_CONTROL_AUTONEG_MODE 3860 #define BCM_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE 3861 #define BCM_PORT_PHY_CONTROL_PRBS_TX_ENABLE _SHR_PORT_PHY_CONTROL_PRBS_TX_ENABLE 3862 #define BCM_PORT_PHY_CONTROL_PRBS_TX_INVERT_DATA _SHR_PORT_PHY_CONTROL_PRBS_TX_INVERT_DATA 3863 #define BCM_PORT_PHY_CONTROL_PRBS_POLYNOMIAL _SHR_PORT_PHY_CONTROL_PRBS_POLYNOMIAL 3864 #define BCM_PORT_PHY_CONTROL_PRBS_RX_STATUS _SHR_PORT_PHY_CONTROL_PRBS_RX_STATUS 3865 #define BCM_PORT_PHY_CONTROL_PRBS_RX_ENABLE _SHR_PORT_PHY_CONTROL_PRBS_RX_ENABLE 3866 #define BCM_PORT_PHY_CONTROL_PRBS_RX_INVERT_DATA _SHR_PORT_PHY_CONTROL_PRBS_RX_INVERT_DATA 3867 #define BCM_PORT_PHY_CONTROL_PRBS_CHECK_MODE _SHR_PORT_PHY_CONTROL_PRBS_CHECK_MODE 3868 #define BCM_PORT_PHY_CONTROL_MOD_AUTO_DETECT_ENABLE _SHR_PORT_PHY_CONTROL_MOD_AUTO_DETECT_ENABLE 3869 #define BCM_PORT_PHY_CONTROL_TX_FIR_PRE _SHR_PORT_PHY_CONTROL_TX_FIR_PRE 3870 #define BCM_PORT_PHY_CONTROL_TX_FIR_MAIN _SHR_PORT_PHY_CONTROL_TX_FIR_MAIN 3871 #define BCM_PORT_PHY_CONTROL_TX_FIR_POST _SHR_PORT_PHY_CONTROL_TX_FIR_POST 3872 #define BCM_PORT_PHY_CONTROL_TX_FIR_POST2 _SHR_PORT_PHY_CONTROL_TX_FIR_POST2 3873 #define BCM_PORT_PHY_CONTROL_TX_FIR_POST3 _SHR_PORT_PHY_CONTROL_TX_FIR_POST3 3874 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE 3875 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PMA_OS _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PMA_OS 3876 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_SCR_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_SCR_MODE 3877 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_ENCODE_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_ENCODE_MODE 3878 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL48_CHECK_END _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL48_CHECK_END 3879 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_BLK_SYNC_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_BLK_SYNC_MODE 3880 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_REORDER_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_REORDER_MODE 3881 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL36_EN _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL36_EN 3882 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESCR1_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESCR1_MODE 3883 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DEC1_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DEC1_MODE 3884 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESKEW_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESKEW_MODE 3885 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_MODE 3886 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_BYTE_DEL _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_DESC2_BYTE_DEL 3887 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_BRCM64B66_DESCR _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_BRCM64B66_DESCR 3888 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_SGMII_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_SGMII_MODE 3889 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT0 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT0 3890 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT1 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLKCNT1 3891 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT0 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT0 3892 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT1 _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_LPCNT1 3893 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_MAC_CGC _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_MAC_CGC 3894 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_REPCNT _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_REPCNT 3895 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CRDTEN _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CREDTEN 3896 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CLKCNT _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CLKCNT 3897 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CGC _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PCS_CGC 3898 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL72_EN _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CL72_EN 3899 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_PLL_DIVIDER _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_PLL_DIVIDER 3900 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLEAR _SHR_PORT_PHY_CONTROL_PCS_SPEED_HTO_CLEAR 3901 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_ENTRY _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_ENTRY 3902 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_HCD _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_HCD 3903 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PMA_OS _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PMA_OS 3904 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_SCR_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_SCR_MODE 3905 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_ENCODE_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_ENCODE_MODE 3906 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CL48_CHECK_END _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL48_CHECK_END 3907 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_BLK_SYNC_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_BLK_SYNC_MODE 3908 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_REORDER_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_REORDER_MODE 3909 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CL36_EN _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL36_EN 3910 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DESCR1_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESCR1_MODE 3911 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DEC1_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DEC1_MODE 3912 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DESKEW_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESKEW_MODE 3913 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_MODE 3914 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_BYTE_DEL _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_DESC2_BYTE_DEL 3915 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_BRCM64B66_DESCR _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_BRCM64B66_DESCR 3916 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_SGMII_MODE _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_SGMII_MODE 3917 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT0 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT0 3918 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT1 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CLKCNT1 3919 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT0 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT0 3920 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT1 _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_LPCNT1 3921 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_MAC_CGC _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_MAC_CGC 3922 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_REPCNT _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_REPCNT 3923 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CRDTEN _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CREDTEN 3924 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CLKCNT _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CLKCNT 3925 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CGC _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PCS_CGC 3926 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_CL72_EN _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_CL72_EN 3927 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_NUM_OF_LANES _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_NUM_OF_LANES 3928 #define BCM_PORT_PHY_CONTROL_PCS_SPEED_ST_PLL_DIVIDER _SHR_PORT_PHY_CONTROL_PCS_SPEED_ST_PLL_DIVIDER 3929 #define BCM_PORT_PHY_CONTROL_LOOPBACK_PMD _SHR_PORT_PHY_CONTROL_LOOPBACK_PMD 3930 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_GEN_ENABLE _SHR_PORT_PHY_CONTROL_TX_PATTERN_GEN_ENABLE 3931 #define BCM_PORT_PHY_CONTROL_TX_PATTERN_LENGTH _SHR_PORT_PHY_CONTROL_TX_PATTERN_LENGTH 3932 #define BCM_PORT_PHY_CONTROL_INTR_MASK _SHR_PORT_PHY_CONTROL_INTR_MASK /* PHY interrupt enable 3933 mask (a bit set to 1 3934 means interrupt 3935 enabled) */ 3936 #define BCM_PORT_PHY_CONTROL_INTR_STATUS _SHR_PORT_PHY_CONTROL_INTR_STATUS /* PHY interrupt control 3937 mask (write 1 to 3938 clear) */ 3939 #define BCM_PORT_PHY_CONTROL_XSW_LANE_MAP _SHR_PORT_PHY_CONTROL_XSW_LANE_MAP /* Cross-switch lane map. 3940 Bits[3:0] map Rx lane 3941 0, bits [7:4] map Rx 3942 lane 1, etc. Default 3943 mapping is 0x76543210. */ 3944 #define BCM_PORT_PHY_CONTROL_FIRMWARE_DFE_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_DFE_ENABLE /* enable digital 3945 feedback equalization */ 3946 #define BCM_PORT_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_LP_DFE_ENABLE /* enable digital 3947 feedback equalization */ 3948 #define BCM_PORT_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_BR_DFE_ENABLE /* enable digital 3949 feedback equalization */ 3950 #define BCM_PORT_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_CL72_RESTART_TIMEOUT_ENABLE /* enable cl72 restart 3951 timeout */ 3952 #define BCM_PORT_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_CL72_AUTO_POLARITY_ENABLE /* enable auto polarity 3953 for cl72 training */ 3954 #define BCM_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_EXTENDED_REACH_ENABLE /* enable firmware lane 3955 config rx forced 3956 extended reach */ 3957 #define BCM_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE _SHR_PORT_PHY_CONTROL_FIRMWARE_RX_FORCE_NORMAL_REACH_ENABLE /* enable firmware lane 3958 config rx forced 3959 normal reach */ 3960 #define BCM_PORT_PHY_CONTROL_GPIO_CONFIG _SHR_PORT_PHY_CONTROL_GPIO_CONFIG /* Config GPIO PINs. Bits 3961 [3:0] controls GPIO 3962 pin 0, bits [7:4] 3963 controls GPIO pin 1, 3964 etc */ 3965 #define BCM_PORT_PHY_CONTROL_GPIO_VALUE _SHR_PORT_PHY_CONTROL_GPIO_VALUE /* Set value for GPIO 3966 PINs. Bits [3:0] 3967 controls GPIO pin 0, 3968 bits [7:4] controls 3969 GPIO pin 1, etc */ 3970 #define BCM_PORT_PHY_CONTROL_GPIO_CONFIG_DISABLED _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_DISABLED 3971 #define BCM_PORT_PHY_CONTROL_GPIO_CONFIG_OUTPUT _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_OUTPUT 3972 #define BCM_PORT_PHY_CONTROL_GPIO_CONFIG_INPUT _SHR_PORT_PHY_CONTROL_GPIO_CONFIG_INPUT 3973 #define BCM_PORT_PHY_CONTROL_PCS_MODE _SHR_PORT_PHY_CONTROL_PCS_MODE 3974 #define BCM_PORT_PHY_CONTROL_AUTONEG_ALLOW_PLL_CHANGE _SHR_PORT_PHY_CONTROL_AUTONEG_ALLOW_PLL_CHANGE 3975 #define BCM_PORT_PHY_CONTROL_MEDIUM_TYPE _SHR_PORT_PHY_CONTROL_MEDIUM_TYPE 3976 #define BCM_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL91 _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL91 3977 #define BCM_PORT_PHY_CONTROL_AUTONEG_FEC_OVERRIDE _SHR_PORT_PHY_CONTROL_AUTONEG_FEC_OVERRIDE /* FEC override for 100G 3978 AN noFEC mode */ 3979 #define BCM_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL108 _SHR_PORT_PHY_CONTROL_FORWARD_ERROR_CORRECTION_CL108 3980 #define BCM_PORT_PHY_CONTROL_FEC_BYPASS_INDICATION_ENABLE _SHR_PORT_PHY_CONTROL_FEC_BYPASS_INDICATION_ENABLE 3981 #define BCM_PORT_PHY_CONTROL_UNRELIABLE_LOS _SHR_PORT_PHY_CONTROL_UNRELIABLE_LOS 3982 #define BCM_PORT_PHY_CONTROL_FORCED_SPEED_LINE_SIDE _SHR_PORT_PHY_CONTROL_FORCED_SPEED_LINE_SIDE /* Set speed on line side 3983 of external PHY in 3984 case of EBE mode only */ 3985 #define BCM_PORT_PHY_CONTROL_EGRESS_FLOW_CONTROL_MODE _SHR_PORT_PHY_EGRESS_FLOW_CONTROL_MODE /* Supported flow modes 3986 as defined in 3987 bcm_port_phy_control_flow_control_mode_t. */ 3988 #define BCM_PORT_PHY_CONTROL_INGRESS_FLOW_CONTROL_MODE _SHR_PORT_PHY_INGRESS_FLOW_CONTROL_MODE /* Supported flow modes 3989 as defined in 3990 bcm_port_phy_control_flow_control_mode_t */ 3991 #define BCM_PORT_PHY_CONTROL_PSM_COS_BMP _SHR_PORT_PHY_CONTROL_PSM_COS_BMP 3992 #define BCM_PORT_PHY_CONTROL_AUTONEG_OUI _SHR_PORT_PHY_CONTROL_AUTONEG_OUI 3993 #define BCM_PORT_PHY_CONTROL_AUTONEG_LINE_SIDE _SHR_PORT_PHY_CONTROL_AUTONEG_LINE_SIDE /* Valid in case of EBE 3994 mode of MT2 PHY device 3995 and can be applied to 3996 enable Autoneg only on 3997 line side of MT2 3998 ports. */ 3999 #define BCM_PORT_PHY_CONTROL_FEC_CORRECTED_BLOCK_COUNT _SHR_PORT_PHY_CONTROL_FEC_CORRECTED_BLOCK_COUNT /* CL74 FEC corrected 4000 block count. */ 4001 #define BCM_PORT_PHY_CONTROL_FEC_UNCORRECTED_BLOCK_COUNT _SHR_PORT_PHY_CONTROL_FEC_UNCORRECTED_BLOCK_COUNT /* CL74 FEC uncorrected 4002 block count. */ 4003 #define BCM_PORT_PHY_CONTROL_FEC_CORRECTED_CODEWORD_COUNT _SHR_PORT_PHY_CONTROL_FEC_CORRECTED_CODEWORD_COUNT /* CL91 FEC corrected 4004 code word count. */ 4005 #define BCM_PORT_PHY_CONTROL_FEC_UNCORRECTED_CODEWORD_COUNT _SHR_PORT_PHY_CONTROL_FEC_UNCORRECTED_CODEWORD_COUNT /* CL91 FEC uncorrected 4006 code word count. */ 4007 #define BCM_PORT_PHY_CONTROL_TX_PAM4_PRECODER_ENABLE _SHR_PORT_PHY_CONTROL_TX_PAM4_PRECODER_ENABLE /* TX pam4 precoder 4008 enable */ 4009 #define BCM_PORT_PHY_CONTROL_LP_TX_PRECODER_ENABLE _SHR_PORT_PHY_CONTROL_LP_TX_PRECODER_ENABLE /* indicate link partner 4010 tx has precoder 4011 enabled */ 4012 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_ENABLE _SHR_PORT_PHY_CONTROL_PAM4_TX_PATTERN_ENABLE /* PAM4 test pattern 4013 enable */ 4014 #define BCM_PORT_PHY_CONTROL_FEC_SYMBOL_ERROR_COUNT _SHR_PORT_PHY_CONTROL_FEC_SYMBOL_ERROR_COUNT /* fec symbol error count */ 4015 #define BCM_PORT_PHY_CONTROL_TX_FIR_MODE _SHR_PORT_PHY_CONTROL_TX_FIR_MODE /* tx fir mode */ 4016 #define BCM_PORT_PHY_CONTROL_TX_FIR_PRE2 _SHR_PORT_PHY_CONTROL_TX_FIR_PRE2 /* tx fir pre2 tap */ 4017 #define BCM_PORT_PHY_CONTROL_RX_HIGH_FREQ_PEAK_FILTER _SHR_PORT_PHY_CONTROL_RX_HIGH_FREQ_PEAK_FILTER /* rx high freq peaking 4018 filter */ 4019 #define BCM_PORT_PHY_CONTROL_FAST_BER_PROJ _SHR_PORT_PHY_CONTROL_FAST_BER_PROJ /* get the BER projection 4020 using PRBS */ 4021 #define BCM_PORT_PHY_CONTROL_CHANNEL_LOSS_HINT _SHR_PORT_PHY_CONTROL_CHANNEL_LOSS_HINT /* specify the channel db 4022 loss */ 4023 #define BCM_PORT_PHY_CONTROL_LINK_TRAINING_INIT_TX_FIR_POST _SHR_PORT_PHY_CONTROL_LINK_TRAINING_INIT_TX_FIR_POST /* set the tx fir post 4024 initial value in uC 4025 RAM for link training */ 4026 #define BCM_PORT_PHY_CONTROL_PFC_USE_IP_COS _SHR_PORT_PHY_CONTROL_PFC_USE_IP_COS /* Use IP COS mapping in 4027 case of PFC mode */ 4028 4029 #define BCM_PORT_PHY_FIRMWARE_DEFAULT _SHR_PORT_PHY_FIRMWARE_DEFAULT /* firmware mode control 4030 default */ 4031 #define BCM_PORT_PHY_FIRMWARE_SFP_OPT_SR4 _SHR_PORT_PHY_FIRMWARE_SFP_OPT_SR4 /* optical short range */ 4032 #define BCM_PORT_PHY_FIRMWARE_SFP_DAC _SHR_PORT_PHY_FIRMWARE_SFP_DAC /* direct attach copper */ 4033 #define BCM_PORT_PHY_FIRMWARE_XLAUI _SHR_PORT_PHY_FIRMWARE_XLAUI /* 40G XLAUI mode */ 4034 #define BCM_PORT_PHY_FIRMWARE_FORCE_OSDFE _SHR_PORT_PHY_FIRMWARE_FORCE_OSDFE /* force over sample 4035 digital feedback 4036 equalization */ 4037 #define BCM_PORT_PHY_FIRMWARE_FORCE_BRDFE _SHR_PORT_PHY_FIRMWARE_FORCE_BRDFE /* force baud rate 4038 digital feedback 4039 equalization */ 4040 #define BCM_PORT_PHY_FIRMWARE_SW_CL72 _SHR_PORT_PHY_FIRMWARE_SW_CL72 /* software cl72 with AN 4041 on */ 4042 #define BCM_PORT_PHY_FIRMWARE_CL72_WITHOUT_AN _SHR_PORT_PHY_FIRMWARE_CL72_WITHOUT_AN /* cl72 without AN */ 4043 4044 #define BCM_PORT_PHY_DFE_AUTO _SHR_PORT_PHY_DFE_AUTO /* Auto control of DFE by firmware */ 4045 #define BCM_PORT_PHY_DFE_FREEZE _SHR_PORT_PHY_DFE_FREEZE /* Freeze DFE to current values */ 4046 4047 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_DEFAULT _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_DEFAULT /* default drivermode */ 4048 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_NOT_SUPPORTED _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_NOT_SUPPORTED /* not supported 4049 drivermode */ 4050 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP /* half amp drivermode */ 4051 #define BCM_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP_HI_IMPED _SHR_PORT_PHY_CONTROL_TX_FIR_DRIVERMODE_HALF_AMP_HI_IMPED /* high impedence half 4052 amp drivermode */ 4053 4054 #define BCM_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_OFF /* hg2 codec off */ 4055 #define BCM_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_8BYTE_IPG _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_8BYTE_IPG /* 8-byte IPG setting */ 4056 #define BCM_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_9BYTE_IPG _SHR_PORT_PHY_CONTROL_HG2_BCM_CODEC_ENABLE_ON_WITH_9BYTE_IPG /* 9-byte IPG setting */ 4057 4058 #define BCM_PORT_PHY_CONTROL_TX_FIR_MODE_INVALID _SHR_PORT_PHY_TX_FIR_MODE_INVALID /* Invalid TX mode */ 4059 #define BCM_PORT_PHY_CONTROL_TX_FIR_3TAP_MODE _SHR_PORT_PHY_TX_FIR_3TAP_MODE /* TX fir 3 tap mode */ 4060 #define BCM_PORT_PHY_CONTROL_TX_FIR_6TAP_MODE _SHR_PORT_PHY_TX_FIR_6TAP_MODE /* tx fir 6 tap mode */ 4061 4062 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_INVALID _SHR_PORT_PHY_PAM4_TX_PATTERN_INVALID /* Invalid PAM4 test 4063 pattern */ 4064 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_OFF _SHR_PORT_PHY_PAM4_TX_PATTERN_OFF /* PAM4 tx test pattern 4065 off */ 4066 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_JP03B _SHR_PORT_PHY_PAM4_TX_PATTERN_JP03B /* PAM4 tx pattern JP03B */ 4067 #define BCM_PORT_PHY_CONTROL_PAM4_TX_PATTERN_LINEAR _SHR_PORT_PHY_PAM4_TX_PATTERN_LINEAR /* PAM4 tx pattern linear */ 4068 4069 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37 /* Autoneg mode CL37 */ 4070 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM /* Autoneg mode CL37 & 4071 BAM */ 4072 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL73 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73 /* Autoneg mode CL73 */ 4073 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM /* Autoneg mode CL73 & 4074 BAM */ 4075 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73 /* Autoneg mode CL37 & 4076 CL73 */ 4077 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73_BAM _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73_BAM /* Autoneg mode CL37 & 4078 CL73 BAM */ 4079 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73 _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73 /* Autoneg mode CL37 BAM 4080 & CL73 */ 4081 #define BCM_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73_BAM _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73_BAM /* Autoneg mode CL37 BAM 4082 & CL73 BAM */ 4083 4084 #define BCM_PORT_PHY_CONTROL_AUTONEG_OUI_DEFAULT _SHR_PORT_PHY_CONTROL_AUTONEG_OUI_DEFAULT /* Autoneg OUI default */ 4085 4086 #ifndef BCM_HIDE_DISPATCHABLE 4087 4088 /* Set/Get PHY specific configurations. */ 4089 extern int bcm_port_phy_control_set( 4090 int unit, 4091 bcm_port_t port, 4092 bcm_port_phy_control_t type, 4093 uint32 value); 4094 4095 /* Set/Get PHY specific configurations. */ 4096 extern int bcm_port_phy_control_get( 4097 int unit, 4098 bcm_port_t port, 4099 bcm_port_phy_control_t type, 4100 uint32 *value); 4101 4102 /* Write the firmware to the PHY device's non-volatile storage. */ 4103 extern int bcm_port_phy_firmware_set( 4104 int unit, 4105 bcm_port_t port, 4106 uint32 flags, 4107 int offset, 4108 uint8 *array, 4109 int length); 4110 4111 /* Get the GPORT ID for the specified physical port. */ 4112 extern int bcm_port_gport_get( 4113 int unit, 4114 bcm_port_t port, 4115 bcm_gport_t *gport); 4116 4117 /* Request if the given gport value is available on the device */ 4118 extern int bcm_port_gport_is_free( 4119 int unit, 4120 bcm_gport_t gport); 4121 4122 /* 4123 * Retrieve the minimum and maximum unallocated gport values for 4124 * a given gport type. 4125 */ 4126 extern int bcm_port_gport_free_range_get( 4127 int unit, 4128 uint32 gport_type, 4129 bcm_gport_t *gport_min, 4130 bcm_gport_t *gport_max); 4131 4132 /* Get the local port from the given GPORT ID. */ 4133 extern int bcm_port_local_get( 4134 int unit, 4135 bcm_gport_t gport, 4136 bcm_port_t *local_port); 4137 4138 #endif /* BCM_HIDE_DISPATCHABLE */ 4139 4140 /* flags for retreiving internal ports */ 4141 #define BCM_PORT_INTERNAL_EGRESS_REPLICATION 0x0001 4142 #define BCM_PORT_INTERNAL_OLP 0x0002 4143 #define BCM_PORT_INTERNAL_RECYCLE 0x0004 4144 #define BCM_PORT_INTERNAL_OAMP 0x0008 4145 #define BCM_PORT_INTERNAL_CONF_SCOPE_CORE0 0x0010 4146 #define BCM_PORT_INTERNAL_CONF_SCOPE_CORE1 0x0020 4147 4148 #ifndef BCM_HIDE_DISPATCHABLE 4149 4150 /* Get the internal ports based of flags */ 4151 extern int bcm_port_internal_get( 4152 int unit, 4153 uint32 flags, 4154 int internal_ports_max, 4155 bcm_gport_t *internal_gport, 4156 int *internal_ports_count); 4157 4158 /* 4159 * Update the specified logical port (GPORT) with the given range(s) 4160 * of VIDs 4161 */ 4162 extern int bcm_port_vlan_vector_set( 4163 int unit, 4164 bcm_gport_t port_id, 4165 bcm_vlan_vector_t vlan_vec); 4166 4167 /* Get the range(s) of VIDs for the specified logical port (GPORT) */ 4168 extern int bcm_port_vlan_vector_get( 4169 int unit, 4170 bcm_gport_t port_id, 4171 bcm_vlan_vector_t vlan_vec); 4172 4173 #endif /* BCM_HIDE_DISPATCHABLE */ 4174 4175 /* Backward compatibility. */ 4176 typedef _shr_port_stp_t bcm_port_stp_t; 4177 4178 /* Backward compatibility. */ 4179 #define BCM_PORT_STP_DISABLE _SHR_PORT_STP_DISABLE 4180 #define BCM_PORT_STP_BLOCK _SHR_PORT_STP_BLOCK 4181 #define BCM_PORT_STP_LISTEN _SHR_PORT_STP_LISTEN 4182 #define BCM_PORT_STP_LEARN _SHR_PORT_STP_LEARN 4183 #define BCM_PORT_STP_FORWARD _SHR_PORT_STP_FORWARD 4184 #define BCM_PORT_STP_COUNT _SHR_PORT_STP_COUNT 4185 4186 /* Backward compatibility. */ 4187 #define bcm_port_vlan_set(u, p, vid) \ 4188 bcm_port_untagged_vlan_set(u, p, vid) 4189 4190 /* Backward compatibility. */ 4191 #define bcm_port_vlan_get(u, p, vdata) \ 4192 bcm_port_untagged_vlan_get((u), (p), &((vdata)->vlan_tag)), \ 4193 bcm_vlan_port_get((u), (vdata)->vlan_tag, \ 4194 &((vdata)->port_bitmap), &((vdata)->ut_port_bitmap)) 4195 4196 #ifndef BCM_HIDE_DISPATCHABLE 4197 4198 /* Retrieve the Policer ID accociated for the specified physical port. */ 4199 extern int bcm_port_policer_get( 4200 int unit, 4201 bcm_port_t port, 4202 bcm_policer_t *policer_id); 4203 4204 /* Set the Policer ID accociated for the specified physical port. */ 4205 extern int bcm_port_policer_set( 4206 int unit, 4207 bcm_port_t port, 4208 bcm_policer_t policer_id); 4209 4210 #endif /* BCM_HIDE_DISPATCHABLE */ 4211 4212 /* Types of statistics that are maintained per gport. */ 4213 typedef enum bcm_port_stat_e { 4214 bcmPortStatIngressPackets = 0, /* Packets that ingress on the gport */ 4215 bcmPortStatIngressBytes = 1, /* Bytes that ingress on the gport */ 4216 bcmPortStatEgressPackets = 2, /* Packets that egress on the gport */ 4217 bcmPortStatEgressBytes = 3, /* Bytes that egress on the gport */ 4218 bcmPortStatIngressPreemptPackets = 4, /* Preemptable packets that ingress on 4219 the gport */ 4220 bcmPortStatIngressPreemptBytes = 5, /* Bytes of preemptable packets that 4221 ingress on the gport */ 4222 bcmPortStatEgressPreemptPackets = 6, /* Preemptable packets that egress on 4223 the gport */ 4224 bcmPortStatEgressPreemptBytes = 7 /* Bytes of preemptable packets that 4225 egress on the gport */ 4226 } bcm_port_stat_t; 4227 4228 #ifndef BCM_HIDE_DISPATCHABLE 4229 4230 /* Enable/disable packet and byte counters for the selected gport. */ 4231 extern int bcm_port_stat_enable_set( 4232 int unit, 4233 bcm_gport_t port, 4234 int enable); 4235 4236 /* Get 64-bit counter value for specified port statistic type. */ 4237 extern int bcm_port_stat_get( 4238 int unit, 4239 bcm_gport_t port, 4240 bcm_port_stat_t stat, 4241 uint64 *val); 4242 4243 /* Get 64-bit counter value for specified port statistic type. */ 4244 extern int bcm_port_stat_sync_get( 4245 int unit, 4246 bcm_gport_t port, 4247 bcm_port_stat_t stat, 4248 uint64 *val); 4249 4250 /* Provide stat counter ids associated with given gport */ 4251 extern int bcm_port_stat_id_get( 4252 int unit, 4253 bcm_gport_t port, 4254 bcm_port_stat_t stat, 4255 uint32 *stat_counter_id); 4256 4257 /* Get lower 32-bit counter value for specified port statistic type. */ 4258 extern int bcm_port_stat_get32( 4259 int unit, 4260 bcm_gport_t port, 4261 bcm_port_stat_t stat, 4262 uint32 *val); 4263 4264 /* Get lower 32-bit counter value for specified port statistic type. */ 4265 extern int bcm_port_stat_sync_get32( 4266 int unit, 4267 bcm_gport_t port, 4268 bcm_port_stat_t stat, 4269 uint32 *val); 4270 4271 /* Set 64-bit counter value for specified port statistic type. */ 4272 extern int bcm_port_stat_set( 4273 int unit, 4274 bcm_gport_t port, 4275 bcm_port_stat_t stat, 4276 uint64 val); 4277 4278 /* Set lower 32-bit counter value for specified port statistic type. */ 4279 extern int bcm_port_stat_set32( 4280 int unit, 4281 bcm_gport_t port, 4282 bcm_port_stat_t stat, 4283 uint32 val); 4284 4285 /* Get 64-bit counter value for multiple port statistic types. */ 4286 extern int bcm_port_stat_multi_get( 4287 int unit, 4288 bcm_gport_t port, 4289 int nstat, 4290 bcm_port_stat_t *stat_arr, 4291 uint64 *value_arr); 4292 4293 /* Get lower 32-bit counter value for multiple port statistic types. */ 4294 extern int bcm_port_stat_multi_get32( 4295 int unit, 4296 bcm_gport_t port, 4297 int nstat, 4298 bcm_port_stat_t *stat_arr, 4299 uint32 *value_arr); 4300 4301 /* Set 64-bit counter value for multiple port statistic types. */ 4302 extern int bcm_port_stat_multi_set( 4303 int unit, 4304 bcm_gport_t port, 4305 int nstat, 4306 bcm_port_stat_t *stat_arr, 4307 uint64 *value_arr); 4308 4309 /* Set lower 32-bit counter value for multiple port statistic types. */ 4310 extern int bcm_port_stat_multi_set32( 4311 int unit, 4312 bcm_gport_t port, 4313 int nstat, 4314 bcm_port_stat_t *stat_arr, 4315 uint32 *value_arr); 4316 4317 #endif /* BCM_HIDE_DISPATCHABLE */ 4318 4319 /* Generic port match criteria */ 4320 typedef enum bcm_port_match_e { 4321 BCM_PORT_MATCH_INVALID = 0, /* Illegal */ 4322 BCM_PORT_MATCH_NONE = 1, /* No matching criteria */ 4323 BCM_PORT_MATCH_PORT = 2, /* Match on module/port or trunk */ 4324 BCM_PORT_MATCH_PORT_VLAN = 3, /* Match on module/port or trunk + outer 4325 VLAN or SVLAN */ 4326 BCM_PORT_MATCH_PORT_VLAN_RANGE = 4, /* Match on module/port or trunk + VLAN 4327 range */ 4328 BCM_PORT_MATCH_PORT_VLAN_STACKED = 5, /* Match on module/port or trunk + 4329 inner/outer VLAN */ 4330 BCM_PORT_MATCH_TUNNEL_VLAN_SRCMAC = 6, /* Match on MiM B-VLAN and source MAC */ 4331 BCM_PORT_MATCH_LABEL = 7, /* Match on MPLS label */ 4332 BCM_PORT_MATCH_LABEL_PORT = 8, /* Match on MPLS label + module/port or 4333 trunk */ 4334 BCM_PORT_MATCH_LABEL_VLAN = 9, /* Match on MPLS label + VLAN */ 4335 BCM_PORT_MATCH_PORT_PCP_VLAN = 10, /* Mod/port/trunk + outer VLAN + outer 4336 PCP. */ 4337 BCM_PORT_MATCH_PORT_PCP_VLAN_STACKED = 11, /* Mod/port/trunk + outer/inner VLAN + 4338 outer/inner PCP. */ 4339 BCM_PORT_MATCH_PORT_INITIAL_VLAN = 12, /* Mod/port/trunk + Initial-VID */ 4340 BCM_PORT_MATCH_PORT_PON_TUNNEL = 13, /* Mod/port/trunk + PON Tunnel Value. */ 4341 BCM_PORT_MATCH_PORT_PON_TUNNEL_VLAN = 14, /* Mod/port/trunk + PON Tunnel Value + 4342 outer VLAN. */ 4343 BCM_PORT_MATCH_PORT_PON_TUNNEL_VLAN_STACKED = 15, /* Mod/port/trunk + PON Tunnel Value + 4344 outer VLAN + inner VLAN. */ 4345 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP_VLAN = 16, /* Mod/port/trunk + PON Tunnel Value + 4346 outer PCP + outer VLAN. */ 4347 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP_VLAN_STACKED = 17, /* Mod/port/trunk + PON Tunnel Value + 4348 outer PCP + outer VLAN + inner VLAN. */ 4349 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP_VLAN_ETHERTYPE = 18, /* Mod/port/trunk + PON Tunnel Value + 4350 Outer PCP + outer VLAN + Ethertype. */ 4351 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP_VLAN_VLAN_ETHERTYPE = 19, /* Mod/port/trunk + PON Tunnel Value + 4352 Outer PCP + outer VLAN + Inner VLAN + 4353 Ethertype. */ 4354 BCM_PORT_MATCH_PORT_PON_TUNNEL_ETHERTYPE = 20, /* Mod/port/trunk + PON Tunnel Value + 4355 Ethertype. */ 4356 BCM_PORT_MATCH_PORT_PON_TUNNEL_VLAN_ETHERTYPE = 21, /* Mod/port/trunk + PON Tunnel Value + 4357 outer VLAN + Ethertype. */ 4358 BCM_PORT_MATCH_PORT_PON_TUNNEL_VLAN_STACKED_ETHERTYPE = 22, /* Mod/port/trunk + PON Tunnel Value + 4359 outer VLAN + inner VLAN + Ethertype. */ 4360 BCM_PORT_MATCH_PORT_VLAN16 = 23, /* Mod/port/trunk + 16-bit outer VLAN 4361 tag. */ 4362 BCM_PORT_MATCH_PORT_PON_TUNNEL_PCP = 24, /* Mod/port/trunk + PON Tunnel Value + 4363 outer PCP. */ 4364 BCM_PORT_MATCH_PORT_UNTAGGED = 25, /* Mod/port/trunk for untagged packets. */ 4365 BCM_PORT_MATCH_PORT_EXTENDED_PORT_VID = 26, /* Mod/port/trunk + Extender port VID */ 4366 BCM_PORT_MATCH_PORT_EXTENDED_PORT_VID_VLAN = 27, /* Mod/port/trunk + Extender port VID + 4367 VLAN */ 4368 BCM_PORT_MATCH_PORT_PON_TUNNEL_INNER_VLAN = 28, /* Mod/port/trunk + LLVID [11:0] of 4369 LLTAG + I-VID[11:0] */ 4370 BCM_PORT_MATCH_PORT_NIV_PORT_VIF = 29, /* Mod/port/trunk + NIV port VIF */ 4371 BCM_PORT_MATCH_PORT_NIV_PORT_VIF_VLAN = 30, /* Mod/port/trunk + NIV port VIF + VLAN */ 4372 BCM_PORT_MATCH_PORT_INNER_VLAN = 31, /* Mod/port/trunk + inner VLAN */ 4373 BCM_PORT_MATCH_PORT_VPN = 32, /* Logical Port + VPN */ 4374 BCM_PORT_MATCH_PORT_EXTENDED_PORT_VID_INITIAL_VLAN = 33, /* Mod/port/trunk + Extender port VID + 4375 initial VLAN */ 4376 BCM_PORT_MATCH_PORT_INNER_VLAN_RANGE = 34, /* Match on module/port or trunk + inner 4377 VLAN range */ 4378 BCM_PORT_MATCH_PORT_VLAN_STACKED_RANGE = 35, /* Match on module/port or trunk + inner 4379 VLAN range + outer VLAN range */ 4380 BCM_PORT_MATCH_PORT_INNER_VLAN16 = 36, /* Mod/port/trunk + 16-bit Inner VLAN 4381 tag */ 4382 BCM_PORT_MATCH_PORT_I2E_CLASS = 37, /* port + Ingress to Egress(I2E) class 4383 id vlan type */ 4384 BCM_PORT_MATCH_PORT_CVLAN = 38, /* Mod/port/trunk + CVLAN */ 4385 BCM_PORT_MATCH_MAC_PORT = 39, /* Match on mac address + Mod/port/trunk 4386 or virtual port */ 4387 BCM_PORT_MATCH_MAC_PORT_CLASS = 40, /* Match on mac address + port class id */ 4388 BCM_PORT_MATCH_PORT_SVLAN_STACKED = 41, /* Match on module/port or trunk + 4389 inner/outer both SVLAN */ 4390 BCM_PORT_MATCH_PORT_CVLAN_STACKED = 42, /* Match on module/port or trunk + 4391 inner/outer both CVLAN */ 4392 BCM_PORT_MATCH_PORT_I2E_CLASS_IFP_TYPE = 43, /* port + Ingress to Egress(I2E) class 4393 id IFP type */ 4394 BCM_PORT_MATCH_COUNT = 44 /* Must be last */ 4395 } bcm_port_match_t; 4396 4397 /* Flags for bcm_port_match_info_t */ 4398 #define BCM_PORT_MATCH_INGRESS_ONLY 0x00000001 /* Indicates Ingress settings */ 4399 #define BCM_PORT_MATCH_EGRESS_ONLY 0x00000002 /* Indicates Egress settings */ 4400 #define BCM_PORT_MATCH_NATIVE 0x00000004 /* Indicates Native Ethernet 4401 settings */ 4402 #define BCM_PORT_MATCH_MIM 0x00000008 /* ISEM entry added contains 4403 an ISID that points to a 4404 MiM LIF. */ 4405 #define BCM_PORT_MATCH_MIM_SERVICE_SMAC 0x00000010 /* Match contains a BSA 4406 nickname (in addition to 4407 ISID). */ 4408 4409 /* Generic port match attribute structure */ 4410 typedef struct bcm_port_match_info_s { 4411 bcm_port_match_t match; /* Match criteria */ 4412 bcm_gport_t port; /* Match port */ 4413 bcm_vlan_t match_vlan; /* Outer VLAN ID to match */ 4414 bcm_vlan_t match_vlan_max; /* Maximum VLAN ID in range to match */ 4415 bcm_vlan_t match_inner_vlan; /* Inner VLAN ID to match */ 4416 bcm_vlan_t match_inner_vlan_max; /* Maximum Inner VLAN ID in range to 4417 match */ 4418 bcm_vlan_t match_tunnel_vlan; /* B-domain VID */ 4419 bcm_mac_t match_tunnel_srcmac; /* B-domain source MAC address */ 4420 bcm_mpls_label_t match_label; /* MPLS label */ 4421 uint32 flags; /* BCM_PORT_MATCH_XXX flags */ 4422 bcm_tunnel_id_t match_pon_tunnel; /* PON Tunnel value to match. */ 4423 bcm_port_ethertype_t match_ethertype; /* Ethernet type value to match */ 4424 int match_pcp; /* Outer PCP ID to match */ 4425 bcm_vlan_action_set_t *action; /* Match action */ 4426 uint16 extended_port_vid; /* Extender port VID */ 4427 bcm_vpn_t vpn; /* VPN ID */ 4428 uint16 niv_port_vif; /* NIV port VIF */ 4429 uint32 isid; 4430 bcm_mac_t src_mac; /* Source Mac Address */ 4431 uint32 port_class; /* Port Class Id */ 4432 } bcm_port_match_info_t; 4433 4434 /* Initialize the port match structure. */ 4435 extern void bcm_port_match_info_t_init( 4436 bcm_port_match_info_t *port_match_info); 4437 4438 #ifndef BCM_HIDE_DISPATCHABLE 4439 4440 /* Add a match to an existing port */ 4441 extern int bcm_port_match_add( 4442 int unit, 4443 bcm_gport_t port, 4444 bcm_port_match_info_t *match); 4445 4446 /* Remove a match from an existing port */ 4447 extern int bcm_port_match_delete( 4448 int unit, 4449 bcm_gport_t port, 4450 bcm_port_match_info_t *match); 4451 4452 /* Replace an old match with a new one for an existing port */ 4453 extern int bcm_port_match_replace( 4454 int unit, 4455 bcm_gport_t port, 4456 bcm_port_match_info_t *old_match, 4457 bcm_port_match_info_t *new_match); 4458 4459 /* Get all the matches for an existing port */ 4460 extern int bcm_port_match_multi_get( 4461 int unit, 4462 bcm_gport_t port, 4463 int size, 4464 bcm_port_match_info_t *match_array, 4465 int *count); 4466 4467 /* Assign a set of matches to an existing port */ 4468 extern int bcm_port_match_set( 4469 int unit, 4470 bcm_gport_t port, 4471 int size, 4472 bcm_port_match_info_t *match_array); 4473 4474 /* Delete all matches for an existing port */ 4475 extern int bcm_port_match_delete_all( 4476 int unit, 4477 bcm_gport_t port); 4478 4479 #endif /* BCM_HIDE_DISPATCHABLE */ 4480 4481 /* Timesync Configuration flags. */ 4482 #define BCM_PORT_TIMESYNC_DEFAULT 0x00000001 /* Port Timesync 4483 configuration */ 4484 #define BCM_PORT_TIMESYNC_MPLS 0x00000002 /* Port Timesync MPLS 4485 configuration */ 4486 #define BCM_PORT_TIMESYNC_ONE_STEP_TIMESTAMP 0x00000004 /* Port one step 4487 timestamp 4488 configuration */ 4489 #define BCM_PORT_TIMESYNC_TWO_STEP_TIMESTAMP 0x00000008 /* Port two step 4490 timestamp 4491 configuration */ 4492 #define BCM_PORT_TIMESYNC_TIMESTAMP_CFUPDATE_ALL 0x00000010 /* All 1588 packets will 4493 be egress timestamped. 4494 By default, only 4495 ingress timestamped 4496 packets are egress 4497 timestamped */ 4498 #define BCM_PORT_TIMESYNC_EXTERNAL_MAC_ENABLE 0x00000020 /* enable external mac 4499 for the port */ 4500 #define BCM_PORT_PHY_CONTROL_FAIL_OVER_MODE _SHR_PORT_PHY_CONTROL_FAIL_OVER_MODE 4501 #define BCM_PORT_PHY_CONTROL_SHORT_CHANNEL_MODE _SHR_PORT_PHY_SHORT_CHANNEL_MODE 4502 #define BCM_PORT_PHY_CONTROL_SHORT_CHANNEL_MODE_STATUS _SHR_PORT_PHY_CONTROL_SHORT_CHANNEL_MODE_STATUS 4503 #define BCM_PORT_PHY_CONTROL_EYE_VAL_HZ_L _SHR_PORT_PHY_CONTROL_EYE_VAL_HZ_L /* Eye scan value, 4504 Horizantal left */ 4505 #define BCM_PORT_PHY_CONTROL_EYE_VAL_HZ_R _SHR_PORT_PHY_CONTROL_EYE_VAL_HZ_R /* Eye scan value, 4506 Horizantal right */ 4507 #define BCM_PORT_PHY_CONTROL_EYE_VAL_VT_U _SHR_PORT_PHY_CONTROL_EYE_VAL_VT_U /* Eye scan value, 4508 vertical up */ 4509 #define BCM_PORT_PHY_CONTROL_EYE_VAL_VT_D _SHR_PORT_PHY_CONTROL_EYE_VAL_VT_D /* Eye scan value, 4510 vertical down */ 4511 4512 /* Timesync Packet type bitmaps. */ 4513 #define BCM_PORT_TIMESYNC_PKT_SYNC 0x00000001 /* Sync Event Packet type */ 4514 #define BCM_PORT_TIMESYNC_PKT_DELAY_REQ 0x00000002 /* Delay Request Event 4515 Packet type */ 4516 #define BCM_PORT_TIMESYNC_PKT_PDELAY_REQ 0x00000004 /* Pdelay Request Event 4517 Packet type */ 4518 #define BCM_PORT_TIMESYNC_PKT_PDELAY_RESP 0x00000008 /* Pdelay Response Event 4519 Packet type */ 4520 #define BCM_PORT_TIMESYNC_PKT_FOLLOWUP 0x00000100 /* Followup General 4521 Packet type */ 4522 #define BCM_PORT_TIMESYNC_PKT_DELAY_RESP 0x00000200 /* Delay_resp General 4523 Packet type */ 4524 #define BCM_PORT_TIMESYNC_PKT_PDELAY_RESP_FOLLOWUP 0x00000400 /* Pdelay_resp_followup 4525 General Packet type */ 4526 #define BCM_PORT_TIMESYNC_PKT_ANNOUNCE 0x00000800 /* Announce General 4527 Packet type */ 4528 #define BCM_PORT_TIMESYNC_PKT_SIGNALLING 0x00001000 /* Signalling General 4529 Packet type */ 4530 #define BCM_PORT_TIMESYNC_PKT_MANAGMENT 0x00002000 /* Management General 4531 Packet type */ 4532 #define BCM_PORT_TIMESYNC_PKT_INVALID 0x00004000 /* Invalid Packet type */ 4533 4534 /* Timesync configuration. */ 4535 typedef struct bcm_port_timesync_config_s { 4536 uint32 flags; /* Timesync Configuration flags */ 4537 uint32 pkt_drop; /* Pakcet Drop bitmap of event and general packet 4538 types */ 4539 uint32 pkt_tocpu; /* CPU forward bitmap of event and general packet 4540 types */ 4541 int mpls_min_label; /* Timesync over MPLS min label */ 4542 int mpls_max_label; /* Timesync over MPLS max label */ 4543 bcm_mac_t src_mac_addr; /* Source mac address for one-step timestamp update */ 4544 int user_trap_id; /* 1588 user trap id */ 4545 } bcm_port_timesync_config_t; 4546 4547 #ifndef BCM_HIDE_DISPATCHABLE 4548 4549 /* bcm_port_timesync_config_set */ 4550 extern int bcm_port_timesync_config_set( 4551 int unit, 4552 bcm_port_t port, 4553 int config_count, 4554 bcm_port_timesync_config_t *config_array); 4555 4556 /* bcm_port_timesync_config_get */ 4557 extern int bcm_port_timesync_config_get( 4558 int unit, 4559 bcm_port_t port, 4560 int array_size, 4561 bcm_port_timesync_config_t *config_array, 4562 int *array_count); 4563 4564 #endif /* BCM_HIDE_DISPATCHABLE */ 4565 4566 #define BCM_PORT_PHY_TIMESYNC_CAP_MPLS _SHR_PORT_PHY_TIMESYNC_CAP_MPLS /* PHY is 1588 over MPLS 4567 capable */ 4568 #define BCM_PORT_PHY_TIMESYNC_CAP_ENHANCED_TSFIFO _SHR_PORT_PHY_TIMESYNC_CAP_ENHANCED_TSFIFO /* PHY has enhanced 4569 TSFIFO */ 4570 #define BCM_PORT_PHY_TIMESYNC_CAP_INBAND_TS _SHR_PORT_PHY_TIMESYNC_CAP_INBAND_TS /* PHY supports inband 4571 timestamping */ 4572 #define BCM_PORT_PHY_TIMESYNC_CAP_FOLLOW_UP_ASSIST _SHR_PORT_PHY_TIMESYNC_CAP_FOLLOW_UP_ASSIST /* PHY supports follow up 4573 assist */ 4574 #define BCM_PORT_PHY_TIMESYNC_CAP_DELAY_RESP_ASSIST _SHR_PORT_PHY_TIMESYNC_CAP_DELAY_RESP_ASSIST /* PHY supports delay 4575 response assist */ 4576 #define BCM_PORT_PHY_TIMESYNC_CAP_CAPTURE_TIMESTAMP_MSG _SHR_PORT_PHY_TIMESYNC_CAP_CAPTURE_TIMESTAMP_MSG /* PHY supports selective 4577 timestamp capture of 4578 1588 messages */ 4579 #define BCM_PORT_PHY_TIMESYNC_VALID_FLAGS _SHR_PORT_PHY_TIMESYNC_VALID_FLAGS /* Flags field is valid */ 4580 #define BCM_PORT_PHY_TIMESYNC_VALID_ITPID _SHR_PORT_PHY_TIMESYNC_VALID_ITPID /* itpid is valid */ 4581 #define BCM_PORT_PHY_TIMESYNC_VALID_OTPID _SHR_PORT_PHY_TIMESYNC_VALID_OTPID /* otpid is valid */ 4582 #define BCM_PORT_PHY_TIMESYNC_VALID_OTPID2 _SHR_PORT_PHY_TIMESYNC_VALID_OTPID2 /* otpid2 is valid */ 4583 #define BCM_PORT_PHY_TIMESYNC_VALID_GMODE _SHR_PORT_PHY_TIMESYNC_VALID_GMODE /* gmode is valid */ 4584 #define BCM_PORT_PHY_TIMESYNC_VALID_FRAMESYNC_MODE _SHR_PORT_PHY_TIMESYNC_VALID_FRAMESYNC_MODE /* framesync mode is 4585 valid */ 4586 #define BCM_PORT_PHY_TIMESYNC_VALID_SYNCOUT_MODE _SHR_PORT_PHY_TIMESYNC_VALID_SYNCOUT_MODE /* syncout mode is valid */ 4587 #define BCM_PORT_PHY_TIMESYNC_VALID_TS_DIVIDER _SHR_PORT_PHY_TIMESYNC_VALID_TS_DIVIDER /* ts divider mode is 4588 valid */ 4589 #define BCM_PORT_PHY_TIMESYNC_VALID_ORIGINAL_TIMECODE _SHR_PORT_PHY_TIMESYNC_VALID_ORIGINAL_TIMECODE /* original timecode is 4590 valid */ 4591 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_TIMESTAMP_OFFSET _SHR_PORT_PHY_TIMESYNC_VALID_TX_TIMESTAMP_OFFSET /* tx timestamp offset is 4592 valid */ 4593 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_TIMESTAMP_OFFSET _SHR_PORT_PHY_TIMESYNC_VALID_RX_TIMESTAMP_OFFSET /* rx timestamp offset is 4594 valid */ 4595 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_SYNC_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_SYNC_MODE /* tx sync mode is valid */ 4596 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_DELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_DELAY_REQUEST_MODE /* tx delay request mode 4597 is valid */ 4598 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_REQUEST_MODE /* tx pdelay request mode 4599 is valid */ 4600 #define BCM_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_RESPONSE_MODE _SHR_PORT_PHY_TIMESYNC_VALID_TX_PDELAY_RESPONSE_MODE /* tx pdelay response 4601 mode is valid */ 4602 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_SYNC_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_SYNC_MODE /* rx sync mode is valid */ 4603 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_DELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_DELAY_REQUEST_MODE /* rx delay request mode 4604 is valid */ 4605 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_REQUEST_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_REQUEST_MODE /* rx pdelay request mode 4606 is valid */ 4607 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_RESPONSE_MODE _SHR_PORT_PHY_TIMESYNC_VALID_RX_PDELAY_RESPONSE_MODE /* rx pdelay response 4608 mode is valid */ 4609 #define BCM_PORT_PHY_TIMESYNC_VALID_MPLS_CONTROL _SHR_PORT_PHY_TIMESYNC_VALID_MPLS_CONTROL /* mpls control is valid */ 4610 #define BCM_PORT_PHY_TIMESYNC_VALID_RX_LINK_DELAY _SHR_PORT_PHY_TIMESYNC_VALID_RX_LINK_DELAY /* rx link delay is valid */ 4611 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_SYNC_FREQ _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_SYNC_FREQ /* sync freq. is valid */ 4612 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K1 _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K1 /* phy 1588 dpll k1 is 4613 valid */ 4614 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K2 _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K2 /* phy 1588 dpll k2 is 4615 valid */ 4616 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K3 _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_K3 /* phy 1588 dpll k3 is 4617 valid */ 4618 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_LOOP_FILTER _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_LOOP_FILTER /* phy 1588 dpll loop 4619 filter is valid */ 4620 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE /* phy 1588 dpll ref 4621 phase is valid */ 4622 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE_DELTA _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_DPLL_REF_PHASE_DELTA /* phy 1588 dpll ref 4623 phase delta is valid */ 4624 #define BCM_PORT_PHY_TIMESYNC_VALID_TIMER_ADJUSTMENT _SHR_PORT_PHY_TIMESYNC_VALID_TIMER_ADJUSTMENT /* phy 1588 direct timer 4625 adjustment is valid */ 4626 #define BCM_PORT_PHY_TIMESYNC_VALID_PHY_1588_INBAND_CONTROL _SHR_PORT_PHY_TIMESYNC_VALID_PHY_1588_INBAND_CONTROL /* phy 1588 inband ts 4627 control is valid */ 4628 #define BCM_PORT_PHY_TIMESYNC_ENABLE _SHR_PORT_PHY_TIMESYNC_ENABLE /* Enable Time 4629 Synchronization 4630 Interface */ 4631 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE _SHR_PORT_PHY_TIMESYNC_CAPTURE_TS_ENABLE /* Enable Packet 4632 Timestamping */ 4633 #define BCM_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE _SHR_PORT_PHY_TIMESYNC_HEARTBEAT_TS_ENABLE /* Enable Heartbeat 4634 Timestamping */ 4635 #define BCM_PORT_PHY_TIMESYNC_RX_CRC_ENABLE _SHR_PORT_PHY_TIMESYNC_RX_CRC_ENABLE /* Enable CRC checking */ 4636 #define BCM_PORT_PHY_TIMESYNC_8021AS_ENABLE _SHR_PORT_PHY_TIMESYNC_8021AS_ENABLE /* Enable IEEE802.1AS 4637 mode */ 4638 #define BCM_PORT_PHY_TIMESYNC_L2_ENABLE _SHR_PORT_PHY_TIMESYNC_L2_ENABLE /* IEEE1588 over Layer 2 */ 4639 #define BCM_PORT_PHY_TIMESYNC_IP4_ENABLE _SHR_PORT_PHY_TIMESYNC_IP4_ENABLE /* IEEE1588 over IPV4 UDP */ 4640 #define BCM_PORT_PHY_TIMESYNC_IP6_ENABLE _SHR_PORT_PHY_TIMESYNC_IP6_ENABLE /* IEEE1588 over IPV6 UDP */ 4641 #define BCM_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT _SHR_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT /* Use external clock 4642 source (DPLL) */ 4643 #define BCM_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT_MODE _SHR_PORT_PHY_TIMESYNC_CLOCK_SRC_EXT_MODE /* DPLL mode, 0 - phase 4644 lock, 1 - frequency 4645 lock */ 4646 #define BCM_PORT_PHY_TIMESYNC_1588_ENCRYPTED_MODE _SHR_PORT_PHY_TIMESYNC_1588_ENCRYPTED_MODE /* Encrypted mode, 0 - 4647 disable, 1 - enable */ 4648 #define BCM_PORT_PHY_TIMESYNC_FOLLOW_UP_ASSIST_ENABLE _SHR_PORT_PHY_TIMESYNC_FOLLOW_UP_ASSIST_ENABLE /* Enable follow up 4649 assistant */ 4650 #define BCM_PORT_PHY_TIMESYNC_DELAY_RESP_ASSIST_ENABLE _SHR_PORT_PHY_TIMESYNC_DELAY_RESP_ASSIST_ENABLE /* Enable delay response 4651 assistant */ 4652 #define BCM_PORT_PHY_TIMESYNC_64BIT_TIMESTAMP_ENABLE _SHR_PORT_PHY_TIMESYNC_64BIT_TIMESTAMP_ENABLE /* Enable 64bit 4653 timestamping */ 4654 #define BCM_PORT_PHY_TIMESYNC_1588_OVER_HSR_ENABLE _SHR_PORT_PHY_TIMESYNC_1588_OVER_HSR_ENABLE /* Enable 1588 over HSR */ 4655 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_SYNC _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_SYNC /* Capture timestamp of 4656 Tx Sync packets */ 4657 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_DELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_DELAY_REQ /* Capture timestamp of 4658 Tx Delay Request 4659 packets */ 4660 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_REQ /* Capture timestamp of 4661 Tx PDelay Request 4662 packets */ 4663 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_RESP _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_TX_PDELAY_RESP /* Capture timestamp of 4664 Tx PDelay Response 4665 packets */ 4666 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_SYNC _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_SYNC /* Capture timestamp of 4667 Rx Sync packets */ 4668 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_DELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_DELAY_REQ /* Capture timestamp of 4669 Rx Delay Request 4670 packets */ 4671 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_REQ _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_REQ /* Capture timestamp of 4672 Rx PDelay Request 4673 packets */ 4674 #define BCM_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_RESP _SHR_PORT_PHY_TIMESYNC_CAPTURE_TIMESTAMP_RX_PDELAY_RESP /* Capture timestamp of 4675 Rx PDelay Response 4676 packets */ 4677 #define BCM_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_CHECK _SHR_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_CHECK /* Enable inband resv0 id 4678 check */ 4679 #define BCM_PORT_PHY_TIMESYNC_INBAND_SYNC_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_SYNC_ENABLE /* Enable inband 4680 timestamping for Sync */ 4681 #define BCM_PORT_PHY_TIMESYNC_INBAND_DELAY_RQ_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_DELAY_RQ_ENABLE /* Enable inband 4682 timestamping for Delay 4683 Request */ 4684 #define BCM_PORT_PHY_TIMESYNC_INBAND_PDELAY_RQ_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_PDELAY_RQ_ENABLE /* Enable inband 4685 timestamping for 4686 PDelay Request */ 4687 #define BCM_PORT_PHY_TIMESYNC_INBAND_PDELAY_RESP_ENABLE _SHR_PORT_PHY_TIMESYNC_INBAND_PDELAY_RESP_ENABLE /* Enable inband 4688 timestamping for 4689 PDelay Response */ 4690 #define BCM_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_UPDATE _SHR_PORT_PHY_TIMESYNC_INBAND_RESV0_ID_UPDATE /* Enables update of 4691 resv0 field in the 4692 ingress packet with 4693 the resv0_id */ 4694 #define BCM_PORT_PHY_TIMESYNC_INBAND_FOLLOW_UP_ASSIST _SHR_PORT_PHY_TIMESYNC_INBAND_FOLLOW_UP_ASSIST /* Enable inband 4695 Follow_Up (T1) assist */ 4696 #define BCM_PORT_PHY_TIMESYNC_INBAND_DELAY_RESP_ASSIST _SHR_PORT_PHY_TIMESYNC_INBAND_DELAY_RESP_ASSIST /* Enable inband 4697 Delay_Response (T3) 4698 assist */ 4699 #define BCM_PORT_PHY_TIMESYNC_INBAND_TIMER_MODE_SELECT _SHR_PORT_PHY_TIMESYNC_INBAND_TIMER_MODE_SELECT /* Select 80- or 48-bit 4700 counter for inband PTP 4701 messages */ 4702 #define BCM_PORT_PHY_TIMESYNC_INBAND_CAP_SRC_PORT_CLK_ID _SHR_PORT_PHY_TIMESYNC_INBAND_CAP_SRC_PORT_CLK_ID /* By default, MAC DA is 4703 captured and saved in 4704 the memory/FIFO. To 4705 capture source port 4706 clock ID instead, this 4707 flag can be used. Only 4708 one of them can be 4709 selected at a time. */ 4710 #define BCM_PORT_PHY_TIMESYNC_INBAND_MATCH_VLAN_ID _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_VLAN_ID /* Enable the comparison 4711 of the VLAN ID field 4712 during delay 4713 response(T3) and 4714 follow up packet. */ 4715 #define BCM_PORT_PHY_TIMESYNC_INBAND_MATCH_SRC_PORT_NUM _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_SRC_PORT_NUM /* Enable the comparison 4716 of the source port 4717 number during delay 4718 response(T3) and 4719 follow up packet. */ 4720 #define BCM_PORT_PHY_TIMESYNC_INBAND_MATCH_MAC_ADDR _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_MAC_ADDR /* Enable the comparison 4721 of the MAC address 4722 during delay 4723 response(T3) and 4724 follow up packet. */ 4725 #define BCM_PORT_PHY_TIMESYNC_INBAND_MATCH_IP_ADDR _SHR_PORT_PHY_TIMESYNC_INBAND_MATCH_IP_ADDR /* Enable the comparison 4726 of the IP address 4727 during delay 4728 response(T3) and 4729 follow up packet. */ 4730 #define BCM_PORT_PHY_TIMESYNC_MPLS_LABEL_IN _SHR_PORT_PHY_TIMESYNC_MPLS_LABEL_IN /* MPLS label applies to 4731 ingress packets */ 4732 #define BCM_PORT_PHY_TIMESYNC_MPLS_LABEL_OUT _SHR_PORT_PHY_TIMESYNC_MPLS_LABEL_OUT /* MPLS label applies to 4733 egress packets */ 4734 #define BCM_PORT_PHY_TIMESYNC_MPLS_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_ENABLE /* Enable processing of 4735 MPLS 1588 packets */ 4736 #define BCM_PORT_PHY_TIMESYNC_MPLS_ENTROPY_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_ENTROPY_ENABLE /* Enable MPLS entropy on 4737 1588 packets */ 4738 #define BCM_PORT_PHY_TIMESYNC_MPLS_SPECIAL_LABEL_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_SPECIAL_LABEL_ENABLE /* Enable MPLS special 4739 label on 1588 packets */ 4740 #define BCM_PORT_PHY_TIMESYNC_MPLS_CONTROL_WORD_ENABLE _SHR_PORT_PHY_TIMESYNC_MPLS_CONTROL_WORD_ENABLE /* Enable MPLS control 4741 word on 1588 packets */ 4742 #define BCM_PORT_PHY_TIMESYNC_TN_LOAD _SHR_PORT_PHY_TIMESYNC_TN_LOAD /* Load Tn upon framesync */ 4743 #define BCM_PORT_PHY_TIMESYNC_TN_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_TN_ALWAYS_LOAD /* Always load Tn upon 4744 framesync */ 4745 #define BCM_PORT_PHY_TIMESYNC_TIMECODE_LOAD _SHR_PORT_PHY_TIMESYNC_TIMECODE_LOAD /* Load timecode upon 4746 framesync */ 4747 #define BCM_PORT_PHY_TIMESYNC_TIMECODE_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_TIMECODE_ALWAYS_LOAD /* Always load timecode 4748 upon framesync */ 4749 #define BCM_PORT_PHY_TIMESYNC_SYNCOUT_LOAD _SHR_PORT_PHY_TIMESYNC_SYNCOUT_LOAD /* Load syncout upon 4750 framesync */ 4751 #define BCM_PORT_PHY_TIMESYNC_SYNCOUT_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_SYNCOUT_ALWAYS_LOAD /* Always load syncout 4752 upon framesync */ 4753 #define BCM_PORT_PHY_TIMESYNC_NCO_DIVIDER_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_DIVIDER_LOAD /* Load NCO divider upon 4754 framesync */ 4755 #define BCM_PORT_PHY_TIMESYNC_NCO_DIVIDER_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_DIVIDER_ALWAYS_LOAD /* Always load NCO 4756 divider upon framesync */ 4757 #define BCM_PORT_PHY_TIMESYNC_LOCAL_TIME_LOAD _SHR_PORT_PHY_TIMESYNC_LOCAL_TIME_LOAD /* Load local time upon 4758 framesync */ 4759 #define BCM_PORT_PHY_TIMESYNC_LOCAL_TIME_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_LOCAL_TIME_ALWAYS_LOAD /* Always load local time 4760 upon framesync */ 4761 #define BCM_PORT_PHY_TIMESYNC_NCO_ADDEND_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_ADDEND_LOAD /* Load NCO addend upon 4762 framesync */ 4763 #define BCM_PORT_PHY_TIMESYNC_NCO_ADDEND_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_NCO_ADDEND_ALWAYS_LOAD /* Always load NCO addend 4764 upon framesync */ 4765 #define BCM_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_LOAD /* Load DPLL loop filter 4766 upon framesync */ 4767 #define BCM_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_LOOP_FILTER_ALWAYS_LOAD /* Always load DPLL loop 4768 filter upon framesync */ 4769 #define BCM_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_LOAD /* Load DPLL ref phase 4770 upon framesync */ 4771 #define BCM_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_ALWAYS_LOAD /* Always load DPLL ref 4772 phase upon framesync */ 4773 #define BCM_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_LOAD /* Load DPLL ref phase 4774 delta upon framesync */ 4775 #define BCM_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_REF_PHASE_DELTA_ALWAYS_LOAD /* Always load DPLL ref 4776 phase delta upon 4777 framesync */ 4778 #define BCM_PORT_PHY_TIMESYNC_DPLL_K3_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K3_LOAD /* Load DPLL coefficient 4779 K3 upon framesync */ 4780 #define BCM_PORT_PHY_TIMESYNC_DPLL_K3_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K3_ALWAYS_LOAD /* Always load DPLL 4781 coefficient K3 upon 4782 framesync */ 4783 #define BCM_PORT_PHY_TIMESYNC_DPLL_K2_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K2_LOAD /* Load DPLL coefficient 4784 K2 upon framesync */ 4785 #define BCM_PORT_PHY_TIMESYNC_DPLL_K2_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K2_ALWAYS_LOAD /* Always load DPLL 4786 coefficient K2 upon 4787 framesync */ 4788 #define BCM_PORT_PHY_TIMESYNC_DPLL_K1_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K1_LOAD /* Load DPLL coefficient 4789 K1 upon framesync */ 4790 #define BCM_PORT_PHY_TIMESYNC_DPLL_K1_ALWAYS_LOAD _SHR_PORT_PHY_TIMESYNC_DPLL_K1_ALWAYS_LOAD /* Always load DPLL 4791 coefficient K1 upon 4792 framesync */ 4793 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT /* Packet timestamp 4794 interrupt */ 4795 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_0 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_0 /* Packet timestamp 4796 interrupt from port 0 */ 4797 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_1 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_1 /* Packet timestamp 4798 interrupt from port 1 */ 4799 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_2 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_2 /* Packet timestamp 4800 interrupt from port 2 */ 4801 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_3 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_3 /* Packet timestamp 4802 interrupt from port 3 */ 4803 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_4 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_4 /* Packet timestamp 4804 interrupt from port 4 */ 4805 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_5 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_5 /* Packet timestamp 4806 interrupt from port 5 */ 4807 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_6 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_6 /* Packet timestamp 4808 interrupt from port 6 */ 4809 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_7 _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_7 /* Packet timestamp 4810 interrupt from port 7 */ 4811 #define BCM_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT /* Framesync interrupt */ 4812 #define BCM_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_MASK _SHR_PORT_PHY_TIMESYNC_TIMESTAMP_INTERRUPT_MASK /* Packet timestamp 4813 interrupt mask */ 4814 #define BCM_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT_MASK _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_INTERRUPT_MASK /* Framesync interrupt 4815 mask */ 4816 #define BCM_PORT_PHY_TIMESYNC_ONE_STEP_ENABLE _SHR_PORT_PHY_TIMESYNC_ONE_STEP_ENABLE /* Enable One-Step 4817 timestamping */ 4818 4819 /* Actions on Egress event messages */ 4820 typedef enum bcm_port_phy_timesync_event_message_egress_mode_e { 4821 bcmPortPhyTimesyncEventMessageEgressModeNone = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_NONE, /* Do nothing */ 4822 bcmPortPhyTimesyncEventMessageEgressModeUpdateCorrectionField = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_UPDATE_CORRECTIONFIELD, /* Update correction field */ 4823 bcmPortPhyTimesyncEventMessageEgressModeReplaceCorrectionFieldOrigin = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_REPLACE_CORRECTIONFIELD_ORIGIN, /* Replace correction field + original 4824 timecode */ 4825 bcmPortPhyTimesyncEventMessageEgressModeCaptureTimestamp = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_EGRESS_MODE_CAPTURE_TIMESTAMP /* Capture TX timestamp */ 4826 } bcm_port_phy_timesync_event_message_egress_mode_t; 4827 4828 /* Actions on ingress event messages */ 4829 typedef enum bcm_port_phy_timesync_event_message_ingress_mode_e { 4830 bcmPortPhyTimesyncEventMessageIngressModeNone = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_NONE, /* Do nothing */ 4831 bcmPortPhyTimesyncEventMessageIngressModeUpdateCorrectionField = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_UPDATE_CORRECTIONFIELD, /* Update correction field */ 4832 bcmPortPhyTimesyncEventMessageIngressModeInsertTimestamp = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_TIMESTAMP, /* Insert timestamp */ 4833 bcmPortPhyTimesyncEventMessageIngressModeInsertDelaytime = _SHR_PORT_PHY_TIMESYNC_EVENT_MESSAGE_INGRESS_MODE_INSERT_DELAYTIME /* Insert delay */ 4834 } bcm_port_phy_timesync_event_message_ingress_mode_t; 4835 4836 /* Global mode actions */ 4837 typedef enum bcm_port_phy_timesync_global_mode_e { 4838 bcmPortPhyTimesyncModeFree = _SHR_PORT_PHY_TIMESYNC_MODE_FREE, /* Do nothing */ 4839 bcmPortPhyTimesyncModeSyncin = _SHR_PORT_PHY_TIMESYNC_MODE_SYNCIN, /* Use syncin as the source */ 4840 bcmPortPhyTimesyncModeCpu = _SHR_PORT_PHY_TIMESYNC_MODE_CPU /* CPU based framesync */ 4841 } bcm_port_phy_timesync_global_mode_t; 4842 4843 /* Fast call actions */ 4844 typedef enum bcm_port_control_phy_timesync_e { 4845 bcmPortControlPhyTimesyncCaptureTimestamp = _SHR_PORT_CONTROL_PHY_TIMESYNC_CAPTURE_TIMESTAMP, /* Captured TS from packets */ 4846 bcmPortControlPhyTimesyncHeartbeatTimestamp = _SHR_PORT_CONTROL_PHY_TIMESYNC_HEARTBEAT_TIMESTAMP, /* Heartbeat TS at framesync */ 4847 bcmPortControlPhyTimesyncNCOAddend = _SHR_PORT_CONTROL_PHY_TIMESYNC_NCOADDEND, /* NCO addend (for non DPLL mode) */ 4848 bcmPortControlPhyTimesyncFrameSync = _SHR_PORT_CONTROL_PHY_TIMESYNC_FRAMESYNC, /* Cause immediate framesync */ 4849 bcmPortControlPhyTimesyncLocalTime = _SHR_PORT_CONTROL_PHY_TIMESYNC_LOCAL_TIME, /* Set local time (44 bits) */ 4850 bcmPortControlPhyTimesyncLoadControl = _SHR_PORT_CONTROL_PHY_TIMESYNC_LOAD_CONTROL, /* Load control and sticky bits */ 4851 bcmPortControlPhyTimesyncInterrupt = _SHR_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT, /* 1588 PHY interrupt status */ 4852 bcmPortControlPhyTimesyncInterruptMask = _SHR_PORT_CONTROL_PHY_TIMESYNC_INTERRUPT_MASK, /* 1588 PHY interrupt mask */ 4853 bcmPortControlPhyTimesyncTxTimestampOffset = _SHR_PORT_CONTROL_PHY_TIMESYNC_TX_TIMESTAMP_OFFSET, /* TX AFE delay */ 4854 bcmPortControlPhyTimesyncRxTimestampOffset = _SHR_PORT_CONTROL_PHY_TIMESYNC_RX_TIMESTAMP_OFFSET, /* RX AFE delay */ 4855 bcmPortControlPhyTimesyncNSETimeOffset = _SHR_PORT_CONTROL_PHY_TIMESYNC_NSE_TIME_OFFSET, /* En_adj_80 << 15 | En_adj_48 << 14 | 4856 14 bit 2's comp value */ 4857 bcmPortControlPhyTimesyncTimestampOffset = _SHR_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_OFFSET, /* the delay from CMIC to the PCS */ 4858 bcmPortControlPhyTimesyncTimestampAdjust = _SHR_PORT_CONTROL_PHY_TIMESYNC_TIMESTAMP_ADJUST, /* the adjustment of TS */ 4859 bcmPortControlPhyTimesyncOneStepEnable = _SHR_PORT_CONTROL_PHY_TIMESYNC_ONE_STEP_ENABLE /* One step proecssing mode for TS */ 4860 } bcm_port_control_phy_timesync_t; 4861 4862 /* AM norm modes for aggregated port speeds */ 4863 typedef enum bcm_port_phy_timesync_compensation_mode_e { 4864 bcmPortPhyTimesyncCompensationModeNone = _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_NONE, /* No compensation */ 4865 bcmPortPhyTimesyncCompensationModeEarliestLane = _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_EARLIEST_LANE, /* Compensate based on the earliest lane */ 4866 bcmPortPhyTimesyncCompensationModeLatestlane = _SHR_PORT_PHY_TIMESYNC_COMPENSATION_MODE_LATEST_LANE /* Compensate based on the latest lane. */ 4867 } bcm_port_phy_timesync_compensation_mode_t; 4868 4869 /* SA-Discard actions */ 4870 #define BCM_PORT_CONTROL_DISCARD_MACSA_NONE 0x1 /* Packets with drop-sa 4871 are switched by the 4872 device */ 4873 #define BCM_PORT_CONTROL_DISCARD_MACSA_DROP 0x2 /* Packets with drop-sa 4874 are dropped */ 4875 #define BCM_PORT_CONTROL_DISCARD_MACSA_TRAP 0x4 /* Packets with drop-sa 4876 are copied to the CPU */ 4877 4878 /* Unknown DA actions */ 4879 #define BCM_PORT_CONTROL_UNKNOWN_MACDA_NONE 0x1 /* Packets with 4880 unknown-da are 4881 switched by the device */ 4882 #define BCM_PORT_CONTROL_UNKNOWN_MACDA_DROP 0x2 /* Packets with 4883 unknown-da are dropped */ 4884 #define BCM_PORT_CONTROL_UNKNOWN_MACDA_TRAP 0x4 /* Packets with 4885 unknown-da are copied 4886 to the CPU */ 4887 4888 /* Per Port Filter enable/disable control */ 4889 #define BCM_PORT_CONTROL_FILTER_DISABLE_UNKNOWN_DA_UC 0x1 /* disable egress filter 4890 for unknown Unicast 4891 packets */ 4892 #define BCM_PORT_CONTROL_FILTER_DISABLE_UNKNOWN_DA_MC 0x2 /* disable egress filter 4893 for unknown Multicast 4894 packets */ 4895 #define BCM_PORT_CONTROL_FILTER_DISABLE_DA_BC 0x4 /* disable egress filter 4896 for Broadcast packets */ 4897 #define BCM_PORT_CONTROL_FILTER_DISABLE_ALL 0xFFFFFFFF /* disable all egress 4898 filter */ 4899 4900 /* sFlow packet sample destiantion flags */ 4901 #define BCM_PORT_CONTROL_SAMPLE_DEST_CPU 0x1 /* Copy packet samples to 4902 CPU */ 4903 #define BCM_PORT_CONTROL_SAMPLE_DEST_MIRROR 0x2 /* Copy packet samples to 4904 all mirror 4905 destinations created 4906 with 4907 BCM_MIRROR_PORT_SFLOW 4908 flag */ 4909 4910 /* Set EVB Port type. */ 4911 typedef enum bcm_port_evb_type_e { 4912 bcmPortEvbTypeNone = 0, 4913 bcmPortEvbTypeUplinkAccess = 1, 4914 bcmPortEvbTypeCount = 2 /* Must be last */ 4915 } bcm_port_evb_type_t; 4916 4917 /* SyncE recovered clock source */ 4918 typedef enum bcm_port_phy_clock_source_e { 4919 bcmPortPhyClockSourcePrimary = _SHR_PORT_PHY_CLOCK_SOURCE_PRIMARY, /* Recovery clock is being derived from 4920 primary port's recovered clock */ 4921 bcmPortPhyClockSourceSecondary = _SHR_PORT_PHY_CLOCK_SOURCE_SECONDARY /* Recovery clock is being derived from 4922 the secondary port's recovered clock */ 4923 } bcm_port_phy_clock_source_t; 4924 4925 /* FrameSync mode */ 4926 typedef enum bcm_port_phy_timesync_framesync_mode_e { 4927 bcmPortPhyTimesyncFramesyncNone = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_NONE, /* Do nothing */ 4928 bcmPortPhyTimesyncFramesyncSyncin0 = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN0, /* Use long pulse on SyncIn0 for 4929 FrameSync */ 4930 bcmPortPhyTimesyncFramesyncSyncin1 = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCIN1, /* Use SyncIn1 as FrameSync */ 4931 bcmPortPhyTimesyncFramesyncSyncout = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_SYNCOUT, /* Use internal SyncOut as FrameSync */ 4932 bcmPortPhyTimesyncFramesyncCpu = _SHR_PORT_PHY_TIMESYNC_FRAMESYNC_CPU /* CPU based immediate FrameSync */ 4933 } bcm_port_phy_timesync_framesync_mode_t; 4934 4935 /* FrameSync configuration type. */ 4936 typedef struct bcm_port_phy_timesync_framesync_s { 4937 bcm_port_phy_timesync_framesync_mode_t mode; /* framesync mode */ 4938 uint32 length_threshold; /* syncin threshold for framesync */ 4939 uint32 event_offset; /* event offset for framesync */ 4940 } bcm_port_phy_timesync_framesync_t; 4941 4942 /* SyncOut mode */ 4943 typedef enum bcm_port_phy_timesync_syncout_mode_e { 4944 bcmPortPhyTimesyncSyncoutDisable = _SHR_PORT_PHY_TIMESYNC_SYNCOUT_DISABLE, /* Do nothing */ 4945 bcmPortPhyTimesyncSyncoutOneTime = _SHR_PORT_PHY_TIMESYNC_SYNCOUT_ONE_TIME, /* One time SYNC pulse on a match with 4946 the timesync heartbeat */ 4947 bcmPortPhyTimesyncSyncoutPulseTrain = _SHR_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN, /* Pulse train on SyncOut */ 4948 bcmPortPhyTimesyncSyncoutPulseTrainWithSync = _SHR_PORT_PHY_TIMESYNC_SYNCOUT_PULSE_TRAIN_WITH_SYNC /* Combination of pulse train and one 4949 time SYNC */ 4950 } bcm_port_phy_timesync_syncout_mode_t; 4951 4952 /* Event Message Type */ 4953 typedef enum bcm_port_phy_timesync_msg_e { 4954 bcmPortPhyTimesyncMsgSync = _SHR_PORT_PHY_TIMESYNC_MSG_SYNC, /* Sync */ 4955 bcmPortPhyTimesyncMsgDelayReq = _SHR_PORT_PHY_TIMESYNC_MSG_DELAY_REQ, /* Delay Request */ 4956 bcmPortPhyTimesyncMsgPdelayReq = _SHR_PORT_PHY_TIMESYNC_MSG_PDELAY_REQ, /* PDelay Request */ 4957 bcmPortPhyTimesyncMsgPdelayResp = _SHR_PORT_PHY_TIMESYNC_MSG_PDELAY_RESP /* PDelay Response */ 4958 } bcm_port_phy_timesync_msg_t; 4959 4960 /* Protocol Type */ 4961 typedef enum bcm_port_phy_timesync_prot_e { 4962 bcmPortPhyTimesyncProtLayer2 = _SHR_PORT_PHY_TIMESYNC_PROT_LAYER2, /* 1588 over Layer 2 */ 4963 bcmPortPhyTimesyncProtIpv4Udp = _SHR_PORT_PHY_TIMESYNC_PROT_IPV4_UDP, /* 1588 over IPv4 UDP */ 4964 bcmbcmPortPhyTimesyncProtIpv6Udp = _SHR_PORT_PHY_TIMESYNC_PROT_IPV6_UDP /* 1588 over IPv6 UDP */ 4965 } bcm_port_phy_timesync_prot_t; 4966 4967 /* Direction Type */ 4968 typedef enum bcm_port_phy_timesync_dir_e { 4969 bcmPortPhyTimesyncDirEgress = _SHR_PORT_PHY_TIMESYNC_DIR_EGRESS, /* Egress Packet */ 4970 bcmPortPhyTimesyncDirIngress = _SHR_PORT_PHY_TIMESYNC_DIR_INGRESS /* Igress Packet */ 4971 } bcm_port_phy_timesync_dir_t; 4972 4973 /* TimeSync timer mode */ 4974 typedef enum bcm_port_phy_timesync_timer_mode_e { 4975 bcmPortPhyTimesyncTimerModeNone = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_NONE, /* No TimeSync timer */ 4976 bcmPortPhyTimesyncTimerModeDefault = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_DEFAULT, /* Use the default TimeSync timer */ 4977 bcmPortPhyTimesyncTimerMode32bit = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_32BIT, /* Use 32-bit TimeSync timer */ 4978 bcmPortPhyTimesyncTimerMode48bit = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_48BIT, /* Use 48-bit TimeSync timer */ 4979 bcmPortPhyTimesyncTimerMode64bit = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_64BIT, /* Use 64-bit TimeSync timer */ 4980 bcmPortPhyTimesyncTimerMode80bit = _SHR_PORT_PHY_TIMESYNC_TIMER_MODE_80BIT /* Use 80-bit TimeSync timer */ 4981 } bcm_port_phy_timesync_timer_mode_t; 4982 4983 /* Flow control modes */ 4984 typedef enum bcm_port_phy_control_flow_control_mode_e { 4985 bcmPortPhyControlFlowCtrlModeNone = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_MODE_NONE, /* No flow control mode (Relay mode) */ 4986 bcmPortPhyControlFlowCtrlLegacyPauseEn = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_LEGACY_PAUSE_EN, /* Lagacy Pause flow control mode */ 4987 bcmPortPhyControlFlowCtrlPfcPause = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_PFC_PAUSE, /* PFC flow control mode */ 4988 bcmPortPhyControlFlowCtrlLlfc = _SHR_PORT_PHY_CONTROL_FLOW_CTRL_LLFC /* LLFC flow control mode */ 4989 } bcm_port_phy_control_flow_control_mode_t; 4990 4991 /* Parameter for bcmPortControlFieldEgressClassSelect */ 4992 typedef enum bcm_port_field_egress_class_select_e { 4993 bcmPortEgressClassSelectNone = 0, /* Class Id Not Assigned. */ 4994 bcmPortEgressClassSelectPort = 1, /* Class Id from Port Interface. */ 4995 bcmPortEgressClassSelectSvp = 2, /* Class Id from SVP. */ 4996 bcmPortEgressClassSelectL3Interface = 3, /* Class Id from L3 IIF Interface. */ 4997 bcmPortEgressClassSelectFieldSrc = 4, /* Class Id from VFP HI. */ 4998 bcmPortEgressClassSelectFieldDst = 5, /* Class Id from VFP LOW. */ 4999 bcmPortEgressClassSelectL2Src = 6, /* Class Id from L2 SRC. */ 5000 bcmPortEgressClassSelectL2Dst = 7, /* Class Id from L2 DST. */ 5001 bcmPortEgressClassSelectL3Src = 8, /* Class Id from L3 SRC. */ 5002 bcmPortEgressClassSelectL3Dst = 9, /* Class Id from L3 DST. */ 5003 bcmPortEgressClassSelectVlan = 10, /* Class Id from VLAN Interface. */ 5004 bcmPortEgressClassSelectVrf = 11, /* Class Id from VRF. */ 5005 bcmPortEgressClassSelectFieldIngress = 12, /* Class Id from IFP Policy Table. */ 5006 bcmPortEgressClassSelectCount = 13 /* Always Last. Not a usable value. */ 5007 } bcm_port_field_egress_class_select_t; 5008 5009 /* Parameter for bcmPortControlFieldHiGigClassSelect */ 5010 typedef enum bcm_port_field_higig_class_select_e { 5011 bcmPortFieldHiGigClassSelectNone = 0, /* Class Id Not Assigned. */ 5012 bcmPortFieldHiGigClassSelectIngressToEgress = 1, /* Class Id passed from ingress to 5013 egress. */ 5014 bcmPortFieldHiGigClassSelectL3Egress = 2, /* Class Id from L3 egress object. */ 5015 bcmPortFieldHiGigClassSelectL3EgressIntf = 3, /* Class Id from L3 egress interface. */ 5016 bcmPortFieldHiGigClassSelectEgressGport = 4, /* Class Id from egress dvp. */ 5017 bcmPortFieldHiGigClassSelectCount = 5 /* Always Last. Not a usable value. */ 5018 } bcm_port_field_higig_class_select_t; 5019 5020 /* syncout configuration type. */ 5021 typedef struct bcm_port_phy_timesync_syncout_s { 5022 bcm_port_phy_timesync_syncout_mode_t mode; /* syncout mode */ 5023 uint16 pulse_1_length; /* pulse 1 length in ns */ 5024 uint16 pulse_2_length; /* pulse 2 length in ns */ 5025 uint32 interval; /* interval in ns */ 5026 uint64 syncout_ts; /* syncout timestamp */ 5027 } bcm_port_phy_timesync_syncout_t; 5028 5029 /* MPLS label type. */ 5030 typedef struct bcm_port_phy_timesync_mpls_label_s { 5031 bcm_mpls_label_t value; /* label value */ 5032 bcm_mpls_label_t mask; /* label mask */ 5033 uint32 flags; /* MPLS label flags */ 5034 } bcm_port_phy_timesync_mpls_label_t; 5035 5036 /* MPLS control type. */ 5037 typedef struct bcm_port_phy_timesync_mpls_control_s { 5038 uint32 flags; /* MPLS control flags */ 5039 bcm_mpls_label_t special_label; /* special label value */ 5040 bcm_port_phy_timesync_mpls_label_t labels[10]; /* Timesync MPLS labels */ 5041 int size; /* Number of valid elements in label 5042 array */ 5043 } bcm_port_phy_timesync_mpls_control_t; 5044 5045 /* Timer adjustment type. */ 5046 typedef struct bcm_port_phy_timesync_timer_adjust_s { 5047 bcm_port_phy_timesync_timer_mode_t mode; /* Timer adjustment mode */ 5048 int delta; /* Timer adjustment delta value */ 5049 } bcm_port_phy_timesync_timer_adjust_t; 5050 5051 /* Inband TS control type. */ 5052 typedef struct bcm_port_phy_timesync_inband_control_s { 5053 uint32 flags; /* Inband TS control flags */ 5054 uint32 resv0_id; /* Resv0 ID used */ 5055 bcm_port_phy_timesync_timer_mode_t timer_mode; /* Timer mode */ 5056 } bcm_port_phy_timesync_inband_control_t; 5057 5058 /* Enhanced capture type. */ 5059 typedef struct bcm_port_phy_timesync_enhanced_capture_s { 5060 bcm_port_phy_timesync_msg_t msg_type; /* Message type */ 5061 bcm_port_phy_timesync_prot_t protocol; /* Protocol type */ 5062 bcm_port_phy_timesync_dir_t direction; /* Direction type */ 5063 uint32 seq_id; /* Sequence ID */ 5064 uint32 domain; /* Domain */ 5065 uint64 timestamp; /* Timestamp */ 5066 uint64 source_port_identity; /* Source port identity */ 5067 uint16 source_port; /* Source port */ 5068 uint16 vlan_id; /* Vlan ID */ 5069 } bcm_port_phy_timesync_enhanced_capture_t; 5070 5071 /* Base timesync configuration type. */ 5072 typedef struct bcm_port_phy_timesync_config_s { 5073 uint32 capabilities; /* Flags BCM_PORT_PHY_TIMESYNC_CAP_* */ 5074 uint32 validity_mask; /* Flags BCM_PORT_PHY_TIMESYNC_VALID_* */ 5075 uint32 flags; /* Flags BCM_PORT_PHY_TIMESYNC_* */ 5076 uint16 itpid; /* 1588 inner tag */ 5077 uint16 otpid; /* 1588 outer tag */ 5078 uint16 otpid2; /* 1588 outer tag2 */ 5079 bcm_port_phy_timesync_timer_adjust_t timer_adjust; /* Direct timer adjustment */ 5080 bcm_port_phy_timesync_inband_control_t inband_control; /* Inband TS control */ 5081 bcm_port_phy_timesync_global_mode_t gmode; /* Global mode */ 5082 bcm_port_phy_timesync_framesync_t framesync; /* Framesync */ 5083 bcm_port_phy_timesync_syncout_t syncout; /* Syncout */ 5084 uint16 ts_divider; /* TS divider */ 5085 bcm_time_spec_t original_timecode; /* Original timecode to be inserted */ 5086 uint32 tx_timestamp_offset; /* TX AFE delay in ns - per port */ 5087 uint32 rx_timestamp_offset; /* RX AFE delay in ns - per port */ 5088 uint32 rx_link_delay; /* RX link delay */ 5089 bcm_port_phy_timesync_event_message_egress_mode_t tx_sync_mode; /* sync */ 5090 bcm_port_phy_timesync_event_message_egress_mode_t tx_delay_request_mode; /* delay request */ 5091 bcm_port_phy_timesync_event_message_egress_mode_t tx_pdelay_request_mode; /* pdelay request */ 5092 bcm_port_phy_timesync_event_message_egress_mode_t tx_pdelay_response_mode; /* pdelay response */ 5093 bcm_port_phy_timesync_event_message_ingress_mode_t rx_sync_mode; /* sync */ 5094 bcm_port_phy_timesync_event_message_ingress_mode_t rx_delay_request_mode; /* delay request */ 5095 bcm_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_request_mode; /* pdelay request */ 5096 bcm_port_phy_timesync_event_message_ingress_mode_t rx_pdelay_response_mode; /* pdelay response */ 5097 bcm_port_phy_timesync_mpls_control_t mpls_control; /* MPLS control */ 5098 uint32 sync_freq; /* DPLL sync freq. */ 5099 uint16 phy_1588_dpll_k1; /* DPLL K1 */ 5100 uint16 phy_1588_dpll_k2; /* DPLL K2 */ 5101 uint16 phy_1588_dpll_k3; /* DPLL K3 */ 5102 uint64 phy_1588_dpll_loop_filter; /* DPLL loop filter */ 5103 uint64 phy_1588_dpll_ref_phase; /* DPLL ref phase */ 5104 uint32 phy_1588_dpll_ref_phase_delta; /* DPLL ref phase delta */ 5105 } bcm_port_phy_timesync_config_t; 5106 5107 /* Initialize the port Timesync config structure. */ 5108 extern void bcm_port_timesync_config_t_init( 5109 bcm_port_timesync_config_t *port_timesync_config); 5110 5111 /* bcm_port_phy_timesync_config_t_init */ 5112 extern void bcm_port_phy_timesync_config_t_init( 5113 bcm_port_phy_timesync_config_t *conf); 5114 5115 #ifndef BCM_HIDE_DISPATCHABLE 5116 5117 /* bcm_port_phy_timesync_config_set */ 5118 extern int bcm_port_phy_timesync_config_set( 5119 int unit, 5120 bcm_port_t port, 5121 bcm_port_phy_timesync_config_t *conf); 5122 5123 /* bcm_port_phy_timesync_config_get */ 5124 extern int bcm_port_phy_timesync_config_get( 5125 int unit, 5126 bcm_port_t port, 5127 bcm_port_phy_timesync_config_t *conf); 5128 5129 /* bcm_port_control_phy_timesync_set */ 5130 extern int bcm_port_control_phy_timesync_set( 5131 int unit, 5132 bcm_port_t port, 5133 bcm_port_control_phy_timesync_t type, 5134 uint64 value); 5135 5136 /* bcm_port_control_phy_timesync_get */ 5137 extern int bcm_port_control_phy_timesync_get( 5138 int unit, 5139 bcm_port_t port, 5140 bcm_port_control_phy_timesync_t type, 5141 uint64 *value); 5142 5143 /* bcm_port_phy_timesync_enhanced_capture_get */ 5144 extern int bcm_port_phy_timesync_enhanced_capture_get( 5145 int unit, 5146 bcm_port_t port, 5147 bcm_port_phy_timesync_enhanced_capture_t *value); 5148 5149 #endif /* BCM_HIDE_DISPATCHABLE */ 5150 5151 #define BCM_PORT_PHY_OAM_DM_MAC_CHECK_ENABLE _SHR_PORT_PHY_OAM_MAC_CHECK_ENABLE /* Enable MAC check for 5152 Delay Measurement */ 5153 #define BCM_PORT_PHY_OAM_DM_CONTROL_WORD_ENABLE _SHR_PORT_PHY_OAM_CONTROL_WORD_ENABLE /* Enable Control Word 5154 for Delay Measurement */ 5155 #define BCM_PORT_PHY_OAM_DM_ENTROPY_ENABLE _SHR_PORT_PHY_OAM_DM_ENTROPY_ENABLE /* Enable entropy for 5156 Delay Measurement */ 5157 #define BCM_PORT_PHY_OAM_DM_TS_FORMAT _SHR_PORT_PHY_OAM_DM_TS_FORMAT /* Select timestamp 5158 format PTP(0)/NTP(1) 5159 for Delay Measurement */ 5160 5161 /* Port controls for phy OAM */ 5162 typedef enum bcm_port_control_phy_oam_e { 5163 bcmPortControlPhyOamDmTxEthertype = _SHR_PORT_CONTROL_PHY_OAM_DM_TX_ETHERTYPE, /* OAM Delay measurement Tx Ethertype */ 5164 bcmPortControlPhyOamDmRxEthertype = _SHR_PORT_CONTROL_PHY_OAM_DM_RX_ETHERTYPE, /* OAM Delay measurement Rx Ethertype */ 5165 bcmPortControlPhyOamDmTxPortMacAddressIndex = _SHR_PORT_CONTROL_PHY_OAM_DM_TX_PORT_MAC_ADDRESS_INDEX, /* Index to select the MAC address. Use 5166 index of 1 to select MacAddress1, 5167 index of 2 for MacAddress2 and so 5168 forth. */ 5169 bcmPortControlPhyOamDmRxPortMacAddressIndex = _SHR_PORT_CONTROL_PHY_OAM_DM_RX_PORT_MAC_ADDRESS_INDEX, /* Index to select the MAC address. Use 5170 index of 1 to select MacAddress1, 5171 index of 2 for MacAddress2 and so 5172 forth. */ 5173 bcmPortControlPhyOamDmMacAddress1 = _SHR_PORT_CONTROL_PHY_OAM_DM_MAC_ADDRESS_1, /* OAM Delay measurement MAC address 1. 5174 There can be multiple MAC address to 5175 choose from in a PHY depending upon 5176 the design */ 5177 bcmPortControlPhyOamDmMacAddress2 = _SHR_PORT_CONTROL_PHY_OAM_DM_MAC_ADDRESS_2, /* OAM Delay measurement MAC address 2. 5178 There can be multiple MAC address to 5179 choose from in a PHY depending upon 5180 the design */ 5181 bcmPortControlPhyOamDmMacAddress3 = _SHR_PORT_CONTROL_PHY_OAM_DM_MAC_ADDRESS_3 /* OAM Delay measurement MAC address 3. 5182 There can be multiple MAC address to 5183 choose from in a PHY depending upon 5184 the design */ 5185 } bcm_port_control_phy_oam_t; 5186 5187 /* Phy OAM Delay Measurement Modes */ 5188 typedef enum bcm_port_config_phy_oam_dm_mode_e { 5189 bcmPortConfigPhyOamDmModeY1731 = _SHR_PORT_CONFIG_PHY_OAM_DM_Y1731, /* OAM Delay measurement Y.7131 Mode */ 5190 bcmPortConfigPhyOamDmModeBhh = _SHR_PORT_CONFIG_PHY_OAM_DM_BHH, /* OAM Delay measurement BHH Mode */ 5191 bcmPortConfigPhyOamDmModeIetf = _SHR_PORT_CONFIG_PHY_OAM_DM_IETF /* OAM Delay measurement IETF Mode */ 5192 } bcm_port_config_phy_oam_dm_mode_t; 5193 5194 /* Phy OAM Delay measurement config type. */ 5195 typedef struct bcm_port_config_phy_oam_dm_s { 5196 uint32 flags; /* OAM Delay Measurement config flags */ 5197 bcm_port_config_phy_oam_dm_mode_t mode; /* OAM Delay Measurement mode Y.1731, 5198 BHH or IETF */ 5199 } bcm_port_config_phy_oam_dm_t; 5200 5201 /* Phy OAM config type. */ 5202 typedef struct bcm_port_config_phy_oam_s { 5203 bcm_port_config_phy_oam_dm_t tx_dm_config; /* OAM delay measurement config for Tx */ 5204 bcm_port_config_phy_oam_dm_t rx_dm_config; /* OAM delay measurement config for Rx */ 5205 } bcm_port_config_phy_oam_t; 5206 5207 #ifndef BCM_HIDE_DISPATCHABLE 5208 5209 /* bcm_port_config_phy_oam_set */ 5210 extern int bcm_port_config_phy_oam_set( 5211 int unit, 5212 bcm_port_t port, 5213 bcm_port_config_phy_oam_t *conf); 5214 5215 /* bcm_port_config_phy_oam_get */ 5216 extern int bcm_port_config_phy_oam_get( 5217 int unit, 5218 bcm_port_t port, 5219 bcm_port_config_phy_oam_t *conf); 5220 5221 /* bcm_port_control_phy_oam_set */ 5222 extern int bcm_port_control_phy_oam_set( 5223 int unit, 5224 bcm_port_t port, 5225 bcm_port_control_phy_oam_t type, 5226 uint64 value); 5227 5228 /* bcm_port_control_phy_oam_get */ 5229 extern int bcm_port_control_phy_oam_get( 5230 int unit, 5231 bcm_port_t port, 5232 bcm_port_control_phy_oam_t type, 5233 uint64 *value); 5234 5235 #endif /* BCM_HIDE_DISPATCHABLE */ 5236 5237 #define BCM_PORT_CONGESTION_MAPPING_CLEAR _SHR_PORT_CONGESTION_MAPPING_CLEAR /* Clear mapping */ 5238 #define BCM_PORT_CONGESTION_MAPPING_RX _SHR_PORT_CONGESTION_MAPPING_RX /* Mapping for Rx 5239 Direction */ 5240 #define BCM_PORT_CONGESTION_MAPPING_TX _SHR_PORT_CONGESTION_MAPPING_TX /* Mapping for Tx 5241 Direction */ 5242 5243 #define BCM_PORT_CHANNEL_ID_SET(_channel_id, _port_base, _port_ch) \ 5244 _SHR_PORT_CHANNEL_ID_SET(_channel_id, _port_base, _port_ch) 5245 5246 #define BCM_PORT_CHANNEL_ID_PORT_BASE_GET(_channel_id) \ 5247 _SHR_PORT_CHANNEL_ID_PORT_BASE_GET(_channel_id) 5248 5249 #define BCM_PORT_CHANNEL_ID_PORT_CH_GET(_channel_id) \ 5250 _SHR_PORT_CHANNEL_ID_PORT_CH_GET(_channel_id) 5251 5252 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_BACKPLANE _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_BACKPLANE 5253 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_COPPER_CABLE _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_COPPER_CABLE 5254 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_OPTICS _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_OPTICS 5255 5256 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_SET(lane_config) \ 5257 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_SET(lane_config) 5258 5259 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_GET(lane_config) \ 5260 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_GET(lane_config) 5261 5262 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_CLEAR(lane_config) \ 5263 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_DFE_CLEAR(lane_config) 5264 5265 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_SET(lane_config) \ 5266 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_SET(lane_config) 5267 5268 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_GET(lane_config) \ 5269 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_GET(lane_config) 5270 5271 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_CLEAR(lane_config) \ 5272 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_DFE_CLEAR(lane_config) 5273 5274 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_SET(lane_config) \ 5275 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_SET(lane_config) 5276 5277 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_GET(lane_config) \ 5278 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_GET(lane_config) 5279 5280 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_CLEAR(lane_config) \ 5281 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_BR_DFE_CLEAR(lane_config) 5282 5283 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_SET(lane_config, medium_type) \ 5284 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_SET(lane_config, medium_type) 5285 5286 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_GET(lane_config) \ 5287 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_GET(lane_config) 5288 5289 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_CLEAR(lane_config) \ 5290 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_MEDIUM_CLEAR(lane_config) 5291 5292 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_SET(lane_config) \ 5293 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_SET(lane_config) 5294 5295 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_GET(lane_config) \ 5296 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_GET(lane_config) 5297 5298 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_CLEAR(lane_config) \ 5299 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_UNRELIABLE_LOS_CLEAR(lane_config) 5300 5301 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_SET(lane_config) \ 5302 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_SET(lane_config) 5303 5304 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_GET(lane_config) \ 5305 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_GET(lane_config) 5306 5307 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_CLEAR(lane_config) \ 5308 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_SCRAMBLING_DISABLE_CLEAR(lane_config) 5309 5310 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_SET(lane_config) \ 5311 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_SET(lane_config) 5312 5313 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_GET(lane_config) \ 5314 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_GET(lane_config) 5315 5316 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_CLEAR(lane_config) \ 5317 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_POLARITY_AUTO_EN_CLEAR(lane_config) 5318 5319 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_SET(lane_config) \ 5320 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_SET(lane_config) 5321 5322 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_GET(lane_config) \ 5323 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_GET(lane_config) 5324 5325 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_CLEAR(lane_config) \ 5326 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_CL72_RESTART_TIMEOUT_EN_CLEAR(lane_config) 5327 5328 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_SET(lane_config) \ 5329 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_SET(lane_config) 5330 5331 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_GET(lane_config) \ 5332 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_GET(lane_config) 5333 5334 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_CLEAR(lane_config) \ 5335 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_ES_CLEAR(lane_config) 5336 5337 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_SET(lane_config) \ 5338 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_SET(lane_config) 5339 5340 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_GET(lane_config) \ 5341 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_GET(lane_config) 5342 5343 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_CLEAR(lane_config) \ 5344 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NS_CLEAR(lane_config) 5345 5346 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_SET(lane_config) \ 5347 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_SET(lane_config) 5348 5349 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_GET(lane_config) \ 5350 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_GET(lane_config) 5351 5352 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_CLEAR(lane_config) \ 5353 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_PAM4_CLEAR(lane_config) 5354 5355 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_SET(lane_config) \ 5356 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_SET(lane_config) 5357 5358 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_GET(lane_config) \ 5359 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_GET(lane_config) 5360 5361 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_CLEAR(lane_config) \ 5362 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_FORCE_NRZ_CLEAR(lane_config) 5363 5364 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_SET(lane_config, channel_loss) \ 5365 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_SET(lane_config, channel_loss) 5366 5367 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_GET(lane_config) \ 5368 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_GET(lane_config) 5369 5370 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_CLEAR(lane_config) \ 5371 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_PAM4_CHANNEL_LOSS_CLEAR(lane_config) 5372 5373 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_SET(lane_config) \ 5374 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_SET(lane_config) 5375 5376 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_GET(lane_config) \ 5377 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_GET(lane_config) 5378 5379 #define BCM_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_CLEAR(lane_config) \ 5380 _SHR_PORT_RESOURCE_PHY_LANE_CONFIG_LP_PREC_EN_CLEAR(lane_config) 5381 5382 #ifndef BCM_HIDE_DISPATCHABLE 5383 5384 /* Set mapping for port to HCFC port(channel_id) */ 5385 extern int bcm_port_congestion_set( 5386 int unit, 5387 bcm_gport_t congestion_port, 5388 bcm_gport_t port, 5389 uint32 flags, 5390 int channel_id); 5391 5392 /* retreive mapping for port to HCFC port(channel_id) */ 5393 extern int bcm_port_congestion_get( 5394 int unit, 5395 bcm_gport_t congestion_port, 5396 bcm_gport_t port, 5397 uint32 flags, 5398 int *channel_id); 5399 5400 /* Attach counter entries to the given gport */ 5401 extern int bcm_port_stat_attach( 5402 int unit, 5403 bcm_gport_t port, 5404 uint32 stat_counter_id); 5405 5406 /* Detach counter entries to the given gport */ 5407 extern int bcm_port_stat_detach( 5408 int unit, 5409 bcm_gport_t port); 5410 5411 /* Detach counter entries to the given gport with a given stat counter id */ 5412 extern int bcm_port_stat_detach_with_id( 5413 int unit, 5414 bcm_gport_t port, 5415 uint32 stat_counter_id); 5416 5417 /* Get counter values for specified gport based on port statistic type */ 5418 extern int bcm_port_stat_counter_get( 5419 int unit, 5420 bcm_gport_t port, 5421 bcm_port_stat_t stat, 5422 uint32 num_entries, 5423 uint32 *counter_indexes, 5424 bcm_stat_value_t *counter_values); 5425 5426 /* Get counter values for specified gport based on port statistic type */ 5427 extern int bcm_port_stat_counter_sync_get( 5428 int unit, 5429 bcm_gport_t port, 5430 bcm_port_stat_t stat, 5431 uint32 num_entries, 5432 uint32 *counter_indexes, 5433 bcm_stat_value_t *counter_values); 5434 5435 /* Set counter values for specified gport based on port statistic type */ 5436 extern int bcm_port_stat_counter_set( 5437 int unit, 5438 bcm_gport_t port, 5439 bcm_port_stat_t stat, 5440 uint32 num_entries, 5441 uint32 *counter_indexes, 5442 bcm_stat_value_t *counter_values); 5443 5444 /* Set the encapsulation to port mapping from encap_id to port. */ 5445 extern int bcm_port_encap_map_set( 5446 int unit, 5447 uint32 flags, 5448 bcm_if_t encap_id, 5449 bcm_gport_t port); 5450 5451 /* Get the encapsulation to port mapping from encap_id. */ 5452 extern int bcm_port_encap_map_get( 5453 int unit, 5454 uint32 flags, 5455 bcm_if_t encap_id, 5456 bcm_gport_t *port); 5457 5458 #endif /* BCM_HIDE_DISPATCHABLE */ 5459 5460 /* Allow remapping an encapsulation to a port on a different core. */ 5461 #define BCM_PORT_ENCAP_MAP_ALLOW_CORE_CHANGE 1 5462 5463 #define BCM_PORT_PON_TUNNEL_WITH_ID 0x01 5464 5465 #ifndef BCM_HIDE_DISPATCHABLE 5466 5467 /* Add service classifications(tunnel-port-ids) per pon port. */ 5468 extern int bcm_port_pon_tunnel_add( 5469 int unit, 5470 bcm_gport_t pon_port, 5471 uint32 flags, 5472 bcm_gport_t *tunnel_port_id); 5473 5474 /* Remove service classifications(tunnel-port-ids) per pon port. */ 5475 extern int bcm_port_pon_tunnel_remove( 5476 int unit, 5477 bcm_gport_t tunnel_port_id); 5478 5479 /* Set the tunnel id to the service class mapping. */ 5480 extern int bcm_port_pon_tunnel_map_set( 5481 int unit, 5482 bcm_gport_t pon_port, 5483 bcm_tunnel_id_t tunnel_id, 5484 bcm_gport_t tunnel_port_id); 5485 5486 /* Get the tunnel id to the service class mapping. */ 5487 extern int bcm_port_pon_tunnel_map_get( 5488 int unit, 5489 bcm_gport_t pon_port, 5490 bcm_tunnel_id_t tunnel_id, 5491 bcm_gport_t *tunnel_port_id); 5492 5493 #endif /* BCM_HIDE_DISPATCHABLE */ 5494 5495 /* Statistics threshold flag. */ 5496 #define BCM_STAT_THRESHOLD_FLAGS_NOT (1 << 0) 5497 5498 /* threshold type */ 5499 typedef enum bcm_stat_threshold_type_e { 5500 bcmStatThresholdDisabled = 0, 5501 bcmStatThresholdSingle = 1, 5502 bcmStatThresholdRange = 2, 5503 bcmStatThresholdZero = 3, 5504 bcmStatThresholdSigned = 4 5505 } bcm_stat_threshold_type_t; 5506 5507 /* 5508 * Statistics threshold information. 5509 * Interpretations of arg1 and arg2: 5510 * single: 5511 * stat > arg1 raises alarm; stat <= arg2 clears alarm 5512 * range: 5513 * !(arg1 <= stat <= arg2) raises alarm; inverse clears alarm 5514 * zero: 5515 * stat == 0 raises alarm; stat != 0 clears alarm. arg1/2 ignored 5516 * signed: 5517 * as range, except arg1/2 are interpreted as signed (int32_t) 5518 */ 5519 typedef struct bcm_stat_threshold_s { 5520 bcm_stat_threshold_type_t type; /* threshold type, per-type data follows */ 5521 uint32 flags; /* threshold flag */ 5522 uint32 arg1; /* threshold parameter 1 */ 5523 uint32 arg2; /* threshold parameter 2 */ 5524 } bcm_stat_threshold_t; 5525 5526 #ifndef BCM_HIDE_DISPATCHABLE 5527 5528 /* Statistics threshold set */ 5529 extern int bcm_stat_threshold_set( 5530 int unit, 5531 bcm_port_t port, 5532 bcm_stat_val_t stat, 5533 bcm_stat_threshold_t *threshold); 5534 5535 /* Statistics threshold get */ 5536 extern int bcm_stat_threshold_get( 5537 int unit, 5538 bcm_port_t port, 5539 bcm_stat_val_t stat, 5540 bcm_stat_threshold_t *threshold); 5541 5542 /* Get a list of tpids and associated color selections for a given port. */ 5543 extern int bcm_port_tpid_get_all( 5544 int unit, 5545 bcm_port_t port, 5546 int size, 5547 uint16 *tpid_array, 5548 int *color_array, 5549 int *count); 5550 5551 #endif /* BCM_HIDE_DISPATCHABLE */ 5552 5553 /* FCOE Fabric select. Used with bcmPortControlFcoeFabricSel */ 5554 typedef enum bcm_port_fcoe_vsan_select_e { 5555 bcmPortFcoeVsanSelectVft = 0, /* use VFT header */ 5556 bcmPortFcoeVsanSelectPort = 1, /* use Port Table value */ 5557 bcmPortFcoeVsanSelectInnerVlan = 2, /* use incoming inner VID/COS */ 5558 bcmPortFcoeVsanSelectOuterVlan = 3 /* use incoming outer VID/COS */ 5559 } bcm_port_fcoe_vsan_select_t; 5560 5561 /* 5562 * BCM56960 Port ASF (Cut-thru) Modes. Used with 5563 * bcmSwitchAlternateStoreForward 5564 */ 5565 typedef enum bcm_port_asf_mode_e { 5566 bcmPortAsfModeStoreAndForward = 0, /* Store and Forward (SAF) forwarding 5567 mode */ 5568 bcmPortAsfModeSameSpeed = 1, /* Cut-thru forwarding between same 5569 speed ports */ 5570 bcmPortAsfModeSlowToFast = 2, /* Cut-thru forwarding between slower to 5571 faster speed ports */ 5572 bcmPortAsfModeFastToSlow = 3 /* Cut-thru forwarding between faster to 5573 slower speed ports */ 5574 } bcm_port_asf_mode_t; 5575 5576 /* Define port mapping type */ 5577 typedef enum bcm_port_extender_mapping_type_e { 5578 bcmPortExtenderMappingTypePonTunnel = 0, /* Map information includes PON port and 5579 Tunnel-ID */ 5580 bcmPortExtenderMappingTypePortVlan = 1, /* Map information includes Phy Port and 5581 VLAN-ID */ 5582 bcmPortExtenderMappingTypeUserDefineValue = 2 /* Map information includes user define 5583 fields */ 5584 } bcm_port_extender_mapping_type_t; 5585 5586 #define BCM_PORT_EXTENDER_MAPPING_INGRESS 0x0001 /* Map information to 5587 Incoming local PP port */ 5588 #define BCM_PORT_EXTENDER_MAPPING_EGRESS 0x0002 /* Map information to 5589 Outgoing local PP port */ 5590 5591 /* port mapping information */ 5592 typedef struct bcm_port_extender_mapping_info_s { 5593 bcm_gport_t pp_port; /* Mapped Local PP port */ 5594 bcm_tunnel_id_t tunnel_id; /* Tunnel-ID */ 5595 bcm_gport_t phy_port; /* Physical Port connected to interface x 5596 channel */ 5597 bcm_vlan_t vlan; /* VLAN-ID */ 5598 uint32 user_define_value; /* User define value from header */ 5599 } bcm_port_extender_mapping_info_t; 5600 5601 /* Initialize a port extender mapping struct. */ 5602 extern void bcm_port_extender_mapping_info_t_init( 5603 bcm_port_extender_mapping_info_t *mapping_info); 5604 5605 #ifndef BCM_HIDE_DISPATCHABLE 5606 5607 /* port mapping info set */ 5608 extern int bcm_port_extender_mapping_info_set( 5609 int unit, 5610 uint32 flags, 5611 bcm_port_extender_mapping_type_t type, 5612 bcm_port_extender_mapping_info_t *mapping_info); 5613 5614 /* port mapping info get */ 5615 extern int bcm_port_extender_mapping_info_get( 5616 int unit, 5617 uint32 flags, 5618 bcm_port_extender_mapping_type_t type, 5619 bcm_port_extender_mapping_info_t *mapping_info); 5620 5621 #endif /* BCM_HIDE_DISPATCHABLE */ 5622 5623 /* Define vxlan vpn assignment criteria type */ 5624 typedef enum bcm_port_vxlan_vpn_assignment_criteria_e { 5625 bcmPortVxlanVpnAssignOnVnid = 0, /* use VNID. */ 5626 bcmPortVxlanVpnAssignOnVnidSrcIp = 1, /* use VNID and SIP. */ 5627 bcmPortVxlanVpnAssignOnVnidOuterVlan = 2, /* use VNID and OVID. */ 5628 bcmPortVxlanVpnAssignOnVnidOuterVlanSrcIp = 3 /* use VNID , OVID and SIP. */ 5629 } bcm_port_vxlan_vpn_assignment_criteria_t; 5630 5631 /* Define vxlan termination match criteria type */ 5632 typedef enum bcm_port_vxlan_termination_match_criteria_e { 5633 bcmPortVxlanTerminationMatchDstIp = 0, /* use DIP. */ 5634 bcmPortVxlanTerminationMatchOuterVlanDstIp = 1 /* use OVID and DIP. */ 5635 } bcm_port_vxlan_termination_match_criteria_t; 5636 5637 /* Define vxlan gport assignment criteria type */ 5638 typedef enum bcm_port_vxlan_gport_assignment_criteria_e { 5639 bcmPortVxlanGportAssignOnSrcIp = 0, /* use SIP. */ 5640 bcmPortVxlanGportAssignOnOuterVlanSrcIp = 1 /* use OVID and SIP. */ 5641 } bcm_port_vxlan_gport_assignment_criteria_t; 5642 5643 #ifndef BCM_HIDE_DISPATCHABLE 5644 5645 /* Add the GPORT ID for the specified physical port. */ 5646 extern int bcm_port_gport_add( 5647 int unit, 5648 bcm_port_t local_port, 5649 bcm_gport_t modport); 5650 5651 /* Delete the GPORT ID for the specified physical port. */ 5652 extern int bcm_port_gport_delete( 5653 int unit, 5654 bcm_port_t local_port, 5655 bcm_gport_t modport); 5656 5657 /* Delete all the GPORT IDs for the specified physical port. */ 5658 extern int bcm_port_gport_delete_all( 5659 int unit, 5660 bcm_port_t local_port); 5661 5662 /* Get all the GPORT IDs for the specified physical port. */ 5663 extern int bcm_port_gport_get_all( 5664 int unit, 5665 bcm_port_t local_port, 5666 int size, 5667 bcm_gport_t *gport_array, 5668 int *count); 5669 5670 /* Set additional data for a wide LIF. */ 5671 extern int bcm_port_wide_data_set( 5672 int unit, 5673 bcm_gport_t gport, 5674 uint32 flags, 5675 uint64 data); 5676 5677 /* Get additional data for a wide LIF. */ 5678 extern int bcm_port_wide_data_get( 5679 int unit, 5680 bcm_gport_t gport, 5681 uint32 flags, 5682 uint64 *data); 5683 5684 /* Get local Encap id per Gport */ 5685 extern int bcm_port_encap_local_get( 5686 int unit, 5687 bcm_gport_t gport, 5688 uint32 flags, 5689 int *encap_local_id); 5690 5691 #endif /* BCM_HIDE_DISPATCHABLE */ 5692 5693 /* Port wide data set/get flags. */ 5694 #define BCM_PORT_WIDE_DATA_INGRESS 0x1 /* If set, wide data related to 5695 ingress port (lif) extension. */ 5696 #define BCM_PORT_WIDE_DATA_EGRESS 0x2 /* If set, wide data related to 5697 egress port (lif) extension. */ 5698 5699 /* Port encap local id get flags. */ 5700 #define BCM_PORT_ENCAP_LOCAL_INGRESS 0x1 /* If set, encap local id 5701 related to ingress port 5702 (lif). */ 5703 #define BCM_PORT_ENCAP_LOCAL_EGRESS 0x2 /* If set, encap local id 5704 related to egress port 5705 (lif). */ 5706 5707 /* serdes channel supported */ 5708 typedef enum bcm_port_phy_channel_e { 5709 bcmPortPhyChannelShort = _SHR_PORT_PHY_CHANNEL_SHORT, /* short channel */ 5710 bcmPortPhyChannelLong = _SHR_PORT_PHY_CHANNEL_LONG, /* long channel */ 5711 bcmPortPhyChannelAll = _SHR_PORT_PHY_CHANNEL_ALL, /* this is only used by 5712 bcm_port_apeed_ability_local_get */ 5713 bcmPortPhyChannelCount = _SHR_PORT_PHY_CHANNEL_COUNT /* channel count */ 5714 } bcm_port_phy_channel_t; 5715 5716 /* serdes pause supported */ 5717 typedef enum bcm_port_phy_pause_e { 5718 bcmPortPhyPauseNone = _SHR_PORT_PHY_PAUSE_NONE, /* no pause */ 5719 bcmPortPhyPauseTx = _SHR_PORT_PHY_PAUSE_TX, /* tx pause */ 5720 bcmPortPhyPauseRx = _SHR_PORT_PHY_PAUSE_RX, /* rx pause */ 5721 bcmPortPhyPauseSymm = _SHR_PORT_PHY_PAUSE_SYMM, /* Symm pause type */ 5722 bcmPortPhyPauseALL = _SHR_PORT_PHY_PAUSE_ALL, /* this type is used only by 5723 bcm_port_speed_ability_local get */ 5724 bcmPortPhyPauseCount = _SHR_PORT_PHY_PAUSE_COUNT /* pause types count */ 5725 } bcm_port_phy_pause_t; 5726 5727 /* antoneg mode supported */ 5728 typedef enum bcm_port_autoneg_mode_e { 5729 bcmPortAnModeCL37 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37, /* cl37 autoneg mode */ 5730 bcmPortAnModeCL37BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM, /* CL37 BAM mode */ 5731 bcmPortAnModeCL73 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73, /* CL73 an mode */ 5732 bcmPortAnModeCL73BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_BAM, /* CL73 BAM an mode */ 5733 bcmPortAnModeCL37_CL73 = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73, /* autoneg CL37 and CL73 */ 5734 bcmPortAnModeCL37_CL73BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_CL73_BAM, /* autoneg CL37 and CL73BAM */ 5735 bcmPortAnModeCL37BAM_CL73BAM = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL37_BAM_CL73_BAM, /* autoneg CL37BAM and CL73BAM */ 5736 bcmPortAnModeCL73MSA = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_CL73_MSA, /* autoneg cl73 msa mode */ 5737 bcmPortAnModeNone = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_NONE, /* this is only used by 5738 bcm_port_apeed_ability_local_get for 5739 forced speed */ 5740 bcmPortAnModeCount = _SHR_PORT_PHY_CONTROL_AUTONEG_MODE_COUNT /* an mode count */ 5741 } bcm_port_autoneg_mode_t; 5742 5743 /* FEC types supported */ 5744 typedef enum bcm_port_phy_fec_e { 5745 bcmPortPhyFecDefaultRequest = _SHR_PORT_PHY_FEC_DEFAULT_REQUEST, /* Set this value to request default 5746 fec_type when calling 5747 bcm_port_resource_default_get */ 5748 bcmPortPhyFecInvalid = _SHR_PORT_PHY_FEC_INVALID, /* invalid */ 5749 bcmPortPhyFecNone = _SHR_PORT_PHY_FEC_NONE, /* no fec */ 5750 bcmPortPhyFecBaseR = _SHR_PORT_PHY_FEC_BASE_R, /* CL74/Base-R. 64/66b KR FEC for fabric */ 5751 bcmPortPhyFecRsFec = _SHR_PORT_PHY_FEC_RS_FEC, /* CL91/RS-FEC */ 5752 bcmPortPhyFecRs544 = _SHR_PORT_PHY_FEC_RS_544, /* Rs544, using 1xN RS FEC architecture */ 5753 bcmPortPhyFecRs272 = _SHR_PORT_PHY_FEC_RS_272, /* Rs272, using 1xN RS FEC architecture */ 5754 bcmPortPhyFecRs206 = _SHR_PORT_PHY_FEC_RS_206, /* Rs206. 64/66b 5T RS FEC for fabric */ 5755 bcmPortPhyFecRs108 = _SHR_PORT_PHY_FEC_RS_108, /* Rs108. 64/66b 5T low latency RS FEC 5756 for fabric */ 5757 bcmPortPhyFecRs545 = _SHR_PORT_PHY_FEC_RS_545, /* Rs545. 64/66b 15T RS FEC for fabric */ 5758 bcmPortPhyFecRs304 = _SHR_PORT_PHY_FEC_RS_304, /* Rs304. 64/66b 15T low latency RS FEC 5759 for fabric */ 5760 bcmPortPhyFecRs544_2xN = _SHR_PORT_PHY_FEC_RS_544_2XN, /* Rs544, using 2xN RS FEC architecture */ 5761 bcmPortPhyFecRs272_2xN = _SHR_PORT_PHY_FEC_RS_272_2XN, /* Rs272, using 2xN RS FEC architecture */ 5762 bcmPortPhyFecCount = _SHR_PORT_PHY_FEC_COUNT /* Fec type count */ 5763 } bcm_port_phy_fec_t; 5764 5765 /* Port resource flags. */ 5766 #define BCM_PORT_RESOURCE_25G_USE_50G_CALENDAR 0x1 /* If set, 25G port will 5767 use 50G calendar. */ 5768 #define BCM_PORT_RESOURCE_SPEED_ONLY 0x2 /* If set, retain port 5769 configuration for 5770 flexport operations 5771 where port mapping, 5772 lanes and encap mode 5773 are unchanged. */ 5774 5775 /* speed_ability supported by a port */ 5776 typedef struct bcm_port_speed_ability_s { 5777 uint32 speed; /* port speed in mbps */ 5778 uint32 resolved_num_lanes; /* autoneg resolved speed num lane */ 5779 bcm_port_phy_fec_t fec_type; /* fec_type for port */ 5780 bcm_port_medium_t medium; /* medium type of a port */ 5781 bcm_port_phy_pause_t pause; /* pause */ 5782 bcm_port_phy_channel_t channel; /* short/long channel for a port */ 5783 bcm_port_autoneg_mode_t an_mode; /* autoneg mode */ 5784 } bcm_port_speed_ability_t; 5785 5786 #ifndef BCM_HIDE_DISPATCHABLE 5787 5788 /* Set or retrieve autonegotiation settings for a port. */ 5789 extern int bcm_port_autoneg_ability_advert_set( 5790 int unit, 5791 bcm_port_t port, 5792 int num_ability, 5793 bcm_port_speed_ability_t *abilities_array); 5794 5795 /* retrieve autonegotiation settings for a port. */ 5796 extern int bcm_port_autoneg_ability_advert_get( 5797 int unit, 5798 bcm_port_t port, 5799 int max_num_ability, 5800 bcm_port_speed_ability_t *abilities_array, 5801 int *actual_num_ability); 5802 5803 /* retrieve autonegotiation settings for a remote link partner */ 5804 extern int bcm_port_autoneg_ability_remote_get( 5805 int unit, 5806 bcm_port_t port, 5807 int max_num_ability, 5808 bcm_port_speed_ability_t *abilities_array, 5809 int *actual_num_ability); 5810 5811 /* 5812 * Retrieve the valid operating modes of a port including speed and FEC, 5813 * etc... 5814 */ 5815 extern int bcm_port_speed_ability_local_get( 5816 int unit, 5817 bcm_port_t port, 5818 int max_num_ability, 5819 bcm_port_speed_ability_t *abilities_array, 5820 int *actual_num_ability); 5821 5822 #endif /* BCM_HIDE_DISPATCHABLE */ 5823 5824 /* Port Resource Configuration */ 5825 typedef struct bcm_port_resource_s { 5826 uint32 flags; /* BCM_PORT_RESOURCE_XXX */ 5827 bcm_gport_t port; /* Local logical port number to connect to 5828 the given physical port */ 5829 int physical_port; /* Local physical port, -1 if the logical to 5830 physical mapping is to be deleted */ 5831 int speed; /* Initial speed after FlexPort operation */ 5832 int lanes; /* Number of PHY lanes for this physical 5833 port */ 5834 bcm_port_encap_t encap; /* Encapsulation mode for port */ 5835 bcm_port_phy_fec_t fec_type; /* fec_type for port */ 5836 int phy_lane_config; /* serdes pmd lane config for port */ 5837 int link_training; /* link training on or off */ 5838 int roe_compression; /* enable roe_compression */ 5839 } bcm_port_resource_t; 5840 5841 /* Initialize a Port Resource data structure. */ 5842 extern void bcm_port_resource_t_init( 5843 bcm_port_resource_t *resource); 5844 5845 #ifndef BCM_HIDE_DISPATCHABLE 5846 5847 /* Modify the Port Resources (e.g. speed, lanes, etc.) for a given port. */ 5848 extern int bcm_port_resource_set( 5849 int unit, 5850 bcm_gport_t port, 5851 bcm_port_resource_t *resource); 5852 5853 /* Get the Port Resource configuration. */ 5854 extern int bcm_port_resource_get( 5855 int unit, 5856 bcm_gport_t port, 5857 bcm_port_resource_t *resource); 5858 5859 #endif /* BCM_HIDE_DISPATCHABLE */ 5860 5861 #define BCM_PORT_RESOURCE_DEFAULT_REQUEST _SHR_PORT_RESOURCE_DEFAULT_REQUEST /* For 5862 bcm_port_resource_default_get 5863 - set this value to 5864 all struct members for 5865 which to get default 5866 value from the API. */ 5867 5868 #ifndef BCM_HIDE_DISPATCHABLE 5869 5870 /* 5871 * Get suggested default resource values prior to calling 5872 * bcm_port_resource_set. 5873 */ 5874 extern int bcm_port_resource_default_get( 5875 int unit, 5876 bcm_gport_t port, 5877 uint32 flags, 5878 bcm_port_resource_t *resource); 5879 5880 /* 5881 * Modify the Port Resources (e.g. speed, lanes, etc.) for a set of 5882 * ports. 5883 */ 5884 extern int bcm_port_resource_multi_set( 5885 int unit, 5886 int nport, 5887 bcm_port_resource_t *resource); 5888 5889 #endif /* BCM_HIDE_DISPATCHABLE */ 5890 5891 /* Port Resource traverse callback. */ 5892 typedef int (*bcm_port_resource_traverse_cb)( 5893 int unit, 5894 bcm_port_resource_t *resource, 5895 void *user_data); 5896 5897 #ifndef BCM_HIDE_DISPATCHABLE 5898 5899 /* 5900 * Iterates over the port resource configurations and calls user-provided 5901 * callback for every entry. 5902 */ 5903 extern int bcm_port_resource_traverse( 5904 int unit, 5905 bcm_port_resource_traverse_cb trav_fn, 5906 void *user_data); 5907 5908 /* Port bitmap of affected ports from the given resource. */ 5909 extern int bcm_port_resource_speed_config_validate( 5910 int unit, 5911 bcm_port_resource_t *resource, 5912 bcm_pbmp_t *pbmp); 5913 5914 /* Get the speed for a given port. */ 5915 extern int bcm_port_resource_speed_get( 5916 int unit, 5917 bcm_gport_t port, 5918 bcm_port_resource_t *resource); 5919 5920 /* Modify the speed for a given port. */ 5921 extern int bcm_port_resource_speed_set( 5922 int unit, 5923 bcm_gport_t port, 5924 bcm_port_resource_t *resource); 5925 5926 /* Modify the Port Speeds for a set of ports in a single Port Macro. */ 5927 extern int bcm_port_resource_speed_multi_set( 5928 int unit, 5929 int nport, 5930 bcm_port_resource_t *resource); 5931 5932 /* 5933 * Configure all ports that allow TDM traffic to ingress the device. TDM 5934 * traffic on any other port will be dropped. 5935 */ 5936 extern int bcm_port_ingress_tdm_failover_set( 5937 int unit, 5938 int flag, 5939 bcm_pbmp_t tdm_enable_pbmp); 5940 5941 /* 5942 * Retrieve all ports that allow TDM traffic to ingress the device. TDM 5943 * traffic on any other port will be dropped. 5944 */ 5945 extern int bcm_port_ingress_tdm_failover_get( 5946 int unit, 5947 int flag, 5948 bcm_pbmp_t *tdm_enable_pbmp); 5949 5950 /* Assign a priority group for the input priority. */ 5951 extern int bcm_port_priority_group_mapping_set( 5952 int unit, 5953 bcm_gport_t gport, 5954 int prio, 5955 int priority_group ); 5956 5957 /* Get the assigned priority group ID of the input priority. */ 5958 extern int bcm_port_priority_group_mapping_get( 5959 int unit, 5960 bcm_gport_t gport, 5961 int prio, 5962 int *priority_group); 5963 5964 #endif /* BCM_HIDE_DISPATCHABLE */ 5965 5966 /* Priority Group attributes */ 5967 typedef struct bcm_port_priority_group_config_s { 5968 int shared_pool_xoff_enable; /* enable/disable of triggering PFC 5969 messages of the Priority Group when 5970 exceeds egress shared pool xoff 5971 threshold */ 5972 int shared_pool_discard_enable; /* enable/disable of dropping packets of 5973 the Priority Group when exceeds 5974 egress shared pool discard threshold */ 5975 int pfc_transmit_enable; /* enable/disable of transmitting PFC 5976 message even in IBP state */ 5977 uint16 priority_enable_vector_mask; /* Priority enable vector mask that 5978 mapped to PriorityEnableVector field 5979 in the PFC message */ 5980 } bcm_port_priority_group_config_t; 5981 5982 #ifndef BCM_HIDE_DISPATCHABLE 5983 5984 /* Set the port priority group configuration. */ 5985 extern int bcm_port_priority_group_config_set( 5986 int unit, 5987 bcm_gport_t gport, 5988 int priority_group, 5989 bcm_port_priority_group_config_t *prigrp_config); 5990 5991 /* Get the port priority group configuration . */ 5992 extern int bcm_port_priority_group_config_get( 5993 int unit, 5994 bcm_gport_t gport, 5995 int priority_group, 5996 bcm_port_priority_group_config_t *prigrp_config); 5997 5998 #endif /* BCM_HIDE_DISPATCHABLE */ 5999 6000 /* Initialize a port priority group configuration structure. */ 6001 extern void bcm_port_priority_group_config_t_init( 6002 bcm_port_priority_group_config_t *prigrp_config); 6003 6004 /* Flags for port based packet redirection. */ 6005 #define BCM_PORT_REDIRECT_TRUNCATE 0x00000001 /* If set, redirected 6006 packets will be 6007 truncated. */ 6008 #define BCM_PORT_REDIRECT_SOURCE_USE_ORIGINAL_SOURCE 0x00000002 /* If set, the original 6009 source port is used as 6010 source of redirected 6011 packets. */ 6012 #define BCM_PORT_REDIRECT_SOURCE_USE_ORIGINAL_DESTINATION 0x00000004 /* If set, the original 6013 destination port is 6014 used as source of 6015 redirected packets. */ 6016 #define BCM_PORT_REDIRECT_DROPPED_PACKET 0x00000008 /* If set, only packets 6017 dropped will be 6018 rediredcted. */ 6019 #define BCM_PORT_REDIRECT_NOT_DROPPED_PACKET 0x00000010 /* If set, only packets 6020 not dropped will be 6021 rediredcted. */ 6022 #define BCM_PORT_REDIRECT_DESTINATION_PORT 0x00000020 /* If set, the 6023 destination for 6024 redirected ports will 6025 be set as a port. */ 6026 #define BCM_PORT_REDIRECT_DESTINATION_TRUNK 0x00000040 /* If set, the 6027 destination for 6028 redirected ports will 6029 be set as a trunk. */ 6030 #define BCM_PORT_REDIRECT_DESTINATION_MCAST 0x00000080 /* If set, the 6031 destination for 6032 redirected ports will 6033 be set as a L2 6034 Multicast group. */ 6035 6036 /* Flags used to select the buffer priority for redirected packets. */ 6037 #define BCM_PORT_REDIRECT_BUFFER_PRIORITY_LOW 0x00000001 /* If set, a low buffer 6038 priority will be used 6039 for redirected 6040 packets. */ 6041 #define BCM_PORT_REDIRECT_BUFFER_PRIORITY_MEDIUM 0x00000002 /* If set, a medium 6042 buffer priority will 6043 be used for redirected 6044 packets. */ 6045 #define BCM_PORT_REDIRECT_BUFFER_PRIORITY_HIGH 0x00000004 /* If set, a high buffer 6046 priority will be used 6047 for redirected 6048 packets. */ 6049 6050 /* New redirection packet color */ 6051 typedef enum bcm_port_redirect_color_e { 6052 bcmPortRedirectColorNone = 0, 6053 bcmPortRedirectColorGreen = 1, 6054 bcmPortRedirectColorYellow = 2, 6055 bcmPortRedirectColorRed = 3 6056 } bcm_port_redirect_color_t; 6057 6058 /* Preemption control */ 6059 typedef enum bcm_port_preempt_control_e { 6060 bcmPortPreemptControlPreemptionSupport = 0, /* Support preemption operation. */ 6061 bcmPortPreemptControlQueueBitmap = 1, /* Specify the preemptable queue in 6062 bitmap. */ 6063 bcmPortPreemptControlEnableTx = 2, /* Enable preemption in transmit 6064 direction. */ 6065 bcmPortPreemptControlVerifyEnable = 3, /* Enable preemption verify operation. */ 6066 bcmPortPreemptControlVerifyTime = 4, /* The wait time in ms between 6067 verification attempts. */ 6068 bcmPortPreemptControlVerifyAttempts = 5, /* The number of verification attempts. */ 6069 bcmPortPreemptControlNonFinalFragSizeTx = 6, /* The minimum size (in Bytes) of 6070 non-final fragment of a packet in 6071 transmit direction. */ 6072 bcmPortPreemptControlFinalFragSizeTx = 7, /* The minimum size (in Bytes) of final 6073 fragment of a packet in transmit 6074 direction. */ 6075 bcmPortPreemptControlNonFinalFragSizeRx = 8, /* The minimum size (in Bytes) of 6076 non-final fragment of a packet in 6077 receive direction. */ 6078 bcmPortPreemptControlFinalFragSizeRx = 9, /* The minimum size (in Bytes) of final 6079 fragment of a packet in receive 6080 direction. */ 6081 bcmPortPreemptControlHoldReqCntMode = 10, /* The MMU preemption request count mode 6082 for snmpBcmMacMergeHoldCount */ 6083 bcmPortPreemptControlCount = 11 /* always the last one */ 6084 } bcm_port_preempt_control_t; 6085 6086 /* Preemption status */ 6087 typedef enum bcm_port_preempt_status_e { 6088 bcmPortPreemptStatusTx = 0, /* Preemption status in the transmit 6089 direction. */ 6090 bcmPortPreemptStatusVerify = 1 /* Preemption verify operation status . */ 6091 } bcm_port_preempt_status_t; 6092 6093 /* Preemption TX status */ 6094 typedef enum bcm_port_preempt_status_tx_e { 6095 bcmPortPreemptStatusTxInactive = 0, /* Verify is enabled but its status is 6096 either failed or not initiated. Or 6097 Preemption is not enabled. */ 6098 bcmPortPreemptStatusTxVerifying = 1, /* Preemption is enabled and proceeding 6099 the verify operation. */ 6100 bcmPortPreemptStatusTxActive = 2 /* Preemption is activated. */ 6101 } bcm_port_preempt_status_tx_t; 6102 6103 /* Preemption Verify status */ 6104 typedef enum bcm_port_preempt_status_verify_e { 6105 bcmPortPreemptStatusVerifyDisabled = 0, /* Verify operation is not enabled. */ 6106 bcmPortPreemptStatusVerifyInitial = 1, /* Verify operation is enabled but the 6107 not started yet. */ 6108 bcmPortPreemptStatusVerifyInProgress = 2, /* Verify operation is in progress. */ 6109 bcmPortPreemptStatusVerifySucceeded = 3, /* Verify operation is succeeded. */ 6110 bcmPortPreemptStatusVerifyFailed = 4 /* Verify operation is failed. */ 6111 } bcm_port_preempt_status_verify_t; 6112 6113 /* Port redirection attributes */ 6114 typedef struct bcm_port_redirect_config_s { 6115 int flags; /* Flags to pass with configuration data */ 6116 int strength; /* Strength of the entry */ 6117 int buffer_priority; /* Buffering priority of the redirected 6118 packet */ 6119 int destination; /* Destination of the redirected packets */ 6120 int priority; /* Priority to be assigned for 6121 redirected packets */ 6122 bcm_port_redirect_color_t color; /* Color to be assigned to redirected 6123 packets */ 6124 } bcm_port_redirect_config_t; 6125 6126 /* Initialize a port redirection structure. */ 6127 extern void bcm_port_redirect_config_t_init( 6128 bcm_port_redirect_config_t *redirect_config); 6129 6130 #ifndef BCM_HIDE_DISPATCHABLE 6131 6132 /* Set the port redirection configuration. */ 6133 extern int bcm_port_redirect_config_set( 6134 int unit, 6135 bcm_gport_t port, 6136 bcm_port_redirect_config_t *redirect_config); 6137 6138 /* Get the port redirection configuration. */ 6139 extern int bcm_port_redirect_config_get( 6140 int unit, 6141 bcm_gport_t gport, 6142 bcm_port_redirect_config_t *redirect_config); 6143 6144 #endif /* BCM_HIDE_DISPATCHABLE */ 6145 6146 /* Port redirection attributes */ 6147 typedef struct bcm_port_nif_prio_s { 6148 int priority_level; /* NIF Priority level to set/get */ 6149 } bcm_port_nif_prio_t; 6150 6151 #ifndef BCM_HIDE_DISPATCHABLE 6152 6153 /* Set the NIF Priority between Ports. */ 6154 extern int bcm_port_nif_priority_set( 6155 int unit, 6156 bcm_gport_t local_port, 6157 uint32 flags, 6158 bcm_port_nif_prio_t *priority, 6159 bcm_pbmp_t *affected_ports); 6160 6161 /* Get the NIF Priority of a Port. */ 6162 extern int bcm_port_nif_priority_get( 6163 int unit, 6164 bcm_gport_t local_port, 6165 uint32 flags, 6166 bcm_port_nif_prio_t *priority, 6167 bcm_pbmp_t *affected_ports); 6168 6169 /* Set various configurations for Preemption. */ 6170 extern int bcm_port_preemption_control_set( 6171 int unit, 6172 bcm_gport_t gport, 6173 bcm_port_preempt_control_t type, 6174 uint32 arg); 6175 6176 /* Get various configurations for Preemption. */ 6177 extern int bcm_port_preemption_control_get( 6178 int unit, 6179 bcm_gport_t gport, 6180 bcm_port_preempt_control_t type, 6181 uint32 *arg); 6182 6183 /* Get the specified preemption status. */ 6184 extern int bcm_port_preemption_status_get( 6185 int unit, 6186 bcm_gport_t gport, 6187 bcm_port_preempt_status_t type, 6188 uint32 *status); 6189 6190 #endif /* BCM_HIDE_DISPATCHABLE */ 6191 6192 /* E2EFC modes */ 6193 typedef enum bcm_port_e2efc_mode_e { 6194 bcmPortE2efcModeTx = 0, /* E2EFC frame transmit mode */ 6195 bcmPortE2efcModeRx = 1, /* E2EFC frame receive mode */ 6196 bcmPortE2efcModeCount = 2 /* Must be last. Not a usable value */ 6197 } bcm_port_e2efc_mode_t; 6198 6199 /* Configuration of remote module */ 6200 typedef struct bcm_port_e2efc_remote_module_config_s { 6201 bcm_gport_t local_port; /* Local port for E2EFC message transaction, only 6202 for E2EFC TX */ 6203 int pkt_per_second; /* Frequency of sending E2EFC messages, only for 6204 E2EFC TX */ 6205 } bcm_port_e2efc_remote_module_config_t; 6206 6207 /* bcm_port_e2efc_remote_module_config_t_init */ 6208 extern void bcm_port_e2efc_remote_module_config_t_init( 6209 bcm_port_e2efc_remote_module_config_t *e2efc_rmod_cfg); 6210 6211 #ifndef BCM_HIDE_DISPATCHABLE 6212 6213 /* bcm_port_e2efc_remote_module_enable_set */ 6214 extern int bcm_port_e2efc_remote_module_enable_set( 6215 int unit, 6216 bcm_module_t remote_module, 6217 bcm_port_e2efc_mode_t mode, 6218 int enable, 6219 bcm_port_e2efc_remote_module_config_t *e2efc_rmod_cfg); 6220 6221 /* bcm_port_e2efc_remote_module_enable_set */ 6222 extern int bcm_port_e2efc_remote_module_enable_get( 6223 int unit, 6224 bcm_module_t remote_module, 6225 bcm_port_e2efc_mode_t mode, 6226 int *enable, 6227 bcm_port_e2efc_remote_module_config_t *e2efc_rmod_cfg); 6228 6229 #endif /* BCM_HIDE_DISPATCHABLE */ 6230 6231 /* bcm_port_e2efc_remote_module_traverse_cb */ 6232 typedef int (*bcm_port_e2efc_remote_module_traverse_cb)( 6233 int unit, 6234 bcm_module_t remote_module, 6235 bcm_port_e2efc_mode_t mode, 6236 void *user_data); 6237 6238 #ifndef BCM_HIDE_DISPATCHABLE 6239 6240 /* bcm_port_e2efc_remote_module_traverse */ 6241 extern int bcm_port_e2efc_remote_module_traverse( 6242 int unit, 6243 bcm_port_e2efc_remote_module_traverse_cb cb, 6244 void *user_data); 6245 6246 #endif /* BCM_HIDE_DISPATCHABLE */ 6247 6248 /* 6249 * Resource type would be used to configure set, reset and discard 6250 * thresholds 6251 */ 6252 typedef enum bcm_port_e2efc_resource_type_e { 6253 BCM_E2EFC_RESOURCE_TYPE_NONE = 0, /* Resource type not needed */ 6254 BCM_E2EFC_RESOURCE_TYPE_INT_MEM = 1, /* Resource type internal Memory 6255 configured in number of bytes */ 6256 BCM_E2EFC_RESOURCE_TYPE_QEN = 2, /* Resource type queue entries 6257 configured in number of packets */ 6258 BCM_E2EFC_RESOURCE_TYPE_RQE = 3, /* Resource type replication queue 6259 engine entries configured in number 6260 of packets */ 6261 BCM_E2EFC_RESOURCE_TYPE_EXT_MEM = 4, /* Resource type external Memory 6262 configured in number of bytes */ 6263 BCM_E2EFC_RESOURCE_TYPE_EMA = 5, /* Resource type external Memory access 6264 configured in number of bytes */ 6265 BCM_E2EFC_RESOURCE_TYPE_COUNT = 6 /* Number of E2EFC Resource type */ 6266 } bcm_port_e2efc_resource_type_t; 6267 6268 /* Configuration for remote port */ 6269 typedef struct bcm_port_e2efc_remote_port_config_s { 6270 bcm_module_t remote_module; /* Remote module id that E2EFC applied */ 6271 bcm_port_t remote_port; /* Remote port id to be configured */ 6272 int xoff_threshold_bytes; /* Assert backpressure when number of 6273 buffers used is at or above this 6274 threshold in bytes */ 6275 int xoff_threshold_packets; /* Assert backpressure when number of 6276 buffers used is at or above this 6277 threshold in packets */ 6278 int xon_threshold_bytes; /* Remove backpressure when number of 6279 buffers used drop below this 6280 threshold in bytes */ 6281 int xon_threshold_packets; /* Remove backpressure when number of 6282 buffers used drop below this 6283 threshold in packets */ 6284 int drop_threshold_bytes; /* Drop packets when number of buffers 6285 used hit this threshold in bytes */ 6286 int drop_threshold_packets; /* Drop packets when number of buffers 6287 used hit this threshold in packets */ 6288 bcm_port_e2efc_resource_type_t e2efc_resource_type; /* Type of resource being 6289 configured.Internal Memory, External 6290 Memory and EMA shall be configured in 6291 terms of bytes and Queue entry and 6292 RQE shall be configured in terms of 6293 packets */ 6294 } bcm_port_e2efc_remote_port_config_t; 6295 6296 /* bcm_port_e2efc_remote_port_config_t_init */ 6297 extern void bcm_port_e2efc_remote_port_config_t_init( 6298 bcm_port_e2efc_remote_port_config_t *e2efc_rport_cfg); 6299 6300 #ifndef BCM_HIDE_DISPATCHABLE 6301 6302 /* bcm_port_e2efc_remote_port_add */ 6303 extern int bcm_port_e2efc_remote_port_add( 6304 int unit, 6305 bcm_port_e2efc_remote_port_config_t *e2efc_rport_cfg, 6306 int *rport_handle_id); 6307 6308 /* bcm_port_e2efc_remote_port_set */ 6309 extern int bcm_port_e2efc_remote_port_set( 6310 int unit, 6311 int rport_handle_id, 6312 bcm_port_e2efc_remote_port_config_t *e2efc_rport_cfg); 6313 6314 /* bcm_port_e2efc_remote_port_get */ 6315 extern int bcm_port_e2efc_remote_port_get( 6316 int unit, 6317 int rport_handle_id, 6318 bcm_port_e2efc_remote_port_config_t *e2efc_rport_cfg); 6319 6320 /* bcm_port_e2efc_remote_port_delete */ 6321 extern int bcm_port_e2efc_remote_port_delete( 6322 int unit, 6323 int rport_handle_id); 6324 6325 #endif /* BCM_HIDE_DISPATCHABLE */ 6326 6327 /* bcm_port_e2efc_remote_port_traverse_cb */ 6328 typedef int (*bcm_port_e2efc_remote_port_traverse_cb)( 6329 int unit, 6330 int rport_handle_id, 6331 void *user_data); 6332 6333 #ifndef BCM_HIDE_DISPATCHABLE 6334 6335 /* bcm_port_e2efc_remote_port_traverse */ 6336 extern int bcm_port_e2efc_remote_port_traverse( 6337 int unit, 6338 bcm_port_e2efc_remote_port_traverse_cb cb, 6339 void *user_data); 6340 6341 #endif /* BCM_HIDE_DISPATCHABLE */ 6342 6343 /* bcm_port_timesync_tx_info */ 6344 typedef struct bcm_port_timesync_tx_info_s { 6345 uint64 timestamp; /* transmit timestamp of ptp packet */ 6346 uint32 sequence_id; /* sequence id of transmitted ptp packet */ 6347 uint32 sub_ns; /* timestamp sub-nanosecond */ 6348 } bcm_port_timesync_tx_info_t; 6349 6350 #ifndef BCM_HIDE_DISPATCHABLE 6351 6352 /* bcm_port_timesync_tx_info_get */ 6353 extern int bcm_port_timesync_tx_info_get( 6354 int unit, 6355 bcm_port_t port, 6356 bcm_port_timesync_tx_info_t *tx_info); 6357 6358 #endif /* BCM_HIDE_DISPATCHABLE */ 6359 6360 /* Timestamp adjust */ 6361 typedef _shr_port_timestamp_adjust_t bcm_port_timestamp_adjust_t; 6362 6363 #ifndef BCM_HIDE_DISPATCHABLE 6364 6365 /* bcm_port_timestamp_adjust_get */ 6366 extern int bcm_port_timestamp_adjust_get( 6367 int unit, 6368 bcm_port_t port, 6369 bcm_port_timestamp_adjust_t *ts_adjust); 6370 6371 /* bcm_port_timestamp_adjust_set */ 6372 extern int bcm_port_timestamp_adjust_set( 6373 int unit, 6374 bcm_port_t port, 6375 bcm_port_timestamp_adjust_t *ts_adjust); 6376 6377 #endif /* BCM_HIDE_DISPATCHABLE */ 6378 6379 /* Port max priority groups. */ 6380 #define BCM_PORT_MAX_NOF_PRIORITY_GROUPS 3 6381 6382 /* Port priority */ 6383 #define BCM_PORT_F_PRIORITY_0 1<<1 /* User defined priority 0. */ 6384 #define BCM_PORT_F_PRIORITY_1 1<<2 /* User defined priority 1. */ 6385 #define BCM_PORT_F_PRIORITY_2 1<<3 /* User defined priority 2. */ 6386 #define BCM_PORT_F_PRIORITY_3 1<<4 /* User defined priority 3. */ 6387 #define BCM_PORT_F_PRIORITY_TDM 1<<16 /* User defined priority TDM */ 6388 6389 /* Priority Scheduler. */ 6390 typedef enum bcm_port_nif_scheduler_e { 6391 bcmPortNifSchedulerLow = 0, /* Low Priority Scheduler */ 6392 bcmPortNifSchedulerHigh = 1, /* High Priority Scheduler */ 6393 bcmPortNifSchedulerTDM = 2 /* TDM Priority Scheduler */ 6394 } bcm_port_nif_scheduler_t; 6395 6396 /* bcm_port_prio_group_config_t */ 6397 typedef struct bcm_port_prio_group_config_s { 6398 uint32 source_priority; /* see BCM_PORT_F_PRIORITY_* */ 6399 bcm_port_nif_scheduler_t sch_priority; /* see bcm_port_nif_scheduler_t */ 6400 int num_of_entries; /* Indicate how many memory entries each 6401 priority group takes. Set to -1 for 6402 equal division between all 6403 priorities; otherwise indicate number 6404 of entries up to 128 per lane */ 6405 } bcm_port_prio_group_config_t; 6406 6407 /* bcm_port_prio_config_t */ 6408 typedef struct bcm_port_prio_config_s { 6409 int nof_priority_groups; /* see BCM_PORT_F_PRIORITY */ 6410 bcm_port_prio_group_config_t priority_groups[BCM_PORT_MAX_NOF_PRIORITY_GROUPS]; 6411 } bcm_port_prio_config_t; 6412 6413 #ifndef BCM_HIDE_DISPATCHABLE 6414 6415 /* 6416 * Configure priority groups for the port. Priority group is meant to 6417 * connect one or more user priorities (see BCM_PORT_F_PRIORITY_*) to a 6418 * scheduler priority (High, Low, TDM) Each priority group acts as a 6419 * logical FIFO. The size of the FIFO can be dynamically specified, in 6420 * entries. 6421 */ 6422 extern int bcm_port_priority_config_set( 6423 int unit, 6424 bcm_port_t port, 6425 bcm_port_prio_config_t *port_priority_config); 6426 6427 /* Retrieve the port priority group configuration. */ 6428 extern int bcm_port_priority_config_get( 6429 int unit, 6430 bcm_port_t port, 6431 bcm_port_prio_config_t *priority_config); 6432 6433 #endif /* BCM_HIDE_DISPATCHABLE */ 6434 6435 #define BCM_PORT_LANE_TO_SERDES_NOT_MAPPED -1 /* A lane is unmapped for 6436 both Tx and Rx. 6437 Unmapped lanes can't 6438 be assigned to a port. */ 6439 6440 /* 6441 * This struct holds serdes information (rx and tx) related to a specific 6442 * lane. 6443 */ 6444 typedef struct bcm_port_lane_to_serdes_map_s { 6445 int serdes_rx_id; 6446 int serdes_tx_id; 6447 } bcm_port_lane_to_serdes_map_t; 6448 6449 #ifndef BCM_HIDE_DISPATCHABLE 6450 6451 /* 6452 * Map lanes to serdeses. The API receive all lanes configuration at 6453 * once. Location in the array represent the lane number (e.g. 6454 * serdes_map[x] holds the information for lane=x). 6455 */ 6456 extern int bcm_port_lane_to_serdes_map_set( 6457 int unit, 6458 int flags, 6459 int map_size, 6460 bcm_port_lane_to_serdes_map_t *serdes_map); 6461 6462 /* 6463 * Map lanes to serdeses. The API receive all lanes configuration at 6464 * once. Location in the array represent the lane number (e.g. 6465 * serdes_map[x] holds the information for lane=x). 6466 */ 6467 extern int bcm_port_lane_to_serdes_map_get( 6468 int unit, 6469 int flags, 6470 int map_size, 6471 bcm_port_lane_to_serdes_map_t *serdes_map); 6472 6473 #endif /* BCM_HIDE_DISPATCHABLE */ 6474 6475 #define BCM_PORT_LANE_TO_SERDES_FABRIC_SIDE 0x1 /* Update lane to serdes 6476 mapping on fabric 6477 side. */ 6478 6479 #ifndef BCM_HIDE_DISPATCHABLE 6480 6481 /* 6482 * This API is used to configure the order of the ILKN lanes. Each index 6483 * in lanes[] array stands for ILKN lane ID. The values of lanes[] array 6484 * is the NIF/Fabric lanes mapped to ILKN logical lane. 6485 */ 6486 extern int bcm_port_ilkn_lane_map_set( 6487 int unit, 6488 int flags, 6489 bcm_port_t port, 6490 int num_of_lanes, 6491 int *lanes); 6492 6493 /* 6494 * Get the order of the ILKN lanes for ILKN ports. Each index in lanes[] 6495 * array stands for ILKN lane ID. The values of lanes[] array is the 6496 * NIF/Fabric lanes mapped to ILKN logical lane. 6497 */ 6498 extern int bcm_port_ilkn_lane_map_get( 6499 int unit, 6500 int flags, 6501 bcm_port_t port, 6502 int num_of_lanes, 6503 int *lanes); 6504 6505 #endif /* BCM_HIDE_DISPATCHABLE */ 6506 6507 /* Per port and LIF flooding destination information. */ 6508 typedef struct bcm_port_flood_group_s { 6509 bcm_gport_t unknown_unicast_group; /* Destination for unknown unicast 6510 packets. */ 6511 bcm_gport_t unknown_multicast_group; /* Destination for unknown multicast 6512 packets. */ 6513 bcm_gport_t broadcast_group; /* Destination for broadcast packets. */ 6514 } bcm_port_flood_group_t; 6515 6516 /* Initialize the port flooding group structure */ 6517 extern void bcm_port_flood_group_t_init( 6518 bcm_port_flood_group_t *flood_groups); 6519 6520 #ifndef BCM_HIDE_DISPATCHABLE 6521 6522 /* Set the flooding groups for port or InLIF. */ 6523 extern int bcm_port_flood_group_set( 6524 int unit, 6525 bcm_gport_t port, 6526 uint32 flags, 6527 bcm_port_flood_group_t *flood_groups); 6528 6529 /* Get the flood groups for port or InLiF. */ 6530 extern int bcm_port_flood_group_get( 6531 int unit, 6532 bcm_gport_t port, 6533 uint32 flags, 6534 bcm_port_flood_group_t *flood_groups); 6535 6536 #endif /* BCM_HIDE_DISPATCHABLE */ 6537 6538 typedef enum bcm_port_phy_tx_tap_mode_e { 6539 bcmPortPhyTxTapMode3Tap = _SHR_PORT_PHY_TX_TAP_MODE_3_TAP, 6540 bcmPortPhyTxTapMode6Tap = _SHR_PORT_PHY_TX_TAP_MODE_6_TAP 6541 } bcm_port_phy_tx_tap_mode_t; 6542 6543 typedef enum bcm_port_phy_signalling_mode_e { 6544 bcmPortPhySignallingModeNRZ = _SHR_PORT_PHY_SIGNALLING_MODE_NRZ, 6545 bcmPortPhySignallingModePAM4 = _SHR_PORT_PHY_SIGNALLING_MODE_PAM4 6546 } bcm_port_phy_signalling_mode_t; 6547 6548 typedef struct bcm_port_phy_tx_s { 6549 int pre2; 6550 int pre; 6551 int main; 6552 int post; 6553 int post2; 6554 int post3; 6555 bcm_port_phy_tx_tap_mode_t tx_tap_mode; 6556 bcm_port_phy_signalling_mode_t signalling_mode; 6557 } bcm_port_phy_tx_t; 6558 6559 /* Initialize the bcm_port_phy_tx_t structure. */ 6560 extern void bcm_port_phy_tx_t_init( 6561 bcm_port_phy_tx_t *tx); 6562 6563 #ifndef BCM_HIDE_DISPATCHABLE 6564 6565 /* Modify TX FIR parameters for a given port */ 6566 extern int bcm_port_phy_tx_set( 6567 int unit, 6568 bcm_port_t port, 6569 bcm_port_phy_tx_t *tx); 6570 6571 /* Get TX FIR parameters for a given port */ 6572 extern int bcm_port_phy_tx_get( 6573 int unit, 6574 bcm_port_t port, 6575 bcm_port_phy_tx_t *tx); 6576 6577 #endif /* BCM_HIDE_DISPATCHABLE */ 6578 6579 typedef struct bcm_port_rlm_config_s { 6580 int is_initiator; 6581 uint32 active_lane_bit_map; /* input only valid for initator */ 6582 } bcm_port_rlm_config_t; 6583 6584 /* Initialize the bcm_port_rlm_config_t structure. */ 6585 extern void bcm_port_rlm_config_t_init( 6586 bcm_port_rlm_config_t *rlm_config); 6587 6588 #ifndef BCM_HIDE_DISPATCHABLE 6589 6590 /* Modify RLM config and enable/disable for a given port */ 6591 extern int bcm_port_rlm_config_set( 6592 int unit, 6593 bcm_port_t port, 6594 bcm_port_rlm_config_t *rlm_config, 6595 int enable); 6596 6597 /* Get RLM config for a given port */ 6598 extern int bcm_port_rlm_config_get( 6599 int unit, 6600 bcm_port_t port, 6601 bcm_port_rlm_config_t *rlm_config, 6602 int *enable); 6603 6604 #endif /* BCM_HIDE_DISPATCHABLE */ 6605 6606 typedef enum bcm_port_rlm_status_e { 6607 bcmPortRlmDisabled = _SHR_PORT_RLM_DISABLED, 6608 bcmPortRlmBusy = _SHR_PORT_RLM_BUSY, 6609 bcmPortRlmDone = _SHR_PORT_RLM_DONE, 6610 bcmPortRlmFailed = _SHR_PORT_RLM_FAILED, 6611 bcmPortRlmCount = _SHR_PORT_RLM_COUNT 6612 } bcm_port_rlm_status_t; 6613 6614 #ifndef BCM_HIDE_DISPATCHABLE 6615 6616 /* Get RLM status for a given port */ 6617 extern int bcm_port_rlm_status_get( 6618 int unit, 6619 bcm_port_t port, 6620 bcm_port_rlm_status_t *rlm_status); 6621 6622 #endif /* BCM_HIDE_DISPATCHABLE */ 6623 6624 #endif /* __BCM_PORT_H__ */