cpri.h (106089B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 7 * 8 * DO NOT EDIT THIS FILE! 9 * This file is auto-generated. 10 * Edits to this file will be lost when it is regenerated. 11 */ 12 13 #ifndef __BCM_CPRI_H__ 14 #define __BCM_CPRI_H__ 15 16 #include <bcm/types.h> 17 #include <shared/cpri.h> 18 19 #ifndef BCM_HIDE_DISPATCHABLE 20 21 /* Initialize the CPRI subsystem. */ 22 extern int bcm_cpri_init( 23 int unit); 24 25 /* De-initialize the CPRI subsystem. */ 26 extern int bcm_cpri_detach( 27 int unit); 28 29 #endif /* BCM_HIDE_DISPATCHABLE */ 30 31 /* CPRI Port types */ 32 typedef enum bcm_cpri_port_type_e { 33 bcmCpriPortTypeCpri = 0, /* CPRI port */ 34 bcmCpriPortTypeRsvd4 = 1 /* RSVD4 port */ 35 } bcm_cpri_port_type_t; 36 37 /* CPRI Port speeds */ 38 typedef enum bcm_cpri_port_speed_e { 39 bcmCpriPortSpeed1228p8 = 0, /* 1228.8Mbps */ 40 bcmCpriPortSpeed2457p6 = 1, /* 2457.6Mbps */ 41 bcmCpriPortSpeed3072p0 = 2, /* 3072.0Mbps */ 42 bcmCpriPortSpeed4915p2 = 3, /* 4915.2Mbps */ 43 bcmCpriPortSpeed6144p0 = 4, /* 6144.0Mbps */ 44 bcmCpriPortSpeed9830p4 = 5, /* 9830.4Mbps */ 45 bcmCpriPortSpeed10137p6 = 6, /* 10137.6Mbps */ 46 bcmCpriPortSpeed12165p12 = 7, /* 12165.12Mbps */ 47 bcmCpriPortSpeed24330p24 = 8 /* 24330.24G */ 48 } bcm_cpri_port_speed_t; 49 50 #ifndef BCM_HIDE_DISPATCHABLE 51 52 /* Configures the Rx speed of the specified CPRI port. */ 53 extern int bcm_cpri_port_rx_speed_set( 54 int unit, 55 bcm_gport_t port, 56 bcm_cpri_port_type_t port_type, 57 bcm_cpri_port_speed_t speed); 58 59 /* Retrieves the Rx speed of the specified CPRI port. */ 60 extern int bcm_cpri_port_rx_speed_get( 61 int unit, 62 bcm_gport_t port, 63 bcm_cpri_port_type_t *port_type, 64 bcm_cpri_port_speed_t *speed); 65 66 /* Configures the Tx speed of the specified CPRI port. */ 67 extern int bcm_cpri_port_tx_speed_set( 68 int unit, 69 bcm_gport_t port, 70 bcm_cpri_port_type_t port_type, 71 bcm_cpri_port_speed_t speed); 72 73 /* Retrieves the Tx speed of the specified CPRI port. */ 74 extern int bcm_cpri_port_tx_speed_get( 75 int unit, 76 bcm_gport_t port, 77 bcm_cpri_port_type_t *port_type, 78 bcm_cpri_port_speed_t *speed); 79 80 #endif /* BCM_HIDE_DISPATCHABLE */ 81 82 /* bcm_cpri_frame_sync_mode_t */ 83 typedef _shr_cpri_frame_sync_mode_t bcm_cpri_frame_sync_mode_t; 84 85 /* CPRI Frame Sync Modes */ 86 #define BCM_CPRI_FRAME_SYNC_MODE_HYPER _shrCpriFrameSyncModeHyper 87 #define BCM_CPRI_FRAME_SYNC_MODE_RADIO _shrCpriFrameSyncModeRadio 88 #define BCM_CPRI_FRAME_SYNC_MODE_BASIC _shrCpriFrameSyncModeBasic 89 90 /* CPRI Frame truncation modes */ 91 typedef enum bcm_cpri_frame_trunc_mode_e { 92 bcmCpriFrameTruncMode15_to_16 = 0, /* Truncation 15 to 16 bits */ 93 bcmCpriFrameTruncModeAdd_0 = 1, /* Truncation Add 0. */ 94 bcmCpriFrameTruncMode16_to_15 = 2, /* Truncation of 16 to 15 bits */ 95 bcmCpriFrameTruncModeAdd_1 = 3 /* Truncation of adding 1. */ 96 } bcm_cpri_frame_trunc_mode_t; 97 98 /* CPRI Frame compression modes */ 99 typedef enum bcm_cpri_frame_compress_mode_e { 100 bcmCpriFrameCompressModeCompress = 0, /* Compress Mode */ 101 bcmCpriFrameCompressModeDecompress = 1, /* Decompress Mode */ 102 bcmCpriFrameCompressModeNone = 2 /* No Compression */ 103 } bcm_cpri_frame_compress_mode_t; 104 105 /* CPRI Framer stages */ 106 typedef enum bcm_cpri_stage_e { 107 bcmCpriStageRxParser = 0, /* Rx Parser */ 108 bcmCpriStageTxAssembler = 1 /* Tx Assembler */ 109 } bcm_cpri_stage_t; 110 111 /* CPRI Axc Framer Configuration */ 112 typedef struct bcm_cpri_axc_frame_info_s { 113 int axc_id; /* AxC ID - output for get_all only */ 114 int start_bit; /* Start bit position of basic frame */ 115 int num_bits; /* Number of bits in AxC */ 116 int map_method; /* Mapping method 0 - Method 1, 1 - 117 Method 2 (not Supported) 2 - Method 3 */ 118 int stuffing_count; /* Nst for method#1 bits */ 119 int K; /* Container block count */ 120 int sample_size_M; /* Sample size */ 121 int Nv; /* Nv value for method 3 */ 122 int Na; /* Na value for method 3 */ 123 int Nc; /* Numnber of containers in a basic 124 frame - method 3 only */ 125 bcm_cpri_frame_sync_mode_t frame_sync_mode; /* CPRI Frame synchronization modes */ 126 int basic_frame_offset; /* Frame number offset of basic frame */ 127 int radio_frame_offset; /* Frame number offset of radio frame */ 128 int hyper_frame_offset; /* Frame number offset of hyper frame */ 129 int num_samples_per_roe_pkt; /* Number of samples in RoE payload */ 130 int truncation_enable; /* True/False */ 131 bcm_cpri_frame_trunc_mode_t truncation_mode; /* */ 132 bcm_cpri_frame_compress_mode_t compress_mode; /* */ 133 uint8 priority; /* Priority 0-3 */ 134 uint16 rx_queue_size; /* Queue size in bytes */ 135 uint16 cycle_size; /* Only for Tx, Jitter buffer size in 136 number of packets. */ 137 } bcm_cpri_axc_frame_info_t; 138 139 #ifndef BCM_HIDE_DISPATCHABLE 140 141 /* 142 * Sets up the AxC (method 1) or AxC group (method 3) on a CPRI port in 143 * the Rx datapath. 144 */ 145 extern int bcm_cpri_port_rx_axc_frame_add( 146 int unit, 147 bcm_gport_t port, 148 int axc_id, 149 bcm_cpri_axc_frame_info_t *axc_info); 150 151 /* 152 * Retrieves the AxC (method 1) or AxC group (method 3) in the Rx datapth 153 * on a CPRI port. 154 */ 155 extern int bcm_cpri_port_rx_axc_frame_get( 156 int unit, 157 bcm_gport_t port, 158 int axc_id, 159 bcm_cpri_axc_frame_info_t *axc_info); 160 161 /* 162 * Retrieves the configured list of AxC (method 1) or AxC group (method 163 * 3) on a CPRI port. 164 */ 165 extern int bcm_cpri_port_rx_axc_frame_get_all( 166 int unit, 167 bcm_gport_t port, 168 int max_count, 169 bcm_cpri_axc_frame_info_t *axc_info_list, 170 int *axc_count); 171 172 /* 173 * Remove the specified AxC (method 1) or AxC group (method 3) on a CPRI 174 * port. 175 */ 176 extern int bcm_cpri_port_rx_axc_frame_delete( 177 int unit, 178 bcm_gport_t port, 179 int axc_id); 180 181 /* 182 * Sets up the AxC (method 1) or AxC group (method 3) in the Tx datapath 183 * on a CPRI port. 184 */ 185 extern int bcm_cpri_port_tx_axc_frame_add( 186 int unit, 187 bcm_gport_t port, 188 int axc_id, 189 bcm_cpri_axc_frame_info_t *axc_info); 190 191 /* 192 * Retrieves the AxC (method 1) or AxC group (method 3) in the Tx datapth 193 * on a CPRI port. 194 */ 195 extern int bcm_cpri_port_tx_axc_frame_get( 196 int unit, 197 bcm_gport_t port, 198 int axc_id, 199 bcm_cpri_axc_frame_info_t *axc_info); 200 201 /* 202 * Retrieves the configured list of AxC (method 1) or AxC group (method 203 * 3) in the Tx datapath on a CPRI port. 204 */ 205 extern int bcm_cpri_port_tx_axc_frame_get_all( 206 int unit, 207 bcm_gport_t port, 208 int max_count, 209 bcm_cpri_axc_frame_info_t *axc_info_list, 210 int *axc_count); 211 212 /* 213 * Remove the specified AxC (method 1) or AxC group (method 3) on a CPRI 214 * port. 215 */ 216 extern int bcm_cpri_port_tx_axc_frame_delete( 217 int unit, 218 bcm_gport_t port, 219 int axc_id); 220 221 #endif /* BCM_HIDE_DISPATCHABLE */ 222 223 /* CPRI Encap flags */ 224 #define BCM_CPRI_ENCAP_USE_TAG_ID_FOR_VLAN 0x1 225 #define BCM_CPRI_ENCAP_USE_TAG_ID_FOR_FLOWID 0x2 226 #define BCM_CPRI_ENCAP_USE_OPCODE 0x4 227 228 /* CPRI VLAN Types */ 229 typedef enum bcm_cpri_vlan_type_e { 230 bcmCpriVlanTypeNone = 0, /* No VLAN */ 231 bcmCpriVlanTypeSingle = 1, /* Single Tagged VLAN */ 232 bcmCpriVlanTypeQinQ = 2, /* VLAN Q in Q */ 233 bcmCpriVlanTypeSingleTable1 = 3 /* Single Tagged VLAN using table 1 */ 234 } bcm_cpri_vlan_type_t; 235 236 /* CPRI RoE Subtypes */ 237 typedef enum bcm_cpri_roe_subtype_e { 238 bcmCpriRoESubtypeControl = 0, /* RoE subtype Control */ 239 bcmCpriRoESubtypeResv = 1, /* RoE subtype Reserve */ 240 bcmCpriRoESubtypeAgnostic = 2, /* RoE subtype Agnostic */ 241 bcmCpriRoESubtypeCpriData = 3, /* Roe subtype Data */ 242 bcmCpriRoESubtypeNative = 4, /* RoE Subtype Native */ 243 bcmCpriRoESubtypeSlowCM = 5 /* RoE subtype Slow C&M */ 244 } bcm_cpri_roe_subtype_t; 245 246 /* CPRI RoE Opcodes */ 247 typedef enum bcm_cpri_roe_opcode_e { 248 bcmCpriRoEOpcodeOamTlv = 0, /* OAM TLV */ 249 bcmCpriRoEOpcodeCtrlAxC = 1, /* Control AxC */ 250 bcmCpriRoEOpcodeVSD = 2, /* VSD */ 251 bcmCpriRoEOpcodeTiming = 3 /* Timing */ 252 } bcm_cpri_roe_opcode_t; 253 254 /* CPRI Header Encapsulation types */ 255 typedef enum bcm_cpri_hdr_encap_type_e { 256 bcmCpriHdrEncapTypeRoe = 0, /* ROE encapsulation type */ 257 bcmCpriHdrEncapTypeNone = 1, /* no ROE encapsulation */ 258 bcmCpriHdrEncapTypeCount = 2 /* should be last */ 259 } bcm_cpri_hdr_encap_type_t; 260 261 /* bcm_cpri_roe_frame_format_t */ 262 typedef _shr_cpri_roe_frame_format_t bcm_cpri_roe_frame_format_t; 263 264 /* CPRI RoE Frame Format. */ 265 #define BCM_CPRI_ROE_FRAME_FORMAT_IEEE1914 _shrCpriRoeFrameFormatIEEE1914 /* Selection of IEEE1914 266 frame format */ 267 #define BCM_CPRI_ROE_FRAME_FORMAT_RSVD3 _shrCpriRoeFrameFormatRsvd3 /* Selection of RSVD3 268 frame format */ 269 #define BCM_CPRI_ROE_FRAME_FORMAT_ECPRI8 _shrCpriRoeFrameFormatEcpri8 /* Selection of 8 bytes 270 eCPRI frame format */ 271 #define BCM_CPRI_ROE_FRAME_FORMAT_ECPRI12 _shrCpriRoeFrameFormatEcpri12 /* Selection of 12 bytes 272 eCPRI frame format */ 273 274 /* CPRI Encap Information */ 275 typedef struct bcm_cpri_encap_info_s { 276 uint32 flags; /* CPRI Encap Info flags */ 277 uint16 flow_id; /* Flow ID */ 278 bcm_cpri_roe_subtype_t subtype; /* RoE subtype */ 279 bcm_cpri_hdr_encap_type_t hdr_type; /* CPRI header encapsulation type */ 280 int roe_ordering_info_index; /* RoE ordering Info index */ 281 int macda_index; /* Index to MAC DA address */ 282 int macsa_index; /* Index to MAC SA address */ 283 bcm_cpri_vlan_type_t vlan_type; /* CPRI Vlan type */ 284 int vlan0_idx; /* VLAN 0 Table index */ 285 int vlan1_idx; /* VLAN 1 table index */ 286 int vlan0_priority; /* VLAN 0 priority */ 287 int vlan1_priority; /* VLAN 1 priority */ 288 uint8 vlan_ethertype_idx; /* VLAN ethertype index */ 289 bcm_cpri_roe_opcode_t opcode; /* RoE opcode */ 290 bcm_cpri_roe_frame_format_t type; /* RoE Frame Header Formatt */ 291 uint8 version; /* Header Version used in RSVD3 */ 292 uint32 ecpri_pc_id; /* PC_ID of eCPRI header, 16 bits for 293 both eCPRI8 and eCPRI12 */ 294 uint32 ecpri_msg_type; /* Message Type eCPRI header, 8 bits 295 only */ 296 } bcm_cpri_encap_info_t; 297 298 #ifndef BCM_HIDE_DISPATCHABLE 299 300 /* Program the specified entry into Encapsulation header table. */ 301 extern int bcm_cpri_port_encap_set( 302 int unit, 303 bcm_gport_t port, 304 int queue_num, 305 bcm_cpri_encap_info_t *encap_config); 306 307 /* Retrieve the encapsulation header info for a given axc ID. */ 308 extern int bcm_cpri_port_encap_get( 309 int unit, 310 bcm_gport_t port, 311 int queue_num, 312 bcm_cpri_encap_info_t *encap_config); 313 314 #endif /* BCM_HIDE_DISPATCHABLE */ 315 316 /* CPRI Encapsulation VLAN configuration */ 317 typedef struct bcm_cpri_encap_vlan_config_s { 318 uint32 ethertype_vlan_tagged; /* Tagged VLAN */ 319 uint32 ethertype_vlan_qinq; /* QinQ VLAN */ 320 uint32 roe_ethertype_0; /* RoE ether type 0 */ 321 uint32 roe_ethertype_1; /* RoE ether type 1 */ 322 } bcm_cpri_encap_vlan_config_t; 323 324 #ifndef BCM_HIDE_DISPATCHABLE 325 326 /* Set the VLAN ethertype config for encapsulation header . */ 327 extern int bcm_cpri_port_encap_vlan_config_set( 328 int unit, 329 bcm_gport_t port, 330 bcm_cpri_encap_vlan_config_t *vlan_config); 331 332 /* Retrieve the VLAN ethertype config for encapsulation header . */ 333 extern int bcm_cpri_port_encap_vlan_config_get( 334 int unit, 335 bcm_gport_t port, 336 bcm_cpri_encap_vlan_config_t *vlan_config); 337 338 #endif /* BCM_HIDE_DISPATCHABLE */ 339 340 /* CPRI Encap RoE Ordering Info Info types */ 341 typedef enum bcm_cpri_roe_info_type_e { 342 bcmCpriRoEInfoTypeUseSeq = 0, /* Use Sequene number */ 343 bcmCpriRoEInfoTypeBfnForQcnt = 1, /* Use Bfn for Qcnt */ 344 bcmCpriRoEInfoTypePInfo = 2 /* P info */ 345 } bcm_cpri_roe_info_type_t; 346 347 /* CPRI Encap RoE Ordering Info Increment types */ 348 typedef enum bcm_cpri_roe_incr_type_e { 349 bcmCpriRoEIncrTypeNone = 0, /* No increment. */ 350 bcmCpriRoEIncrTypeConstant = 1, /* Increment by a Contant */ 351 bcmCpriRoEIncrTypePayloadSize = 2 /* Increment by payload size */ 352 } bcm_cpri_roe_incr_type_t; 353 354 /* CPRI Encap RoE Ordering Information */ 355 typedef struct bcm_cpri_encap_roe_oi_s { 356 bcm_cpri_roe_info_type_t info_type; /* ordering info type */ 357 bcm_cpri_roe_incr_type_t p_seq_incr; /* seqNumPIncProp */ 358 bcm_cpri_roe_incr_type_t q_seq_incr; /* seqNumQIncProp */ 359 uint32 pcnt_size; /* Number in the range 1 to 32 */ 360 uint32 pcnt_increment; /* seqNumPInc */ 361 uint32 pcnt_max; /* seqNumPMax */ 362 uint32 qcnt_size; /* Number in the range 0 to (32-pcnt) */ 363 uint32 qcnt_increment; /* seqNumQInc */ 364 uint32 qcnt_max; /* seqNumQMax */ 365 uint32 seq_rsvd; /* seqNumRsvd Value */ 366 } bcm_cpri_encap_roe_oi_t; 367 368 #ifndef BCM_HIDE_DISPATCHABLE 369 370 /* Set the ordering info for encapsulation header. */ 371 extern int bcm_cpri_port_encap_roe_ordering_info_set( 372 int unit, 373 bcm_gport_t port, 374 int index, 375 bcm_cpri_encap_roe_oi_t *ordering_info); 376 377 /* Get the ordering info for encapsulation header. */ 378 extern int bcm_cpri_port_encap_roe_ordering_info_get( 379 int unit, 380 bcm_gport_t port, 381 int index, 382 bcm_cpri_encap_roe_oi_t *ordering_info); 383 384 #endif /* BCM_HIDE_DISPATCHABLE */ 385 386 /* CPRI Encap RoE Ordering Info Sequence Offset configuration */ 387 typedef struct bcm_cpri_roe_oi_seq_offset_s { 388 uint32 pcnt_size; /* Pcnt Size */ 389 uint32 pcnt_offset; /* Pcnt Offset */ 390 uint32 qcnt_size; /* Qcnt Size */ 391 uint32 qcnt_offset; /* Qcnt Offset */ 392 } bcm_cpri_roe_oi_seq_offset_t; 393 394 #ifndef BCM_HIDE_DISPATCHABLE 395 396 /* Configure sequence offset info associated with the ordering info. */ 397 extern int bcm_cpri_port_encap_roe_ordering_sequence_offset_set( 398 int unit, 399 bcm_gport_t port, 400 int queue, 401 int control, 402 bcm_cpri_roe_oi_seq_offset_t *seq_offset); 403 404 /* Get sequence offset info associated with the ordering info. */ 405 extern int bcm_cpri_port_encap_roe_ordering_sequence_offset_get( 406 int unit, 407 bcm_gport_t port, 408 int queue, 409 int control, 410 bcm_cpri_roe_oi_seq_offset_t *seq_offset); 411 412 /* Set the encap entry MAC DA. */ 413 extern int bcm_cpri_port_encap_roe_entry_macda_set( 414 int unit, 415 bcm_gport_t port, 416 int index, 417 bcm_mac_t macaddr); 418 419 /* Set the encap entry MAC SA. */ 420 extern int bcm_cpri_port_encap_roe_entry_macsa_set( 421 int unit, 422 bcm_gport_t port, 423 int index, 424 bcm_mac_t macaddr); 425 426 /* Get the encap entry MAC DA. */ 427 extern int bcm_cpri_port_encap_roe_entry_macda_get( 428 int unit, 429 bcm_gport_t port, 430 int index, 431 bcm_mac_t *macaddr); 432 433 /* Get the encap entry MAC SA. */ 434 extern int bcm_cpri_port_encap_roe_entry_macsa_get( 435 int unit, 436 bcm_gport_t port, 437 int index, 438 bcm_mac_t *macaddr); 439 440 #endif /* BCM_HIDE_DISPATCHABLE */ 441 442 /* CPRI Vlan flags */ 443 #define BCM_CPRI_VLAN_FLAG_VLAN_0 0x0 444 #define BCM_CPRI_VLAN_FLAG_VLAN_1 0x1 445 446 #ifndef BCM_HIDE_DISPATCHABLE 447 448 /* Configure VLAN ID for the given the encap entry. */ 449 extern int bcm_cpri_port_encap_roe_entry_vlan_set( 450 int unit, 451 bcm_gport_t port, 452 uint32 flags, 453 uint32 index, 454 bcm_vlan_t vlan_id); 455 456 /* Get the VLAN ID for the given encap entry. */ 457 extern int bcm_cpri_port_encap_roe_entry_vlan_get( 458 int unit, 459 bcm_gport_t port, 460 uint32 flags, 461 uint32 index, 462 bcm_vlan_t *vlan_id); 463 464 #endif /* BCM_HIDE_DISPATCHABLE */ 465 466 /* CPRI Packet Ethertypes */ 467 typedef enum bcm_cpri_ethertype_e { 468 bcmCpriEthertypeRoe = 0, /* Ethertype RoE */ 469 bcmCpriEthertypeFast = 1, /* Ethertype Fast Ethernet */ 470 bcmCpriEthertypeVlan = 2, /* Ethertype VLAN */ 471 bcmCpriEthertypeQinQ = 3 /* Ethertype QinQ */ 472 } bcm_cpri_ethertype_t; 473 474 #ifndef BCM_HIDE_DISPATCHABLE 475 476 /* Set the ethertype for CPRI decap. */ 477 extern int bcm_cpri_port_decap_ethertype_set( 478 int unit, 479 bcm_gport_t port, 480 bcm_cpri_ethertype_t type, 481 uint16 tpid); 482 483 /* Set the ethertype for CPRI decap. */ 484 extern int bcm_cpri_port_decap_ethertype_get( 485 int unit, 486 bcm_gport_t port, 487 bcm_cpri_ethertype_t type, 488 uint16 *tpid); 489 490 #endif /* BCM_HIDE_DISPATCHABLE */ 491 492 /* CPRI Decap Flow types */ 493 typedef enum bcm_cpri_decap_flow_type_e { 494 bcmCpriDecapFlowTypeIQData = 0, /* Flow Type IQ Data */ 495 bcmCpriDecapFlowTypeIQDataWithTimestamp = 1, /* Flow Type IQ Data with Timestamp */ 496 bcmCpriDecapFlowTypeControlWithOpcode = 2, /* Flow Type Control with Opcode */ 497 bcmCpriDecapFlowTypeControl = 3 /* Flow Type Control, without opcode */ 498 } bcm_cpri_decap_flow_type_t; 499 500 /* CPRI Decap Flow lookup options */ 501 typedef enum bcm_cpri_decap_flow_lookup_e { 502 bcmCpriDecapFlowLookupQueueNum = 0, /* Use Queue Number */ 503 bcmCpriDecapFlowLookupFlowID = 1, /* Use Flow ID to look up Queue number */ 504 bcmCpriDecapFlowLookupOpcode = 2 /* User Opcode to look up Queue number */ 505 } bcm_cpri_decap_flow_lookup_t; 506 507 /* CPRI Decap Flow classification information */ 508 typedef struct bcm_cpri_decap_flow_config_s { 509 bcm_cpri_decap_flow_type_t flow_type; /* Flow Type */ 510 bcm_cpri_decap_flow_lookup_t lookup_option; /* Look Up option */ 511 int queue_num; /* Queue Number */ 512 } bcm_cpri_decap_flow_config_t; 513 514 #ifndef BCM_HIDE_DISPATCHABLE 515 516 /* Configure flow classification table in CPRI decap. */ 517 extern int bcm_cpri_port_decap_flow_config_set( 518 int unit, 519 bcm_gport_t port, 520 uint8 roe_subtype, 521 bcm_cpri_decap_flow_config_t *config); 522 523 /* Retrieve flow classification table in CPRI decap. */ 524 extern int bcm_cpri_port_decap_flow_config_get( 525 int unit, 526 bcm_gport_t port, 527 uint8 roe_subtype, 528 bcm_cpri_decap_flow_config_t *config); 529 530 #endif /* BCM_HIDE_DISPATCHABLE */ 531 532 /* CPRI Decapsulation RoE Ordering Information */ 533 typedef struct bcm_cpri_decap_roe_oi_s { 534 bcm_cpri_roe_info_type_t info_type; /* */ 535 uint32 pcnt_size; /* Number in the range 1 to 32 */ 536 uint32 pcnt_increment; /* seqNumPInc */ 537 uint32 pcnt_max; /* seqNumPMax */ 538 uint32 p_inc_p2; /* seqNumPInc to be power of 2 */ 539 uint32 p_bias; /* Bias for P count */ 540 uint32 qcnt_size; /* Number in the range 0 to (32-pcnt) */ 541 uint32 qcnt_increment; /* seqNumQInc */ 542 uint32 qcnt_max; /* seqNumQMax */ 543 uint32 q_inc_p2; /* seqNumQInc to be power of 2 */ 544 uint32 q_bias; /* Bias for Q count */ 545 uint8 p_ext; /* Extended P Counter */ 546 uint8 gsm_tsn_bitmap; /* TSN bitmap */ 547 uint32 pcnt_pkt_count; /* Maximum pkt count described by P 548 counter */ 549 uint32 modulo_2; /* Queue Cycle Size is modulo 2 */ 550 uint32 seq_rsvd; /* seqNumRsvd Value */ 551 } bcm_cpri_decap_roe_oi_t; 552 553 #ifndef BCM_HIDE_DISPATCHABLE 554 555 /* Set the ordering info for Decapsulation. */ 556 extern int bcm_cpri_port_decap_roe_ordering_info_set( 557 int unit, 558 bcm_gport_t port, 559 int index, 560 bcm_cpri_decap_roe_oi_t *ordering_info); 561 562 /* Get the ordering info for Decapsulation. */ 563 extern int bcm_cpri_port_decap_roe_ordering_info_get( 564 int unit, 565 bcm_gport_t port, 566 int index, 567 bcm_cpri_decap_roe_oi_t *ordering_info); 568 569 /* Configure sequence offset info associated with the ordering info. */ 570 extern int bcm_cpri_port_decap_roe_ordering_sequence_offset_set( 571 int unit, 572 bcm_gport_t port, 573 int queue, 574 bcm_cpri_roe_oi_seq_offset_t *seq_offset); 575 576 /* Get sequence offset info associated with the ordering info. */ 577 extern int bcm_cpri_port_decap_roe_ordering_sequence_offset_get( 578 int unit, 579 bcm_gport_t port, 580 int queue, 581 bcm_cpri_roe_oi_seq_offset_t *seq_offset); 582 583 #endif /* BCM_HIDE_DISPATCHABLE */ 584 585 /* Tx TGEN configuration */ 586 typedef struct bcm_cpri_tx_frame_tgen_config_s { 587 uint32 tx_tgen_hfn; /* new hyperframe hfn number on next hyperframe */ 588 uint32 tx_tgen_bfn; /* new radio frame bfn number on next radio 589 frame */ 590 uint32 tx_tgen_bfn_sel; /* use cfg_tgen_bfn on next hyperframe or radio 591 frame */ 592 uint64 tx_tgen_ts_offset; /* start frame event after matching this offset */ 593 } bcm_cpri_tx_frame_tgen_config_t; 594 595 #ifndef BCM_HIDE_DISPATCHABLE 596 597 /* Configure tgen for port */ 598 extern int bcm_cpri_port_tx_frame_tgen_config_set( 599 int unit, 600 bcm_gport_t port, 601 int enable, 602 bcm_cpri_tx_frame_tgen_config_t *tgen_config); 603 604 #endif /* BCM_HIDE_DISPATCHABLE */ 605 606 /* RSVD4 Rx frame configuration */ 607 typedef struct bcm_rsvd4_rx_frame_config_s { 608 int speed_multiple; /* Only values 4 and 8 are supported */ 609 } bcm_rsvd4_rx_frame_config_t; 610 611 #ifndef BCM_HIDE_DISPATCHABLE 612 613 /* Set RSVD4 frame configuration */ 614 extern int bcm_cpri_port_rsvd4_rx_frame_config_set( 615 int unit, 616 bcm_gport_t port, 617 bcm_rsvd4_rx_frame_config_t *config); 618 619 /* Get RSVD4 frame configuration */ 620 extern int bcm_cpri_port_rsvd4_rx_frame_config_get( 621 int unit, 622 bcm_gport_t port, 623 bcm_rsvd4_rx_frame_config_t *config); 624 625 #endif /* BCM_HIDE_DISPATCHABLE */ 626 627 /* RSVD4 Rx Config fields */ 628 typedef enum bcm_rsvd4_rx_config_e { 629 bcmRsvd4RxConfigDescrambleEnable = 0, /* Descrambling Enable */ 630 bcmRsvd4RxConfigSyncThreshold = 1, /* Sync Threshold */ 631 bcmRsvd4RxConfigUnsyncThreshold = 2, /* Unsync Threshold */ 632 bcmRsvd4RxConfigFrameSyncThreshold = 3, /* Frame Sync Threshold */ 633 bcmRsvd4RxConfigFrameUnsyncThreshold = 4, /* Frame Unsync Threshold */ 634 bcmRsvd4RxConfigBlockSize = 5 /* Block Size */ 635 } bcm_rsvd4_rx_config_t; 636 637 #ifndef BCM_HIDE_DISPATCHABLE 638 639 /* Set RSVD4 frame configuration for debug purpose */ 640 extern int bcm_cpri_port_rsvd4_rx_frame_config_debug_set( 641 int unit, 642 bcm_gport_t port, 643 bcm_rsvd4_rx_config_t config_type, 644 uint32 value); 645 646 #endif /* BCM_HIDE_DISPATCHABLE */ 647 648 /* RSVD4 Rx FSM States */ 649 typedef enum bcm_rsvd4_rx_fsm_state_e { 650 bcmRsvd4RxFsmStateUnsync = 0, /* State Unsync */ 651 bcmRsvd4RxFsmStateWaitForSeed = 1, /* State Wait For Seed */ 652 bcmRsvd4RxFsmStateWaitForAck = 2, /* State Wait For Seed */ 653 bcmRsvd4RxFsmStateWaitForK28p7Idles = 3, /* State Wait for K28.7 Idles */ 654 bcmRsvd4RxFsmStateWaitForFrameSync = 4, /* State Wait for Frame Sync */ 655 bcmRsvd4RxFsmStateFrameSync = 5 /* State Frame Sync */ 656 } bcm_rsvd4_rx_fsm_state_t; 657 658 #ifndef BCM_HIDE_DISPATCHABLE 659 660 /* To set the RSVD4 state machine to a particular state for debug purpose */ 661 extern int bcm_cpri_port_rsvd4_rx_fsm_state_set( 662 int unit, 663 bcm_gport_t port, 664 bcm_rsvd4_rx_fsm_state_t state); 665 666 #endif /* BCM_HIDE_DISPATCHABLE */ 667 668 /* RSVD4 Rx FSM Override parameters */ 669 typedef enum bcm_rsvd4_rx_params_e { 670 bcmRsvd4RxParams_Frame_Unsync_T_Invalid_MG_Rcvd = 0, /* Frame Unsync Threshold */ 671 bcmRsvd4RxParams_Frame_Sync_T_Valid_MG_Rcvd = 1, /* Frame Sync Threshold */ 672 bcmRsvd4RxParams_K_MG_Idles_Rcvd = 2, /* K Frame Received */ 673 bcmRsvd4RxParams_Idle_Req_Rcvd = 3, /* Idle Request Received */ 674 bcmRsvd4RxParams_Idle_Ack_Rcvd = 4, /* Idle Ack Received */ 675 bcmRsvd4RxParams_SeedCapAndVerifyDone = 5 /* Seed Capture and Verify Done */ 676 } bcm_rsvd4_rx_params_t; 677 678 #ifndef BCM_HIDE_DISPATCHABLE 679 680 /* To set the RSVD4 state machine to a particular state for debug purpose */ 681 extern int bcm_cpri_port_rsvd4_rx_override_set( 682 int unit, 683 bcm_gport_t port, 684 bcm_rsvd4_rx_params_t parameter, 685 int enable, 686 int value); 687 688 #endif /* BCM_HIDE_DISPATCHABLE */ 689 690 /* bcm_rsvd4_msg_ts_mode_t */ 691 typedef _shr_rsvd4_msg_ts_mode_t bcm_rsvd4_msg_ts_mode_t; 692 693 /* RSVD4 TS MSG Modes. */ 694 #define BCM_RSVD4_MSG_TSMODE_WCDMA _shrRsvd4MsgTsModeWCDMA /* Msg Timestamp WCDMA mode */ 695 #define BCM_RSVD4_MSG_TSMODE_LTE _shrRsvd4MsgTsModeLTE /* Msg Timestamp LTE mode */ 696 #define BCM_RSVD4_MSG_TSMODE_GSM_DL _shrRsvd4MsgTsModeGSMDL /* Msg Timestamp GSM DL mode */ 697 #define BCM_RSVD4_MSG_TSMODE_GSM_UL _shrRsvd4MsgTsModeGSMUL /* Msg Timestamp GSM UL mode */ 698 699 /* bcm_rsvd4_sync_mode_t */ 700 typedef _shr_rsvd4_sync_mode_t bcm_rsvd4_sync_mode_t; 701 702 /* RSVD4 Frame Sync Modes. */ 703 #define BCM_RSVD4_SYNC_MODE_NO_SYNC _shrRsvd4SyncModeNoSync /* Sync On any message */ 704 #define BCM_RSVD4_SYNC_MODE_MSG_OFFSET _shrRsvd4SyncModeMsgOffset /* Sync On Message Offset */ 705 #define BCM_RSVD4_SYNC_MODE_MSG_AND_MASTER_FRAME_OFFSET _shrRsvd4SyncModeMsgAndMasterFrameOffset /* Sync On Master Frame 706 and Msg Offset */ 707 #define BCM_RSVD4_SYNC_MODE_TS_NO_SYNC _shrRsvd4SyncModeTsNoSync /* Sync On any message 708 timestamp, GSM Only */ 709 #define BCM_RSVD4_SYNC_MODE_TS_MSG_OFFSET _shrRsvd4SyncModeTsMsgOffset /* Sync On Msg Offset 710 timestamp, GSM Only */ 711 #define BCM_RSVD4_SYNC_MODE_TS_MSG_AND_MASTER_FRAME_OFFSET _shrRsvd4SyncModeTsMsgAndMasterFrameOffset /* Sync On Master Frame 712 And Msg Offset 713 timestamp, GSM Only */ 714 715 /* RSVD4 Rx Flow configuration */ 716 typedef struct bcm_rsvd4_rx_flow_info_s { 717 uint32 mask; /* header mask */ 718 uint32 match_data; /* header data to match */ 719 uint16 payload_size; /* payload size in bits */ 720 uint16 last_payload_index; /* last payload index */ 721 bcm_rsvd4_msg_ts_mode_t msg_ts_mode; /* Msg timestamp mode */ 722 bcm_rsvd4_sync_mode_t sync_mode; /* Sync Mode */ 723 uint16 stuffing_count; /* Stuffing Count */ 724 uint32 message_number_offset; /* Message number Offset for Sync */ 725 uint16 master_frame_offset; /* Master Frame Offset for Sync */ 726 uint16 msg_ts_count; /* Msg timestamp Count */ 727 uint16 container_blk_count; /* Container Block Count */ 728 uint8 priority; /* Priority */ 729 uint32 queue_size; /* Queue Size in bytes. */ 730 uint8 gsm_pad_size; /* GSM Pad Size */ 731 uint8 gsm_extra_pad_size; /* GSM Extra Pad size */ 732 uint8 gsm_pad_en; /* GSM Pad Enable */ 733 uint8 gsm_ctrl_loc; /* GSM control location */ 734 uint32 axc_id; /* AxC ID */ 735 uint32 last_payload_size; /* last Payload size */ 736 uint8 gsm_tsn_bitmap; /* GSM TSN bitmap */ 737 } bcm_rsvd4_rx_flow_info_t; 738 739 #ifndef BCM_HIDE_DISPATCHABLE 740 741 /* Add RSVD4 Rx Flow data AxC */ 742 extern int bcm_cpri_port_rsvd4_rx_flow_add( 743 int unit, 744 bcm_gport_t port, 745 int flow_id, 746 bcm_rsvd4_rx_flow_info_t *flow_info); 747 748 /* Delete RSVD4 Rx Flow data AxC */ 749 extern int bcm_cpri_port_rsvd4_rx_flow_delete( 750 int unit, 751 bcm_gport_t port, 752 int flow_id); 753 754 /* Set RSVD4 Rx master frame sync info */ 755 extern int bcm_cpri_port_rsvd4_rx_bfn_sync_config_set( 756 int unit, 757 bcm_gport_t port, 758 uint16 master_frame_count, 759 uint64 master_frame_start); 760 761 #endif /* BCM_HIDE_DISPATCHABLE */ 762 763 /* RSVD4 Frame Synchronization Info. */ 764 typedef struct bcm_rsvd4_frame_sync_info_s { 765 uint32 master_frame_number; /* RSVD4 Master Frame Number */ 766 } bcm_rsvd4_frame_sync_info_t; 767 768 #ifndef BCM_HIDE_DISPATCHABLE 769 770 /* Get RSVD4 Rx current frame sync info */ 771 extern int bcm_cpri_port_rsvd4_rx_current_frame_sync_info_get( 772 int unit, 773 bcm_gport_t port, 774 bcm_rsvd4_frame_sync_info_t *frame_sync_info); 775 776 /* Get RSVD4 Tx current frame sync info. */ 777 extern int bcm_cpri_port_rsvd4_tx_current_frame_sync_info_get( 778 int unit, 779 bcm_gport_t port, 780 bcm_rsvd4_frame_sync_info_t *frame_sync_info); 781 782 #endif /* BCM_HIDE_DISPATCHABLE */ 783 784 /* RSVD4 Tx frame configuration */ 785 typedef struct bcm_rsvd4_tx_frame_config_s { 786 uint8 los_enable; /* LOS enable */ 787 uint8 rsvd4_scrambler_seed; /* RSVD4 scrambler seed */ 788 int speed_multiple; /* Only values 4 and 8 are supported */ 789 } bcm_rsvd4_tx_frame_config_t; 790 791 #ifndef BCM_HIDE_DISPATCHABLE 792 793 /* RSVD4 Tx frame configuration */ 794 extern int bcm_cpri_port_rsvd4_tx_frame_config_set( 795 int unit, 796 bcm_gport_t port, 797 bcm_rsvd4_tx_frame_config_t *config); 798 799 /* RSVD4 Tx frame configuration get */ 800 extern int bcm_cpri_port_rsvd4_tx_frame_config_get( 801 int unit, 802 bcm_gport_t port, 803 bcm_rsvd4_tx_frame_config_t *config); 804 805 #endif /* BCM_HIDE_DISPATCHABLE */ 806 807 /* RSVD4 Tx Config fields */ 808 typedef enum bcm_rsvd4_tx_config_e { 809 bcmRsvd4TxConfigForceOffState = 0, /* Force Off State */ 810 bcmRsvd4TxConfigAckT = 1, /* Ack T */ 811 bcmRsvd4TxConfigForceIdleAck = 2, /* Force Idle Ack */ 812 bcmRsvd4TxConfigLosEnable = 3, /* LOS Enable */ 813 bcmRsvd4TxConfigScrambleEnable = 4, /* Scrambling Enable */ 814 bcmRsvd4TxConfigTransmitterEnable = 5 /* Transmitter Enable */ 815 } bcm_rsvd4_tx_config_t; 816 817 #ifndef BCM_HIDE_DISPATCHABLE 818 819 /* Set RSVD4 Tx frame configuration for debug purpose */ 820 extern int bcm_cpri_port_rsvd4_tx_frame_config_debug_set( 821 int unit, 822 bcm_gport_t port, 823 bcm_rsvd4_tx_config_t config_type, 824 uint32 value); 825 826 #endif /* BCM_HIDE_DISPATCHABLE */ 827 828 /* RSVD4 Tx FSM States */ 829 typedef enum bcm_rsvd4_tx_fsm_state_e { 830 bcmRsvd4TxFsmStateOff = 0, /* State Off */ 831 bcmRsvd4TxFsmStateIdle = 1, /* State Idle */ 832 bcmRsvd4TxFsmStateIdleReq = 2, /* State Idle request */ 833 bcmRsvd4TxFsmStateIdleAck = 3, /* State Idle Acknowledge */ 834 bcmRsvd4TxFsmStateFrameTx = 4 /* State frame Tx */ 835 } bcm_rsvd4_tx_fsm_state_t; 836 837 #ifndef BCM_HIDE_DISPATCHABLE 838 839 /* To set the RSVD4 state machine to a particular state for debug purpose */ 840 extern int bcm_cpri_port_rsvd4_tx_fsm_state_set( 841 int unit, 842 bcm_gport_t port, 843 bcm_rsvd4_tx_fsm_state_t state); 844 845 #endif /* BCM_HIDE_DISPATCHABLE */ 846 847 /* RSVD4 Tx override parameteres for debug purpose */ 848 typedef enum bcm_rsvd4_tx_params_e { 849 bcmRsvd4TxParams_StartTx = 0, /* Start Tx */ 850 bcmRsvd4TxParams_PCS_Ack_CAP = 1, /* PCS Ack */ 851 bcmRsvd4TxParams_PCS_Idle_REQ = 2, /* PCS Idle Req */ 852 bcmRsvd4TxParams_PCS_SCR_Lock = 3, /* PCS SCR locked */ 853 bcmRsvd4TxParams_LOS_Status = 4 /* LOS Status */ 854 } bcm_rsvd4_tx_params_t; 855 856 #ifndef BCM_HIDE_DISPATCHABLE 857 858 /* To set the RSVD4 state machine to a particular state for debug purpose */ 859 extern int bcm_cpri_port_rsvd4_tx_override_set( 860 int unit, 861 bcm_gport_t port, 862 bcm_rsvd4_tx_params_t parameter, 863 int enable, 864 int value); 865 866 #endif /* BCM_HIDE_DISPATCHABLE */ 867 868 /* RSVD4 Tx Flow configuration */ 869 typedef struct bcm_rsvd4_tx_flow_info_s { 870 int axc_id; /* axc_id */ 871 uint16 stuffing_count; /* Stuffing Count */ 872 uint32 message_number_offset; /* Msg Number Offset for Sync */ 873 uint16 master_frame_offset; /* Master Frame number offset for Sync */ 874 uint32 container_blk_count; /* Container Block Count */ 875 uint16 message_addr; /* Message Address */ 876 uint32 msg_ts_offset; /* Msg Timestamp Offset */ 877 bcm_rsvd4_msg_ts_mode_t msg_ts_mode; /* Msg Timestamp Mode */ 878 uint8 message_type; /* Message Type */ 879 bcm_rsvd4_sync_mode_t sync_mode; /* Sync Mode */ 880 uint16 msg_ts_count; /* Msg Timestamp Count */ 881 uint8 index_to_secondary_dbm; /* index to secondary DBM */ 882 uint8 secondary_dbm_enable; /* Secondary DBM enable */ 883 uint8 num_active_slot; /* number of active slot */ 884 uint16 payload_size; /* payload size in bits */ 885 uint16 last_payload_size; /* last payload size */ 886 uint8 last_index; /* last payload index */ 887 uint8 pad_enable; 888 uint8 pad_size; /* pad size */ 889 uint8 extra_pad_size; /* extra pad size */ 890 uint8 cycle_size; /* Jitter buffer size in number of 891 packets */ 892 uint32 buffer_size; /* Packet size in bytes */ 893 uint8 gsm_ctrl_loc; /* GSM control location */ 894 } bcm_rsvd4_tx_flow_info_t; 895 896 #ifndef BCM_HIDE_DISPATCHABLE 897 898 /* Add RSVD4 Tx Flow data AxC */ 899 extern int bcm_cpri_port_rsvd4_tx_flow_add( 900 int unit, 901 bcm_gport_t port, 902 int flow_id, 903 bcm_rsvd4_tx_flow_info_t *flow_info); 904 905 /* Delete a RSVD4 Tx Flow data AxC */ 906 extern int bcm_cpri_port_rsvd4_tx_flow_delete( 907 int unit, 908 bcm_gport_t port, 909 int flow_id); 910 911 #endif /* BCM_HIDE_DISPATCHABLE */ 912 913 /* RSVD4 dual bitmap entry */ 914 typedef struct bcm_rsvd4_dbm_entry_s { 915 uint8 bm1_multiple; /* Bit Map 1 Multiple */ 916 uint32 bm1[3]; /* Bit Map 1 */ 917 uint8 bm1_size; /* Bit Map 1 size */ 918 uint32 bm2[2]; /* Bit Map 2 */ 919 uint8 bm2_size; /* Bit map 2 size */ 920 uint8 num_slots; /* number of slot for Each bit map */ 921 uint8 pos_index; /* Position Index */ 922 uint8 pos_entries; /* Number of Position Table Entries */ 923 } bcm_rsvd4_dbm_entry_t; 924 925 #ifndef BCM_HIDE_DISPATCHABLE 926 927 /* Set up a DBM entry */ 928 extern int bcm_cpri_port_rsvd4_dbm_entry_set( 929 int unit, 930 bcm_gport_t port, 931 int index, 932 bcm_rsvd4_dbm_entry_t *entry); 933 934 /* Retrieve a DBM entry */ 935 extern int bcm_cpri_port_rsvd4_dbm_entry_get( 936 int unit, 937 bcm_gport_t port, 938 int index, 939 bcm_rsvd4_dbm_entry_t *entry); 940 941 /* Clear a DBM entry */ 942 extern int bcm_cpri_port_rsvd4_dbm_entry_clear( 943 int unit, 944 bcm_gport_t port, 945 int index); 946 947 #endif /* BCM_HIDE_DISPATCHABLE */ 948 949 /* RSVD4 Secondary dual bitmap entry */ 950 typedef struct bcm_rsvd4_secondary_dbm_entry_s { 951 uint8 bm1_multiple; /* Bit Map 1 multiple */ 952 uint8 bm1; /* Bit Map 1 */ 953 uint8 bm1_size; /* Bit Map 1 size */ 954 uint8 bm2; /* Bit Map 2 */ 955 uint8 bm2_size; /* Bit Map 2 Size */ 956 uint8 num_slots; /* Number of Slots for each Bit */ 957 } bcm_rsvd4_secondary_dbm_entry_t; 958 959 #ifndef BCM_HIDE_DISPATCHABLE 960 961 /* Set up a secondary DBM entry */ 962 extern int bcm_cpri_port_rsvd4_secondary_dbm_entry_set( 963 int unit, 964 bcm_gport_t port, 965 int index, 966 bcm_rsvd4_secondary_dbm_entry_t *entry); 967 968 /* Retrieve a secondary DBM entry */ 969 extern int bcm_cpri_port_rsvd4_secondary_dbm_entry_get( 970 int unit, 971 bcm_gport_t port, 972 int index, 973 bcm_rsvd4_secondary_dbm_entry_t *entry); 974 975 /* Clear a Secondary DBM entry */ 976 extern int bcm_cpri_port_rsvd4_secondary_dbm_entry_clear( 977 int unit, 978 bcm_gport_t port, 979 int index); 980 981 #endif /* BCM_HIDE_DISPATCHABLE */ 982 983 /* CPRI Flow types */ 984 typedef enum bcm_cpri_flow_type_e { 985 bcmCpriFlowTypeData = 0, /* Data Flow Type */ 986 bcmCpriFlowTypeCtrl = 1, /* Control Flow Type */ 987 bcmCpriFlowTypeCount = 2 /* Should be last */ 988 } bcm_cpri_flow_type_t; 989 990 /* CPRI dbm position table entry */ 991 typedef struct bcm_cpri_dbm_position_entry_s { 992 uint8 valid; /* Valid */ 993 uint8 flow_id; /* Flow id */ 994 bcm_cpri_flow_type_t flow_type; /* Flow type - Data or Ctrl */ 995 uint8 index; /* X slot position , 0 to (Num_slot-1) */ 996 } bcm_cpri_dbm_position_entry_t; 997 998 /* CPRI transmission rule types */ 999 typedef enum bcm_cpri_tx_rule_type_e { 1000 bcmCpriTxRuleTypeData = 0, /* Tx Rule type Data */ 1001 bcmCpriTxRuleTypeCtrl = 1, /* Tx Rule Type Control */ 1002 bcmCpriTxRuleTypeCount = 2 /* Should be last */ 1003 } bcm_cpri_tx_rule_type_t; 1004 1005 /* CPRI modulo rule types */ 1006 typedef enum bcm_cpri_modulo_rule_mod_e { 1007 bcmCpriModuloRuleMod1 = 0, /* Modulo 1 */ 1008 bcmCpriModuloRuleMod2 = 1, /* Modulo 2 */ 1009 bcmCpriModuloRuleMod4 = 2, /* Module 4 */ 1010 bcmCpriModuloRuleMod8 = 3, /* Modulo 8 */ 1011 bcmCpriModuloRuleMod16 = 4, /* Modulo 16 */ 1012 bcmCpriModuloRuleMod32 = 5, /* Modulo 32 */ 1013 bcmCpriModuloRuleMod64 = 6, /* Modulo 64 */ 1014 bcmCpriModuloRuleModCount = 7 /* Should be last */ 1015 } bcm_cpri_modulo_rule_mod_t; 1016 1017 /* CPRI modulo rule entry */ 1018 typedef struct bcm_cpri_modulo_rule_entry_s { 1019 uint8 active; /* Entry is active */ 1020 bcm_cpri_modulo_rule_mod_t modulo_value; /* Modulo value */ 1021 uint8 modulo_index; /* Modulo index */ 1022 uint8 dbm_enable; /* Dual bitmap rule is enabled */ 1023 uint8 dbm_dbm_id; /* Flow Id or DBM profile ID if dbm is 1024 enabled */ 1025 bcm_cpri_flow_type_t flow_type; /* Flow type - Data or Ctrl */ 1026 } bcm_cpri_modulo_rule_entry_t; 1027 1028 #ifndef BCM_HIDE_DISPATCHABLE 1029 1030 /* Set the modulo Rule configuration */ 1031 extern int bcm_cpri_port_rsvd4_tx_modulo_rule_entry_set( 1032 int unit, 1033 bcm_gport_t port, 1034 uint32 modulo_rule_num, 1035 bcm_cpri_tx_rule_type_t modulo_rule_type, 1036 bcm_cpri_modulo_rule_entry_t *modulo_rule); 1037 1038 /* Get Modulo Rule Configuration */ 1039 extern int bcm_cpri_port_rsvd4_tx_modulo_rule_entry_get( 1040 int unit, 1041 bcm_gport_t port, 1042 uint32 modulo_rule_num, 1043 bcm_cpri_tx_rule_type_t modulo_rule_type, 1044 bcm_cpri_modulo_rule_entry_t *modulo_rule); 1045 1046 /* Set position entry configuration */ 1047 extern int bcm_cpri_port_rsvd4_tx_position_entry_set( 1048 int unit, 1049 bcm_gport_t port, 1050 uint32 pos_index, 1051 bcm_cpri_dbm_position_entry_t *pos_entry); 1052 1053 /* Get position entry configuration */ 1054 extern int bcm_cpri_port_rsvd4_tx_position_entry_get( 1055 int unit, 1056 bcm_gport_t port, 1057 uint32 pos_index, 1058 bcm_cpri_dbm_position_entry_t *pos_entry); 1059 1060 /* Configure decap flow to queue mapping. */ 1061 extern int bcm_cpri_port_decap_flow_to_queue_mapping_set( 1062 int unit, 1063 bcm_gport_t port, 1064 uint32 flow_id, 1065 uint32 queue_num); 1066 1067 /* Retrieve decap flow to queue mapping. */ 1068 extern int bcm_cpri_port_decap_flow_to_queue_mapping_get( 1069 int unit, 1070 bcm_gport_t port, 1071 uint32 flow_id, 1072 uint32 *queue_num); 1073 1074 /* Configure decap queue to ordering info index. */ 1075 extern int bcm_cpri_port_decap_queue_to_ordering_info_index_set( 1076 int unit, 1077 bcm_gport_t port, 1078 uint32 queue_num, 1079 uint32 ordering_info_index); 1080 1081 /* Retrieve decap queue to ordering info index. */ 1082 extern int bcm_cpri_port_decap_queue_to_ordering_info_index_get( 1083 int unit, 1084 bcm_gport_t port, 1085 uint32 queue_num, 1086 uint32 *ordering_info_index); 1087 1088 #endif /* BCM_HIDE_DISPATCHABLE */ 1089 1090 /* bcm_rsvd4_control_msg_proc_type_t */ 1091 typedef _shr_rsvd4_control_msg_proc_type_t bcm_rsvd4_control_msg_proc_type_t; 1092 1093 /* RSVD4 Control Message Processing Type. */ 1094 #define BCM_RSVD4_CONTROL_MSG_PROC_ETH _shrRsvd4CtrlMsgProcFE /* Multi Message Fast 1095 Ethernet. */ 1096 #define BCM_RSVD4_CONTROL_MSG_PROC_FCB _shrRsvd4CtrlMsgProcFE /* FCB. */ 1097 #define BCM_RSVD4_CONTROL_MSG_PROC_PAYLOAD _shrRsvd4CtrlMsgProcPayload /* Message Payload 1098 Extraction. */ 1099 #define BCM_RSVD4_CONTROL_MSG_PROC_FULL _shrRsvd4CtrlMsgProcFull /* Full Message. */ 1100 #define BCM_RSVD4_CONTROL_MSG_PROC_FULL_WITH_TAG _shrRsvd4CtrlMsgProcFullWithTag /* Full Message with Tag. */ 1101 1102 /* RSVD4 control flow configuration */ 1103 typedef struct bcm_rsvd4_control_flow_config_s { 1104 uint32 match_mask; /* Header Mask */ 1105 uint32 match_data; /* Header Match Data */ 1106 uint8 queue_num; /* Queue number */ 1107 bcm_rsvd4_control_msg_proc_type_t type; /* Message process type */ 1108 int sync_en; /* sync profile enable */ 1109 uint8 sync_profile; /* sync profile number */ 1110 uint8 priority; /* 0-3 */ 1111 uint32 queue_size; /* in bytes */ 1112 } bcm_rsvd4_control_flow_config_t; 1113 1114 #ifndef BCM_HIDE_DISPATCHABLE 1115 1116 /* Add control message flow. */ 1117 extern int bcm_cpri_port_rsvd4_rx_control_flow_add( 1118 int unit, 1119 int port, 1120 int control_flow_id, 1121 bcm_rsvd4_control_flow_config_t *config); 1122 1123 /* Delete control message flow. */ 1124 extern int bcm_cpri_port_rsvd4_rx_control_flow_delete( 1125 int unit, 1126 int port, 1127 int control_flow_id, 1128 bcm_rsvd4_control_flow_config_t *control_flow_cfg); 1129 1130 #endif /* BCM_HIDE_DISPATCHABLE */ 1131 1132 /* bcm_rsvd4_fast_eth_config_info_t */ 1133 typedef struct bcm_rsvd4_fast_eth_config_info_s { 1134 uint32 queue_num; /* Queue Number */ 1135 int no_fcs_err_check; /* Ignore FCS Error */ 1136 uint32 min_packet_size; /* Minimum packet size */ 1137 uint32 max_packet_size; /* Maximum Packet Size */ 1138 int min_packet_drop; /* Enable drop of Packet size below min packet size */ 1139 int max_packet_drop; /* Enable drop of Packet size above max packet 1140 size */ 1141 int strip_crc; /* Strip CRC */ 1142 } bcm_rsvd4_fast_eth_config_info_t; 1143 1144 #ifndef BCM_HIDE_DISPATCHABLE 1145 1146 /* Setup the fast ethernet control flow. */ 1147 extern int bcm_cpri_port_rsvd4_cm_fast_eth_config_set( 1148 int unit, 1149 int port, 1150 int control_flow_id, 1151 bcm_rsvd4_fast_eth_config_info_t *config); 1152 1153 #endif /* BCM_HIDE_DISPATCHABLE */ 1154 1155 /* bcm_rsvd4_sync_count_cycle_t */ 1156 typedef _shr_rsvd4_sync_count_cycle_t bcm_rsvd4_sync_count_cycle_t; 1157 1158 /* RSVD4 Sync Count Cycle. */ 1159 #define BCM_RSVD4_SYNC_COUNT_EVERY_MF _shrRsvd4SyncCountCycleEveryMF 1160 #define BCM_RSVD4_SYNC_COUNT_UPTO_SIX_MF _shrRsvd4SyncCountCycleUpToSixMF 1161 1162 /* */ 1163 typedef struct bcm_rsvd4_sync_profile_entry_s { 1164 uint32 master_frame_offset; /* Master frame Offset */ 1165 uint32 message_offset; /* Message Number Offset */ 1166 bcm_rsvd4_sync_count_cycle_t count_cycle; /* Count Cycle */ 1167 } bcm_rsvd4_sync_profile_entry_t; 1168 1169 #ifndef BCM_HIDE_DISPATCHABLE 1170 1171 /* Configure sync profile entry. */ 1172 extern int bcm_cpri_port_rsvd4_sync_profile_entry_set( 1173 int unit, 1174 int port, 1175 int index, 1176 bcm_rsvd4_sync_profile_entry_t *config); 1177 1178 /* Retrieve sync profile entry. */ 1179 extern int bcm_cpri_port_rsvd4_sync_profile_entry_get( 1180 int unit, 1181 int port, 1182 int index, 1183 bcm_rsvd4_sync_profile_entry_t *config); 1184 1185 #endif /* BCM_HIDE_DISPATCHABLE */ 1186 1187 /* Tag Generation Entry information. */ 1188 typedef struct bcm_cpri_tag_gen_entry_s { 1189 uint32 tag_id; /* Tag ID */ 1190 uint32 mask; /* Mask */ 1191 uint32 header; /* Header Info */ 1192 uint32 word_count; /* Word Count, Only for RTWP` */ 1193 } bcm_cpri_tag_gen_entry_t; 1194 1195 /* RSVD4 Control flow group */ 1196 typedef enum bcm_rsvd4_control_group_id_e { 1197 bcmRsvd4ControlGroupId0 = 0, /* RSVD4 Control Flow Group 0 */ 1198 bcmRsvd4ControlGroupId1 = 1 /* RSVD4 Control Flow Group 1 */ 1199 } bcm_rsvd4_control_group_id_t; 1200 1201 /* RSVD4 Slot Type */ 1202 typedef enum bcm_rsvd4_slot_type_e { 1203 bcmRsvd4SlotData = 0, /* RSVD4 Slot Type Data */ 1204 bcmRsvd4SlotControl = 1 /* RSVD4 Slot Type Control */ 1205 } bcm_rsvd4_slot_type_t; 1206 1207 /* RSVD4 Priority */ 1208 typedef enum bcm_rsvd4_priority_e { 1209 bcmRsvd4Priority0 = 0, /* RSVD4 Priority 0 */ 1210 bcmRsvd4Priority1 = 1, /* RSVD4 Priority 1 */ 1211 bcmRsvd4Priority2 = 2, /* RSVD4 Priority 2 */ 1212 bcmRsvd4Priority3 = 3 /* RSVD4 Priority 3 */ 1213 } bcm_rsvd4_priority_t; 1214 1215 /* RSVD4 Control flow configuration */ 1216 typedef struct bcm_rsvd4_tx_control_flow_group_config_s { 1217 uint8 queue_num; /* Queue Number */ 1218 bcm_rsvd4_control_msg_proc_type_t type; /* Process type */ 1219 bcm_rsvd4_priority_t priority; /* Queue priority */ 1220 } bcm_rsvd4_tx_control_flow_group_config_t; 1221 1222 #ifndef BCM_HIDE_DISPATCHABLE 1223 1224 /* Add Control flow Group Member */ 1225 extern int bcm_cpri_port_rsvd4_tx_control_flow_group_member_add( 1226 int unit, 1227 int port, 1228 bcm_rsvd4_control_group_id_t group_num, 1229 bcm_rsvd4_tx_control_flow_group_config_t *config); 1230 1231 /* Delete control flow group memeber. */ 1232 extern int bcm_cpri_port_rsvd4_tx_control_flow_group_member_delete( 1233 int unit, 1234 int port, 1235 bcm_rsvd4_control_group_id_t group_num, 1236 bcm_rsvd4_priority_t priority); 1237 1238 #endif /* BCM_HIDE_DISPATCHABLE */ 1239 1240 /* */ 1241 typedef struct bcm_rsvd4_tx_cm_eth_config_s { 1242 uint8 msg_node; /* Message Node */ 1243 uint8 msg_subnode; /* Message Subnode */ 1244 uint8 msg_type; /* Message Type */ 1245 uint8 msg_padding; /* Message Padding */ 1246 } bcm_rsvd4_tx_cm_eth_config_t; 1247 1248 #ifndef BCM_HIDE_DISPATCHABLE 1249 1250 /* Set RSVD4 control message ethernet configuration */ 1251 extern int bcm_cpri_port_rsvd4_tx_cm_eth_config_set( 1252 int unit, 1253 int port, 1254 bcm_rsvd4_tx_cm_eth_config_t *config); 1255 1256 #endif /* BCM_HIDE_DISPATCHABLE */ 1257 1258 /* RSVD4 Tx control message raw configuration */ 1259 typedef struct bcm_rsvd4_tx_cm_raw_config_s { 1260 uint8 msg_id; /* Message ID */ 1261 uint8 msg_type; /* Message Type */ 1262 } bcm_rsvd4_tx_cm_raw_config_t; 1263 1264 #ifndef BCM_HIDE_DISPATCHABLE 1265 1266 /* Set RSVD4 Tx Control message raw configuration */ 1267 extern int bcm_cpri_port_rsvd4_tx_cm_raw_config_set( 1268 int unit, 1269 int port, 1270 bcm_rsvd4_tx_cm_raw_config_t *config); 1271 1272 #endif /* BCM_HIDE_DISPATCHABLE */ 1273 1274 /* RSVD4 tx control flow configuration */ 1275 typedef struct bcm_rsvd4_tx_control_flow_config_s { 1276 uint8 queue_num; /* Queue Number */ 1277 uint8 crc_mode; /* crc mode for multi eth control axc */ 1278 uint32 cycle_size; /* cycle size of control axc for buffer 1279 allocation */ 1280 uint32 queue_size; /* queue size of control axc */ 1281 bcm_rsvd4_control_msg_proc_type_t type; /* Message processing type */ 1282 } bcm_rsvd4_tx_control_flow_config_t; 1283 1284 #ifndef BCM_HIDE_DISPATCHABLE 1285 1286 /* Add RSVD4 Tx Control flow */ 1287 extern int bcm_cpri_port_rsvd4_tx_control_flow_add( 1288 int unit, 1289 int port, 1290 int control_flow_id, 1291 bcm_rsvd4_tx_control_flow_config_t *config); 1292 1293 #endif /* BCM_HIDE_DISPATCHABLE */ 1294 1295 /* RSVD4 Control Message tunnel CRC options */ 1296 typedef _shr_rsvd4_crc_option_t bcm_rsvd4_cm_tunnel_crc_option_t; 1297 1298 /* RSVD4 Control Message tunnel CRC options. */ 1299 #define BCM_RSVD4_CM_TUNNEL_CRC_USE_ROE _shrRsvd4CrcOptionUseRoe /* Use CRC from ROE 1300 packet. */ 1301 #define BCM_RSVD4_CM_TUNNEL_CRC_REGENERATE _shrRsvd4CrcOptionRegenerate /* Regenerate New CRC */ 1302 1303 #ifndef BCM_HIDE_DISPATCHABLE 1304 1305 /* set RSVD4 control message tunnel CRC configuration */ 1306 extern int bcm_cpri_port_rsvd4_tx_cm_tunnel_crc_config_set( 1307 int unit, 1308 int port, 1309 bcm_rsvd4_cm_tunnel_crc_option_t crc_option); 1310 1311 #endif /* BCM_HIDE_DISPATCHABLE */ 1312 1313 /* RSVD4 control message header config */ 1314 typedef struct bcm_rsvd4_tx_cm_hdr_entry_s { 1315 uint8 rsvd4_header_node; /* Message Header Node */ 1316 uint8 rsvd4_header_subnode; /* Message Header subnode */ 1317 uint8 rsvd4_control_payload_node; /* Control Payload node */ 1318 } bcm_rsvd4_tx_cm_hdr_entry_t; 1319 1320 #ifndef BCM_HIDE_DISPATCHABLE 1321 1322 /* SetRSVD4 Control Message header configuration */ 1323 extern int bcm_cpri_port_rsvd4_tx_cm_hdr_config_entry_set( 1324 int unit, 1325 int port, 1326 int index, 1327 bcm_rsvd4_tx_cm_hdr_entry_t *entry); 1328 1329 /* Set RSVD4 Control Message Header Lookup Entry */ 1330 extern int bcm_cpri_port_rsvd4_tx_cm_hdr_lkup_entry_set( 1331 int unit, 1332 int port, 1333 int flow_id, 1334 int header_index); 1335 1336 #endif /* BCM_HIDE_DISPATCHABLE */ 1337 1338 /* bcm_cpri_crc_mode_t */ 1339 typedef _shr_cpri_hdlc_crc_mode_t bcm_cpri_crc_mode_t; 1340 1341 /* bcm_cpri_hdlc_flag_size_t */ 1342 typedef _shr_cpri_hdlc_flag_size_t bcm_cpri_hdlc_flag_size_t; 1343 1344 /* cpri_cw_filter_mode_t */ 1345 typedef _shr_cpri_cw_filter_mode_t bcm_cpri_cw_filter_mode_t; 1346 1347 /* bcm_cpri_hdlc_filling_pattern_t */ 1348 typedef _shr_cpri_hdlc_filling_flag_pattern_t bcm_cpri_hdlc_filling_pattern_t; 1349 1350 /* bcm_cpri_gcw_mask_t */ 1351 typedef _shr_cpri_gcw_mask_t bcm_cpri_gcw_mask_t; 1352 1353 #define BCM_CPRI_CW_L1_SIGNAL_LOF 0x01 1354 #define BCM_CPRI_CW_L1_SIGNAL_LOS 0x02 1355 #define BCM_CPRI_CW_L1_SIGNAL_SDI 0x04 1356 #define BCM_CPRI_CW_L1_SIGNAL_RAI 0x08 1357 #define BCM_CPRI_CW_L1_SIGNAL_RESET 0x10 1358 #define BCM_CPRI_CW_L1_SIGNAL_HDLC_RATE 0x20 1359 #define BCM_CPRI_CW_L1_SIGNAL_ETH_POINTER 0x40 1360 #define BCM_CPRI_CW_L1_SIGNAL_PROTOCOL_VERSION 0x80 1361 1362 #define BCM_CPRI_CRC_APPEND _shrCpriHdlcCrcAppend 1363 #define BCM_CPRI_CRC_REPLACE _shrCpriHdlcCrcReplace 1364 #define BCM_CPRI_CRC_NO_UPDATE _shrCpriHdlcCrcNoUpdate 1365 1366 #define BCM_CPRI_HDLC_FLAG_SIZE_1_BYTE _shrCpriHdlcNumFlagSizeOneByte 1367 #define BCM_CPRI_HDLC_FLAG_SIZE_2_BYTE _shrCpriHdlcNumFlagSizeTwoByte 1368 1369 #define BCM_CPRI_HDLC_FILLING_PATTERN_7E _shrCpriHdlcFillingFlagPattern7E 1370 #define BCM_CPRI_HDLC_FILLING_PATTERN_7F _shrCpriHdlcFillingFlagPattern7F 1371 #define BCM_CPRI_HDLC_FILLING_PATTERN_FF _shrCpriHdlcFillingFlagPatternFF 1372 1373 #define BCM_CPRI_HDLC_FCS_SIZE_8_BITS _shrCpriHdlcFcsSize8Bits 1374 #define BCM_CPRI_HDLC_FCS_SIZE_16_BITS _shrCpriHdlcFcsSize16Bits 1375 #define BCM_CPRI_HDLC_FCS_SIZE_32_BITS _shrCpriHdlcFcsSize32Bits 1376 1377 #define BCM_CPRI_FILTER_DISABLE _shrCpriFilterDisable 1378 #define BCM_CPRI_FILTER_NON_ZERO _shrCpriFilterNonZero 1379 #define BCM_CPRI_FILTER_PERIODIC _shrCpriFilterPeriodic 1380 #define BCM_CPRI_FILTER_CHANGE _shrCpriFilterChange 1381 #define BCM_CPRI_FILTER_PATTERN _shrCpriFilterPatternMatch 1382 1383 #define BCM_CPRI_GCW_MASK_NO_BYTE _shrCpriGcwMaskNone 1384 #define BCM_CPRI_GCW_MASK_LSB_BYTE _shrCpriGcwMaskLSB 1385 #define BCM_CPRI_GCW_MASK_MSB_BYTE _shrCpriGcwMaskMSB 1386 #define BCM_CPRI_GCW_MASK_BOTH_BYTE _shrCpriGcwMaskBOTH 1387 1388 /* Layer 1 Control Word protocol information. */ 1389 typedef struct bcm_cpri_cw_l1_protocol_info_s { 1390 uint32 protocol_ver; /* Protocol Version */ 1391 uint32 hdlc_rate; /* HDLC data rate */ 1392 int reset; /* DL request, UL ack */ 1393 int l1_lof; /* Layer 1 LOF */ 1394 int l1_los; /* Layer 1 LOS */ 1395 int l1_sdi; /* Layer 1 SDI */ 1396 int l1_rai; /* Layer 1 RAI */ 1397 uint32 eth_pointer; /* ETH Control location 010100 - 11111 */ 1398 } bcm_cpri_cw_l1_protocol_info_t; 1399 1400 typedef enum bcm_cpri_crc_init_value_e { 1401 bcmCpriHdlcCrcInitValAll0 = _shrCpriHdlcCrcInitValAll0, /* All 0s */ 1402 bcmCpriHdlcCrcInitValAll1 = _shrCpriHdlcCrcInitValAll1, /* All 1s */ 1403 bcmCpriHdlcCrcInitValCount = _shrCpriHdlcCrcInitValCount /* Should be last */ 1404 } bcm_cpri_crc_init_value_t; 1405 1406 typedef enum bcm_cpri_hdlc_fcs_size_e { 1407 bcmCpriHdlcFcsSize8Bits = _shrCpriHdlcFcsSize8Bits, /* 8 bits */ 1408 bcmCpriHdlcFcsSize16Bits = _shrCpriHdlcFcsSize16Bits, /* 16 bits */ 1409 bcmCpriHdlcFcsSize32Bits = _shrCpriHdlcFcsSize32Bits, /* 32 bits */ 1410 bcmCpriHdlcFcsSizeCount = _shrCpriHdlcFcsSizeCount /* Should be last */ 1411 } bcm_cpri_hdlc_fcs_size_t; 1412 1413 /* */ 1414 typedef struct bcm_cpri_slow_hdlc_config_info_s { 1415 bcm_cpri_crc_mode_t hdlc_crc_mode; /* HDLC CRC mode */ 1416 bcm_cpri_hdlc_flag_size_t tx_flag_size; /* Flag Size */ 1417 bcm_cpri_hdlc_filling_pattern_t tx_filling_pattern; /* Fill Pattern */ 1418 bcm_cpri_crc_init_value_t crc_init_val; /* all 0's or all 1's */ 1419 int use_fe_mac; /* True/False */ 1420 int crc_byte_swap; /* True/False */ 1421 int no_fcs_err_check; /* True/False */ 1422 uint32 hdlc_cw_sel; /* Control Word Select */ 1423 uint32 hdlc_cw_size; /* Control Word Size */ 1424 bcm_cpri_hdlc_fcs_size_t hdlc_fcs_size; /* FCS size */ 1425 int hdlc_run_drop; /* Runt Drop Threshold */ 1426 int hdlc_max_drop; /* Max Drop Threshold */ 1427 uint32 hdlc_min_size; /* Min Size Thereshold */ 1428 uint32 hdlc_max_size; /* Max Size Threshold */ 1429 uint32 hdlc_queue_num; /* Queue number */ 1430 uint32 priority; /* 0-3 */ 1431 uint32 queue_size; /* in bytes */ 1432 uint32 cycle_size; /* Jitter Buffer Size in number of 1433 packets */ 1434 uint32 buffer_size; /* pkt size */ 1435 } bcm_cpri_slow_hdlc_config_info_t; 1436 1437 /* */ 1438 typedef struct bcm_cpri_fast_eth_config_info_s { 1439 uint32 sub_channel_start; /* The first sub-channel allocated for fast 1440 c&m */ 1441 uint32 sub_channel_size; /* sub channel size */ 1442 uint32 cw_sel; /* Select sub-channel words */ 1443 uint32 cw_size; /* Number of bytes per word to use. Valid 1444 values are 0 to 16. */ 1445 uint32 queue_num; /* queue number */ 1446 int ignore_fcs_err; /* True or False */ 1447 uint32 min_pkt_size; /* min packet size */ 1448 uint32 max_pkt_size; /* max packet size */ 1449 uint32 drop_min_pkt_size; /* min packet size to drop */ 1450 uint32 drop_max_pkt_size; /* max packet size to drop */ 1451 int strip_crc; /* True or False */ 1452 uint32 min_ipg; /* Min Inter Packet Gap */ 1453 bcm_cpri_crc_mode_t crc_mode; /* 0-append 1-replace 2-No update */ 1454 uint32 priority; /* 0-3 */ 1455 uint32 queue_size; /* in bytes */ 1456 uint32 cycle_size; /* Jitter Buffer size, in number of packets */ 1457 uint32 buffer_size; /* pkt size */ 1458 } bcm_cpri_fast_eth_config_info_t; 1459 1460 /* bcm_cpri_vsd_control_subchan_num_bytes_t */ 1461 typedef _shr_cpri_vsd_control_subchan_num_bytes_t bcm_cpri_vsd_control_subchan_num_bytes_t; 1462 1463 #define BCM_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_1 _shrVsdCtrlSubchanNumBytes1 1464 #define BCM_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_2 _shrVsdCtrlSubchanNumBytes2 1465 #define BCM_CPRI_VSD_CONTROL_SUBCHAN_NUM_BYTES_4 _shrVsdCtrlSubchanNumBytes4 1466 1467 /* bcm_cpri_vsd_control_subchan_size_t */ 1468 typedef _shr_cpri_vsd_control_subchan_size_t bcm_cpri_vsd_control_subchan_size_t; 1469 1470 #define BCM_CPRI_VSD_CONTROL_SUBCHAN_SIZE_2 _shrVsdCtrlSubchanSize2 1471 #define BCM_CPRI_VSD_CONTROL_SUBCHAN_SIZE_4 _shrVsdCtrlSubchanSize4 1472 1473 /* bcm_cpri_vsd_control_flow_num_bytes_t */ 1474 typedef _shr_cpri_vsd_control_flow_num_bytes_t bcm_cpri_vsd_control_flow_num_bytes_t; 1475 1476 #define BCM_CPRI_CONTROL_FLOW_NUM_BYTES_2 _shrVsdCtrlFlowNumBytes2 1477 #define BCM_CPRI_CONTROL_FLOW_NUM_BYTES_4 _shrVsdCtrlFlowNumBytes4 1478 1479 /* */ 1480 typedef struct bcm_cpri_rx_vsd_config_info_s { 1481 uint32 subchan_start; /* starting control subchannel number */ 1482 bcm_cpri_vsd_control_subchan_size_t subchan_size; /* 2 or 4 sub channels. */ 1483 bcm_cpri_vsd_control_subchan_num_bytes_t subchan_bytes; /* Sub Channel Number of Bytes 1,2 or 4. */ 1484 int subchan_step; /* 0 - No Skip 1- Skip One Sub Chan. */ 1485 uint32 queue_num; /* Queue Number */ 1486 uint32 vsd_valid_sector_mask[4]; /* total of 128 possible sectors */ 1487 uint32 priority; /* 0-3 */ 1488 uint32 queue_size; /* in bytes */ 1489 bcm_cpri_vsd_control_flow_num_bytes_t flow_bytes; /* number of bytes per flow 2 or 4. */ 1490 } bcm_cpri_rx_vsd_config_info_t; 1491 1492 /* VSD Flow Information */ 1493 typedef struct bcm_cpri_rx_vsd_flow_info_s { 1494 uint32 hyper_frame_number; /* Hyper Frame Number */ 1495 uint32 hyper_frame_modulo; /* Hyper Frame Modulo */ 1496 int filter_zero_data; /* Filer all 0's Data. */ 1497 uint32 section_num[4]; /* Section numbers of the group, 0 .. 127 . */ 1498 uint32 num_sector; /* Number of Sectors */ 1499 uint32 tag_id; /* Tag ID */ 1500 } bcm_cpri_rx_vsd_flow_info_t; 1501 1502 /* */ 1503 typedef struct bcm_cpri_rx_vsd_raw_config_info_s { 1504 uint32 schan_start; /* starting control subchannel number */ 1505 uint32 schan_size; /* Number of sub channels */ 1506 uint32 cw_sel; /* 4 bits bit map. which Xs bytes to 1507 use */ 1508 uint32 cw_size; /* number of bytes per word to extract 1509 0 to Tcw/8. Max 16 bytes */ 1510 uint32 queue_num; /* The queue number to be used for the 1511 payload data in the encapsulation 1512 memory. */ 1513 uint32 match_mask; /* Mask to apply to the data before 1514 comparing to the match_value. */ 1515 uint32 match_value; /* Value to match. */ 1516 uint32 match_offset; /* The offset of the first byte in the 1517 flow to match. */ 1518 uint32 hfn_modulo; /* Modulo value. Valid values are 1 to 1519 150. */ 1520 uint32 hfn_offset; /* Programmable offset. Valid values are 1521 0 to 149. */ 1522 bcm_cpri_cw_filter_mode_t filter_mode; /* Filter Mode */ 1523 uint32 priority; /* 0-3 */ 1524 uint32 queue_size; /* in_bytes */ 1525 } bcm_cpri_rx_vsd_raw_config_info_t; 1526 1527 /* */ 1528 typedef struct bcm_cpri_rx_rsvd5_config_info_s { 1529 uint32 schan_start; /* The first sub-channel allocated for the RSVD5 1530 parser. Valid values are 16 to 63 */ 1531 uint32 schan_size; /* Number of sub channels 1, 2 or 4 for CPRI 1532 4x, 8x and 16x.2 or 4 for CPRI 2x and 1533 10x.Setting the field to 0 disables the 1534 engine. Values other than 1, 2, 4 not 1535 supported. */ 1536 int disable_parity_check; /* True/False */ 1537 uint32 queue_num; /* Queue Number */ 1538 uint32 priority; /* 0-3 */ 1539 uint32 queue_size; /* in_bytes */ 1540 } bcm_cpri_rx_rsvd5_config_info_t; 1541 1542 /* Tag configuration */ 1543 typedef struct bcm_cpri_control_tag_config_s { 1544 uint32 default_tag; /* Default tag ID */ 1545 uint32 no_match_tag; /* No Match Tag ID */ 1546 } bcm_cpri_control_tag_config_t; 1547 1548 /* RX GCW Configuration */ 1549 typedef struct bcm_cpri_rx_gcw_config_info_s { 1550 uint32 Ns; /* sub channel # */ 1551 uint32 Xs; /* word number */ 1552 uint32 Y; /* first byte number valid value 0-7 1553 for 0,2,4,..14) */ 1554 bcm_cpri_gcw_mask_t mask; /* Mask */ 1555 bcm_cpri_cw_filter_mode_t filter_mode; /* Filter Mode */ 1556 uint32 hfn_index; /* Programmable offset. Valid values 1557 are 0 to 149. */ 1558 uint32 hfn_modulo; /* Modulo value. Valid values are 1 to 1559 150. */ 1560 uint32 match_value; /* Match Value */ 1561 uint32 match_mask; /* Mask to apply to the data before 1562 comparing to the match_value. */ 1563 } bcm_cpri_rx_gcw_config_info_t; 1564 1565 /* Control Word Sync Info */ 1566 typedef struct bcm_cpri_cw_sync_info_s { 1567 uint32 hfn; /* current hyperframe number Z.64.0 */ 1568 uint32 bfn; /* cpri radio frame number Z.192.0 Z.128.0 */ 1569 } bcm_cpri_cw_sync_info_t; 1570 1571 /* Tx L1 Config information. */ 1572 typedef struct bcm_cpri_cw_l1_config_info_s { 1573 uint32 enet_ptr; /* Z.194.0 Ethernet pointer p. */ 1574 uint32 l1_fun; /* Z.130.0 l1 function */ 1575 uint32 hdlc_rate; /* HDLC rate */ 1576 uint32 protocol_ver; /* Byte Z.2.0 version 1 or 2 */ 1577 } bcm_cpri_cw_l1_config_info_t; 1578 1579 /* VSD Config informations. */ 1580 typedef struct bcm_cpri_tx_vsd_config_info_s { 1581 uint32 subchan_start; /* starting control subchannel number */ 1582 bcm_cpri_vsd_control_subchan_size_t subchan_size; /* 2 or 4 sub channels. */ 1583 bcm_cpri_vsd_control_subchan_num_bytes_t subchan_bytes; /* Sub Channel Number of Bytes 1,2 or 4. */ 1584 int subchan_step; /* 0 - No Skip 1- Skip One Sub Chan. */ 1585 uint32 queue; /* 0x44 (68) default */ 1586 uint32 vsd_valid_sector_mask[4]; /* total of 128 possible sectors */ 1587 uint32 cycle_size; /* hdlc rate */ 1588 uint32 buffer_size; /* pkt size */ 1589 bcm_cpri_vsd_control_flow_num_bytes_t flow_bytes; /* number of bytes per flow 2 or 4. */ 1590 int byte_order_swap; /* Byte Order Swap 0:[15:8]=byte0 1591 [7:0]=byte1 1: [15:8]=byte1 1592 [7:0]=byte0 */ 1593 } bcm_cpri_tx_vsd_config_info_t; 1594 1595 /* VSD Flow Information */ 1596 typedef struct bcm_cpri_tx_vsd_flow_info_s { 1597 uint32 hyper_frame_number; /* Hyper Frame Number */ 1598 uint32 hyper_frame_modulo; /* Hyper Frame Modulo */ 1599 int repeat_mode; /* Repeat Mode. */ 1600 uint32 section_num[4]; /* Section numbers of the group, 0 .. 127 . */ 1601 uint32 num_sector; /* Number of Sectors */ 1602 uint32 roe_flow_id; /* RoE Flow ID */ 1603 } bcm_cpri_tx_vsd_flow_info_t; 1604 1605 /* VSD Raw configuration */ 1606 typedef struct bcm_cpri_tx_vsd_raw_config_info_s { 1607 uint32 schan_start; /* starting control subchannel number */ 1608 uint32 schan_size; /* Number of sub channels */ 1609 uint32 cw_sel; /* 4 bits bit map. which Xs bytes to use */ 1610 uint32 cw_size; /* number of bytes per word to extract 0 to Tcw/8. 1611 Max 16 bytes */ 1612 uint32 queue_num; /* The decap queue number to be used for VSD raw 1613 data. Valid values are 64-79. Should be different 1614 than other control queue numbers.. */ 1615 uint32 map_mode; /* Map Mode */ 1616 int repeat_mode; /* True/False */ 1617 int bfn0_filter_enable; /* True/False */ 1618 int bfn1_filter_enable; /* True/False */ 1619 uint32 hfn_index; /* hfn number */ 1620 uint32 hfn_modulo; /* hfn modulo */ 1621 uint32 idle_value; /* Idle value */ 1622 uint32 cycle_size; /* jitter buffer size in number of pakcets */ 1623 uint32 buffer_size; /* packet size size */ 1624 } bcm_cpri_tx_vsd_raw_config_info_t; 1625 1626 /* VSD raw fiter information */ 1627 typedef struct bcm_cpri_tx_cw_vsd_raw_filter_info_s { 1628 uint32 bfn0_value; /* BFN value for filter */ 1629 uint32 bfn0_mask; /* BFN mask for filter */ 1630 uint32 bfn1_value; /* BFN value for filter */ 1631 uint32 bfn1_mask; /* BFN mask for filter */ 1632 } bcm_cpri_tx_cw_vsd_raw_filter_info_t; 1633 1634 /* RSVD5 configuration */ 1635 typedef struct bcm_cpri_tx_cw_rsvd5_config_info_s { 1636 uint32 schan_start; /* The first sub-channel allocated for the RSVD5 1637 parser. Valid values are 16 to 63 */ 1638 uint32 schan_size; /* Number of sub channels 1, 2 or 4 for CPRI 4x, 8x 1639 and 16x.2 or 4 for CPRI 2x and 10x.Setting the 1640 field to 0 disables the engine. Values other than 1641 1, 2, 4 not supported. */ 1642 int crc_check_enable; /* True/False */ 1643 uint32 queue_num; /* Queue number */ 1644 uint32 cycle_size; /* Jitter buffer size in number of packets */ 1645 uint32 buffer_size; /* packet size */ 1646 } bcm_cpri_tx_cw_rsvd5_config_info_t; 1647 1648 /* GCW config information */ 1649 typedef struct bcm_cpri_tx_gcw_config_info_s { 1650 uint32 Ns; /* sub channel # */ 1651 uint32 Xs; /* word number */ 1652 uint32 Y; /* first byte number valid value 0-7 for 1653 0,2,4,..14) */ 1654 bcm_cpri_gcw_mask_t mask; /* Mask */ 1655 int repeat_mode; /* True/False */ 1656 int bfn0_filter_enable; /* Insert only when BFN matches values 1657 specified by the BFN configuration register. */ 1658 int bfn1_filter_enable; /* Insert only when BFN matches values 1659 specified by the BFN configuration register. */ 1660 uint32 hfn_index; /* Programmable offset. Valid values are 0 to 1661 149. */ 1662 uint32 hfn_modulo; /* Modulo value. Valid values are 1 to 150. */ 1663 } bcm_cpri_tx_gcw_config_info_t; 1664 1665 /* GCW Filter information */ 1666 typedef struct bcm_cpri_tx_gcw_tx_filter_info_s { 1667 uint32 bfn0_value; /* BFN value for filter */ 1668 uint32 bfn0_mask; /* BFN mask for filter */ 1669 uint32 bfn1_value; /* BFN value for filter */ 1670 uint32 bfn1_mask; /* BFN mask for filter */ 1671 } bcm_cpri_tx_gcw_tx_filter_info_t; 1672 1673 #ifndef BCM_HIDE_DISPATCHABLE 1674 1675 /* Retrieve Control word sync information */ 1676 extern int bcm_cpri_port_rx_cw_sync_info_get( 1677 int unit, 1678 int port, 1679 uint32 *hyper_frame_num, 1680 uint32 *radio_frame_num); 1681 1682 /* Retrieve Control word L1 Signal information */ 1683 extern int bcm_cpri_port_rx_cw_l1_signal_info_get( 1684 int unit, 1685 int port, 1686 bcm_cpri_cw_l1_protocol_info_t *l1_info); 1687 1688 /* Set L1 signal protection */ 1689 extern int bcm_cpri_port_rx_cw_l1_signal_protection_set( 1690 int unit, 1691 int port, 1692 uint32 signal_map, 1693 uint32 enable); 1694 1695 /* Retrieve L1 signal protection */ 1696 extern int bcm_cpri_port_rx_cw_l1_signal_protection_get( 1697 int unit, 1698 int port, 1699 uint32 signal_map, 1700 uint32 *enable); 1701 1702 /* set SLow HDLC Configuration */ 1703 extern int bcm_cpri_port_cw_slow_hdlc_config_set( 1704 int unit, 1705 int port, 1706 bcm_cpri_slow_hdlc_config_info_t *config); 1707 1708 /* Retrieve slow HDLC configuration */ 1709 extern int bcm_cpri_port_cw_slow_hdlc_config_get( 1710 int unit, 1711 int port, 1712 bcm_cpri_slow_hdlc_config_info_t *config); 1713 1714 /* Set control fast ethernet configuration */ 1715 extern int bcm_cpri_port_cw_fast_eth_config_set( 1716 int unit, 1717 int port, 1718 bcm_cpri_fast_eth_config_info_t *config); 1719 1720 /* Retrieve control fast ethernet configuration */ 1721 extern int bcm_cpri_port_cw_fast_eth_config_get( 1722 int unit, 1723 int port, 1724 bcm_cpri_fast_eth_config_info_t *config); 1725 1726 /* Set Rx VSD configuration */ 1727 extern int bcm_cpri_port_rx_cw_vsd_config_set( 1728 int unit, 1729 int port, 1730 bcm_cpri_rx_vsd_config_info_t *config); 1731 1732 /* Retrieve Rx VSD configuration */ 1733 extern int bcm_cpri_port_rx_cw_vsd_config_get( 1734 int unit, 1735 int port, 1736 bcm_cpri_rx_vsd_config_info_t *config); 1737 1738 /* Set/Add Rx VSD Control flow */ 1739 extern int bcm_cpri_port_rx_cw_vsd_ctrl_flow_add( 1740 int unit, 1741 int port, 1742 uint16 group_id, 1743 bcm_cpri_rx_vsd_flow_info_t *config); 1744 1745 /* Delete Rx VSD Control flow */ 1746 extern int bcm_cpri_port_rx_cw_vsd_ctrl_flow_delete( 1747 int unit, 1748 int port, 1749 uint16 group_id); 1750 1751 /* Retrieve Rx VSD control flow */ 1752 extern int bcm_cpri_port_rx_cw_vsd_ctrl_flow_get( 1753 int unit, 1754 int port, 1755 uint16 group_id, 1756 bcm_cpri_rx_vsd_flow_info_t *config); 1757 1758 /* Set Encapsulation Control Queue, tag to flow mapping */ 1759 extern int bcm_cpri_encap_control_queue_tag_to_flow_id_map_set( 1760 int unit, 1761 int port, 1762 uint32 tag_id, 1763 uint32 flow_id); 1764 1765 /* Set Rx VSD Raw Configuration */ 1766 extern int bcm_cpri_port_rx_cw_vsd_raw_config_set( 1767 int unit, 1768 int port, 1769 uint8 vsd_raw_id, 1770 bcm_cpri_rx_vsd_raw_config_info_t *config); 1771 1772 /* Retrieve Rx VSD Raw Configuration */ 1773 extern int bcm_cpri_port_rx_cw_vsd_raw_config_get( 1774 int unit, 1775 int port, 1776 uint8 vsd_raw_id, 1777 bcm_cpri_rx_vsd_raw_config_info_t *config); 1778 1779 /* Set Rx RSVD5 configuration */ 1780 extern int bcm_cpri_port_rx_cw_rsvd5_config_set( 1781 int unit, 1782 int port, 1783 bcm_cpri_rx_rsvd5_config_info_t *config); 1784 1785 /* Retrieve Rx RSVD5 configuration */ 1786 extern int bcm_cpri_port_rx_cw_rsvd5_config_get( 1787 int unit, 1788 int port, 1789 bcm_cpri_rx_rsvd5_config_info_t *config); 1790 1791 /* Set Rx tag configuration */ 1792 extern int bcm_cpri_port_rx_tag_config_set( 1793 int unit, 1794 int port, 1795 bcm_cpri_control_tag_config_t *config); 1796 1797 /* Add tag generation entry */ 1798 extern int bcm_cpri_port_rx_tag_entry_add( 1799 int unit, 1800 int port, 1801 bcm_cpri_tag_gen_entry_t *config); 1802 1803 /* delete tag generation entry */ 1804 extern int bcm_cpri_port_rx_tag_entry_delete( 1805 int unit, 1806 int port, 1807 bcm_cpri_tag_gen_entry_t *config); 1808 1809 /* Set Rx GCW configuration */ 1810 extern int bcm_cpri_port_rx_cw_gcw_config_set( 1811 int unit, 1812 int port, 1813 uint8 index, 1814 bcm_cpri_rx_gcw_config_info_t *config); 1815 1816 /* Retrieve Rx GCW configuration */ 1817 extern int bcm_cpri_port_rx_cw_gcw_config_get( 1818 int unit, 1819 int port, 1820 uint8 index, 1821 bcm_cpri_rx_gcw_config_info_t *config); 1822 1823 /* Set Tx Control Sync Information */ 1824 extern int bcm_cpri_port_tx_cw_sync_info_set( 1825 int unit, 1826 int port, 1827 bcm_cpri_cw_sync_info_t *entry); 1828 1829 /* Retrieve Rx Control Sync information */ 1830 extern int bcm_cpri_port_tx_cw_sync_info_get( 1831 int unit, 1832 int port, 1833 bcm_cpri_cw_sync_info_t *entry); 1834 1835 /* Set Tx L1 configuration */ 1836 extern int bcm_cpri_port_tx_cw_l1_config_set( 1837 int unit, 1838 int port, 1839 bcm_cpri_cw_l1_config_info_t *entry); 1840 1841 /* Set Tx VSD configuration */ 1842 extern int bcm_cpri_port_tx_cw_vsd_config_set( 1843 int unit, 1844 int port, 1845 bcm_cpri_tx_vsd_config_info_t *entry); 1846 1847 /* Retrieve Tx VSD configuration */ 1848 extern int bcm_cpri_port_tx_cw_vsd_config_get( 1849 int unit, 1850 int port, 1851 bcm_cpri_tx_vsd_config_info_t *entry); 1852 1853 /* Set/Add Tx VSD control flow */ 1854 extern int bcm_cpri_port_tx_cw_vsd_ctrl_flow_add( 1855 int unit, 1856 int port, 1857 uint16 group_id, 1858 bcm_cpri_tx_vsd_flow_info_t *config); 1859 1860 /* Delete Tx VSD Control flow */ 1861 extern int bcm_cpri_port_tx_cw_vsd_ctrl_flow_delete( 1862 int unit, 1863 int port, 1864 uint16 group_id); 1865 1866 /* Get Tx VSD control flow */ 1867 extern int bcm_cpri_port_tx_cw_vsd_ctrl_flow_get( 1868 int unit, 1869 int port, 1870 uint16 group_id, 1871 bcm_cpri_tx_vsd_flow_info_t *config); 1872 1873 /* Retrieve Tx VSD control flow */ 1874 extern int bcm_cpri_port_tx_cw_vsd_raw_flow_config_set( 1875 int unit, 1876 int port, 1877 uint8 index, 1878 bcm_cpri_tx_vsd_raw_config_info_t *config); 1879 1880 /* Retrieve Tx VSD Raw flow configuration */ 1881 extern int bcm_cpri_port_tx_cw_vsd_raw_flow_config_get( 1882 int unit, 1883 int port, 1884 uint8 index, 1885 bcm_cpri_tx_vsd_raw_config_info_t *config); 1886 1887 /* Set Tx VSD raw filter */ 1888 extern int bcm_cpri_port_tx_cw_vsd_raw_filter_set( 1889 int unit, 1890 int port, 1891 bcm_cpri_tx_cw_vsd_raw_filter_info_t *config); 1892 1893 /* Retrieve VSD raw filter */ 1894 extern int bcm_cpri_port_tx_cw_vsd_raw_filter_get( 1895 int unit, 1896 int port, 1897 bcm_cpri_tx_cw_vsd_raw_filter_info_t *config); 1898 1899 /* Set RSVD5 configuration */ 1900 extern int bcm_cpri_port_tx_cw_rsvd5_config_set( 1901 int unit, 1902 int port, 1903 bcm_cpri_tx_cw_rsvd5_config_info_t *config); 1904 1905 /* Retrieve RSVD5 configuration information */ 1906 extern int bcm_cpri_port_tx_cw_rsvd5_config_get( 1907 int unit, 1908 int port, 1909 bcm_cpri_tx_cw_rsvd5_config_info_t *config); 1910 1911 /* Set Tx GCW configuration */ 1912 extern int bcm_cpri_port_tx_cw_gcw_config_set( 1913 int unit, 1914 int port, 1915 uint8 index, 1916 bcm_cpri_tx_gcw_config_info_t *config); 1917 1918 /* Get Tx GCW configuration */ 1919 extern int bcm_cpri_port_tx_cw_gcw_config_get( 1920 int unit, 1921 int port, 1922 uint8 index, 1923 bcm_cpri_tx_gcw_config_info_t *config); 1924 1925 /* Set Tx GCW Filter */ 1926 extern int bcm_cpri_port_tx_cw_gcw_filter_set( 1927 int unit, 1928 int port, 1929 bcm_cpri_tx_gcw_tx_filter_info_t *config); 1930 1931 /* Get Tx GCW Filter */ 1932 extern int bcm_cpri_port_tx_cw_gcw_filter_get( 1933 int unit, 1934 int port, 1935 bcm_cpri_tx_gcw_tx_filter_info_t *config); 1936 1937 #endif /* BCM_HIDE_DISPATCHABLE */ 1938 1939 /* CPRI interrupt types */ 1940 typedef _shr_cpri_interrupt_type_t bcm_cpri_interrupt_type_t; 1941 1942 /* CPRI interrupt types */ 1943 #define BCM_CPRI_INTR_RX_PCS_64B66B_BLK_LCK_LL _shrCpriIntrRxPcs64B66BBlkLckLl /* RX PCS Block lock 1944 status - latch low 1945 version. */ 1946 #define BCM_CPRI_INTR_RX_PCS_64B66B_BLK_LCK_LH _shrCpriIntrRxPcs64B66BBlkLckLh /* RX PCS Block lock 1947 status - latch high 1948 version. */ 1949 #define BCM_CPRI_INTR_RX_PCS_64B66B_HI_BER_LL _shrCpriIntrRxPcs64B66BHiBerLl /* RX PCS BER - latch low 1950 version. */ 1951 #define BCM_CPRI_INTR_RX_PCS_64B66B_HI_BER_LH _shrCpriIntrRxPcs64B66BHiBerLh /* RX PCS BER - latch 1952 high version. */ 1953 #define BCM_CPRI_INTR_RX_PCS_LOS_LL _shrCpriIntrRxPcsLosLl /* RX PCS LOS - CPRI port 1954 Link UP. */ 1955 #define BCM_CPRI_INTR_RX_PCS_LOS_LH _shrCpriIntrRxPcsLosLh /* RX PCS LOS - CPRI port 1956 Link DOWN. */ 1957 #define BCM_CPRI_INTR_RX_PCS_LINK_STATUS_LL _shrCpriIntrRxPcsLinkStatusLl /* RX PCS link status - 1958 latch low version. */ 1959 #define BCM_CPRI_INTR_RX_PCS_LINK_STATUS_LH _shrCpriIntrRxPcsLinkStatusLh /* RX PCS link status - 1960 latch high version. */ 1961 #define BCM_CPRI_INTR_RX_PCS_EXTRACT_FIFO_OVRFLOW _shrCpriIntrRxPcsExtractFifoOvrFlow /* RX PCS extract FIFO 1962 overflow interrupt. */ 1963 #define BCM_CPRI_INTR_RX_GCW _shrCpriIntrRxGcw /* Interrupt for RX GCW 1964 Word(0-15) is loaded. */ 1965 #define BCM_CPRI_INTR_RX_1588_TS_FIFO _shrCpriIntrRx1588TsFifo /* RX 1588 Fifo intr */ 1966 #define BCM_CPRI_INTR_RX_1588_CAPTURED_TS _shrCpriIntrRx1588CapturedTs /* RX 1588 Sw capture 1967 interrupt. */ 1968 #define BCM_CPRI_INTR_RX_ENCAP_DATA_Q_OVERFLOW _shrCpriIntrRxEncapDataQOverflow /* Encap Data Queue FIFO 1969 Over-Flow */ 1970 #define BCM_CPRI_INTR_RX_ENCAP_CTRL_Q_OVERFLOW _shrCpriIntrRxEncapCtrlQOverflow /* Encap Ctrl Queue FIFO 1971 Over-Flow */ 1972 #define BCM_CPRI_INTR_RX_ENCAP_GSM_TS_Q_ERR _shrCpriIntrRxEncapGsmTsQErr /* Encap Per Queue GSM 1973 Time-Slot Error */ 1974 #define BCM_CPRI_INTR_RX_ENCAP_WORKQ_FIFO_OVERFLOW _shrCpriIntrRxEncapWqFiFoOverflow /* Encap Per Work-Queue 1975 FIFO Over Error */ 1976 #define BCM_CPRI_INTR_RX_ENCAP_RXFRM_IN_FIFO_OVERFLOW _shrCpriIntrRxEncapRxFrmInFifoOverflow /* Encap RX-framer 1977 Input-buffer FIFO Over 1978 Error */ 1979 #define BCM_CPRI_INTR_RX_ENCAP_IPSM_CDC_FIFO_ERR _shrCpriIntrRxEncapIpsmCdcFifoErr /* Encap IPSM CDC FIFO 1980 Error */ 1981 #define BCM_CPRI_INTR_RX_FRM_RSVD4_TS _shrCpriIntrRxFrmRsvd4Ts /* Per Axc(0-63) 1982 Timestamp interrupt in 1983 RSVD4 mode */ 1984 #define BCM_CPRI_INTR_RX_FRM_RSVD4_SINGLE_TS_ERR _shrCpriIntrRxFrmRsvd4SingleTsErr /* single timestamp 1985 error in RSVD4 mode */ 1986 #define BCM_CPRI_INTR_RX_FRM_L1_SIGNAL_CHANGE _shrCpriIntrRxFrmL1SigChange /* L1 signal change */ 1987 #define BCM_CPRI_INTR_RX_PCS_FEC_CS_CW_BAD _shrCpriIntrRxPcsFecCsCwBad /* cw_bad during CW_SYNC 1988 state */ 1989 #define BCM_CPRI_INTR_TX_DECAP_DATA_Q_OVFL_ERR _shrCpriIntrTxDecapDataQOvflErr /* Decap Per Queue Decap 1990 Data Queue FIFO 1991 Over-Flow Error */ 1992 #define BCM_CPRI_INTR_TX_DECAP_DATA_Q_UDFL_ERR _shrCpriIntrTxDecapDataQUdflErr /* Decap Per Queue Decap 1993 Data Queue FIFO 1994 underflow Error */ 1995 #define BCM_CPRI_INTR_TX_DECAP_DATA_BUFSIZE_ERR _shrCpriIntrTxDecapDataQBufSizeErr /* Decap Per Queue Decap 1996 Data Queue BUFF SIZE 1997 Error */ 1998 #define BCM_CPRI_INTR_TX_DECAP_AG_MODE_PKT_MISS _shrCpriIntrTxDecapAgModePktMiss /* Agnostic mode missing 1999 packet */ 2000 #define BCM_CPRI_INTR_TX_1588_CAPTURED_TS _shrCpriIntrTx1588CapturedTs /* TX 1588 Sw capture 2001 interrupt. */ 2002 #define BCM_CPRI_INTR_TX_1588_TS_FIFO _shrCpriIntrTx1588TsFifo /* TX 1588 Fifo capture 2003 interrupt. */ 2004 #define BCM_CPRI_INTR_TX_FRM_CWA_CTRL_PKT_FLOW_ID_ERR _shrCpriIntrTxFrmCwaCtrlPktFlowIdErr /* CWA ctrl flow packet 2005 flow id error */ 2006 #define BCM_CPRI_INTR_TX_FRM_BFA_HF_START_MISALIGN _shrCpriIntrTxFrmBfaHfStartMisalign /* BFA hf start misalign */ 2007 #define BCM_CPRI_INTR_TX_FRM_DR_MULTI_ETH_PSIZE_UNDERSIZE _shrCpriIntrTxFrmDrMultiEthPsizeUndersize /* RSVD4 control proc 2008 decap req multi eth - 2009 packet undersize */ 2010 #define BCM_CPRI_INTR_TX_FRM_DR_ACK_MISALIGN _shrCpriIntrTxFrmDrAckMisalign /* RSVD4 control proc 2011 decap req multi eth - 2012 packet undersize */ 2013 #define BCM_CPRI_INTR_TX_FRM_CWA_MULTIPLE_VALIDS _shrCpriIntrTxFrmCwaMultipleValids /* CPRI control asm 2014 valids from multiple 2015 engines are asserted 2016 at same time */ 2017 #define BCM_CPRI_INTR_TX_FRM_CWA_SDVM_PROC_OVERFLOW _shrCpriIntrTxFrmCwaSdvmProcOverflow /* CPRI control asm RSVD5 2018 proc buffer overflow */ 2019 #define BCM_CPRI_INTR_TX_FRM_ARB_PSIZE_ZERO _shrCpriIntrTxFrmArbPsizeZero /* decap sop control word 2020 packet size = 0 */ 2021 #define BCM_CPRI_INTR_TX_FRM_ARB_CPRI_ACK_MISMATCH _shrCpriIntrTxFrmArbCpriAckMismatch /* arbiter cpri ack 2022 mismatch */ 2023 #define BCM_CPRI_INTR_TX_FRM_ARB_RSVD4_REQ_CONFLICT _shrCpriIntrTxFrmArbRsvd4ReqConflict /* arbiter RSVD4 req 2024 conflict */ 2025 #define BCM_CPRI_INTR_TX_FRM_ARB_RSVD4_ACK_MISALIGN _shrCpriIntrTxFrmArbRsvd4AckMisalign /* arbiter RSVD4 ack 2026 misaligned */ 2027 #define BCM_CPRI_INTR_TX_FRM_CWA_HDLC_BUF_OVERFLOW _shrCpriIntrTxFrmCwaHdlcBufferOverflow /* CPRI control asm hdlc 2028 (slow cm) buffer 2029 overflow */ 2030 #define BCM_CPRI_INTR_TX_FRM_CWA_FAST_ETH_BUF_OVERFLOW _shrCpriIntrTxFrmCwaFastEthBufferOverflow /* CPRI control asm fast 2031 ethernet (fast cm) 2032 buffer overflow */ 2033 #define BCM_CPRI_INTR_TX_FRM_CWA_VSD_RAW_BUF_OVERFLOW _shrCpriIntrTxFrmCwaVsdRawBufferOverflow /* CPRI control asm vsd 2034 raw buffer overflow */ 2035 #define BCM_CPRI_INTR_TX_FRM_CWA_SDVM_BUF_OVERFLOW _shrCpriIntrTxFrmCwaSdvmBufferOverflow /* CPRI control asm Rsvd5 2036 buffer overflow */ 2037 #define BCM_CPRI_INTR_TX_FRM_MULTI_ETH_BUF_OVERFLOW _shrCpriIntrTxFrmMultiEthBufferOverflow /* RSVD4 control 2038 multi-msg eth buffer 2039 overflow */ 2040 #define BCM_CPRI_INTR_TX_FRM_MULTI_ETH_BUF_UNDERFLOW _shrCpriIntrTxFrmMultiEthBufferUnderflow /* RSVD4 control 2041 multi-msg eth buffer 2042 underflow */ 2043 #define BCM_CPRI_INTR_TX_GCW _shrCpriIntrTxGcw /* RSVD4 control 2044 multi-msg eth buffer 2045 underflow */ 2046 #define BCM_CPRI_INTR_TX_PCS_GBOX_OVERFLOW _shrCpriIntrTxPcsGboxOverflow /* gearbox buffer 2047 overflow */ 2048 #define BCM_CPRI_INTR_TX_PCS_GBOX_UNDERFLOW _shrCpriIntrTxPcsGboxUnderflow /* gearbox buffer 2049 underflow */ 2050 #define BCM_CPRI_INTR_TX_PCS_FIFO_OVERFLOW _shrCpriIntrTxPcsFifoOverflow /* TX assembly FIFO 2051 overflow */ 2052 #define BCM_CPRI_INTR_TX_PCS_FIFO_UNDERFLOW _shrCpriIntrTxPcsFifoUnderflow /* TX assembly FIFO 2053 underflow */ 2054 2055 /* CPRI port interrupt info */ 2056 typedef _shr_cpri_intr_info_t bcm_cpri_interrupt_info_t; 2057 2058 #define BCM_CPRI_INTR_DATA_NUM_OF_DATA64 _shrIntrDataNumOfData64 2059 2060 /* CPRI interrupt data, ths is sent to the user registered callback */ 2061 typedef bcm_cpri_interrupt_info_t bcm_cpri_interrupt_data_t; 2062 2063 /* 2064 * Callback function used for receiving notification about CPRI port RX, 2065 * TX, 1588 interrupts. 2066 */ 2067 typedef void (*bcm_cpri_port_interrupt_callback_t)( 2068 int unit, 2069 bcm_port_t port, 2070 bcm_cpri_interrupt_data_t *data, 2071 void *userdata); 2072 2073 #ifndef BCM_HIDE_DISPATCHABLE 2074 2075 /* Register a callback routine for CPRI interrupts. */ 2076 extern int bcm_cpri_port_interrupt_callback_register( 2077 int unit, 2078 bcm_cpri_interrupt_type_t cpri_intr_type, 2079 bcm_cpri_port_interrupt_callback_t callback, 2080 void *user_data); 2081 2082 /* Unregister a callback routine registered for CPRI interrupts. */ 2083 extern int bcm_cpri_port_interrupt_callback_unregister( 2084 int unit, 2085 bcm_cpri_interrupt_type_t cpri_intr_type, 2086 bcm_cpri_port_interrupt_callback_t callback); 2087 2088 /* Enable/Disable CPRI port RX/TX interrupts. */ 2089 extern int bcm_cpri_port_interrupt_enable_set( 2090 int unit, 2091 bcm_port_t port, 2092 bcm_cpri_interrupt_type_t cpri_intr_type, 2093 int data, 2094 int enable); 2095 2096 #endif /* BCM_HIDE_DISPATCHABLE */ 2097 2098 /* Cpri direction info */ 2099 typedef _shr_cpri_dir_t bcm_cpri_dir_t; 2100 2101 /* CPRI directions flags */ 2102 #define BCM_CPRI_DIR_TX _shrCpriDirTx 2103 #define BCM_CPRI_DIR_RX _shrCpriDirRx 2104 2105 /* Cpri capture mode info */ 2106 typedef _shr_cpri_1588_capture_mode_t bcm_cpri_1588_capture_mode_t; 2107 2108 /* CPRI port 1588 timestamp capture modes */ 2109 #define BCM_CPRI_1588_MATCH_BFN_AND_HFN _shrCpri1588CaptureModeMatchBfnHfn /* */ 2110 #define BCM_CPRI_1588_MATCH_HFN_ONLY _shrCpri1588CaptureModeMatchHfnOnly /* */ 2111 2112 /* CPRI 1588 Timestamp capture config information. */ 2113 typedef struct bcm_cpri_1588_capture_config_s { 2114 bcm_cpri_1588_capture_mode_t mode; /* Timestamp Capture type */ 2115 uint32 capture_bfn_num; /* if RSVD4, upper 12 bits of msg grp 2116 count */ 2117 uint32 capture_hfn_num; /* if RSVD4, lower 8 bits of msg grp 2118 count */ 2119 } bcm_cpri_1588_capture_config_t; 2120 2121 #ifndef BCM_HIDE_DISPATCHABLE 2122 2123 /* Set CPRI port 1588 timestamp capture configuration. */ 2124 extern int bcm_cpri_port_1588_timestamp_capture_config_set( 2125 int unit, 2126 bcm_port_t port, 2127 bcm_cpri_dir_t direction, 2128 bcm_cpri_1588_capture_config_t *config); 2129 2130 /* Get CPRI port 1588 timestamp capture configuration. */ 2131 extern int bcm_cpri_port_1588_timestamp_capture_config_get( 2132 int unit, 2133 bcm_port_t port, 2134 bcm_cpri_dir_t direction, 2135 bcm_cpri_1588_capture_config_t *config); 2136 2137 #endif /* BCM_HIDE_DISPATCHABLE */ 2138 2139 /* CPRI 1588 Timestamp config information. */ 2140 typedef struct bcm_cpri_1588_config_s { 2141 uint64 nano_sec; /* 48 bits only */ 2142 uint8 sub_nano_sec; /* 4 bits only */ 2143 uint8 sign_bit; /* 1 bit only */ 2144 } bcm_cpri_1588_config_t; 2145 2146 #ifndef BCM_HIDE_DISPATCHABLE 2147 2148 /* Set CPRI port 1588 timestamp capture configuration for FIFO and GDPLL. */ 2149 extern int bcm_cpri_port_1588_timestamp_config_set( 2150 int unit, 2151 bcm_port_t port, 2152 bcm_cpri_dir_t direction, 2153 bcm_cpri_1588_config_t *config); 2154 2155 /* Get CPRI port 1588 timestamp capture configuration for FIFO and GDPLL. */ 2156 extern int bcm_cpri_port_1588_timestamp_config_get( 2157 int unit, 2158 bcm_port_t port, 2159 bcm_cpri_dir_t direction, 2160 bcm_cpri_1588_config_t *config); 2161 2162 #endif /* BCM_HIDE_DISPATCHABLE */ 2163 2164 /* Cpri timestamp capture type info */ 2165 typedef _shr_cpri_1588_ts_type_t bcm_cpri_1588_ts_type_t; 2166 2167 /* CPRI port 1588 timestamp capture types */ 2168 #define BCM_CPRI_1588_TS_TYPE_FIFO _shrCpri1588TsTypeFifo /* */ 2169 #define BCM_CPRI_1588_TS_TYPE_CMIC _shrCpri1588TsTypeCMIC /* */ 2170 #define BCM_CPRI_1588_TS_TYPE_SW _shrCpri1588TsTypeSw /* */ 2171 2172 /* Cpri timestamp ts config info */ 2173 typedef struct bcm_cpri_1588_timestamp_ts_config_s { 2174 int enable; /* enable/disable */ 2175 uint32 modulo_count; /* modulo count */ 2176 } bcm_cpri_1588_timestamp_ts_config_t; 2177 2178 #ifndef BCM_HIDE_DISPATCHABLE 2179 2180 /* Set CPRI port 1588 timestamp parameter configuration. */ 2181 extern int bcm_cpri_port_1588_timestamp_ts_config_set( 2182 int unit, 2183 bcm_port_t port, 2184 bcm_cpri_dir_t direction, 2185 bcm_cpri_1588_ts_type_t type, 2186 bcm_cpri_1588_timestamp_ts_config_t *config); 2187 2188 /* Get CPRI port 1588 timestamp parameter configuration. */ 2189 extern int bcm_cpri_port_1588_timestamp_ts_config_get( 2190 int unit, 2191 bcm_port_t port, 2192 bcm_cpri_dir_t direction, 2193 bcm_cpri_1588_ts_type_t type, 2194 bcm_cpri_1588_timestamp_ts_config_t *config); 2195 2196 #endif /* BCM_HIDE_DISPATCHABLE */ 2197 2198 /* Cpri timestamp value */ 2199 typedef uint64 bcm_cpri_1588_timestamp_t; 2200 2201 #ifndef BCM_HIDE_DISPATCHABLE 2202 2203 /* Get CPRI port 1588 timestamp. */ 2204 extern int bcm_cpri_port_1588_timestamp_get( 2205 int unit, 2206 bcm_port_t port, 2207 bcm_cpri_dir_t direction, 2208 bcm_cpri_1588_ts_type_t type, 2209 int max_count, 2210 int *count, 2211 bcm_cpri_1588_timestamp_t *ts_list); 2212 2213 #endif /* BCM_HIDE_DISPATCHABLE */ 2214 2215 /* multiples of basic frame length */ 2216 typedef _shr_cpri_roe_payload_multiple_t bcm_cpri_roe_payload_multiple_t; 2217 2218 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_1X _shrCpriPayloadMultiple1X 2219 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_1P5X _shrCpriPayloadMultiple1p5X 2220 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_2X _shrCpriPayloadMultiple2X 2221 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_4X _shrCpriPayloadMultiple4X 2222 #define BCM_CPRI_PAYLOAD_MULTIPLE_BASIC_FRAME_8X _shrCpriPayloadMultiple8X 2223 2224 /* CPRI Order Info Type .orderInfoType. */ 2225 typedef _shr_cpri_roe_ordering_info_option_t bcm_cpri_ordering_info_option_t; 2226 2227 /* CPRI Order Info Type .orderInfoType */ 2228 #define BCM_CPRI_ORDERING_INFO_OPTION_SEQ_NUM _shrCpriRoeOrderingInfoOptionSeqNum /* Sequnece number in 2229 ordering info. */ 2230 #define BCM_CPRI_ORDERING_INFO_OPTION_TIMESTAMP _shrCpriRoeOrderingInfoOptionTimestamp /* Timestamp in ordering 2231 info */ 2232 2233 /* CPRI agnostic configuration */ 2234 typedef struct bcm_cpri_port_agnostic_config_s { 2235 bcm_cpri_frame_sync_mode_t frame_sync_mode; /* Radio, Hyper or Basic */ 2236 uint32 basic_frame_offset; /* Basic frame offset */ 2237 uint32 radio_frame_offset; /* Radio frame offset */ 2238 uint32 hyper_frame_offset; /* Hyper frame offset */ 2239 bcm_cpri_roe_payload_multiple_t payload_multiple; /* ROE payload size */ 2240 uint32 presentation_mod_count; /* timestamp filtering */ 2241 uint32 presentation_mod_offset; /* tx only */ 2242 uint32 tx_queue_mod_cnt; /* jitter buffer cycle size tx only */ 2243 bcm_cpri_ordering_info_option_t ordering_info_option; /* Ordering info option. */ 2244 } bcm_cpri_port_agnostic_config_t; 2245 2246 #ifndef BCM_HIDE_DISPATCHABLE 2247 2248 /* API to setup the agnostic mode and its configuration. */ 2249 extern int bcm_cpri_port_agnostic_config_set( 2250 int unit, 2251 bcm_port_t port, 2252 bcm_cpri_dir_t dir, 2253 int enable, 2254 bcm_cpri_port_agnostic_config_t *config); 2255 2256 /* API to get the agnostic mode and its configuration. */ 2257 extern int bcm_cpri_port_agnostic_config_get( 2258 int unit, 2259 bcm_port_t port, 2260 bcm_cpri_dir_t dir, 2261 int *enable, 2262 bcm_cpri_port_agnostic_config_t *config); 2263 2264 #endif /* BCM_HIDE_DISPATCHABLE */ 2265 2266 /* Cpri encapsulation presentation timestamp attribute */ 2267 typedef _shr_cpri_presentation_ts_attribute_t bcm_cpri_presentation_ts_attribute_t; 2268 2269 #define BCM_CPRI_ENCAP_PRESENTATION_TS_ADJUST _shrCpriEncapPresentationTsAdjust 2270 #define BCM_CPRI_ENCAP_PRESENTATION_APPROX_INC _shrCpriEncapPresentationApproxInc 2271 2272 /* Cpri presentation time */ 2273 typedef _shr_cpri_presentation_time_t bcm_cpri_presentation_time_t; 2274 2275 #ifndef BCM_HIDE_DISPATCHABLE 2276 2277 /* API to set the presentation attribute. */ 2278 extern int bcm_cpri_encap_presentation_time_config_set( 2279 int unit, 2280 bcm_port_t port, 2281 bcm_cpri_presentation_ts_attribute_t attribute, 2282 bcm_cpri_presentation_time_t *time); 2283 2284 /* API to get the presentation attribute. */ 2285 extern int bcm_cpri_encap_presentation_time_config_get( 2286 int unit, 2287 bcm_port_t port, 2288 bcm_cpri_presentation_ts_attribute_t attribute, 2289 bcm_cpri_presentation_time_t *time_offset); 2290 2291 #endif /* BCM_HIDE_DISPATCHABLE */ 2292 2293 /* Cpri decap presentation config */ 2294 typedef _shr_cpri_decap_presentation_config_t bcm_cpri_decap_presentation_config_t; 2295 2296 #ifndef BCM_HIDE_DISPATCHABLE 2297 2298 /* API to configure the decap presentation time. */ 2299 extern int bcm_cpri_decap_presentation_time_config_set( 2300 int unit, 2301 bcm_port_t port, 2302 bcm_cpri_decap_presentation_config_t *config); 2303 2304 /* API to retrieve the decap presentation time. */ 2305 extern int bcm_cpri_decap_presentation_time_config_get( 2306 int unit, 2307 bcm_port_t port, 2308 bcm_cpri_decap_presentation_config_t *config); 2309 2310 #endif /* BCM_HIDE_DISPATCHABLE */ 2311 2312 /* CPRI Port stats */ 2313 typedef enum bcm_cpri_stat_type_e { 2314 bcmCpriStatRxSymbolErr = 0, /* Rx Bytes Symbol Error Count. */ 2315 bcmCpriStatRxSeedMismatch = 1, /* Rx Seed Mismatch Count. */ 2316 bcmCpriStatRxStateErrTransition = 2, /* Rx number of transuition into Err 2317 state. */ 2318 bcmCpriStatTxVsdCtrlFlowIdErr = 3, /* Tx Vsd Control Flow ID out of range 2319 (0..127) error Count. */ 2320 bcmCpriStatTxVsdCtrlPktSizeErr = 4, /* Tx Vsd Control Packet size error 2321 count. >16 bytes. */ 2322 bcmCpriStatTxVsdRawPktSizeErr = 5, /* Tx Vsd Raw Packet size error count. */ 2323 bcmCpriStatTxRsvd5CrcErr = 6, /* Tx RSVD5 Dropped Packet Count due to 2324 CRC error. */ 2325 bcmCpriStatRxRsvd4SingleMsgCrcErr = 7, /* Rx RSVD4 Control Single Message 2326 Dropped Packet Count due to CRC 2327 error. */ 2328 bcmCpriStatRxTagLookupFailed = 8, /* Rx Tag Look up failed Count. */ 2329 bcmCpriStatRxRsvd4SingleMsgCnt = 9, /* Rx RSVD4 Single Message Count . */ 2330 bcmCpriStatRxRsvd4MultiMsgCnt = 10, /* Rx RSVD4 Multi Message Count. */ 2331 bcmCpriStatRxRsvd4MultiMsgSeqErr = 11, /* Rx RSVD4 Multi Message Sequence Error 2332 Count. */ 2333 bcmCpriStatRxDataByteErr = 12, /* Rx Data Bytes in Error. */ 2334 bcmCpriStatRxRsvd4HeaderErr = 13, /* Rx RSVD4 Dropped Messages Due to 2335 Header Error. */ 2336 bcmCpriStatRxRsvd4HeaderNoMatch = 14, /* Rx RSVD4 Messags Header No Match 2337 Found. */ 2338 bcmCpriStatRxRsvd4MsgCnt = 15, /* Rx RSVD4 Total Message Count. */ 2339 bcmCpriStatRxHfnErr = 16, /* Rx incorrect Hyper frame 2340 number(HFN). */ 2341 bcmCpriStatRxBfnErr = 17, /* Rx incorrect Radio frame 2342 number(BFN). */ 2343 bcmCpriStatRxCtrlWordErr = 18, /* Rx Control Word Error. */ 2344 bcmCpriStatRxGcwErr = 19, /* Rx GCW Dropped Words due to Byte 2345 Error. */ 2346 bcmCpriStatRxVsdRawErr = 20, /* Rx VSD Raw Dropped packets Due to 2347 byte error. */ 2348 bcmCpriStatRxVsdCtrlErr = 21, /* Rx VSD Control Dropped packets Due 2349 to byte error. */ 2350 bcmCpriStatTxRsvd4DataMsgCnt = 22, /* Tx Rsvd4 Data Message Count. */ 2351 bcmCpriStatTxRsvd4DataEmptyMsgCnt = 23, /* Tx Rsvd4 Data Empty Message Count. */ 2352 bcmCpriStatTxRsvd4CtrlMsgCnt = 24, /* Tx Rsvd4 Control Message Count. */ 2353 bcmCpriStatTxRsvd4CtrlEmptyMsgCnt = 25, /* Tx Rsvd4 Control Empty Message 2354 Count. */ 2355 bcmCpriStatRxRsvd5ParityErr = 26, /* Rx RSVD5 Parity Errored Message 2356 Count. */ 2357 bcmCpriStatRxHdlcErrFrame = 27, /* Rx HDLC Errored frame Count. */ 2358 bcmCpriStatRxHdlcGoodFrame = 28, /* Rx HDLC Good Frame Count. */ 2359 bcmCpriStatRxFastEthDroppedPkt = 29, /* Rx Fast Ethernet Dropped Packet. */ 2360 bcmCpriStatRxFastEthGoodPkt = 30, /* Rx Fast Ethernet Good Packet. */ 2361 bcmCpriStatMax = 31 /* Last One. */ 2362 } bcm_cpri_stat_type_t; 2363 2364 #ifndef BCM_HIDE_DISPATCHABLE 2365 2366 /* API to retrieve the CPRI port stats. */ 2367 extern int bcm_cpri_port_stat_get( 2368 int unit, 2369 bcm_gport_t port, 2370 bcm_cpri_stat_type_t type, 2371 uint64 *val); 2372 2373 /* API to enable/disable FEC Clause 91. */ 2374 extern int bcm_cpri_port_fec_enable_set( 2375 int unit, 2376 bcm_gport_t port, 2377 bcm_cpri_dir_t dir, 2378 int enable); 2379 2380 /* API to get status if FEC Clause 91 is enabled. */ 2381 extern int bcm_cpri_port_fec_enable_get( 2382 int unit, 2383 bcm_gport_t port, 2384 bcm_cpri_dir_t dir, 2385 int *enable); 2386 2387 #endif /* BCM_HIDE_DISPATCHABLE */ 2388 2389 /* Cpri FEC timestamp source */ 2390 typedef _shr_cpri_fec_ts_source_t bcm_cpri_fec_ts_source_t; 2391 2392 #define BCM_CPRI_FEC_TS_SOURCE_66b _shrCpriFecTsSource66b 2393 #define BCM_CPRI_FEC_TS_SOURCE_257b _shrCpriFecTsSource257b 2394 2395 /* Cpri FEC timestamp config info */ 2396 typedef struct bcm_cpri_fec_timestamp_config_s { 2397 int enable; /* Enable/Disable. */ 2398 bcm_cpri_fec_ts_source_t fec_fifo_ts_source_select; /* Source 66 bit or 257 bit. */ 2399 bcm_cpri_fec_ts_source_t fec_cmic_ts_source_select; /* Source 66 bit or 257 bit. */ 2400 uint32 control_bit_offset_0; /* Control Bit Offset. */ 2401 uint32 control_bit_offset_1; /* Control Bit Offset. */ 2402 uint32 control_bit_offset_2; /* Control Bit Offset. */ 2403 uint32 control_bit_offset_3; /* Control Bit Offset. */ 2404 } bcm_cpri_fec_timestamp_config_t; 2405 2406 #ifndef BCM_HIDE_DISPATCHABLE 2407 2408 /* API to set FEC timestamp config. */ 2409 extern int bcm_cpri_port_fec_timestamp_config_set( 2410 int unit, 2411 bcm_gport_t port, 2412 bcm_cpri_dir_t dir, 2413 bcm_cpri_fec_timestamp_config_t *config); 2414 2415 /* API to retrieve FEC timestamp config. */ 2416 extern int bcm_cpri_port_fec_timestamp_config_get( 2417 int unit, 2418 bcm_gport_t port, 2419 bcm_cpri_dir_t dir, 2420 bcm_cpri_fec_timestamp_config_t *config); 2421 2422 #endif /* BCM_HIDE_DISPATCHABLE */ 2423 2424 /* Cpri FEC aux config para */ 2425 typedef _shr_cpri_fec_aux_config_t bcm_cpri_fec_aux_config_t; 2426 2427 #define BCM_CPRI_FEC_AUX_CONFIG_SCRAMBLE_BYPASS_TX _shrCpriFecAuxConfigScrambleBypassTx 2428 #define BCM_CPRI_FEC_AUX_CONFIG_DESCRAMBLE_BYPASS_RX _shrCpriFecAuxConfigDescrambleBypassRx 2429 #define BCM_CPRI_FEC_AUX_CONFIG_BYPASS_INDICATION_ENABLE _shrCpriFecAuxConfigBypassIndicationEnable 2430 #define BCM_CPRI_FEC_AUX_CONFIG_BYPASS_CORRECTION_ENABLE _shrCpriFecAuxConfigBypassCorrectionEnable 2431 #define BCM_CPRI_FEC_AUX_CONFIG_CORRUPT_ALTERNATE_BLOCKS_ENABLE _shrCpriFecAuxConfigCorruptAlternateBlocksEnable 2432 #define BCM_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_CORRUPT_ENABLE _shrCpriFecAuxConfigSymbolErrorCorruptEnable 2433 #define BCM_CPRI_FEC_AUX_CONFIG_SYMBOL_ERROR_TMR_PERIOD _shrCpriFecAuxConfigSymbolErrorTmrPeriod 2434 #define BCM_CPRI_FEC_AUX_CONFIG_SYMBOL_ERR_CNT_THRESHOLD _shrCpriFecAuxConfigSymbolErrCntThreshold 2435 #define BCM_CPRI_FEC_AUX_CONFIG_SET_SYMB_ERR_WINDOW_128 _shrCpriFecAuxConfigSetSymbErrWindow128 2436 #define BCM_CPRI_FEC_AUX_CONFIG_GBOX_TICK_DENOMINATOR _shrCpriFecAuxConfigGboxTickDenominator 2437 #define BCM_CPRI_FEC_AUX_CONFIG_GBOX_TICK_NUMERATOR _shrCpriFecAuxConfigGboxTickNumerator 2438 #define BCM_CPRI_FEC_AUX_CONFIG_SOFT_RESET _shrCpriFecAuxConfigSoftReset 2439 2440 #ifndef BCM_HIDE_DISPATCHABLE 2441 2442 /* API to set FEC aux config. */ 2443 extern int bcm_cpri_port_fec_aux_config_set( 2444 int unit, 2445 bcm_gport_t port, 2446 bcm_cpri_fec_aux_config_t param_id, 2447 uint32 value); 2448 2449 /* API to retrieve FEC aux config. */ 2450 extern int bcm_cpri_port_fec_aux_config_get( 2451 int unit, 2452 bcm_gport_t port, 2453 bcm_cpri_fec_aux_config_t param_id, 2454 uint32 *value); 2455 2456 /* Set and Program Compression Table. */ 2457 extern int bcm_cpri_port_compression_lookup_table_set( 2458 int unit, 2459 bcm_gport_t port, 2460 int table_depth, 2461 uint32 *comp_table); 2462 2463 /* Get Compression Table. */ 2464 extern int bcm_cpri_port_compression_lookup_table_get( 2465 int unit, 2466 bcm_gport_t port, 2467 int max_depth, 2468 int *table_depth, 2469 uint32 *comp_table); 2470 2471 /* Set and Program DeCompression Table. */ 2472 extern int bcm_cpri_port_decompression_lookup_table_set( 2473 int unit, 2474 bcm_gport_t port, 2475 int table_depth, 2476 uint32 *comp_table); 2477 2478 /* Get DeCompression Table. */ 2479 extern int bcm_cpri_port_decompression_lookup_table_get( 2480 int unit, 2481 bcm_gport_t port, 2482 int max_depth, 2483 int *table_depth, 2484 uint32 *comp_table); 2485 2486 /* Set Decapsulation Queue Flow Control configuration. */ 2487 extern int bcm_cpri_port_decap_queue_flow_control_set( 2488 int unit, 2489 bcm_gport_t port, 2490 uint32 queue_num, 2491 uint32 xon_threshold, 2492 uint32 xoff_threshold, 2493 int enable); 2494 2495 /* Get Decapsulation Queue Flow Control configuration. */ 2496 extern int bcm_cpri_port_decap_queue_flow_control_get( 2497 int unit, 2498 bcm_gport_t port, 2499 uint32 queue_num, 2500 uint32 *xon_threshold, 2501 uint32 *xoff_threshold, 2502 int *enable); 2503 2504 /* Get Rx GCW word. */ 2505 extern int bcm_cpri_port_rx_cw_gcw_word_get( 2506 int unit, 2507 bcm_port_t port, 2508 int group_index, 2509 uint16 *gcw_word); 2510 2511 /* Set Tx GCW word. */ 2512 extern int bcm_cpri_port_tx_cw_gcw_word_set( 2513 int unit, 2514 bcm_port_t port, 2515 int group_index, 2516 uint16 gcw_word); 2517 2518 #endif /* BCM_HIDE_DISPATCHABLE */ 2519 2520 /* CPRI Tunnel Mode Configuration. */ 2521 typedef struct bcm_cpri_port_tunnel_config_s { 2522 uint32 payload_size; /* RoE payload size. In bytes. */ 2523 bcm_cpri_ordering_info_option_t ordering_info_option; /* Ordering info option. */ 2524 uint32 presentation_mod_count; /* Mod Count for Presentation time. */ 2525 uint32 presentation_mod_offset; /* Mod Offset for Presentation time. */ 2526 uint32 tx_queue_mod_count; /* Jitter buffer cycle size, Tx Only. */ 2527 } bcm_cpri_port_tunnel_config_t; 2528 2529 #ifndef BCM_HIDE_DISPATCHABLE 2530 2531 /* Set tunnel Mode configuration. */ 2532 extern int bcm_cpri_port_tunnel_mode_config_set( 2533 int unit, 2534 bcm_port_t port, 2535 bcm_cpri_dir_t direction, 2536 int enable, 2537 bcm_cpri_port_tunnel_config_t *config); 2538 2539 /* Get tunnel Mode configuration. */ 2540 extern int bcm_cpri_port_tunnel_mode_config_get( 2541 int unit, 2542 bcm_port_t port, 2543 bcm_cpri_dir_t direction, 2544 int *enable, 2545 bcm_cpri_port_tunnel_config_t *config); 2546 2547 #endif /* BCM_HIDE_DISPATCHABLE */ 2548 2549 /* CPRI RSVD4 Agnostic Mode Configuration. */ 2550 typedef struct bcm_cpri_port_rsvd4_agnostic_config_s { 2551 bcm_cpri_ordering_info_option_t ordering_info_option; /* Ordering info option. */ 2552 bcm_rsvd4_sync_mode_t sync_mode; /* Sync Mode */ 2553 uint32 payload_multiple; /* Multiple of Message group 1-3. */ 2554 uint32 master_frame_offset; /* Master Frame Offset for Sync */ 2555 uint32 message_group_offset; /* Message Group Offset for Sync */ 2556 uint32 presentation_mod_count; /* Mod Count for Presentation time. */ 2557 uint32 presentation_mod_offset; /* Mod Offset for Presentation time. */ 2558 uint32 tx_queue_mod_count; /* Jitter buffer cycle size, Tx Only. */ 2559 } bcm_cpri_port_rsvd4_agnostic_config_t; 2560 2561 #ifndef BCM_HIDE_DISPATCHABLE 2562 2563 /* Set RSVD4 Agnostic Mode configuration. */ 2564 extern int bcm_cpri_port_rsvd4_agnostic_mode_config_set( 2565 int unit, 2566 bcm_port_t port, 2567 bcm_cpri_dir_t direction, 2568 int enable, 2569 bcm_cpri_port_rsvd4_agnostic_config_t *config); 2570 2571 /* Get RSVD4 Agnostic Mode configuration. */ 2572 extern int bcm_cpri_port_rsvd4_agnostic_mode_config_get( 2573 int unit, 2574 bcm_port_t port, 2575 bcm_cpri_dir_t direction, 2576 int *enable, 2577 bcm_cpri_port_rsvd4_agnostic_config_t *config); 2578 2579 #endif /* BCM_HIDE_DISPATCHABLE */ 2580 2581 /* CPRI RoE Header Field, */ 2582 typedef _shr_cpri_roe_header_field_t bcm_cpri_roe_header_field_t; 2583 2584 #define BCM_CPRI_ROE_HEADER_FIELD_SUBTYPE _shrCpriRoeHeaderFieldSubType 2585 #define BCM_CPRI_ROE_HEADER_FIELD_FLOW_ID _shrCpriRoeHeaderFieldFlowID 2586 #define BCM_CPRI_ROE_HEADER_FIELD_LENGTH_15_8 _shrCpriRoeHeaderFieldLength_15_8 2587 #define BCM_CPRI_ROE_HEADER_FIELD_LENGTH_7_0 _shrCpriRoeHeaderFieldLength_7_0 2588 #define BCM_CPRI_ROE_HEADER_FIELD_ORDER_INFO_32_34 _shrCpriRoeHeaderFieldOrderInfo_32_24 2589 #define BCM_CPRI_ROE_HEADER_FIELD_ORDER_INFO_23_16 _shrCpriRoeHeaderFieldOrderInfo_23_16 2590 #define BCM_CPRI_ROE_HEADER_FIELD_ORDER_INFO_15_8 _shrCpriRoeHeaderFieldOrderInfo_15_8 2591 #define BCM_CPRI_ROE_HEADER_FIELD_ORDER_INFO_7_0 _shrCpriRoeHeaderFieldOrderInfo_7_0 2592 #define BCM_CPRI_ROE_HEADER_FIELD_OPCODE _shrCpriRoeHeaderFieldOpcode 2593 #define BCM_CPRI_ROE_HEADER_FIELD_UNMAPPED _shrCpriRoeHeaderFieldUnmapped 2594 2595 /* CPRI eCPRI Header Field, */ 2596 typedef _shr_cpri_ecpri_header_field_t bcm_cpri_ecpri_header_field_t; 2597 2598 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_0 _shrCpriEcpriHeaderFieldByte0 2599 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_1 _shrCpriEcpriHeaderFieldByte1 2600 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_2 _shrCpriEcpriHeaderFieldByte2 2601 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_3 _shrCpriEcpriHeaderFieldByte3 2602 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_4 _shrCpriEcpriHeaderFieldByte4 2603 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_5 _shrCpriEcpriHeaderFieldByte5 2604 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_6 _shrCpriEcpriHeaderFieldByte6 2605 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_7 _shrCpriEcpriHeaderFieldByte7 2606 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_8 _shrCpriEcpriHeaderFieldByte8 2607 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_9 _shrCpriEcpriHeaderFieldByte9 2608 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_10 _shrCpriEcpriHeaderFieldByte10 2609 #define BCM_CPRI_ECPRI_HEADER_FIELD_BYTE_11 _shrCpriEcpriHeaderFieldByte11 2610 #define BCM_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_0 _shrCpriEcpriHeaderFieldVlan0Byte0 2611 #define BCM_CPRI_ECPRI_HEADER_FIELD_VLAN_0_BYTE_1 _shrCpriEcpriHeaderFieldVlan0Byte1 2612 #define BCM_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_0 _shrCpriEcpriHeaderFieldVlan1Byte0 2613 #define BCM_CPRI_ECPRI_HEADER_FIELD_VLAN_1_BYTE_1 _shrCpriEcpriHeaderFieldVlan1Byte1 2614 2615 /* CPRI RoE Frame Configuration. */ 2616 typedef struct bcm_cpri_port_frame_config_s { 2617 bcm_cpri_roe_frame_format_t port_frame_format; /* Port Frame Format. */ 2618 bcm_cpri_ecpri_header_field_t decap_primary_key; /* Decap Primary Key */ 2619 bcm_cpri_ecpri_header_field_t decap_secondary_key; /* Decap Secondary Key. */ 2620 } bcm_cpri_port_frame_config_t; 2621 2622 #ifndef BCM_HIDE_DISPATCHABLE 2623 2624 /* Set RoE frame format for the port. */ 2625 extern int bcm_cpri_port_frame_config_set( 2626 int unit, 2627 bcm_port_t port, 2628 bcm_cpri_port_frame_config_t *config); 2629 2630 /* Configure decap secondary key to queue mapping. */ 2631 extern int bcm_cpri_port_decap_secondary_key_to_queue_mapping_set( 2632 int unit, 2633 bcm_port_t port, 2634 uint32 secondary_key, 2635 uint32 queue_num); 2636 2637 /* Retrieve decap secondary key to queue mapping. */ 2638 extern int bcm_cpri_port_decap_secondary_key_to_queue_mapping_get( 2639 int unit, 2640 bcm_port_t port, 2641 uint32 secondary_key, 2642 uint32 *queue_num); 2643 2644 /* Set Compression Saturation Threshold Value. */ 2645 extern int bcm_cpri_port_compression_saturation_config_set( 2646 int unit, 2647 bcm_port_t port, 2648 uint32 threshold_value); 2649 2650 /* Get Compression Saturation Threshold Value. */ 2651 extern int bcm_cpri_port_compression_saturation_config_get( 2652 int unit, 2653 bcm_port_t port, 2654 uint32 *threshold_value); 2655 2656 /* Set DeCompression Saturation Value. */ 2657 extern int bcm_cpri_port_decompression_saturation_config_set( 2658 int unit, 2659 bcm_port_t port, 2660 uint32 sat_value); 2661 2662 /* Set DeCompression Saturation Value. */ 2663 extern int bcm_cpri_port_decompression_saturation_config_get( 2664 int unit, 2665 bcm_port_t port, 2666 uint32 *sat_value); 2667 2668 #endif /* BCM_HIDE_DISPATCHABLE */ 2669 2670 #endif /* __BCM_CPRI_H__ */