pciefw_Loader_install.txt (11011B)
1 2 NOTE: For DNX devices (BCM88xxx devices), please refer to the "DNX16 Hardware 3 Design Guidelines for StrataDNX 16-nm Devices", DNX16-AN1xx.pdf, "DNX16 4 (BCM88790, BCM88690) QSPI Flash Programming" section. 5 6 For XGS devices (BCM56xxx devices), please follow instrutions below. 7 8 How to install PCIe FW Loader 9 ============================= 10 PCIe Gen3 FW can be programmed into serial flash using various methods. The 11 customer can use whatever method suits their manufacturing flow best. 12 13 Method 1: Using external flash programmer or gang programmer 14 This method requires all of the flash memory devices to be pre-programmed 15 with the provided firmware using an external programming device prior to 16 being mounted on the board. See programmers manual of external programmer for 17 instructions on how to erase and program serial flash device. 18 19 Method 2: Using ARM DS-5 and ARM DSTREAM 20 This method allows a blank flash device to be populated on the board at the 21 time of manufacturing. A small programming utility as well as the PCIe 22 firmware are loaded into the ARM R5 inside of the Broadcom switch device via 23 its JTAG interface. Once the load is complete, the programming utility will 24 be run by the ARM R5 and will program the firmware to the flash device. This 25 package includes further instructions on this flow in 26 tools/flashwrite/ARM_DS-5 27 28 Method 3: Initially advertise Gen1-only support from PCIe link partner 29 This method allows a blank flash device to be populated on the board at the 30 time of manufacturing. The Broadcom switch device is strapped to support PCIe 31 Gen3 and boot using the firmware (BOOT_DEV[2:0]=3'b000, MHOST0_BOOT_DEV=1'b1, 32 and PCIE_FORCE_GENTYPE[1:0]=2'b00). Since the PCIe link partner is 33 advertising Gen1 only support, the PCIe link will be able to come up and the 34 device will enumerate and function. The Broadcom SDK can then be loaded and 35 the SDK's PCIe Gen3 firmware in-field upgrade utility (SDK diag command 36 "pciephy fw load") can be used to program the firmware to the blank flash 37 device. Following that, the system can be reset and the PCIe link partner 38 can be reconfigured to advertise all supported PCIe speeds. 39 40 Syntax of in-field upgrade command: 41 BCM.0> pciephy fw load <Firmware file> 42 e.g., 43 BCM.0> pciephy fw load pciefw-r5.bin 44 45 NOTE: Use pciefw-m0.bin for BCM56370 (Helix5 family) and 46 use pciefw-r5-m7.bin for Merlin7 devices (Trident4 family) 47 48 The flash driver in SDK is based on MT25QL256. If the mounted flash part is 49 compatible with MT25QL256's instruction set but unrecognized by the driver, 50 please use SoC property "pcie_flash_mem_params" to specify the parameters of 51 the flash device. 52 53 pcie_flash_mem_params=<id>,<sector_size>,<page_size> 54 <id>: Manufacturer ID. 55 <sector_size>: The smallest erase unit in bytes. 56 <page_size>: The smallest access unit in bytes. 57 58 Method 4: Initially advertise Gen1-only support from Broadcom switch device 59 This method allows a blank flash device to be populated on the board at the 60 time of manufacturing. The Broadcom switch device is initially strapped to 61 support PCIe Gen1 and boot using the firmware (BOOT_DEV[2:0]=3'b000, 62 MHOST0_BOOT_DEV=1'b1, and PCIE_FORCE_GENTYPE[1:0]=2'b01). The PCIe link 63 will be able to come up and the device will enumerate and function. The 64 Broadcom SDK can then be loaded and the SDK's PCIe Gen3 firmware in-field 65 upgrade utility (SDK diag command "pciephy fw load") can be used to program 66 the firmware to the blank flash device. Following that, the 67 PCIE_FORCE_GENTYPE0 strap signal should be changed to 1'b0 and system should 68 be reset to advertise all supported PCIe speeds. 69 70 Syntax of in-field upgrade command: 71 BCM.0> pciephy fw load <Firmware file> 72 e.g., 73 BCM.0> pciephy fw load ppciefw-r5.bin 74 75 NOTE: Use pciefw-m0.bin for BCM56370 (Helix5 family) and 76 use pciefw-r5-m7.bin for Merlin7 devices (Trident4 family) 77 78 Method 5: Use I2C to write the firmware. 79 This requires the CPU that the SDK is running as to be an I2C master of an 80 I2C bus to which the Broadcom switch device is connected. 81 In such a case you need to know the I2C bus number (as Linux enumerates I2C 82 buses). And also know the I2C device number of the Broadcom switch device in 83 the bus which is by default 0x44. 84 This method also requires the SDK to be built with CPU I2C support. 85 This means that FEATURE_LIST in the make.local file should contain CPU_I2C . 86 87 Here is an example command making pciephy firmware handling use I2c with a 88 specific bus number and device number: 89 BCM.0> pciephy fw access i2c 0 0x44 90 91 After this command you can either test that I2C device access work using: 92 "pciephy fw version" or directly attempt to write the firmware to the flash 93 memory: "pciephy fw load <firmware file>" 94 95 If the BDE you are using with the SDK supports I2C access to the device 96 internally, removing the need to specify the I2C bus and device numbers, 97 instead of "pciephy fw access i2c <bus id> <device id>" you may use 98 "pciephy fw i2c_bde". 99 100 101 How to boot and verify PCIe FW 102 =================================== 103 1. Ensure that strap signals are set to load the firmware: 104 BOOT_DEV[2:0] = 3'b000 105 MHOST0_BOOT_DEV = 1'b1 106 PCIE_FORCE_GENTYPE[1:0] = 2'b00 107 108 2. Power On the system 109 110 3. Load and run linux 111 a) At a linux prompt run 112 lspci -d 0x14e4: -vvv 113 114 b) The Broadcom switch device should have enumerated and should show 115 something similar to the following: 116 "05:00.0 Ethernet controller: Broadcom Limited Device b870 (rev 01)" 117 118 c) In the lspci output, check that the link status register field shows 119 speed set to 8GT/s 120 8GT/s - PCIe Gen3 121 5GT/s - PCIe Gen2 122 2.5GT/s - PCIe Gen1 123 124 d) check that link capability register shows "ASPM not supported" and 125 link control register shows "ASPM disabled" 126 127 e) Run SDK and verify that "tr 502" completes successfully 128 129 How to apply custom/user settings in MAC/PHY registers 130 ====================================================== 131 It is anticipated that some of MAC/PHY settings, like TX FIR etc, may be tuned 132 by customer based on customer system requirements. PCIe Gen3 FW offers 133 provision for such cases. This provision offers optional custom settings 134 programming prior to and after SerDes FW loading. This provision requires 135 custom or system specific PCIe MAC/PHY register settings to be programmed at 136 30K offset of QSPI flash in the format described below i.e 137 {type, address, value} triplets. 138 139 ----------------------- __ 140 | 0x50434945 | | 141 | 0x41524753 | |__ Header, fixed, 4x32-bit words 142 | 0x00000000 | | 143 | 0x00000000 | __| 144 ----------------------- __ 145 | 0x4354524C | | Optional controls for FW load 146 | controls_0 | |__ Must have 0x4354524C as first word 147 | controls_1 | __| followed be two controls words 148 ----------------------- __ 149 | 0x5052454c | | 150 | {type, addr, val} | | 151 | {type, addr, val} | | Optional pre FW load settings 152 | : | | Must have 0x5052454c as first word 153 | : | |__ followed by {type, addr, val} 154 | : | | triplets (triplet - 3x32bit words) 155 | : | | type: 0 - MAC address, 1 - PHY addr 156 | : | | addr: MAC/PHY register address 157 | {type, addr, val} | __| Val: Value to be programmed 158 ----------------------- __ 159 | 0x504f5354 | | 160 | {type, addr, val} | | Optional post FW load settings 161 | : | | Must have 0x504f5354 as first word 162 | : | |__ followed by {type, addr, val} 163 | : | | triplets (triplet - 3x32bit words). 164 | : | | type: 0 - MAC address, 1 - PHY addr 165 | : | | addr: MAC/PHY register address 166 | {type, addr, val} | __| Val: Value to be programmed 167 ----------------------- __ 168 | 0x00454E44 | |__Footer, fixed, 2x32-bit words 169 | 0x41524753 | __| 170 ----------------------- 171 172 User can program up to maximum 168 triplets (i.e 504x32-bit words). 173 There is no restriction on number of triplets for pre FW load settings or post 174 FW load settings, provided total number of triplets do not exceed max limit 175 of 168. 176 177 Control section is used for optionally disable some loader feature or change 178 basic settings. Currently support below controls: 179 control_0[0:0] - Ignore enabling hotswap 180 control_0[1:1] - Ignore PERST status initial check 181 control_0[7:4] - Link Speed (PCIE generation) override, 182 1 - 2.5G, 2 - 5G, 3 - 8G, 0 - unconfigured 183 control_0[11:8] - Link width override, 1, 2 or 4 lanes are valid 184 Other fields are reserved for future. 185 186 Each type customer settings are optional, and total support up to 168 settings. 187 The settings should be organized as the below sequence. 188 [Controls] -> [Pre] -> [Post] 189 190 The address[26:16] of lane based PHY registers is used for lane number 191 assignment. 0 ~ 3 are used for selecting lane 1 ~ 4, and 0x1ff means 192 broadcast configuration to all PCIE lanes. 193 194 A sample format file in text format (custom.txt) and perl based text to binary 195 conversion utility provided under tools/flashwrite/custom/ directory of this 196 release package to help customer to generate customer settings in binary format. 197 198 Customer settings in text format may have comments with '#' at the begining of 199 the line and also blank lines which will be ignored by text to binary conversion 200 tool. 201 202 Syntax of text to binary conversion tool: 203 perl custom_ascii2bin.pl <input text file> <output file> 204 205 Example: Conversion of sample custom.txt file 206 207 linux#: perl custom_ascii2bin.pl custom.txt custom.bin 208 454943505347524100000000000000004c45525000000000381800000040088254534f5001000000b0d000008024000001000000b1d0000007000000444E450053475241 209 210 Hexdump of generated file should look like the following: 211 linux#: hexdump -c custom.bin 212 0000000 E I C P S G R A \0 \0 \0 \0 \0 \0 \0 \0 213 0000010 L E R P \0 \0 \0 \0 8 030 \0 \0 \0 @ \b 202 214 0000020 T S O P 001 \0 \0 \0 � � \0 \0 200 $ \0 \0 215 0000030 001 \0 \0 \0 � � \0 \0 \a \0 \0 \0 D N E \0 216 0000040 S G R A 217 0000044 218 219 Installing custom settings binary file: 220 1) Append binary file to PCIe Gen3 FW file (pciefw-r5.bin/pciefw-r5-m7.bin/pciefw-m0.bin) 221 e.g., 222 cat pciefw-r5.bin custom.bin >custom_pciefw-r5.bin 223 2) Install the appended binary into QSPI flash at offset 0x0 using one of the 224 FW installation methods mentioned above.