pciefw_Loader_install.txt (10389B)
1 2 NOTE: For DNX devices (BCM88xxx devices), please refer to the "DNX16 Hardware 3 Design Guidelines for StrataDNX 16-nm Devices", DNX16-AN1xx.pdf, "DNX16 4 (BCM88790, BCM88690) QSPI Flash Programming" section. 5 6 For XGS devices (BCM56xxx devices), please follow instrutions below. 7 8 How to install PCIe FW Loader 9 ============================= 10 PCIe Gen3 FW can be programmed into serial flash using various methods. The 11 customer can use whatever method suits their manufacturing flow best. 12 13 Method 1: Using external flash programmer or gang programmer 14 This method requires all of the flash memory devices to be pre-programmed 15 with the provided firmware using an external programming device prior to 16 being mounted on the board. See programmers manual of external programmer for 17 instructions on how to erase and program serial flash device. 18 19 Method 2: Using ARM DS-5 and ARM DSTREAM 20 This method allows a blank flash device to be populated on the board at the 21 time of manufacturing. A small programming utility as well as the PCIe 22 firmware are loaded into the ARM R5 inside of the Broadcom switch device via 23 its JTAG interface. Once the load is complete, the programming utility will 24 be run by the ARM R5 and will program the firmware to the flash device. This 25 package includes further instructions on this flow in 26 tools/flashwrite/ARM_DS-5 27 28 Method 3: Initially advertise Gen1-only support from PCIe link partner 29 This method allows a blank flash device to be populated on the board at the 30 time of manufacturing. The Broadcom switch device is strapped to support PCIe 31 Gen3 and boot using the firmware (BOOT_DEV[2:0]=3'b000, MHOST0_BOOT_DEV=1'b1, 32 and PCIE_FORCE_GENTYPE[1:0]=2'b00). Since the PCIe link partner is 33 advertising Gen1 only support, the PCIe link will be able to come up and the 34 device will enumerate and function. The Broadcom SDK can then be loaded and 35 the SDK's PCIe Gen3 firmware in-field upgrade utility (SDK diag command 36 "pciephy fw load") can be used to program the firmware to the blank flash 37 device. Following that, the system can be reset and the PCIe link partner 38 can be reconfigured to advertise all supported PCIe speeds. 39 40 Syntax of in-field upgrade command: 41 BCM.0> pciephy fw load <Firmware file> 42 e.g., 43 BCM.0> pciephy fw load pciefw-r5.bin 44 45 NOTE: Use pciefw-m0.bin for BCM56370 (Helix5 family) and 46 use pciefw-r5-m7.bin for Merlin7 devices (Trident4 family) 47 48 Method 4: Initially advertise Gen1-only support from Broadcom switch device 49 This method allows a blank flash device to be populated on the board at the 50 time of manufacturing. The Broadcom switch device is initially strapped to 51 support PCIe Gen1 and boot using the firmware (BOOT_DEV[2:0]=3'b000, 52 MHOST0_BOOT_DEV=1'b1, and PCIE_FORCE_GENTYPE[1:0]=2'b01). The PCIe link 53 will be able to come up and the device will enumerate and function. The 54 Broadcom SDK can then be loaded and the SDK's PCIe Gen3 firmware in-field 55 upgrade utility (SDK diag command "pciephy fw load") can be used to program 56 the firmware to the blank flash device. Following that, the 57 PCIE_FORCE_GENTYPE0 strap signal should be changed to 1'b0 and system should 58 be reset to advertise all supported PCIe speeds. 59 60 Syntax of in-field upgrade command: 61 BCM.0> pciephy fw load <Firmware file> 62 e.g., 63 BCM.0> pciephy fw load ppciefw-r5.bin 64 65 NOTE: Use pciefw-m0.bin for BCM56370 (Helix5 family) and 66 use pciefw-r5-m7.bin for Merlin7 devices (Trident4 family) 67 68 Method 5: Use I2C to write the firmware. 69 This requires the CPU that the SDK is running as to be an I2C master of an 70 I2C bus to which the Broadcom switch device is connected. 71 In such a case you need to know the I2C bus number (as Linux enumerates I2C 72 buses). And also know the I2C device number of the Broadcom switch device in 73 the bus which is by default 0x44. 74 This method also requires the SDK to be built with CPU I2C support. 75 This means that FEATURE_LIST in the make.local file should contain CPU_I2C . 76 77 Here is an example command making pciephy firmware handling use I2c with a 78 specific bus number and device number: 79 BCM.0> pciephy fw access i2c 0 0x44 80 81 After this command you can either test that I2C device access work using: 82 "pciephy fw version" or directly attempt to write the firmware to the flash 83 memory: "pciephy fw load <firmware file>" 84 85 If the BDE you are using with the SDK supports I2C access to the device 86 internally, removing the need to specify the I2C bus and device numbers, 87 instead of "pciephy fw access i2c <bus id> <device id>" you may use 88 "pciephy fw i2c_bde". 89 90 91 How to boot and verify PCIe FW 92 =================================== 93 1. Ensure that strap signals are set to load the firmware: 94 BOOT_DEV[2:0] = 3'b000 95 MHOST0_BOOT_DEV = 1'b1 96 PCIE_FORCE_GENTYPE[1:0] = 2'b00 97 98 2. Power On the system 99 100 3. Load and run linux 101 a) At a linux prompt run 102 lspci -d 0x14e4: -vvv 103 104 b) The Broadcom switch device should have enumerated and should show 105 something similar to the following: 106 "05:00.0 Ethernet controller: Broadcom Limited Device b870 (rev 01)" 107 108 c) In the lspci output, check that the link status register field shows 109 speed set to 8GT/s 110 8GT/s - PCIe Gen3 111 5GT/s - PCIe Gen2 112 2.5GT/s - PCIe Gen1 113 114 d) check that link capability register shows "ASPM not supported" and 115 link control register shows "ASPM disabled" 116 117 e) Run SDK and verify that "tr 502" completes successfully 118 119 How to apply custom/user settings in MAC/PHY registers 120 ====================================================== 121 It is anticipated that some of MAC/PHY settings, like TX FIR etc, may be tuned 122 by customer based on customer system requirements. PCIe Gen3 FW offers 123 provision for such cases. This provision offers optional custom settings 124 programming prior to and after SerDes FW loading. This provision requires 125 custom or system specific PCIe MAC/PHY register settings to be programmed at 126 30K offset of QSPI flash in the format described below i.e 127 {type, address, value} triplets. 128 129 ----------------------- __ 130 | 0x50434945 | | 131 | 0x41524753 | |__ Header, fixed, 4x32-bit words 132 | 0x00000000 | | 133 | 0x00000000 | __| 134 ----------------------- __ 135 | 0x4354524C | | Optional controls for FW load 136 | controls_0 | |__ Must have 0x4354524C as first word 137 | controls_1 | __| followed be two controls words 138 ----------------------- __ 139 | 0x5052454c | | 140 | {type, addr, val} | | 141 | {type, addr, val} | | Optional pre FW load settings 142 | : | | Must have 0x5052454c as first word 143 | : | |__ followed by {type, addr, val} 144 | : | | triplets (triplet - 3x32bit words) 145 | : | | type: 0 - MAC address, 1 - PHY addr 146 | : | | addr: MAC/PHY register address 147 | {type, addr, val} | __| Val: Value to be programmed 148 ----------------------- __ 149 | 0x504f5354 | | 150 | {type, addr, val} | | Optional post FW load settings 151 | : | | Must have 0x504f5354 as first word 152 | : | |__ followed by {type, addr, val} 153 | : | | triplets (triplet - 3x32bit words). 154 | : | | type: 0 - MAC address, 1 - PHY addr 155 | : | | addr: MAC/PHY register address 156 | {type, addr, val} | __| Val: Value to be programmed 157 ----------------------- __ 158 | 0x00454E44 | |__Footer, fixed, 2x32-bit words 159 | 0x41524753 | __| 160 ----------------------- 161 162 User can program up to maximum 168 triplets (i.e 504x32-bit words). 163 There is no restriction on number of triplets for pre FW load settings or post 164 FW load settings, provided total number of triplets do not exceed max limit 165 of 168. 166 167 Control section is used for optionally disable some loader feature or change 168 basic settings. Currently support below controls: 169 control_0[0:0] - Ignore enabling hotswap 170 control_0[1:1] - Ignore PERST status initial check 171 control_0[7:4] - Link Speed (PCIE generation) override, 172 1 - 2.5G, 2 - 5G, 3 - 8G, 0 - unconfigured 173 control_0[11:8] - Link width override, 1, 2 or 4 lanes are valid 174 Other fields are reserved for future. 175 176 Each type customer settings are optional, and total support up to 168 settings. 177 The settings should be organized as the below sequence. 178 [Controls] -> [Pre] -> [Post] 179 180 A sample format file in text format (custom.txt) and perl based text to binary 181 conversion utility provided under tools/flashwrite/custom/ directory of this 182 release package to help customer to generate customer settings in binary format. 183 184 Customer settings in text format may have comments with '#' at the begining of 185 the line and also blank lines which will be ignored by text to binary conversion 186 tool. 187 188 Syntax of text to binary conversion tool: 189 perl custom_ascii2bin.pl <input text file> <output file> 190 191 Example: Conversion of sample custom.txt file 192 193 linux#: perl custom_ascii2bin.pl custom.txt custom.bin 194 454943505347524100000000000000004c45525000000000381800000040088254534f5001000000b0d000008024000001000000b1d0000007000000444E450053475241 195 196 Hexdump of generated file should look like the following: 197 linux#: hexdump -c custom.bin 198 0000000 E I C P S G R A \0 \0 \0 \0 \0 \0 \0 \0 199 0000010 L E R P \0 \0 \0 \0 8 030 \0 \0 \0 @ \b 202 200 0000020 T S O P 001 \0 \0 \0 � � \0 \0 200 $ \0 \0 201 0000030 001 \0 \0 \0 � � \0 \0 \a \0 \0 \0 D N E \0 202 0000040 S G R A 203 0000044 204 205 Installing custom settings binary file: 206 1) Append binary file to PCIe Gen3 FW file (pciefw-r5.bin/pciefw-r5-m7.bin/pciefw-m0.bin) 207 e.g., 208 cat pciefw-r5.bin custom.bin >custom_pciefw-r5.bin 209 2) Install the appended binary into QSPI flash at offset 0x0 using one of the 210 FW installation methods mentioned above.